US20040135613A1

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Publication number: US20040135613A1
Application number: US10/743,955
Authority: US
Inventors: Evangelos Arkas; Nicholas Arkas
Original assignee: Individual
Current assignee: Individual
Priority date: 1999-03-27
Filing date: 2003-12-23
Publication date: 2004-07-15
Also published as: CA2365105A1; WO2000059113A1; EP1166445B1; WO2000059113A9; DE60000981D1; GB9907038D0; US6696875B1; AU3447500A; DE60000981T2; GB2348753A; EP1166445A1; GB2348753B

Abstract

A Pulse Clock Delay (PCT) apparatus (208) includes a selectable plurality (Nd) of series-connected pulse transition delay units (209) from a total plurality (Nmax) of such units. Each unit provides an incremental proximal node (n1a) and an adjacent electrically isolated second intermediate node (n1b) where the first and second intermediate nodes are in a shorter (215a, 215b) of two signal paths having respective proximal and spaced apart distal ends (212, 216) in an electrical network. Control means (205), responsive to the difference in electrical length between the two signal paths (214, 215), configures the switchable selection means to select a particular number of delay segments such that the propagation of a first edge transition (102) through the series combination of the shorter first path (215a, 215b) and the delay segment (208) is delayed sufficiently to arrive at the second path distal end (216) within +/−DELTA t of the time of arrival of the first edge transition propagating through the second path. Multiple PCDs may be distributed on a PCB to compensate delay differences for multiple pairs of unequal length bifurcated clock/signal lines.

Description

BACKGROUND OF THE INVENTION

Electrical Networks[0001]

An electrical network consists of signal nodes connected by electrically active elements. The electrically active elements include conductors, linear passive elements and linear and non-linear active elements. A given network is partially described by the kinds of elements involved and the network geometry, i.e., the manner in which the various elements are grouped and interconnected at their terminals. Passive elements such as conductors, resistors, capacitors and inductors may be interspersed with active elements such as transistors, gates, integrated circuits and the like.[0002]

All of these elements may be considered branches of the network. The geometry of a network is described in schematic form by the nodes to which two or more terminals of the elements are connected. The electrical conductors of the network are themselves elements or branches of the network.[0003]

One portrayal of a network shows the geometrical interconnection of elements only, and takes the form of a graph; i.e. each element of the network is represented as a line having two small circles at either end denoting the terminals of the elements connected at a node.[0004]

In digital logic networks (circuits), active elements (devices) may have terminals that are bi-directional (sometimes operating as an input and sometimes as an output) but are generally unilateral, i.e., signal transmission for related terminal pairs proceeds in one direction only, e.g. from an input terminal to an output terminal. Even bi-directional terminals exhibit unilateral behaviour for certain time periods, e.g., during a portion of a system clock cycle or cycles when they are designated as input or output.[0005]

Complex Elements in Networks[0006]

Complex elements, such as logic arrays, microprocessors and memory components are generally represented as rectangular boxes with multiple lines extending to small circles denoting terminals. The lines are annotated to represent input and output logic variable names. For example, in FIG. 1, n[0007]1, n2 indicate signal node n1 and signal node n2,1(1,2) indicates a signal link or path between

nodes

1 and2. The links1(1,2) may be composed of any combination of passive and active elements connected in series-parallel combinations. That is, signal nodes n1 and n2 are connected by signal paths1(1,2) that may represent a simple conductor or may represent a complex bi-bilateral element such as a combined microprocessor/logic array or a series-parallel combination of many different kinds of each.

Let S[r] represent all signal paths of interest for the network of FIG. 1.[0008]

Networks may be built from any one of a number of particular logic families, e.g., TTL (transistor-transistor logic), RTL (resistor-transistor logic), ECL (emitter-coupled logic), CMOS complementary-insulated gate and the like. Basic active elements, viz logic functions, such as NAND, NOR, AND, INVERT gates, pass transistors are generally interconnected to form the complex elements described above which in turn are interconnected to form still more complex elements.[0009]

Network Element Delay[0010]

Complex logic elements may be characterised to a first order by a plurality of input and output terminals, each having a respective logic threshold. The logic thresholds at input and output (the voltage level or current level at an input or output terminal which defines the transition between a logic one and zero) may be the same or different. A logic function of a complex element, i.e., the logical response at an output from a logic transition at one or more activating inputs, typically can also be characterised as having a time interval or propagation delay through the active element or function between a logic transition of an activating signal at an input and a logic transition of a responsive signal (if any) at an output. The propagation delay is the time interval between the logic transition of the input signal at an input terminal and a corresponding logic transition of a respective responsive signal at a corresponding output terminal. The propagation delay of a branch or element is the interval or span of time between an input signal transition (for digital circuits, a logic transition) originating at one terminal of an element or branch until the occupancy of a corresponding output signal transition (or edge) at another terminal (the output terminal) of the element or branch by the propagation of the effect of the input signal through the element or branch.[0011]

A multiple terminal active element may have a multiplicity of signal edge delay time delay intervals between a particular pair of terminals associated with different functions or state transitions. Typically the design of electrical network systems will take into account a worst-case delay interval for such terminal pairs.[0012]

Another important feature of high-speed digital networks is the topology of the physical network. There is generally little correspondence between the topology of the schematic or network graph and the topology of the actual physical layout of the circuit elements and interconnections. Frequently, in translating a complex circuit design from schematic to printed circuit board (PCB) layout, the physical length (and consequently the electrical length or delay time) of the conductor traces between different nodes (terminals) of logic elements (due to the excessive signal edge delays caused by the interconnect) impacts the performance of the system so significantly, that the layout must be redesigned. Redesigning the layout adds significant cost and schedule delays in the process of introducing a new product to the marketplace. There is no assurance that a re-layout will not introduce another critical delay limitation in the same or some other path.[0013]

The propagation delays of circuit elements themselves can also be problematic. Components made by different component manufacturers may have inherent propagation delay times between input and output terminals that have different probability distributions. Worst case design to cover different ranges of propagation delay tend to decrease performance for lower cost devices, or increase cost for higher performance (i.e., faster or tighter distribution) devices.[0014]

Some physical layout design tools are available from Computer Aided Design Tool services and manufacturers that are typically used to analyse the performance and timing of topological layouts for instances of limitations caused by the delay issues discussed above. Once a problem is identified, components may be relocated and a timing analysis run again. This layout-analysis step often can become a loop procedure repeated several times until the performance is satisfactory.[0015]

The propagation delays between input signal transitions and output signal transitions of logic elements and of the interconnect (branches) between nodes (terminals) is one very significant feature of high speed networks. A series connection of two or more branches forms a signal path having an associated cumulative signal propagation delay.[0016]

The cumulative propagation delay, t[0017]_d, of a signal path composed of a series of branches, 1≦k≦K, is sometimes approximated by computing

t_d=Σt_k,

the simple arithmetic sum of the propagation delays of the series branches, t[0018]_k.

Another useful approximation is the geometric sum of the individual branch propagation delays:[0019]

t_d={square root}{square root over (Σt_k)}.

Generally, the total branch delay intervals lie between these two approximations.[0020]

Practical Considerations to Signal Delays[0021]

For complex, high performance networks, such as computer motherboards and microprocessor chips the delay time delay interval of the interconnect (i.e., wires and PCB traces) can have a significant impact on the maximum speed of the network. Particularly as the operational cycle time of computer chips and boards increases to 300-400 and 500 MHz the length of half a clock period is decreased from 15 to 12.5 to 10 ns. Since the speed of an electrical signal on a PCB can be about 1.5 ns per foot, for an 18 inch PCB the time delay of a signal propagating along an interconnect line can amount to 10 to 15% or more of the time allocated to the to the computing circuits. This is an unacceptable penalty for performance. In some cases, a critical signal may be delayed sufficiently in one part of the physical layout that the network will not operate at the desired clock frequency. In such a situation it may be necessary to add an extra clock cycle or wait state to the system operation, to allow the lagging signal to be used in the next system cycle. The critical delays may be associated with clock signals or data signals or both.[0022]

A good discussion of the challenges presented for designing and building high speed digital systems is found in the March, 1998 issue of Computer Design magazine from pages 27 through 35. Clock and signal skew can be effected by a host of factors: manufacturing and component tolerances vary statistically around some mean value. Output loading of drivers and input loading of receiver can vary as well. Cross sectional tolerances of fine-pitch PCB can vary as well up to 5 to 10% or worse. Dielectric constant variation in the surface layer of a PCB or differences between layers can result in substantial differences in equal length signal lines routed on different layers[0023]

A motherboard designed to accept components from many different suppliers might force the design engineer to make undesirable worst-case assumptions about partitioning the clock and the allowable skew. At today's high clock (and signal) speeds, interconnect is just another component in the clock-signal chain.[0024]

Impedance matching and Schottky-diode clamping can improve rise-time and overshoot problems but do not contribute to a solution to the variability of signal/clock delay interval through the logic element-interconnect chain.[0025]

Some techniques for addressing the delay variability problem include careful layout of power and ground planes of a PCB; isolating all high-frequency components (processor, clock generator, chipset, etc.) by placing them over an isolated ground plane. Alternatively, a common ground plane can be used for the entire board, with two or three internal ground layers inside the PCB. Other techniques include high-speed differential drivers, specialised clock-distribution topologies (Star, point-to-point-routing, distributed low-frequency clock generators driving local PLL multipliers for local high-frequency clocks). Hand routing of clock traces before any other signals are placed is another good design practice. Other design practices limit the placement of clock generators, crossing of clock traces, and eliminate the use of sockets for clock generators. Almost all of these techniques require additional board space, increase component cost, and increase manpower required for design and verification of the layout.[0026]

Signal Delay Mismatch and Prior Art Solutions[0027]

With regard to FIG. 3, there is shown a schematic representation of a[0028]

clock line

10 in an electrical network, e.g., a PC motherboard. Theclock line10 has a node n0 connected to a clock generator CLK that produces aclock signal edge102 at node n0 that occurs at time instance t0. Theclock signal edge102 propagates from node n0 at one end of theclock line10 to anintermediate node202. Theclock line10 splits into two

branches

214 and215 with proximal ends joined atnode202 to distribute theclock signal102 to different parts of the circuit, e.g., spaced apartnode212 at a distal end ofclock conductor segment214 andnode216 at distal end ofclock conductor segment215. For the present discussion impedance matching is assumed but not shown. Theconductor214 is of length L1 fromnode202 tonode212. Theconductor215 is of length L2 betweennode202 andnode216. L2 is electrically shorter than L1. Theclock signal edge102 propagates fromproximal node202 to

distal nodes

212 and216. After travelling the length of L1 and L2,edge102 arrives atnode212 at time t2 asedge102band arrives atnode216 at time t3 asedge102a. Since L2 is electrically shorter than L1 t3−t0 is less than t2−t0.

The extra delay of[0029]

edge

102bover that of102a, i.e., t2−t3 (clock timing skew) can cause logic function errors in circuits connected to clock signals at

nodes

212 and216. If logic circuits (e.g. microprocessor, memory chips, not shown) connected to the two

nodes

212,216 are connected to input logic signal lines (not shown) that have logic levels changing near the edge time t0, they can latch incorrect output logic levels because of this timing skew.

Selectable Time Delay (STD) Circuit Elements[0030]

Inverter Chains; Reference Examples[0031]

Circuit elements having extra time delays may be inserted into the shorter electrical path L2 to bring the[0032]

signal edge

102ainto synchronism withedge102b. For example, a series chain of inverter pairs each having a small propagation delay, Δt, can be inserted into line L2 to add extra delay to a delayed edge of102a. Alternatively, a circuit element having a controllable delay time can be inserted. Examples of these are active hybrid delay lines and Silicon Timed Circuits (STCs) by Dallas Semiconductor, Dallas, Tex. The STCs are offered in the two basic architectural types of delay lines: a single input with multiple outputs (taps) with delay elements between each, and single input/single output delays, usually with multiple independent delays in a single package.

Both of these derive time delays from voltage ramps obtained from charging selectable members of a capacitor array with a constant current and detecting the time when the voltage ramp crosses some threshold. Different time delays may be selected by choosing one or more of the parameters, threshold voltage, ramp current and capacitor value.[0033]

Connection of the Time Delays into Selected Signal Paths Crosspoint Switches[0034]

Once a signal path needing additional signal delay is identified the path must be opened and the STD having the desired additional delay inserted. Methods of inserting additional circuits into other circuit paths are known. U.S. Pat. No. 5,400,262 by Mohsen, describes a “interconnect matrix array” (the '262 matrix) that allows any one of a set of input/output pads (or conductive lead end terminals) arranged in an area matrix to be connected to any other one of the set of pads (end terminals). Mohsen's array or crosspoint switch is comprised of a first set of conductive leads formed in a first direction, a second set of conductive leads formed in a second direction, the second direction being not parallel to the first, and programmable element structure for electrically interconnecting selected ones of the conductive leads in the first set to one or more of the conductive leads of the second set at respective crossing points. Selected ones of the conductive leads are segmented. Associated with each row and column of input/output pads/leads is a channel having one or more parallel conductive tracks each capable of being broken into segments. The '262 matrix provides great flexibility in interconnecting external circuit connections. However the '262 matrix has the disadvantage that for practical circuits, an equal number of multiple tracks are required for each desired input pad and output pad interconnection (i.e., terminal ends). This causes a rapid increase in the circuit area of the switch and the introduction of possible undesired signal noise coupling between different signals on closely adjacent tracks.[0035]

Other cross point matrix configurations are known, such as Reissue patent RE 35,483 ('483) by Harrand. In FIG. 3 of Harrand any output column m is connected to any input row n by a crosspoint switch element. Each column and row comprise two differential lines Oj[0036]1, Oj2 and Ii1, Ii2. The crosspoint switch element comprises the two drains of a differential amplifier M1, M2. M1 and M2 are differentially driven by separate drains of another differential pair M3, M4 whose gates are driven by the differential row inputs of row n. Two selection lines Sij and Sij* (the complement of Sij) enable the differential pair M3, M4.

The matrices of '262 and '483 both have the common disadvantage that selection lines (e.g., Sij and Sij*) that enable the connection of a row to a column must run across the full width and breadth of the matrix. The disadvantage arises from two factors: first, the size of the array must accommodate space for the signal rows and signal columns in addition to the space for the selection lines. For practical arrays, this means there must be space for twice the number of lines crossing the array in both X and Y directions.[0037]

Second, for very high-speed signals in such cross point switch matrices, there will be coupling between selection lines and signal lines when they are closely spaced. This can be seen with reference to the matrix shown in FIG. 2, that depicts a simplified schematic of a typical crosspoint matrix such as that of the '262 and '483 patents. Like many other prior art cross point switch matrices, matrix has crossing (e.g., X and Y axis) input and output signal lines running the full width and breadth of the array. Programmable elements a[0038]102(1n,m) connect the signal row lines Ri/o,[n] to signal columns lines Ci/0,[m] when enabled by suitable logic levels on the respective rowselect input104,n,mand columnselect input106,n,m.

Row[0039]

select lines

104,n and columnselect lines106,m provide the logic levels to the respective switch row and column select inputs and also run the full width and height of the array respectively. Again, the programming lines for selected rows rsel,n and for selected columns csel,m take up more array space, i.e., a larger array for a given number of interconnections to be made, and also are subject to noise coupling between closely adjacent programming lines and I/O signal lines.

It would be advantageous to combine a selectable delay circuit element with an interconnection element that could provide selectable propagation delay to selected circuit paths while minimising increased circuit area and minimising noise coupling between I/o signal lines and programming lines.[0040]

C. SUMMARY

Pulse Clock Distribution (PCD) System and Method.[0041]

The present invention provides a method and system for correction of unwanted delay mis-matches that exist or are introduced between respective clock signal and/or data signal edges in corresponding clock and/or signal paths.[0042]

Signal Path Transition Edge Delay Equalization.[0043]

The method and apparatus of the present invention provides for introduction of a series connection of a selected number of elemental signal edge transition delay units in series relationship with an electrical path propagating a selected clock signal or data signal of an electrical signal network. An edge transition equalisation system incorporating a signal transition edge delay controller that may be connected to a multiplicity of such signal edge delay units in selected branches of a pulsed signal network.[0044]

An embodiment of the present invention may be used as an apparatus for a novel method for inserting or interposing additional signal edge transition delays in one or more of selected signal branches.[0045]

Clock/Signal Pulse Edge Distribution and Control.[0046]

The present invention provides an apparatus and method for distributing clock/signal pulses with selected signal transition edge instances delayed by a selectable propagation delay from an initiating clock/signal pulse edge transition. Insertion of an embodiment of the programmable delay line of the present invention into one signal path (branch) of a multi-branch clock/signal line causes a first clock/signal edge at one node of the one branch to occur at an edge time instance (the edge time) simultaneously with the edge time instance of a second clock/signal edge from the same initiating clock/signal pulse edge but propagating on an electrically longer bifurcated branch portion of the same clock/signal line.[0047]

One feature of some embodiments of the present invention is a novel diagonal cross point (DCP) matrix used to connect the selected number of propagation delay line elements into the desired signal or clock line. The DCP provides isolation between the row/column select lines and the row/column signal lines in two ways. First, the row select and column select lines for any selection switch of a linear array of select switches are disposed on one side of the linear array and the row signal lines and column signal lines are disposed on the opposite side of the array. Secondly, each selection switch of the array provides isolation between the proximal end of the select lines and the proximal end of the signal lines.[0048]

DESCRIPTION OF DRAWINGS

FIG. 1 is an illustration of electrical network nodes and branches.[0049]

FIG. 2 shows typical prior art cross point switch architecture.[0050]

FIG. 3, depicts a schematic representation of a[0051]

clock line

10 in an electrical network with different electrical length (delay) clock branches between two network nodes.

FIG. 4, shows a modification in the clock line circuitry of FIG. 3 incorporating an[0052]

embodiment

208 of the PCD of the present invention.

FIG. 5 depicts a simplified schematic representation of FIG. 3.[0053]

FIG. 6 illustrates a block diagram of a larger network with a portion of the[0054]

clock line

10 of FIG. 4 modified to include an embodiment of thePCD system208 of the present invention shown as.

FIG. 7 indicates the relative timing of a delayed clock edges at different nodes on[0055]

clock line

10 of FIG. 5.

FIG. 8 exhibits an alternate embodiment of the output select logic for the[0056]

PCD

208 shown in FIG. 6.

FIG. 9 presents a more detailed schematic representation of a[0057]

novel embodiment

400 of the cross pointselect matrix250.

FIG. 10 shows an ECL embodiment of the[0058]

delay block

260.

FIG. 11 illustrates an alternative ECL delay block including level shifters.[0059]

FIG. 12 depicts a CMOS embodiment of the[0060]

delay block

260.

FIG. 13 illustrates a PCB with timing mismatches of the[0061]

layout

700 modified by the addition of PCD devices in accordance with this invention.

FIG. 14 depicts one option for inserting the PCDs of FIG. 13 into the[0062]

PCB layout

700.

DETAILED DESCRIPTION OF THE INVENTION

The Pulse Clock Distribution apparatus of this invention will be described in conjunction with several embodiments. Other embodiments will be apparent to those skilled in the art in view of the following description. The following descriptions are meant to be illustrative only and not limiting.[0063]

A Single Edge Delay Generation Embodiment of the PCD.[0064]

With reference to FIG. 3 and FIG. 4 an[0065]

embodiment

208 of the present invention modifies the structure of theclock line10 in FIG. 3 to that of theclock line100 of FIG. 4. Theclock line100 is modified byPCD208 to equalise the edge delay at separated circuit nodes receiving a pulse edge from a common source. Theshorter conductor215 of FIG. 3 is divided at an intermediate node n1 into two electrically isolated

conductors

215aand215b. The

conductors

215aand215bare separated at node n1 just enough to define immediately adjacent, electrically isolated nodes n1aand n1b. Nodes n1aand n1bare respectively connected to input and output nodes xin and Xout of an embodiment ofPCD device208 of the present invention. Node n1aand n1bonly need to be separated sufficiently to electrically isolate

conductors

215aand215bwithout significantly changing the length L2.

The[0066]

PCD device

208 is an electrically programmable delay generator comprised of a plurality, Nd, of delay elements209[j] each having a respective input and output with a respective increment of propagation delay, Δt, there between. The plurality of delay elements209[j] are connected in series between xin and Xout. A first one of the delay elements209[j] has its input connected to xin, and a last one of the elements209[Nd] has its output connected to Xout. Each element209[j] except the first and last has its respective input and output connected to the corresponding preceding and following element209[j−1] and209[j+1].

The[0067]

clock signal

102 propagates from node n0 to node n1aalongclock line100 andsegment215aand appears on xin as a delayedinput signal edge102′ at time txin. Thesignal edge102′ is received by theinput262 of the first element209[l]. Each delay element209[j] adds an increment of propagation delay, Δt, to the delayedinput clock signal102′ propagating from the first element209[l] in series to the last element209[Nd]. The last element209[Nd] outputs a further delayedclock signal102″ at Xout that is delayed by the sum of the Δt's of the Nd elements209[j]. The number Nd of elements209[j] is arranged so that sum of the Δt's, ΣΔt, for the Nd elements209[j] adds to the delay of thesignal102′ to produce a final delayed clock signal102a′ which appears atnode216 in synchronism with theclock edge102batnode212 within one Δt; i.e., ΣΔt=t2−t3+/−Δt.

The selection and connection of the Nd delay elements[0068]209[j] is carried out by co-operating switch connection control circuits (not shown) in thePCD208. The switch connection control circuits in208 may be of the conventional selector and multiplexor types known in the art or may be as described by the '262 and '483 patents, e.g., variations of the cross point matrix shown therein. For example, a cross point switch may be used to connect the output of the Ndth element of a series of Nmax elements to the output Xout, where Nmax>Nd.

A preferred embodiment of the present invention includes a[0069]

controller

205 with acontrol program207 combined to providecontrol signals203 to controlinput201 of thePCD208 that selects and connects at least Nd out of Nmax delay elements209[j] to produce the desired delay.

Referring to the timing diagram of FIG. 4, the[0070]

signals

201 on timedelay control input203 in combination with the switch connection control circuits (not shown) causes thePCD208 to insert a desired propagation delay, tdel, between the instance, txin, of the delayedclock pulse102 received at xin and a corresponding instance, txout, of a further delayed outputpulse clock edge102″ at Xout at the node nib. One method of the generation ofcontrol signal201 and the method of selecting tdel is described generally below. The value of tdel is selected so that the instance t3′ of the delayedclock signal edge102aatnode216 is delayed equally (within one Δt) with that ofsignal edge102batnode212; therefore t3+tdel=t3′=t2+/−Δt.

Embodiments of the[0071]

PCD

208 invention of FIG. 4 are preferably implemented by tapping from a selected one of an intermediate stage of a long series chain of incremental delay elements as described. Alternatively, prior art programmable delay devices such as hybrid delay lines known in the art or programmable delay devices such as the SCTs by Dallas Semiconductor may be used as the delay elements209[j]. The connection of a Ndth output of a series of Nmax elements may be implemented by conventional selector/multiplexor circuits, with a prior art cross point switch as shown in the '262 patent or the '483 reissue, or with a novel diagonal cross point (DCP), described below, that is a feature of embodiments of the present invention.

Detailed Functional Block Diagram of One Single Edge Delay Embodiment of the PCD[0072]

Referring to FIGS. 4, 6 and FIG. 7, the[0073]

clock line

10 of the digital network in FIG. 3 is modified toclock line100 of FIG. 4.Clock line100 includes an embodiment of thePCD system208 of the present invention shown in a more detailed block diagram.

Referring to FIG. 6, and the timing diagram of FIG. 4, there is shown a more detailed block diagram of an embodiment of the[0074]

PCD

208 included in a portion of theclock line100 for adigital controller network200.

The[0075]

clock line

100 is driven at thefirst clock node202 by a clock source204 (CLK). The first clock line (branch)215a,215bof length L2 connects theclock node202 to a nearby first portion of thenetwork200, e.g., a counter registerinput clock node216. The (electrically) longer second clock line (branch)214 of length L1 also connectsclock node202 to another more remote portion of thenetwork200, e.g., a spaced apart address registerinput clock node212. L1 is considerably longer (electrically) than L2.

FIG. 7 shows the relative timing of the fast rising[0076]

clock edge

102 atinput node202 originating at time instance t0. Theclock edge102 divides atnode202 and propagates along the bifurcated

clock line branches

215a,215band214 and arrives as a first delayedclock edge102aand seconddelayed edge102bat

nodes

216 and212 respectively. The first delayedclock edge102aarrives at delay instance t1 fromedge102, and the second delayedclock edge102barrives at second delay instance t2 fromedge102 due to the longer branch length L1.

The[0077]

clock branch

215 of FIG. 3 is electrically separated at node n1 into two electrically separate nodes, n1aand n1bconnected respectively to an input node xin and a delayed output node Xout, leaving the line lengths L1 and L2 essentially the same as before. Node Xin and node Xout are connected to thePCD208. ThePCD208 receives theclock edge102′ at the input node Xin and outputs a delayedclock signal edge102″ at the delayed output node Xout. With regard to FIGS. 6 and 7, thePCD208 adds additional propagation delay tdel to theclock edge102a.

Propagation delay tdel consists of two portions: the selectable delay ΣΔt and excess delay, txs, contributed by supporting circuitry within the[0078]

PCD

208. Txs represents fixed propagation delays (the sum of parasitic delays) within thePCD208 caused by the physical structure of any particular embodiment ofPCD208, not contributed by the selectable delay elements209[j]. As such, Txs allows the delay characteristics of thePCD208 to be represented as an assembly of ideal, i.e., zero delay components in series with the selectable delay ΣΔt and the hypothetical excess delay, Txs.

[0079]

PCD

208 generates delay tdel between xin and Xout to produce an intermediate delayedclock edge102″ at Xout. The intermediate delayedclock edge102″ is arranged to cause the further delayedclock edge102a′ (edge102′ delayed by tdel) to arrive at theregister node216 coincident with the arrival of theclock edge102batregister node212. The selection and connection structure and method of adjustment of the delay interval tdel, for theembodiment208 of the present invention is described in detail below.

PCD Functional Blocks[0080]

The[0081]

PCD

208 includes a seriesdelay unit block260, row access select/column access select (RAS/CAS)decode block226, atiming control block220, a RAS/CASaddress decode block226, an outputaddress decode block228, a diagonal cross pointselect matrix250, and an outputselect logic block252.

Series Delay Block[0082]

The[0083]

series delay block

260 has adelay block input262 connected to the node Xin that receives the delayedclock edge102′. Theseries delay block260 includes a series string of Nmax spaced apart delay units209[j], where j is an integer, 1<j<Nmax. A first delay unit209[l], has a first delay unit input211[l] connected to theinput262 and a first delay output213[l]. Each successive delay unit209[j],2<j<Nmax has a corresponding delay input211[j] and delay output213[j]. Each delay unit,209[j], is characterised by an incremental delay Δt between an input logic transition Xin[j] at its input211[j] and an output logic transition Xout[j] at its output213[j]. Each delay unit209[j] has its output213[j] connected to the input211[j+1] of the next delay unit209[j+1]. The time delay between a logic transition Xin[j] at the first input211[i] and an output transition Xout[j] at the jth output213[j] is j*Δt. A delayed clock edge Xout[j] therefore appears at each output213[j] with a delay of j*Δt from the initiatingclock edge102′ at node xin. Adjacent delay units209[j] are spaced closely enough so any time delay between an output213[j] and a following input211[j+1] is negligible compared to Δt.

The delay units[0084]209[j] may be selected from standard hybrid delay lines, commercial delay devices such as a family of STC delay devices of Dallas Semiconductor, or specific delay units described further below.

Timing Delay Control Block[0085]

The timing[0086]

delay control block

220 has atiming control input201.Input201 receives timing control input signals203 from a system control function205 (e.g., a hard wired logic circuit, micro programmed controller or microprocessor operating apredefined control program207 stored on ROM, RAM, disk or similar storage device) for controlling the relative timing of the clock edges102band102a′ at

nodes

216 and212.

Control block[0087]220 is a conventional combinatorial conversion logic block that converts timing control commands203 from thesystem control function205 and outputs suitable timing delay address signals222 onaddress bus224. The logic for converting control commands203 to address signals222 will typically be specified by a manufacturer of an embodiment of aPCD device208 or by a user of a programmable embodiment of the PCD device to provide a user with a limited set ofcommands203 to be used to generated the storedprogram207. The specification and design of timing delay control block conversion logic is within the capability of an ordinary practitioner of logic and circuit design and is not part of the present invention.

205

205 interprets stored program commands (not shown) from theprogram store207 according to the specific network requirements and provides necessary control signals203 to input201 of thetiming control block220. The design of suitable conversion logic structures for thecontrol logic block205 depends partially on the requirements of a particular digital system implementation, which incorporates thePCD208 of the present invention. The specification and design of such logic conversion structures depends on the specific requirements for aparticular network200. Such specification and design is within the capabilities of a knowledgeable practitioner of system and digital logic design and is not part of the present invention.Function205 typically will be supplied by a system designer who wishes to implement specific corrective and/or system compensation delay functions by using the PCD of the present invention as part of thenetwork200.

RAS/CAS Decode and Output Address Decode[0090]

RAS/[0091]

CAS decode block

226 decodes the address signals222[r,c] (1≦r≦R and 1≦c≦C) and drives decoded matrixselect lines240. Matrixselect lines240 include RAS delay select signals xr[m], 1≦m≦M, and CAS delay select signals yc[n], 1≦n≦N. In the single output delay embodiment of FIG. 6, the RAS/CAS address signals222[r,c] are mapped so that M=N and each one of the [r,c] bit combinations produce a single logic one on a specific one of the RAS select signals xr[m] and a specific one of the CAS select signals yc[n]. Similarly,output address block228 decodes the output address signals222[o] 1≦o≧0 and produces decoded output select signals242. The decoded outputselect signals242 connect to outputselect logic block252.

The RAS/[0092]

CAS decode block

226 is typically a conventional combinatorial logic function for selecting specific xr[m] and yc[n] lines from the address signals222[r,c] in order to enable a specific switch sx[j]. Again, the specification and design of such conventional logic is not part of this invention and can be done by a person having ordinary skill in the art.

Cross Point Select Matrix Switch[0093]

The cross point[0094]

select matrix

250 includes Nmax independently selectable switches, sx[j]. 1≦j≦Nmax. Each switch, sx[j], separately receives a corresponding one of delayed matrix outputs signals211[j] from thedelay block260. Each one of the plurality of delayed output signals211[j] are individually connected to a corresponding input xin[j] of the respective switch sx[j]. Each switch sx[j] has a switch output xout[j] connected separately to the outputselect logic block252. Each of the logically selectable switches, sx[j], connects (on when selected) or disconnects (off when deselected) the corresponding output xout[j] to the respective input xin[j] allowing the selected delayed clock/signal211[j] (i.e., theedge102′ delayed by +j*Δt) to pass there through.

To select a particular delay, Nd*Δt, the Ndth one of the logically selectable switches sx[j] is selected (on) by the corresponding one unique combination of logic true levels on the RAS/CAS select lines. A particular switch sx[j] is selected by a logic one (I) on the particular corresponding one of the RAS delay select lines, xr[m], 1<m<M, and a logic one (1) on the particular corresponding one of CAS select line, yc[n]. 1<n<N, where M and N are integers.[0095]

The mapping from n,m to j is fixed for the single edge[0096]

delay embodiment PCD

208.

Each selected (on) switch xout[j] therefore separately connects the corresponding delayed signal (edge)[0097]211[j] (i.e., xin delayed by the corresponding delay j*Δt) to the outputselect block252. A unique one of the switch outputs xout[j] is selected by appropriate address pair xr[m], yc[n] from theaddress bus240 from the RAS/CAS address decode226. Thesystem controller205 is programmed to output the necessary address pair xr[m], yc[n] to select the correct switch xout[j] according to thecontrol program207 and the desired value of tdel.

In the[0098]

embodiment

208 of a single time delay selection, m=[, and M=N=Nmax, and thedecode226 is arranged to select only one row (xr[m]) line and one column (yc[n]) at a time. A delayed clock/signal output line254 from outputselect logic block252 connects the selected signal to the output Xout through the fixed (hypothetical) delay txs.

For the purpose of this discussion, the time delay from the input xin to the first input[0099]211[l] and the time delay from the output213[Nd] to Xout will be assumed to be small compared with the delay intervals of interest. It can be shown that small excess time delays caused by finite conductor lengths and parasitic reactive loads (inductive and capacitive loading) between physically separated nodes of thedelay block260, theselect matrix250, the outputselect logic252, the input nodes xin,node262 andoutput nodes254, Xout can be compensated by selection of a suitable number of delay units209[j].

In addition, any excess time delays caused by the non-ideal physical traces and parasitic reactive loads in the[0100]

PCD

208 are accounted for by lumping the excess delays into the effective fixed delay, txs in series with the selectable delay EΔt=Nd*Δt.

More General Embodiments of the PCD of the Present Invention[0101]

FIG. 6 has shown a specific embodiment of a single edge delay control and compensation system. A large body of alternative embodiments of PCDs in accordance with the present invention will be apparent to a person having ordinary skill in the digital system design art. For example, multiple sets of PCDs may be placed on one network to compensate more than one pair of discrepant signal path delays S[0102]1 and S2. Other alternatives in accordance with the present invention include PCDs capable of selecting and connecting more than one single delayed edge derived from one originatingedge102 as shown with regard to FIG. 6.

Multiple delayed edges[0103]102 (time0+n*Δt) that occur at different delays n*Δt from an originatingedge102 at time0 can be combined and inserted onto the

signal path

215a,215bby merely changing thecontrol program207 and the address logic of

blocks

220,226 and228 into a signal path.

For an example of a more general case, more than one output switch sx[j] with a single address[0104]222[r,c] may be selected by changing the mapping of the signals222[r,c] to the select lines xr[m] and yc[n] such that theaddress decode226 enables more than a single switch sx[j] for each address222[r,c]. A subset of switches E sx[j] may then be selected by a single address222[r,c] to connect a corresponding subset of delayed signals E xout[j] to the outputselect logic252 and the output address decode228 logic may be easily arranged to connect each of the subset E xout[j] to the Xout line.

Output Address Decode and Selection[0105]

The output[0106]

select logic block

252 receives the subset of selected signal (edges) E210[j] through the selected set of switch outputs Exout[j]. For a single time-delay-generator embodiment208 of the present invention, two possibilities exist:

A) First, appropriate logic functions (not shown) for the[0107]

select logic block

252, the outputaddress decode block228, thecontrol logic220 and thesystem function205 may be chosen by a knowledgeable logic design practitioner so that thesystem function205 will cause the output select logic to select a single required switch xout[j], for connecting the desired single one of the delayed outputs211jto be routed to the delayedoutput262 by choosing to appropriately drive only the corresponding one of the switches sx[j] to which it is connected from among the whole set of delayed outputs, Nmax. One knowledgeable in the art may select any one of a number of known logic functions.

B) With reference to FIG. 8, an alternate embodiment of the single time delay generation may be implemented by replacing the output[0108]

select logic block

252 with a wired ANDconnection252″ of the outputs xout. In this case the RAS/CAS addresses are limited to those which only select a single one of the outputs xout at a time. This can be implemented in thecontrol program207 of the digital system incorporating thePCD208.

Diagonal Cross Point Select Matrix[0109]

With reference to FIG. 9, there is shown a more detailed schematic representation of a novel diagonal cross point (DCP)[0110]

matrix

400 performing the function of the cross pointselect matrix250.

The[0111]

cross point

400 includes; a) M parallel and spaced apart row select input lines402[m] each connected separately at an outer peripheral end to a corresponding one of the RAS select lines xr[m] of the matrixselect bus240; b) N parallel and spaced apart column select input lines404[n] each connected separately at an outer peripheral end to a corresponding one of the N CAS select lines yc[n] of the matrixselect bus240. The M row lines402[m] are not parallel to the N column lines404[n] and are directed proximally away from the respective outer peripheral ends toward one side of a diagonal500 disposed from opposite corners C1, C3 of theDCP400.

The[0112]

DCP

400 also includes; c) Nmax parallel and spaced apart column delay signal input lines406[j], each separately connected at a respective outer peripheral end to a corresponding one of the delayed signal outputs213[j] from theseries delay block260; and d) Nmax parallel and spaced apart row switch outputs lines are each separately connected at a respective outer peripheral end to the corresponding matrix output xout[j] of the cross pointselect matrix250; and e) where M=N=Nmax. The column lines406[j] are not parallel to the row switch output lines and are both directed proximally from the respective outer peripheral ends toward the opposite side of the diagonal500.

The row select input lines[0113]402[j] and row switch outputs409[j] may be aligned or be offset from each other. The column input signal406[j] and column select input lines404[j] may also be aligned or be offset from each other.

An array of the switches sx[j], 1<j<Nmax, is disposed generally along the diagonal[0114]500 across theDCP400. Each switch sx[j] is disposed at each intersection of row select lines402[m=j] and column select lines404[n=j]; i.e., only at the intersections where j=m=n. Each switch sx[j] includes a two input AND gate410[j]. One input of each AND gate410[j] is connected to the corresponding row select line402[j] and the other input is connected to the corresponding column select line404[j]. AND gate410[j] drives a base input412[j] of an adjacent NPN transistor switch414[j] that has its collector416[j] connected to an opposite proximal end of the corresponding column delay signal input line406[j] and its emitter418[j] connected to the corresponding opposite proximal end of the row switch output409[j].

A logic “1’ is required in both the AND gate row select inputs[0115]402[j=Nd] and the AND gate column select inputs404j=Nd] to form an electrical connection between a column input signal line406[j=Nd] and row output signal line409[j=Nd] whereby the particular delayed clock/data signal102′+Nd*Δt may pass therethrough. It is apparent that the CAS column address select signals404[n] (from yc[n]) and RAS row address select signals402[m] (from xr[m]) are spatially well separated from the delayed input clock signals406[j] (from xout[j]) and switched delayed output signals xout[j] except for their end-to-end proximity near the AND inputs406[j] and409[j] along the diagonal500.

This spatial separation tends to minimise coupling between the switch logic selection signals and the critical delayed signal edges thereby tending to improve isolation between control and signal data.[0116]

The selection of the NPN transistor[0117]414[j] is applicable to one embodiment of the invention. An N-channel FET could also be used Alternatively a PNP transistor or P-channel FET could be used with inverted logic levels.

In an alternative embodiment of the invention, a programmable fixed connection such as an EEPROM programmable FET can replace the active transistor[0118]414[j]. Once a desired delay j*tdel is selected, thematrix400 could have a selected transistor location m,n=j burned in to establish a fixed delay. Other programmable matrix selection methods are also applicable, such as arrays of metal fuses or anti-fuses as are known in the art.

ECL Implementation of the Series Delay Block[0119]

Referring now to FIG. 10 there is shown a schematic of one preferred embodiment of a Emitter Coupled[0120]

logic implementation

550 for theseries delay block260 in thePCD208 of FIG. 6. Theblock260 is composed of a series connection of ECL cells551[j]1≦j≦Nmax. Each cell551[j] includes two

NPN transistors

554 and556 with

collectors

558,560 joined to a +VCC bus.

Separate emitters

562 and564 form the outputs of each cell551[j].Emitter562 is connected to a −VEE bus through a resistors of value R1 to provide the proper bias to thetransistor554.Emitter564 is also connected to the −VEE bus by a resistor of value R1.

Independent bases

566 and568 of

transistors

554 and556 are respective inputs of each cell551[j].

A first stage,[0121]551[l], hasbase connection568 oftransistor556 driven by an output of aninverter570. Thetransistor554 of551[l] hasbase connection566 driven by an output of abuffer572. Bothinverter570 and buffer572 are driven by thedelay block input262 of FIG. 6. The emitter outputs562 and564 are therefore logically complementary. The emitter outputs562 and564 are separately connected to

respective base inputs

566 and568 of a second delay stage551[2] replicating the cell551[l]. Successive series replicates551[j] of the cell551[l] connect

output emitters

562,564 of cell551[j] to input

bases

566,568 of cell551[j+1] and are chained together to form the delay block of length Nmax.

Each stage,[0122]551[j], of thedelay block550 has one of thetransistor emitters562 of each stage connected to the cross pointselect matrix250 of FIG. 6 as the corresponding delayed clock signal213[j]. Each stage,551[j], adds its own characteristic time delay, Δt, to the delay of the input signal to that stage,213[j−1]. The total delay from theinput262 to output213[Nd of the Nd-th cell again is Nd*Δt (not including excess delay if any, through thebuffer572 and inverter570).

In other embodiments of the present invention, the[0123]

complementary emitter output

564 of each stage, j, may be connected to external circuitry (not shown) as a complementary delayed output having essentially the same delay j*Δt as the output213[j].

The[0124]

inverter

570 andcomplementary buffer572 in combination with the dual transistor cells551[j] provide a balanced power supply current drain behaviour for the network to which the delay line of FIG. 10 is connected. When one transistor e.g.,556, of the cell551[j] is conducting heavily, the other transistor,554, of the cell is conducting less, thereby balancing the total current drain on the VEE and VCC power buses.

One half of the cell[0125]551[j] (e.g.,transistor556 and associated resistor R1) may be omitted in cases where current balance is unimportant. The cells551[j] may be formed by conventional photolithographic processes on a single integrated circuit, or may be individual devices wired together on a printed circuit board.

ECL Delay Stage Coupling by Level Shifting[0126]

Referring to FIG. 11 there is shown an example 580 of the ECL delay line of FIG. 10 in which the length of the delay line (i.e., the number of delay cells, Nmax) is extended by including level shifting circuitry. The[0127]

ECL delay line

580 is comprised of a firstdelay line stage550 as shown in FIG. 10 and a seconddelay line stage553. The first delay line comprises series cells551[j] with a first cell driven by thebuffer572 and complementinginverter570. Each cell551[j] has its output213[j] driving an input of an ECLlevel converter circuit582. Eachcircuit582 has its output231[j] providing the signal at213[j] with the ECL level restored. ECL level restoring circuits are found for example in U.S. Pat. No. 4,435,654 by Koide; U.S. Pat. No. 4,978,871 by Jordan and U.S. Pat. No. 5,237,220 by Kurashima.

The last cell[0128]551[j] ofdelay line stage550 also has its restored level output213[j] driving the input of thenext stage553. ECL delay lines for the PCD of any desired number of delay cell551[j] can be built by concatenating thestages553.

CMOS Implementation of Series Delay Block[0129]

Referring to FIG. 12, there is shown a CMOS implementation of the series delay block[0130]260 of FIG. 6 in which the cells551[j] are implemented with CMOS inverters in place of the transistor-resistor combination of FIG. 10 and the

inverters

570,572 are omitted.

It is apparent that the delay element type in the[0131]

delay line block

250 may be of a different technology than the element type in the other blocks, e.g., the address decode blocks226,228 andselect matrix250 or outputselect logic block252.

It is contemplated that the[0132]

delay line block

250 may be a high-speed technology such as ECL, and the other blocks be CMOS for example. In addition, the element type of the network to which the PCD may be connected may also be of a different type. For example, the network that connects to

nodes

216,212 may be a PC motherboard or other printed circuit board. Alternatively, the network may be an integrated circuit or hybrid circuit with thePCD208 connected thereto.

In order to obtain high resolution in adjusting time delays, it is an advantage to have delay elements[0133]209[j] made from the highest speed (i.e., shortest Δt) technology available; for example, in ECL technology or in High Electron Mobility transistor (HEMT) technology. For a fixed base clock pulse width, a faster delay element209[J] consequently requires Nmax be proportionately increased to cover all possible divisions (multiplications) of the base clock pulse width (frequency).

Networks with Multiple PCDs.[0134]

With regard to FIG. 13, there is shown a[0135]

network

700. Thenetwork700 includes a plurality of associated pairs of digital pulse signal paths S1[p] and S2[p] of different electrical lengths (delay) Δt1[p] and Δt2[p] where Δt2[p]>Δt1[p] from one common end connected to associated digital pulse signal sources704[p] to respective distal ends. Other signal paths S[r] not having critical timing relationships are not shown.

Where it is desired that the electrically shorter path S[0136]2[p] have the same or nearly the same delay as S1[p] from the common ends of S1[p] and S2[p] to the respective distal ends, the shorter signal paths S2[p] are provided with a respective PCD702[p] connected in series at insertion nodes705[p] therein as indicated by the dashed lines.

Referring to FIG. 14, insertion nodes[0137]705[p] include two electrically isolated adjacent lands710[p] and711[p] joined by a removable conductive link712[p]. Each PCD702[p] is connected to acentral control bus706.Central control bus706 is connected to programming means714. Programming means714 communicates to all the PCDs to set up delays Δtp[p] determined for each PCD[p] that cause the combination of the path S1[p] and PCD702[p] to match delays Δt2[p] of associated signal paths S2[p] within the precision of the PCD delay element Δt, i.e., Δtp[p]+Δt1p]=Δt2[p]+/−Δt. The removable link712[p] may be removed by physically cutting after a PC board is fabricated and measured, or may be part of the photolithography-etching process during manufacture.

Alternatively, the delays Δt2[p]>Δt1[p] may be measured on an[0138]

actual circuit board

700, and individual PCD circuits having delays Δtp[p] determined and programmed externally may be installed in pre-assigned lands710[p].

PCD Design Tool Embodiment[0139]

A PCD circuit layout and timing design tool (CLDT) and PCD network design process in accordance with an embodiment of the present invention are indicated by the[0140]

numerals

750 and751 respectively. TheCLDT750, e.g., a CAD system, includes acomputing resource752, (such as a SUN™ computer workstation, a high end Pentium™ PC or a mainframe computer), an on-linedisc storage system754, an integrated circuit design program and tool set756, and adisplay757 presenting a graphicaluser interface GUI758 coordinating thecomputing resource752, thestorage system754 and the design program756 with circuit design and verification data base I/O759 (e.g., document entry from magnetic tape and/or keyboard and manual net list) by means ofinternal bus755.

Referring again to FIGS. 4, 5,[0141]6 and FIG. 13, the CAD program756 must include the following prior art capability: 1) convert a predefined net list (circuit element and terminal name lists, terminal-to-terminal connection list) and predefined physical layout of circuit element terminals into an interconnected physical PCB layout for the technology of interest. 2) perform timing analysis of all signal paths, S[r], on thePCB700 with a verification portion (not shown) ofdesign database759. 3) identify all critical pairs S1[p] and S2[p] of signal paths S[r] that have a common pulse source (204) and a critical timing difference tdel=t2−t3 as do

paths

214 and215. CAD programs of this type are available in the marketplace and more will be developed in the future.

The PCD[0142]

network design process

751 of the present invention is represented as a two headed arrow to indicate the iterative relationship between the circuitdesign data base759, the PCD cells702[p] and thePCD network layout700. A particular implementation of the PCDnetwork design process750 is represented by theprocess symbol751asignifying the portion of the CAD program756 which controls the configuration of the PCD cells702[p].

Referring to Table 1, there are shown the pertinent steps of a PCD network layout process.[0143]751ain accordance with the present invention after the preparation of the circuit design database759 (not a part of this invention). Represent thecircuit design database759 prior to physical layout as the set of all pertinent signal paths S[r]. S[r] by itself has inadequate indicators for signal path electrical length (i.e., delay time from a proximal circuit node or terminal to a distal circuit node or terminal) since a physical signal path length L[r] is not determined until layout is completed.

Therefore a timing analysis of the circuit S[r] would be useless for computing possible delay time compensation since paths S[0144]1[p] and S2[p] which have critical timing relationships are not created until the layout is complete. No compensation for the influence of physical and thus electrical path length delt[L[r]] and circuit element delays can be performed until at least one circuit layout pass is complete and the relative timing of signals computed by the timing analysis routine of the CAD program756. It is only after at least onephysical layout700 is complete that the CAD program timing analysis will include signal paths S1[p], S2[p] that will be found to have critical timing relationships.

TABLE 1


		go to	on	else
step	description	step	condition	go to

10	input circuit data base,	20	done	10
	S[r]) (from design input.)
20	perform physical layout	30	done	20
	of S[r] including a
	predetermined plurality,
	P, of PCDs with Nd[p] =
	0 distributed throughout
	thelayout 700 at corre-
	sponding insertion points
	705[p]. (from existing cell
	libraries and CAD programs),
	according to an a priori
	decision rule (Rule[P])
30	perform timing analysis	40	done	30
	usingverification database
	759 and identify node pairs
	S1[p] and S2[p]. (From
	existing CAD programs)
40	Assign corrective Nd(p)	50	done	40
	for each pair of discrepant
	signal paths S1[p],
	S2[p] having common
	signal source.
50	install (or place) PCDs	60	done	50
	with assigned Nd[p]'s at
	each insertion point 705[p].
60	End

The[0145]

DLT

750 is used by a knowledgeable person, i.e., a trained IC design engineer, or trained technician to layout printed circuit boards (PCBs) or integrated circuits (ICs) from a circuit design input source760 (e.g., a net list or the like).

The CDLT is provided with a plurality of PCD cells[0146]702[p] that are placed in the circuit layout (network)700, each PCD having a predetermined maximum number of delay elements, Nmax[p]. The delay values Δt1[p] for each PCD[p] may be set to zero initially, e.g., Nd[p]=0.

A[0147]

design process

751 in accordance with the present invention is indicated by the accompanying table 1.Process751 may proceed with the design tool operator using thedesign tool750 to lay out thephysical topology700 of a plurality of circuit paths S1[p], typically from anet list760. The circuit paths S1[p] typically include path circuit elements (not shown) such as combinatorial logic, chip memory elements, micro controllers and the like with

known or specified delays between respective inputs and outputs.[0148]

The[0149]

design tool

750 is programmed (by currently known means) to compute the cumulative delays Δt1[p], Δt2[p] for each path S1[p], S2[p] from known characteristics of the signal path circuit elements. Thedesign tool750 then computes the associated path delays S1[p] according to the timing analysis portion of the design program756

A plurality of PCDs[0150]702[p] and PCD insertion points705[p] are placed according to a suitable a priori decision rule (R[P]) which may be developed by knowledgeable design persons according to the needs of a particular technology. For example, a simple decision rule is to place PCDs on a grid disposed across the area of a proposedPCB700 with a fraction, say 5%, of the PCB area allocated to potential PCDs and insertion points705[p].

The advantage of this[0151]

design process

751 is primarily in that the layout of the circuit netlist S[r] is only done once and any signal path delay discrepancies for signal paths S1[p], S2[p] can be corrected by simply inserting the selected PCD circuits in thePCB layout700. Thus a single corrective step provided by thedesign process751 can reduce layout iterations.

Another alternative of the[0152]

process

751 applies to PCBs already completed in final form, with discrepancies in signal path delays for pairs of paths S1[p], S2[p]. Programmable PCD components702[p] having the structure of thePCD208 in FIG. 6 may be programmed with anexternal control205 to provide a compensating delay Nd*Δt for a signal path S1[p] of a completedPCB700. The programmed PCD702[p] can then be inserted in the discrepant path S1[p] by known means for breaking a signal path on a PCB and inserting a component therein.

PCD Architecture Partition Options.[0153]

Single Package.[0154]

The[0155]

entire PCD

208 may be fabricated as a single component for insertion into a printed circuit board, by packaging thePCD208 in a conventional IC package and presenting the two nodes xin and Xout andconnection203 as device pins for soldering or socketing to receiving holes or lands provided on such a board. A propagation delay difference, tdel, between the two

nodes

212 and216 may then be eliminated by programming thePCD208 with a sufficient number of delay stages, Nd, to off set tdel, e.g., selecting Nd to be a number large enough to make □Nd*Δ−tdel□smaller than Δt.

Programming the PCD.[0156]

Embodiments of the[0157]

PCD

208 may be programmed by an external programming device (not shown) in the manner described with regard to FIG. 13. External programming devices are well known in the art and are generally easily programmed by persons knowledgeable in that art.

Embodiments of the PCD in accordance with this invention include the[0158]

PCD

208 and incorporate thecontroller205 andcontrol program207 therein. The addition of a timing delay self test capability to a PCD give rise to another class of PCD devices that are auto-compensating after measuring the discrepant tdel between two S1[p], S2[p] nodes. Alternatively, the desired tdel, may be selected by measuring the undesired delay, tdel, between two S1[p] and S2[p] nodes such as212 and216.

It is apparent that a plurality of pairs of clock/signal line-node pairs having associated pairs of clock or signal edges with undesired delay differences there between may exist in any one network. It is also apparent that duplicates of the apparatus and method of the present invention may be used in the manner described herein for compensation of such a plurality of delay differences.[0159]