US20040135157A1 - Combined semiconductor apparatus with semiconductor thin film - Google Patents

Abstract

A combined semiconductor apparatus includes a semiconductor substrate having an integrated circuit, a planarized region formed in a surface of the semiconductor substrate, and a semiconductor thin film including at least one semiconductor device and bonded on the planarized region. A surface of the semiconductor thin film, in which the semiconductor device is formed, is disposed on a side of the planarized region. The apparatus may further include a planarized film disposed between the planarized region and the semiconductor thin film.

Description

BACKGROUND OF THE INVENTION
• 1. Field of the Invention[0001]
• The present invention relates to a combined semiconductor apparatus useful in, for example, a light-emitting diode (LED) print head in an electrophotographic printer.[0002]
• 2. Description of the Related Art[0003]
• FIG. 26 is a perspective view schematically showing a part of a conventional LED print unit, and FIG. 27 is a plan view showing a part of an LED array chip provided to the LED print unit of FIG. 26. Referring to FIG. 26, a conventional[0004]LED print unit900 includes acircuit board901 on which are mounted a plurality ofLED array chips902 havingelectrode pads903, and a plurality of driving integrated circuit (IC)chips904 havingelectrode pads905. Theelectrode pads903 and905 are interconnected bybonding wires906 through which current is supplied from the driving-IC chips904 toLEDs907 formed in theLED array chips902.Further electrode pads909 on the driving-IC chips904 are connected tobonding pads910 on thecircuit board901 byfurther bonding wires911.
• For reliable wire bonding, the[0005]electrode pads903,905, and909 must be comparatively large, e.g., one hundred micrometers square (100 μm×100 μm), and theLED array chips902 must have approximately the same thickness as the driving-IC chips904 (typically 250-300 μm), even though the functional parts of the LED array chips902 (the LEDs907) have a depth of only about 5 μm from the surface. To accommodate the needs of wire bonding, anLED array chip902 must therefore be much larger and thicker than necessary simply to accommodate theLEDs907. These requirements drive up the size and material cost of theLED array chips902.
• As shown in plan view in FIG. 27, the[0006]electrode pads903 may need to be arranged in a staggered formation on eachLED array chip902. This arrangement further increases the chip area and, by increasing the length of the path from some of theLEDs907 to theirelectrode pads903, increases the associated voltage drop.
• The size of the driving-[0007]IC chips904 also has to be increased to accommodate the large number ofbonding pads905 by which they are interconnected to theLED array chips902.
• Light-emitting elements having a thin-film structure are disclosed in Japanese Patent Laid-Open Publication No. 10-063807 (FIGS. 3-6, FIG. 8, and paragraph 0021), but these light-emitting elements have electrode pads for solder bumps through which current is supplied. An array of such light-emitting elements would occupy substantially the same area as a conventional[0008]LED array chip902.
SUMMARY OF THE INVENTION
• It is an object of the present invention to provide a combined semiconductor apparatus with a semiconductor thin film that can reduce its size and material cost.[0009]
• According to the present invention, a combined semiconductor apparatus includes a semiconductor substrate having an integrated circuit, a planarized region formed in a surface of the semiconductor substrate, and a semiconductor thin film including at least one semiconductor device and bonded on the planarized region. A surface of the semiconductor thin film, in which the semiconductor device is formed, may be disposed on a side of the planarized region. The apparatus may further include a planarized film disposed between the planarized region and the semiconductor thin film.[0010]
BRIEF DESCRIPTION OF THE DRAWINGS
• In the attached drawings:[0011]
• FIG. 1 is a perspective view schematically showing a part of an integrated LED/driving-IC chip in accordance with a first embodiment of the present invention;[0012]
• FIG. 2 is a perspective view schematically showing a part of the integrated LED/driving-IC chip of the first embodiment before an LED epitaxial film is bonded;[0013]
• FIG. 3 is a plan view schematically showing a part of the integrated LED/driving-IC chip of the first embodiment;[0014]
• FIG. 4 is a schematic cross sectional view showing a cross section through line S[0015]₄-S₄in FIG. 3;
• FIGS. 5A and 5B are schematic cross sectional views for explaining a process of forming a planarized film in the integrated LED/driving-IC chip of the first embodiment;[0016]
• FIG. 6 is a plan view schematically showing a part of the integrated LED/driving-IC chip of the first embodiment after forming common interconnecting layers;[0017]
• FIG. 7 is a schematic cross sectional view for explaining a first process of fabricating an LED epitaxial film of the first embodiment;[0018]
• FIG. 8 is a schematic cross sectional view for explaining a second process of fabricating the LED epitaxial film in the first embodiment;[0019]
• FIG. 9 is a schematic cross sectional view for explaining a third process of fabricating the LED epitaxial-film in the first embodiment;[0020]
• FIG. 10 is a schematic cross sectional view showing a cross section through line S[0021]₁₀-S₁₀in FIG. 9;
• FIGS. 11A to[0022]11D are schematic cross sectional views for explaining a process of bonding the LED epitaxial in the first embodiment;
• FIG. 12 is a schematic plan view showing a part of the integrated LED/driving-IC chip in accordance with a modification of the first embodiment;[0023]
• FIG. 13 is a perspective view schematically showing a part of an integrated LED/driving-IC chip in accordance with a second embodiment of the present invention;[0024]
• FIG. 14 is a schematic perspective view showing the integrated LED/driving-IC chip of the second embodiment before an LED epitaxial film is bonded;[0025]
• FIG. 15 is a schematic cross sectional view showing a cross section through line S[0026]₁₅-S₁₅in FIG. 13;
• FIG. 16 is a perspective view schematically showing a part of an integrated LED/driving-IC chip in accordance with a third embodiment of the present invention;[0027]
• FIG. 17 is a perspective view schematically showing the integrated LED/driving-IC chip of the third embodiment before an LED epitaxial film is bonded;[0028]
• FIG. 18 is a plan view schematically showing a part of the integrated LED/driving-IC chip of the third embodiment;[0029]
• FIG. 19 is a perspective view schematically showing a part of an integrated LED/driving-IC chip in accordance with a fourth embodiment of the present invention;[0030]
• FIG. 20 is a perspective view schematically showing the integrated LED/driving-IC chip of the fourth embodiment before an LED epitaxial film is bonded;[0031]
• FIG. 21 is a plan view schematically showing a part of the integrated LED/driving-IC chip of the fourth embodiment;[0032]
• FIG. 22 is a schematic cross sectional view showing a cross section through line S[0033]₂₂-S₂₂in FIG. 21;
• FIG. 23 is a schematic cross sectional view showing an integrated LED/driving-IC chip in accordance with a fifth embodiment of the present invention;[0034]
• FIG. 24 is a schematic cross sectional view showing an LED print head equipped with a combined semiconductor apparatus of the present invention;[0035]
• FIG. 25 is a schematic cutaway side view of an LED printer employing the invented semiconductor apparatus;[0036]
• FIG. 26 is a perspective view schematically showing a part of a conventional LED print unit; and[0037]
• FIG. 27 is a plan view showing a part of an LED array chip provided in the LED print unit of FIG. 26.[0038]
DETAILED DESCRIPTION OF THE INVENTION
• Embodiments of the invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters.[0039]
First Embodiment
• FIG. 1 is a perspective view schematically showing a part of an integrated LED/driving-[0040]IC chip100 as a combined semiconductor apparatus in accordance with a first embodiment of the present invention, and FIG. 2 is a perspective view schematically showing the integrated LED/driving-IC chip100 before an LEDepitaxial film110 is bonded. FIG. 3 is a plan view schematically showing a part of the integrated LED/driving-IC chip100, and FIG. 4 is a schematic cross sectional view showing a cross section through line S₄-S₄in FIG. 3.
• As shown in FIGS.[0041]1 to4, an integrated LED/driving-IC chip100 of the first embodiment includes a silicon (Si)substrate101 as a semiconductor substrate which has anintegrated circuit102 and aplanarized region103 formed in a surface of theSi substrate101. Theplanarized region103 is obtained by forming a dielectric layer (not shown in the figures) on the surface of theSi substrate101 and then subjecting the surface of theSi substrate101 to a planarizing process such as chemical mechanical polishing (CMP). Although theplanarized region103 is formed on theintegrated circuit102 of theSi substrate101 in the first embodiment, theplanarized region103 may be formed in a region of theSi substrate101 adjacent to theintegrated circuit102.
• As shown in FIGS.[0042]1 to4, further, the integrated LED/driving-IC chip100 of the first embodiment also includes aplanarized film104 disposed on theplanarized region103. Theplanarized film104 has ametal layer105 and aninterdielectric layer106 formed in a region peripheral to themetal layer105. An upper surface of the planarizedfilm104 is subjected to a planarizing process such as CMP.
• As shown in FIGS.[0043]1 to4, the integrated LED/driving-IC chip100 further includes a sheet-likesemiconductor epitaxial film110 includingLEDs120 and bonded on the upper surface of theplanarized film104. In this connection, theplanarized film104 may be omitted and theLED epitaxial film110 may be bonded directly on the surface of theplanarized region103.
• The[0044]LED epitaxial film110 is formed with a plurality of LEDs (also referred to below as light-emitting parts or regions)120. The plurality ofLEDs120 is arranged in a row at regular intervals. However, the arrangement of theLEDs120 is not limited to the regular intervals. Further, the arrangement of theLEDs120 is not limited to a single row, but theLEDs120 may be arranged as regularly shifted in a direction perpendicular to a direction of the arrangement of theLEDs120. Furthermore, number ofLEDs120 to be formed to theLED epitaxial film110 is not limited to the illustrated number. Further, as shown in FIG. 3, theLED epitaxial film110 has a width W₁larger than a width W₂of the light-emittingregion120. For example, the width W₂of the light-emittingregion120 is set to be 20 μm, and the width W₁of theLED epitaxial film110 is set to be 50 μm, so that a margin of 15 μm is provided to each of both sides of the light-emittingregion120. The width W₁of theLED epitaxial film110 is much smaller than width (typically, about 400 μm) of a substrate of the conventional LED print head having electrode pads. However, the width W₁of theLED epitaxial film110 and the width W₂of the light-emittingregion120 are not limited to the aforementioned values.
• It is desirable that the[0045]LED epitaxial film110 will be made of only epitaxial layers to be explained later. The thickness of theLED epitaxial film110 may be about 2 μm that is sufficient to secure stable characteristics (e.g., light-emitting characteristics or electrical characteristics) of theLED120. The thickness of theLED epitaxial film110 is much smaller than the thickness (typically, about 300 μm) of the conventional LED print head. As the thickness of theLED epitaxial film110 is increased, a disconnection due to poor step coverage tends to probably occur in the thin-film wiring layer (e.g. thelayer130 shown in FIG. 6) formed on theLED epitaxial film110. In order to avoid occurrence of the disconnection, it is desirable that theLED epitaxial film110 have a thickness of about 10 μm or less. In this connection, by taking measures, e.g., to planarize the stepped zone with use of insulating material such as polyimide, it is also possible to set the thickness of theLED epitaxial film110 to exceed 10 μm.
• The[0046]Si substrate101 is a monolithic Si substrate, in which theintegrated circuit102 is formed. Theintegrated circuit102 includes a plurality of driving-ICs for driving theLEDs120 formed in theLED epitaxial film110. Besides the driving circuits, theintegrated circuit102 includes shared circuitry for illumination control of theLEDs120. TheSi substrate101 has a thickness of about 300 μm, for example. Theintegrated circuit102 of theSi substrate101 has a rough or irregular surface due to the openings of the interdielectric layer, wiring pattern, etching pattern, etc. A dielectric layer (not shown in the figures) is formed on the irregular surface of theintegrated circuit102 and then subjected to a planarizing process such as CMP, thus forming theplanarized region103.
• The[0047]planarized film104 disposed on theplanarized region103 includes a plurality of the metal layers105 formed on predetermined regions on which theLEDs120 of theLED epitaxial film110 are to be bonded, and theinterdielectric layer106 formed on the peripheral region of the metal layers105 to have the same thickness as that of the metal layers105. However, the structure and material of theplanarized film104 are not restricted to the illustrated or above-described ones. The structure and material of theplanarized film104 may be determined by various factors including the structure and material of theplanarized region103 of theSi substrate101, and the shape, size, thickness and material of theLED epitaxial film110.
• FIGS. 5A and 5B are schematic cross sectional views for explaining a process of forming the[0048]planarized film104. When forming theplanarized film104, as shown in FIG. 5A, an interconnectinglayer105a,aninterdielectric layer106aand ametal layer105bare sequentially formed on theplanarized region103 of theSi substrate101. Next, as shown in FIG. 5B, theinterdielectric layer106aandmetal layer105bare subjected to a planarizing process such as CMP (Chemical Mechanical Polishing) to planarize surfaces of the metal layers105 andinterdielectric layer106. In this way, theplanarized film104 is formed on theplanarized region103. However, the structure of theplanarized film104 and a method of forming theplanarized film104 are not restricted to the aforementioned structure and method. Instead of the aforementioned planarizing method, a spin-on-glass (SOG) method, which is generally used for forming a surface protective film of an IC or an LSI, may be used for forming a planarized film on theSi substrate101. The SOG method includes, for example, the steps of dropping ether-series solvent with dissolved organic silicon onto theSi substrate101, rotating theSi substrate101 at a high speed to form a uniform and thin SOG film on theSi substrate101, and subsequently heating theSi substrate101 at a range between 300 to 500 degrees centigrade to remelt the SOG film for a certain period for hardening the SOG film. In the illustrated example, theinterdielectric layer106ais made of an insulating film such as an oxide film or a nitride film made of, e.g., SiO₂, SiN or polyamide. Themetal layer105 is made of, e.g., palladium or gold or metal material including palladium and/or gold. Themetal layer105 may be a conduction layer of electrically conductive material (such as polysilicon) other than metal. Furthermore, flatness (which is an indicator used for indicating unevenness on the surface) of theplanarized region103 is preferably not more than 10 nanometers. The smaller the value of flatness becomes, the more preferable theplanarized region103 becomes.
• As shown in FIG. 2 or[0049]4, theLED epitaxial film110 has afirst surface110a,in which theLEDs120 are formed, and asecond surface110bopposed to thefirst surface110aand having acommon electrode layer116. In other words, the light-emittingparts120 are positioned in thefirst surface110ain theLED epitaxial film110. In the first embodiment, thefirst surface110aof theLED epitaxial film110 is located on the side of theplanarized region103. As shown in FIG. 2, theLED epitaxial film110 is bonded on theplanarized film104 in such a way that the plurality ofLEDs120 are in contact with the associated metal layers105.
• Next, cross sectional structure of the integrated LED/driving-[0050]IC chip100 will be described. As shown in FIG. 4, the integrated LED/driving-IC chip100 has a structure in which sequentially laminated are theSi substrate101, theintegrated circuit102, theplanarized region103, theplanarized film104, theLED epitaxial film110, and acommon electrode layer116. More specifically, theplanarized region103 is formed on theintegrated circuit102 of theSi substrate101, theplanarized film104 is formed on theplanarized region103, thefirst surface110aprovided with theLEDs120 is disposed on the side of theplanarized region103 in theLED epitaxial film110. Thecommon electrode layer116 may be made of an electrically conductive material, through which light can pass, such as a transparent oxide electrically conductive film. The transparent oxide electrically conductive film may be made of, e.g., indium tin oxide (ITO) or zinc oxide (ZnO).
• As shown in FIG. 4, the[0051]LED epitaxial film110 has a stacking layered structure of an n-type Al_zGa_1-zAs layer114 (0≦z≦1), an n-type Al_yGa_1-yAs layer113 (0≦y≦1), and an n-type Al_xGa_1-xAs layer112 (0≦x≦1), and an n-type GaAs layer111. AZn diffusion region115 is formed in the n-type Al_yGa_1-yAslayer113 and n-type Al_zGa_1-zAslayer114. Thecommon electrode layer116 is formed on the n-type GaAs layer111.
• The n-[0052]type GaAs layer111 has a thickness of about 10 nm (=0.01 μm), the n-type Al_xGa_1-xAslayer112 has a thickness of about 0.5 μm, the n-type Al_yGa_1-yAslayer113 has a thickness of about 1 μm, and the n-type Al_zGa_1-zAslayer114 has a thickness of about 0.5 μm. In this case, the thickness of theLED epitaxial film110 becomes about 2 μm. However, the thicknesses of the above layers are not limited to the above values. Further, the material of theLED epitaxial film110 may be replaced by other material such as (Al_xGa_1-x)_yIn_1-yP, where 0≦x≦1 and 0≦z≦1, in this case, GaN, AlGaN, or InGaN.
• The aluminum composition ratios x, y, z of the AlGaAs layers are preferably selected so that x>y and z>y (e.g., x=z=0.4, y=0.1), and the diffusion front of the[0053]zinc diffusion region115 is preferably located within the n-type Al_yGa_1-yAs active layer active113. In this structure, minority carriers injected through the pn junction are confined within the n-type Al_yGa_1-yAsactive layer113 and the p-type Al_yGa_1-yAs region created therein by zinc diffusion, so that high luminous efficiency is obtained. The structure shown in FIG. 4 enables high luminous efficiency to be obtained with anLED epitaxial film110 as thin as about 2 μm.
• The[0054]LED epitaxial film110 is not limited to thicknesses or materials given above. Other materials, such as an aluminum-gallium indium phosphide ((Al_xGa_1-x)_yIn_1-yP, where 0≦x≦1 and 0≦y≦1, a gallium nitride (GaN), an aluminum gallium nitride (AlGaN), and an indium gallium nitride (InGaN), may also be employed. Other than a double hetero-epitaxial structure described in FIG. 4, a single hetero-epitaxial structure and a homo-epitaxial structure can be also applied in LEDs.
• Shown in FIG. 6 is a schematic plan view of a part of the integrated LED/driving-[0055]IC chip100 after common interconnectinglayers130 are formed. Thecommon interconnecting layers130 are electrically connected to associatedcommon electrode terminals107 of theintegrated circuit102 of theSi substrate101. TheZn diffusion region115 shown in FIG. 4) is electrically connected to the metal layer orconductive layer105. Themetal layer105 is electrically connected to the integrated circuit102 (not shown in the figure). Thecommon interconnecting layer130 is, for example, a thin metal wiring film. Specific examples of suitable films of the individual interconnectinglayers130 include (1) a film containing gold (Au), e.g., a single-layer gold film, a multi-layer film with titanium, platinum, and gold layers (a Ti/Pt/Au film), a multi-layer film with gold and zinc layers (an Au/Zn film), or a multi-layer film with a gold layer and a gold-germanium-nickel layer (an AuGeNi/Au film); (2) a film containing palladium (Pd), e.g., a single-layer palladium film or a multi-layer film with palladium and gold layers (a Pd/Au film); (3) a film containing aluminum (Al), e.g., a single-layer aluminum film or a multi-layer film with aluminum and nickel layers (an Al/Ni film); (4) a polycrystalline silicon (polysilicon) film; (5) a thin, electrically conductive oxide film such as an indium tin oxide (ITO) film or a zinc oxide (ZnO) film. Thecommon interconnecting layer130 may be formed by photolithography.
• An interdielectric thin film (not shown in the figures) is provided in a region where electric short-circuiting should be avoided, for example, between the[0056]common interconnecting layer130 and top- and side-surface of the LEDepitaxial films110, between thecommon interconnecting layer130 and the integrated circuit, or the like, thereby securing normal operation. Thecommon interconnecting layer130 must cross steps, such as the step at the edge of theLED epitaxial film110 or theintegrated circuit102 area. To prevent short- and open-circuit faults in the common interconnectinglayers130 at the steps, the interlayer dielectric film is preferably formed by a method such as a plasma chemical vapor deposition (P-CVD) method that provides good step coverage. The steps may also be planarized with a polyimide film, a spin-on-glass film, or other interdielectric thin film (e.g., silicon oxide or silicon nitride).
• Next, a fabrication process for the[0057]LED epitaxial film110 will be described with reference to FIGS.7 to10, which are schematic cross sectional views for explaining process of fabricating anLED epitaxial film110 of the first embodiment. Further, FIG. 9 shows a cross section through line S₉-S₉in FIG. 10, and FIG. 10 shows a cross section through line S₁₀-S₁₀in FIG. 9.
• An[0058]LED epitaxial layer110ccan be fabricated by the techniques such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). After lifting off theLED epitaxial layer110c,it becomes theLED epitaxial film110. Before fabricating theLED epitaxial layer110c,as shown in FIG. 7, the LED epitaxialfilm fabrication substrate140 is formed. Thefabrication substrate140 in FIG. 7 includes aGaAs substrate141, aGaAs buffer layer142, an aluminum-gallium indium phosphide ((AlGa)InP)etching stop layer143, and an aluminum arsenide (AlAs)sacrificial layer144. The n-typeGaAs contact layer111, n-type Al_xGa_1-xAslower cladding layer112, n-type Al_yGa_1-yAsactive layer113, and n-type Al_zGa_1-zAsupper cladding layer114 are formed in this order on the AlAssacrificial layer144, creating anLED epitaxial layer110c.Lifting-off of theLED epitaxial layer110ccan be carried out by a chemical lift off method. In this case, the (AlGa)InPetching stop layer143 can be omitted. Further, the structures of thesemiconductor epitaxial layer110cand thefabrication substrate140 are not limited to those shown in FIG. 7, and various modifications of theLED epitaxial layer110cand thefabrication substrate140 can be made.
• Referring to FIG. 8, a p-type impurity comprising zinc (Zn) is diffused by, for example, a solid-phase diffusion method to create the[0059]zinc diffusion regions115. The diffusion source film (not shown in the figures) used for the solid-phase diffusion process is then removed to expose the surface of thezinc diffusion regions115.
• As shown in FIGS. 9 and 10, the AlAs[0060]sacrificial layer144 is selectively removed with use of a 10% HF (hydrogen fluoride) solution. Since an etching rate for the AlAssacrificial layer144 is much larger than an etching rate for the AlGaAs layers112 to114, GaAs layers111,141,142, andetching stop layer143; the AlAssacrificial layer144 can be selectively etched. As a result, theLED epitaxial layer110c(LED epitaxial film110) can be lifted off from the LED epitaxialfilm fabrication substrate140.
• In this connection, for the purpose of making the[0061]LED epitaxial film110 thin and also to lift off theLED epitaxial film110 from thefabrication substrate140 in a comparative short time, it is desirable that theLED epitaxial film110 have a width of 300 μm or less, e.g., about 50 μm. To this end, as shown in FIG. 10, the respectiveepitaxial layers111 to114 are previously etched so thattrenches145 are made therein and the layers have a width W₁of 50 μm. The formation of thetrenches145 are carried out by photolithography for masking the epitaxial layers with use of resist for the trench formation and etching the epitaxial layers using a phosphate peroxide etchant (i.e., a solution of phosphoric acid and hydrogen peroxide). For simplicity, only onetrench145 is shown in FIG. 10. The phosphate peroxide etchant etches the AlGaAs layers112 to114 andGaAs layers111,141,142. However, since the etching rate of the etchant for theetching stop layer143 is low, thetrench145 formed from the upper surface can be prevented from arriving at theGaAs substrate141 during the etching. After thetrench145 is formed, the AlAssacrificial layer144 is etched using the HF solution and then theLED epitaxial film110 is lifted off. Although the AlAssacrificial layer144 is illustrated as still remain (as etched halfway) in FIG. 10, the AlAssacrificial layer144 is completely removed in such a condition as to carry theLED epitaxial film110. After the AlAssacrificial layer144 has been completely removed by etching, theLED epitaxial film110 is immersed in deionized water so that no etching solution residue remains. When lifting off theLED epitaxial film110, a supporting material for carrying and protecting the LED epitaxial film can be provided on theLED epitaxial film110. For example, when the supporting material is provided on theLED epitaxial film110, the supporting material can be transferred to a predetermined position by sucking the surface of the supporting material for the LED epitaxial film by vacuum suction or bonding the surface of the supporting material for the LED epitaxial film by a photo-hardening adhesive sheet, which hardens and loses its adhesive property when subjected to light irradiation.
• FIGS. 11A to[0062]11D are schematic cross sectional views for explaining a process of bonding theLED epitaxial film110 in the integrated LED/driving-IC chip of the first embodiment. As shown in FIG. 11A, the LED epitaxial film110 (corresponding to theLED epitaxial layer110cin FIGS. 9 and 10 before lifting-off) is lifted from thefabrication substrate140 and carried by a photo-hardeningadhesive sheet150aof a first supportingmaterial150, and, as shown in FIG. 11B, is bonded onto a photo-hardeningadhesive sheet160aof a second supportingmaterial160. Next, light irradiation such as UV irradiation on the photo-hardeningadhesive sheet150aof the first supportingmaterial150 causes thesheet150ato lose its adhesive property. Thereafter, the second supportingmaterial160 is located upside down so that theLED epitaxial film110 is at a lower position as shown in FIG. 11D. In this condition, theLED epitaxial film110 is bonded onto the planarized region103 (or onto theplanarized film104 formed on the planarized region103) of theSi substrate101, and then subjected to light irradiation (e.g., UV irradiation) to lose the adhesive property of the photo-hardeningadhesive sheet160aof the second supportingmaterial160 and to lift the second supportingmaterial160 therefrom.
• As mentioned above, the integrated LED/driving-[0063]IC chip100 of the first embodiment is arranged so that theplanarized region103 is formed on the surface of theintegrated circuit102 of theSi substrate101, theplanarized film104 is formed on theplanarized region103, and theLED epitaxial film110 is bonded onto theplanarized film104. As a result, the need for providing the wire bond electrode pad for wire bonding to theLED epitaxial film110 can be eliminated. In the integrated LED/driving-IC chip100 of the first embodiment, further, since thecommon interconnecting layer130 is formed as a thin film by photolithography, the need for providing the wire bond electrode pad for the common electrode to theLED epitaxial film110 can also be eliminated. As a result, the surface area of theLED epitaxial film110 can be made small and thus the integrated LED/driving-IC chip100 can be made small in size. In addition, since the surface area of theLED epitaxial film110 can be made small, its material cost can be reduced.
• In the integrated LED/driving-[0064]IC chip100 of the first embodiment, since theLED epitaxial film110 is supported by theSi substrate101 and need not be thickened to provide strength for wire bonding, it can be much thinner than a conventional LED array chip. This effect lead to a substantial reduction in material costs.
• In the integrated LED/driving-[0065]IC chip100 of the first embodiment, further, thefirst surface110aof theLED epitaxial film110 provided with theLEDs120 is located on the side of theSi substrate101 provided with theplanarized region103 and overlapped with themetal layer105. Thus the need for providing individual interconnecting lines for connection of theLEDs120 to theintegrated circuit102 can be eliminated and the arrangement and fabricating process can be simplified.
• In the integrated LED/driving-[0066]IC chip100 of the first embodiment, furthermore, since theLED epitaxial film110 is provided on theplanarized region103 above theintegrated circuit102, the width of the Si substrate having the integratedcircuit102 can be reduced to a large extent.
• In the integrated LED/driving-[0067]IC chip100 of the first embodiment, in addition, since the plurality of common interconnectinglayers130 are arranged at regular intervals in a direction of a row of the LEDs, fluctuations in the potential of thecommon electrode layer116 of theLED epitaxial film110 can be made small and fluctuations in the luminous intensity of theLEDs120 can be made small.
• FIG. 12 is a cross sectional view schematically showing an integrated LED/driving-[0068]IC chip170 as a combined semiconductor apparatus in accordance with a modification of the first embodiment of the present invention. In FIG. 12, parts that are the same as or correspond to those in FIG. 6 (first embodiment) are denoted by the same reference numerals. The integrated LED/driving-IC chip170 shown in FIG. 12 is different from that shown in FIG. 6 in that the shape of acommon interconnecting layer131 is different from that of thecommon interconnecting layer130 in FIG. 6. In the integrated LED/driving-IC chip170 shown in FIG. 12, thecommon interconnecting layer131 has such a shape as to spread nearly all over theLED epitaxial film110 other thanopenings131aon theLEDs120. As thecommon interconnecting layer131, a metal layer or a transparent electrode or a semi-transparent electrode can be used. In this case, fluctuations in the potential of thecommon electrode layer116 of theLED epitaxial film110 can be made small and fluctuations in the luminous intensities of theLEDs120 can be made small.
Second Embodiment
• FIG. 13 is a perspective view schematically showing a part of an integrated LED/driving-[0069]IC chip200 in accordance with a second embodiment of the present invention, and FIG. 14 is a perspective view schematically showing the integrated LED/driving-IC chip200 of the second embodiment before the LEDepitaxial films210 are bonded. FIG. 15 is a schematic cross sectional view showing a cross section through line S₁₅-S₁₅in FIG. 13.
• In FIG. 13, parts that are the same as or correspond to those in FIG. 1 (first embodiment) are denoted by the same reference numerals. In FIG. 14, parts that are the same as or correspond to those in FIG. 2 (first embodiment) are denoted by the same reference numerals. In FIG. 15, parts that are the same as or correspond to those in FIG. 4 (first embodiment) are denoted by the same reference numerals. An integrated LED/driving-[0070]IC chip200 shown in FIGS. 13 and 14 is different from the integrated LED/driving-IC chip100 of the first embodiment shown in FIGS. 1 and 2 in that a singleLED epitaxial film210 is bonded onto eachmetal layer105 and that eachLED epitaxial film210 has a single LED.
• As shown in FIG. 15, the[0071]LED epitaxial film210 has a stacking layered structure in which a p-type Al_xGa_1-xAslayer214, a p-type Al_yGa_1-yAslayer213, an n-type Al_zGa_1-zAslayer212 and an n-type GaAs layer211 are sequentially grown on a p-type GaAs layer215. When fabricating theLED epitaxial film210, similarly to the first embodiment, the n-type GaAs layer211, n-type Al_zGa_1-zAslayer212, p-type Al_yGa_1-yAslayer213, p-type Al_xGa_1-xAslayer214 and p-type GaAs layer215 are sequentially formed on an LED epitaxial film fabrication substrate. When bonding theLED epitaxial film210, similarly to the first embodiment, theLED epitaxial film210 is lifted off from the LED epitaxial film fabrication substrate, afirst surface210aof theLED epitaxial film210 provided with the LEDs is located upside down so that thefirst surface210ais located on the side of theplanarized region103, and theLED epitaxial film210 is bonded onto the metal layers105 on theSi substrate101. Thereafter, acommon interconnecting layer230 having an opening230ais formed. Similarly to thecommon interconnecting layer130 in the first embodiment, thecommon interconnecting layer230 is a thin interconnecting layer which extends from the surface of the common electrode area of theLED epitaxial film210 to the surface of the common electrode terminal of theintegrated circuit102. The composition of each of the above layers can be set to satisfy a relation of x>y and z>y (e.g., x=z=0.4 and y=0.1). However, the structure and composition of theLED epitaxial film210 are not limited to such those as mentioned above. The LED shown in FIG. 15 has a double hetero-junction structure, but it is also possible to fabricate LEDs with a single hetero-junction structure or a homojunction structure. Further, various types of structures including provision of nondoped active layer between cladding layers or insertion of a quantum-well layer between in the cladding layers can be employed. Such a modification as a p-type layer as the upper layer and an n-type layer as the lower layer is also possible.
• As has been explained above, in the integrated LED/driving-[0072]IC chip200 of the second embodiment, the LEDepitaxial films210 are divided to be small. As a result, a problem with the internal stress of the LEDepitaxial films210 involved when the thermal expansion coefficient of the LEDepitaxial films210 and the thermal expansion coefficient of theSi substrate101 are largely different, can be reduced, and thus one of factors causing a defect in the LED epitaxial films204 can be eliminated. For this reason, the integrated LED/driving-IC chip200 of the second embodiment can be increased in reliability.
• In the integrated LED/driving-[0073]IC chip200 of the second embodiment, furthermore, the LEDepitaxial films210 are divided to be small and the bonding area is small. Thus a process of tightly bonding the LEDepitaxial films210 to the metal layers105 can be facilitated, and therefore a defect generation rate caused by incomplete adhesion can be decreased.
• In the integrated LED/driving-[0074]IC chip200 of the second embodiment, further, since theLED epitaxial film210 has only light-emitting regions, the width of theLED epitaxial film210 can be made small and the length of the common interconnecting layer can be made short.
• The second embodiment is substantially the same as the above first embodiment, except for the above-described respects.[0075]
Third Embodiment
• FIG. 16 is a perspective view schematically showing a part of an integrated LED/driving-[0076]IC chip300 in accordance with a third embodiment of the present invention, and FIG. 17 is a perspective view schematically showing the integrated LED/driving-IC chip300 before anLED epitaxial film310 is bonded. Further, FIG. 18 is a plan view schematically showing a part of the integrated LED/driving-IC chip300.
• As shown in FIGS.[0077]16 to18, an integrated LED/driving-IC chip300 of the third embodiment includes anSi substrate301 having anintegrated circuit302, aplanarized region303 formed in a surface of theSi substrate301, and aplanarized film304 formed on theplanarized region303. Theplanarized region303 is obtained by forming a dielectric layer (not shown in the figures) on theSi substrate301 and subjecting the surface of theSi substrate301 formed with the dielectric layer to a planarizing process such as CMP. Although theplanarized region303 is formed in a surface of theintegrated circuit302 of theSi substrate301 in the third embodiment, the planarized region may be formed in a region of theSi substrate301 adjacent to theintegrated circuit302. Further, theplanarized film304 in the third embodiment is ametal layer305.
• As shown in FIGS.[0078]16 to18, the integrated LED/driving-IC chip300 a sheet-likeLED epitaxial film310 including theLEDs320 and bonded on theplanarized film304. TheLED epitaxial film310 has a common interconnecting layer (not shown in FIGS.16 to18) on asecond surface310bof theLED epitaxial film310 opposed to afirst surface310a,in which theLEDs320 are formed. Thesecond surface310bof theLED epitaxial film310 is positioned on the side of theplanarized region303 of theSi substrate301 and bonded on themetal layer305. In this connection, theplanarized film304 as themetal layer305 may not be provided on theplanarized region303 of theSi substrate301, and theLED epitaxial film310 may be bonded directly on the surface (e.g., electrode area) of theplanarized region303 of theSi substrate301.
• As shown in FIGS.[0079]16 to18, the integrated LED/driving-IC chip300 also includes thin individual interconnecting layers330 formed on a region extending from the upper surfaces of theLEDs320 of theLED epitaxial film310 to the upper surfaces ofindividual electrode terminals308 of theintegrated circuit302. Formed under the individual interconnectinglines330 is a suitable interdielectric layer (not shown in the figures). Themetal layer305 is electrically connected to a common potential terminal provided on thesubstrate301.
• As has been explained above, in the integrated LED/driving-[0080]IC chip300 of the third embodiment, since thesecond surface310bof theLED epitaxial film310 is bonded on themetal layer305, a strong adhesion strength can be obtained.
• The third embodiment is substantially the same as the above first or second embodiment, except for the above-described respects.[0081]
Fourth Embodiment
• FIG. 19 is a perspective view schematically showing a part of an integrated LED/driving-[0082]IC chip400 in accordance with a fourth embodiment of the present invention, and FIG. 20 is a perspective view schematically showing the integrated LED/driving-IC chip400 before anLED epitaxial film410 is bonded. FIG. 21 is a plan view schematically showing a part of the integrated LED/driving-IC chip400, and FIG. 22 is a cross sectional view showing a cross section through line S₂₂-S₂₂in FIG. 21.
• As shown in FIGS.[0083]19 to21, an integrated LED/driving-IC chip400 of the fourth embodiment includes anSi substrate401 having anintegrated circuit402, aplanarized region403 formed in (or on) a surface of theSi substrate401, and ametal layer405 as a planarized film formed on theplanarized region403. Theplanarized region403 is obtained by forming a dielectric layer (not shown in the figures) on the surface of theSi substrate401 and subjecting the surface of theSi substrate401 having the dielectric layer to a planarizing process such as CMP. In the fourth embodiment, theplanarized region403 is formed on theintegrated circuit402 of theSi substrate401 and on aregion403aadjacent to theintegrated circuit402. Themetal layer405 is formed on theregion403aadjacent to a region where the integrated circuit is formed, and anLED epitaxial film410 is bonded on the surface of themetal layer405.
• As shown in FIGS.[0084]19 to21, the integrated LED/driving-IC chip400 also a sheet-likeLED epitaxial film410 includingLEDs420 and bonded on themetal layer405. TheLED epitaxial film410 has a common interconnecting layer (not shown in the figures) on asecond surface410bof the epitaxial film opposed to afirst surface410a,in which theLEDs420 is formed. TheLED epitaxial film410 is bonded on themetal layer405 so that thesecond surface410bis located on the side of theplanarized region403 of theSi substrate301. In this connection, similarly to the first embodiment, a plurality of metal layers may be formed so that theLEDs420 of thefirst surface410aare placed on the metal layers respectively. Similarly to the second embodiment, further, a plurality of LED epitaxial films each having a single LED may be arranged in a row on the metal layer. Furthermore, it is also possible not to provide themetal layer405 and to bond theLED epitaxial film410 directly on the surface (e.g., electrode area) of theregion403aof theSi substrate401.
• As shown in FIGS.[0085]19 to21, the integrated LED/driving-IC chip400 also includes thin individual interconnecting layers430 formed on a region extending from the upper surfaces of theLEDs420 of theLED epitaxial film410 to the upper surfaces ofindividual electrode terminals408 of theintegrated circuit402. A suitable interdielectric layer (not shown in the figures) is provided under the thin individual interconnecting layers430 (e.g., between the interconnecting layers and metal layer405). Themetal layer405 is electrically connected to a common potential (e.g., ground potential) terminal provided on thesubstrate401.
• As has been explained above, in the integrated LED/driving-[0086]IC chip400 of the fourth embodiment, theLED epitaxial film410 can be bonded on theSi substrate401 at a position higher than anirregular surface402aof theintegrated circuit402 of theSi substrate401. For this reason, such a problem that a part (e.g., a bonding collet) of a device used in the process of bonding theLED epitaxial film410 onto themetal layer405 abuts against thesurface402aof anintegrated circuit502 can be avoided.
• The fourth embodiment is substantially the same as the above first to third embodiments, except for the above-described respects.[0087]
Fifth Embodiment
• FIG. 23 is a cross sectional view schematically showing an integrated LED/driving-[0088]IC chip500 in accordance with a fifth embodiment of the present invention.
• The integrated LED/driving-[0089]IC chip500 of the fifth embodiment includes anSi substrate501 having the integratedcircuit502, and a raisedlayer504 which is formed on aregion503 adjacent to a region where theintegrated circuit502 is placed. The raisedlayer504 has asurface504aat a position higher than a surface of theintegrated circuit502. The integrated LED/driving-IC chip500 also includes ametal layer505 formed on the raisedlayer504, and anLED epitaxial film510 bonded on the surface of themetal layer505. The material and structure of the raisedlayer504 can be freely selected. The raisedlayer504 includes an interconnecting layer electrically connected to themetal layer505 and an insulating layer formed in a region peripheral thereto.
• As has been explained above, in the integrated LED/driving-[0090]IC chip500 of the fifth embodiment, theLED epitaxial film510 can be bonded at a position higher than theirregular surface502aof theintegrated circuit502 of theSi substrate501. For this reason, a problem that a part (e.g., bonding collet) of a device used in the process of bonding theLED epitaxial film510 onto themetal layer505 on the raisedlayer504 can be easily avoided.
• The fifth embodiment is substantially the same as the above first to fourth embodiments, except for the above-described respects.[0091]
LED Print Head
• FIG. 24 is a schematic cross sectional view of an[0092]LED print head700 having the semiconductor apparatus of the present invention built therein. As shown in FIG. 24, theLED print head700 includes a base701 on which anLED unit702 is mounted. TheLED unit702 includes a plurality of integrated LED/driving-IC chips702aof the type described in any of the preceding embodiments, mounted so that their light-emitting parts are positioned beneath arod lens array703. Therod lens array703 is supported by aholder704. Thebase701,LED unit702, andholder704 are held together byclamps705. Light emitted by the light-emitting elements in theLED unit702 is focused by rod lenses in therod lens array703 onto, for example, a photosensitive drum (not shown) in an electrophotographic printer or copier.
• Use of integrated LED/driving-[0093]IC chips702ainstead of the conventional paired LED array chips and driver IC chips enables theLED unit702 to be reduced in size and reduces its assembly cost, as there are fewer chips to be mounted.
LED Printer
• FIG. 25 shows an example of a full-[0094]color LED printer800 in which the present invention may be employed. Theprinter800 has a yellow (Y)process unit801, a magenta (M)process unit802, a cyan (C)process unit803, and a black (K)process unit804, which are mounted following one another in tandem fashion. Thecyan process unit803, for example, includes aphotosensitive drum803athat turns in the direction indicated by the arrow, a chargingunit803bthat supplies current to thephotosensitive drum803ato charge the surface thereof, anLED print head803cthat selectively illuminates the charged surface of thephotosensitive drum803ato form an electrostatic latent image, a developingunit803dthat supplies cyan toner particles to the surface of thephotosensitive drum803ato develop the electrostatic latent image, and acleaning unit803ethat removes remaining toner from thephotosensitive drum803aafter the developed image has been transferred to paper. TheLED print head803chas, for example, the structure shown in FIG. 24, including integrated LED/driving-IC chips702aof the type described in any of the nine embodiments above. Theother process units801,802,804 are similar in structure to thecyan process unit803, but use different toner colors.
• The paper[0095]805 (or other media) is held as a stack of sheets in acassette806. A hoppingroller807 feeds thepaper805 one sheet at a time toward a pairedtransport roller810 andpinch roller808. After passing between these rollers, thepaper805 travels to aregistration roller811 andpinch roller809, which feed the paper toward theyellow process unit801.
• The[0096]paper810 passes through theprocess units801,802,803,804 in turn, traveling in each process unit between the photosensitive drum and atransfer roller812 made of, for example, semi-conductive rubber. Thetransfer roller812 is charged so as to create a potential difference between it and the photosensitive drum. The potential difference attracts the toner image from the photosensitive drum onto thepaper805. A full-color image is built up on thepaper805 in four stages, theyellow process unit801 printing a yellow image, the magenta process unit802 a magenta image, thecyan process unit803 a cyan image, and the black process unit804 a black image.
• From the[0097]black process unit804, thepaper805 travels through afuser813, in which a heat roller and back-up roller apply heat and pressure to fuse the transferred toner image onto the paper. Afirst delivery roller814 andpinch roller816 then feed thepaper805 upward to asecond delivery roller815 andpinch roller817, which deliver the printed paper onto astacker818 at the top of the printer.
• The photosensitive drums and various of the rollers are driven by motors and gears not shown in the drawing. The motors are controlled by a control unit (not shown) that, for example, drives the[0098]transport roller810 and halts theregistration roller811 until the front edge of a sheet ofpaper805 rests flush againstregistration roller811, then drives theregistration roller811, thereby assuring that thepaper805 is correctly aligned during its travel through theprocess units801,802,803,804. Thetransport roller810,registration roller811,delivery rollers814,815, and pinchrollers808,809,816,817 also have the function of changing the direction of travel of thepaper805.
• The LED heads account for a significant part of the manufacturing cost of this type of[0099]LED printer800. By using highly reliable and space-efficient integrated LED/driving-IC chips and enabling these chips and the LED units in the LED heads to be manufactured by a simplified fabrication process with reduced material costs, the present invention enables a high-quality printer to be produced at a comparatively low cost.
• Similar advantages are obtainable if the invention is applied to a full-color copier. The invention can also be advantageously used in a monochrome printer or copier or a multiple-color printer or copier, but its effect is particularly great in a full-color image-forming apparatus (printer or copier), because of the large number of exposure devices (print heads) required in such apparatus.[0100]
Modifications of Embodiments
• Although explanation has been made in the foregoing embodiments in connection with the case where the planarized film on the Si substrate includes the metal layer, the metal layer may be replaced by an electrically conductive thin layer such as polysilicon, electrically conductive oxide (ITO, ZnO), or the like.[0101]
• Explanation has been made in the foregoing embodiments in connection with the case where the Si substrate is used as the semiconductor substrate. However, the semiconductor substrate may be made of other materials such as amorphous silicon, single crystal silicon, polysilicon, compound semiconductor or organic semiconductor.[0102]
• Although explanation has been made in the foregoing embodiments in connection with the case where the semiconductor device provided to the semiconductor thin film is the LED, the semiconductor device may be another light-emitting element such as a laser, a light-sensing element, a Hall element, or a piezoelectric element.[0103]
• Explanation has been made in the foregoing embodiments in connection with the case where the LED epitaxial film is made of epitaxial layers. However, a semiconductor thin film other than the epitaxial layer may be employed as the LED epitaxial film.[0104]
• Explanation has been made in the foregoing embodiments in connection with the case where the LED epitaxial film is bonded onto the planarized region on the semiconductor substrate or on the planarized film. When the semiconductor substrate has a less roughened surface, however, the LED epitaxial film may be bonded on a region not subjected to planarizing process such as CMP.[0105]

Claims (25)

What is claimed is:

1. A combined semiconductor apparatus comprising:

a semiconductor substrate having an integrated circuit;

a planarized region formed in a surface of said semiconductor substrate; and

a semiconductor thin film including at least one semiconductor device and bonded on said planarized region.

2. The combined semiconductor apparatus according toclaim 1, wherein said planarized region is a part of said surface of said semiconductor substrate which has been subjected to a planarizing process.

3. The combined semiconductor apparatus according toclaim 1, wherein said planarized region is disposed above said integrated circuit of said semiconductor substrate.

4. The combined semiconductor apparatus according toclaim 1, wherein said planarized region is disposed in a region of said semiconductor substrate adjacent to said integrated circuit of said semiconductor substrate.

5. The combined semiconductor apparatus according toclaim 1, further comprising a planarized film disposed between said planarized region and said semiconductor thin film, wherein a surface of said planarized film on a side of said semiconductor thin film has been subjected to a planarizing process.

6. The combined semiconductor apparatus according toclaim 5, wherein said planarized film includes:

an electrically conductive layer; and

an interdielectric layer formed in a region peripheral to said electrically conductive layer.

7. The combined semiconductor apparatus according toclaim 1, wherein a first surface of said semiconductor thin film, in which said semiconductor device is formed, is disposed on a side of said planarized region of said semiconductor substrate.

8. The combined semiconductor apparatus according toclaim 7, wherein said semiconductor thin film includes a common electrode layer on a second surface of said semiconductor thin film opposed to said first surface, and said integrated circuit has a common electrode terminal;

said apparatus further comprising a common interconnecting layer formed on a region extending from an upper surface of said common electrode layer of said semiconductor thin film to said common electrode terminal of said integrated circuit.

9. The combined semiconductor apparatus according toclaim 1, wherein said semiconductor thin film has a common electrode layer on a second surface of the semiconductor thin film opposed to a first surface of the semiconductor thin film, in which said semiconductor device is formed, and

said second surface of said semiconductor thin film is disposed on a side of said planarized region of said semiconductor substrate.

10. The combined semiconductor apparatus according toclaim 9, wherein said integrated circuit includes individual electrode terminals;

said apparatus further comprising individual interconnecting lines formed on a region extending from an upper surface of said semiconductor device to said individual electrode terminal.

11. A combined semiconductor apparatus comprising:

a semiconductor substrate;

an integrated circuit device disposed on said semiconductor substrate;

a raised layer formed on a surface of said semiconductor substrate in a region adjacent to said integrated circuit device, an upper surface of said raised layer being at a position higher than an upper surface of said integrated circuit device; and

a semiconductor thin film bonded on the upper surface of said raised layer.

12. A combined semiconductor apparatus comprising:

a semiconductor substrate having an integrated circuit; and

a semiconductor thin film including at least one semiconductor device and bonded on said semiconductor substrate;

wherein a first surface of said semiconductor thin film, in which said semiconductor device is formed, is disposed on a side of said semiconductor substrate.

13. The combined semiconductor apparatus according toclaim 12, further comprising an electrically conductive layer disposed between said semiconductor substrate and said semiconductor thin film.

14. The combined semiconductor apparatus according toclaim 13, further comprising an interdielectric layer disposed between said semiconductor substrate and said semiconductor thin film and in a region peripheral to said electrically conductive layer.

15. The combined semiconductor apparatus according toclaim 12, wherein said semiconductor thin film includes a common electrode layer on a second surface of said semiconductor thin film opposed to said first surface, and said integrated circuit has a common electrode terminal;

said apparatus further comprising a common interconnecting layer formed on a region extending from an upper surface of said common electrode layer of said semiconductor thin film to said common electrode terminal of said integrated circuit.

16. The combined semiconductor apparatus according toclaim 1, wherein said semiconductor thin film is made of compound semiconductor as a main materials.

17. The combined semiconductor apparatus according toclaim 1, wherein said at least one semiconductor device is any of a light-emitting element, a light-sensing element, a Hall element and a piezoelectric element, and said integrated circuit includes a driving-IC for driving said at least one semiconductor device.

18. The combined semiconductor apparatus according toclaim 1, wherein said at least one semiconductor device is a plurality of said semiconductor devices arranged in said semiconductor thin film.

19. The combined semiconductor apparatus according toclaim 1, wherein said at least one semiconductor device is a single semiconductor device disposed in said semiconductor thin film.

20. An optical print head including the combined semiconductor apparatus ofclaim 1.

21. An optical print head including the combined semiconductor apparatus ofclaim 11.

22. An optical print head including the combined semiconductor apparatus ofclaim 12.

23. An image-forming apparatus comprising at least one optical print head including the combined semiconductor apparatus ofclaim 1.

24. An image-forming apparatus comprising at least one optical print head including the combined semiconductor apparatus ofclaim 11.

25. An image-forming apparatus comprising at least one optical print head including the combined semiconductor apparatus ofclaim 12.

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