US20040124508A1 - High performance chip scale leadframe package and method of manufacturing the package - Google Patents

Abstract

An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip. Each of the wires has a first end electrically conductively joined to the first face of the integrated circuit chip. The first end of the wire, therefore, is disposed between a plane defined by the second face of the die pad and a plane defined by the first face of the integrated circuit chip. Each of the wires also has a second end electrically conductively joined to the first face of one of the leads. The second end of the wire, therefore, is disposed between a plane defined by a first face of the die pad and a plane defined by the first face of the lead to which it is joined.

Description

• This application claims the benefit of the co-pending U.S. Provisional Application No. 60/429,315 filed on Nov. 27, 2002, and incorporated herein by reference.[0001]
BACKGROUND OF THE INVENTION
• 1.Field of the Invention[0002]
• The present invention generally relates to the field of semiconductors. In particular, the present invention relates to an improved integrated circuit package and a method of assembling the same.[0003]
• 2. Discussion of Related Art[0004]
• Semiconductors are materials that have characteristics of insulators and conductors. In today's technology, semiconductor materials have become extremely important as the basis for transistors, diodes, and other solid-state devices. Semiconductors are usually made from germanium or silicon, but selenium and copper oxide, as well as other materials are also used. When properly made, semiconductors will conduct electricity in one direction better than they will in the other direction.[0005]
• Semiconductor devices and integrated circuits (ICs) are made up of components such as transistors, and diodes, and elements such as resistors and capacitors linked together by conductive connections to form one or more functional circuits. Interconnects on an IC chip serve the same function as the wiring in a conventional circuit.[0006]
• Often, IC manufacturing methods use molds to form the IC package. The protective coatings on the package typically completely encompass the IC, wire bonds, and electrical contacts of the IC carrier or substrate.[0007]
• Emerging electronic product applications are creating a set of challenges for the IC packaging industry.[0008]
• Once the IC chips have been produced and encapsulated in semiconductor packages as described, they may be used in a wide variety of electronic appliances. The variety of these electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically include a motherboard on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic appliances are typically manufactured in reduced sizes and at reduced costs, which results in increased consumer demand. It is increasingly desirable, therefore, to reduce the profile of the semiconductor package so that electronic systems can be incorporated into more compact devices and products.[0009]
• As ICs operate, they tend to consume an amount of electricity that is used to operate the various electrical components of the IC. As the speed of ICs increases, so does the amount of electricity which they consume increase. The electricity consumed by an IC tends to be predominantly discarded as heat. Thus, as the speed of ICs has increased, so has the amount of heat which the ICs produce increased.[0010]
• As mentioned, some IC manufacturing methods use molds or encapsulants to form the IC packages and to protect the package. Unfortunately, the protective coatings also tend to function as an insulating layer and may substantially impede thermal dissipation from the IC. Thus, the heat dissipation of such IC packages is degraded due to the configuration of the protective coatings of the package.[0011]
SUMMARY OF THE INVENTION
• An IC package according to the present invention comprises a plurality of leads, each having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the plurality of leads, so that the second face of the die pad and the second face of the plurality of leads are not coplanar. The package also comprises an IC chip substantially laterally disposed between the plurality of leads and having a first face and a second face opposite to the first face. The package further comprises a plurality of wires linking the plurality of leads to the IC chip. Each of the plurality of wires has a first end electrically conductively joined to the first face of the IC chip. The first end of each of the plurality of wires is disposed between a plane defined by the second face of the die pad and a plane defined by the first face of the IC chip. Each of the plurality of wires also has a second end electrically conductively joined to the first face of one of the plurality of leads. The second end of each of the plurality of wires is disposed between a plane defined by the first face of the die pad and a plane defined by the first face of the lead to which the die pad is joined.[0012]
• According to a further aspect of a first exemplary embodiment, the first face of the die pad is adapted to direct coupling with a heat sink.[0013]
• According to another further aspect of the first exemplary embodiment, the IC package further comprises an encapsulant surrounding the first face of the IC chip, the first faces of the plurality of leads, the wires, and the second face of the die pad. The first face of the die pad is adapted to direct coupling with a heat sink. Additionally, the encapsulant can be a polymer-based molding compound. Further, a planar surface can be formed comprising the first face of the die pad and an outer surface of the encapsulant.[0014]
• According to yet another aspect of the first embodiment, the IC package further comprises a thermal dissipation element having a first face and a second face opposite to the first face, wherein the second face of the thermal dissipation element is coupled to the first face of the die pad.[0015]
• According to a second exemplary embodiment of the present invention, an IC package comprises a plurality of leads, each having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the plurality of leads, so that the second face of the die pad and the second face of the plurality of leads are not coplanar. The package also comprises an IC chip substantially laterally disposed between the plurality of leads and having a first face and a second face opposite to the first face. The package also comprises a plurality of wires linking the plurality of leads to the IC chip. Each of the wires has a first end electrically conductively joined to the first face of the IC chip and a second end electrically conductively joined to a first face of one of the plurality of leads. The package further comprises an annular element, substantially laterally disposed between the IC chip and the plurality of leads, so that the annular element substantially encircles the IC chip. The package further comprises at least one secondary wire linking the IC chip to the annular element. Each one of the secondary wires has a first end electrically conductively joined to the first face of the IC element and a second end electrically conductively joined to the first face of the annular element. The annular element according to an aspect of the second exemplary embodiment can be electrically grounded or it can comprise a power source.[0016]
• According to a third exemplary embodiment of the present invention, an IC package comprises a plurality of leads, each having a first face and a second face opposite to the first face. The package also comprises an IC chip substantially laterally disposed between the plurality of leads and having a first face and a second face opposite to the first face. The package also comprises a thermal dissipation element having a first face and a second face opposite to the first face. The second face of the thermal dissipation element is proximate to the first face of the IC chip and is coupled to the first face of the IC chip through a first coupling material. The second face of the thermal dissipation element extends laterally so that it overhangs the first face to the plurality of leads. The package further comprises a plurality of wires linking the plurality of leads to the IC chip. Each of the plurality of wires has a first end electrically conductively joined to the first face of the IC chip, wherein the first end is disposed between the second face of the thermal dissipation element and the first face of the IC chip. Each of the plurality of wires also has a second end electrically conductively joined to the first face of one of the plurality of leads, wherein the second end is disposed between the second face of the thermal dissipation element and the first face of the one of the plurality of leads.[0017]
• According to one aspect of the third exemplary embodiment of the present invention, the thermal dissipation element is further coupled to the first face of each of the plurality of leads through a second coupling material.[0018]
• According to another aspect of the third exemplary embodiment of the present invention, the IC package further comprises an annular element and at least one secondary wire linking the IC chip to the annular element. The annular element is substantially laterally disposed between the IC chip and the plurality of leads, so that the annular element substantially encircles the IC chip. Each of the secondary wires comprises a first end electrically conductively joined to the first face of the IC and a second end electrically conductively joined to the first face of the annular element.[0019]
BRIEF DESCRIPTION OF THE DRAWINGS
• These and other features, aspects, and advantages of the present invention will become better understood with reference to the following description, amended claims, and accompanying drawings, which should not be read to limit the invention in any way, in which:[0020]
• FIG. 1 is a cross-section of a conventional IC package.[0021]
• FIG. 2 is a cross-section of an IC package according to a first exemplary embodiment of the present invention.[0022]
• FIG. 3 is a cross-section of an IC package according to an aspect of the first exemplary embodiment of the present invention.[0023]
• FIG. 4 is a cross-section of an IC package according to another aspect of the first exemplary embodiment of the present invention.[0024]
• FIG. 5 is a cross-section of an IC package according to a second exemplary embodiment of the present invention.[0025]
• FIG. 6 is a cross-section of an IC package according to a third exemplary embodiment of the present invention.[0026]
• FIGS. 7A through 7G are cross-sections of an IC package in consecutive steps of a manufacturing process according to an exemplary embodiment of the present invention.[0027]
• FIGS. 7H and 7I are additional cross-sections and plane views of the IC package manufacturing process of FIGS. 7A through 7G.[0028]
• FIGS. 8 and 9 are plane views of leadframes according to exemplary aspects of the present invention.[0029]
• FIGS. 10 and 11 are cross-sections of a die pad according to exemplary aspects of the present invention.[0030]
• FIGS. 12 through 15 are cross-sections of IC packages according to alternate embodiments of the present invention.[0031]
DETAILED DESCRIPTION OF THE INVENTION
• The present invention will be explained in further detail with reference to the accompanying drawings.[0032]
• FIG. 2 illustrates a cross-section of an IC package according to a first exemplary embodiment of the present invention. The[0033]IC package200 comprises a plurality ofleads201, each having afirst face201aand a second face201bopposite to the first face. Hereinafter, the terms “first” and “second” are merely used for convenience and do not reflect the order of formation, placement, or observation. Adie pad202, as shown has afirst face202aand a second face202bopposite to the first face. Thedie pad202 is orthogonally offset from theleads201, so that the second face202bof thedie pad202 is not coplanar with the second face201bof the leads. The leads201 and thedie pad202 can be composed of a common copper alloy, such as C194, C7025, C151, or Eftec64T, for example.
• An[0034]IC chip203, is disposed, typically laterally, between theleads201 and has a first face203aand asecond face203bopposite to the first face. The first face203aof theIC chip203 is coupled to the second face202bof thedie pad202 by an adhesive or the like, which may comprise for example, electrically conductive or non-conductive epoxy, paste or adhesive film, or the like as would be understood by those skilled in the art, and are intended to be encompassed here.
• The[0035]IC package200 also comprises a plurality ofwires205 that link theleads201 to theIC chip203. Thewires205 can be composed of gold, gold with some level of impurities, aluminum or copper, for example. For use in thewires205, the gold may contain 1% impurities. These impurities could include dopants or additives included to improve the properties of the wires as would be understood by one of skill in the art. Thewires205 are positioned so as to minimize the profile of thetotal IC package200. As such, the first end205aof each of the wires is electrically conductively joined to the first face203aof theIC chip203. This first connection point at the first end205ais positioned so that it falls between two planes defined within the package. A plane260 is defined by the second face202bof thedie pad202. A plane270 is defined by the first face203aof theIC chip203. The first connection point at the first end205abetweenwire205 and the first face203aof theIC chip203 is positioned between plane260 and plane270. The second end205bof each of the wires is electrically conductively joined to thefirst face201aof alead201. This second connection point at second end205bis positioned so that it falls between two other planes defined within the package. A plane250 is defined by thefirst face202aof thedie pad202. A plane280 is defined by thefirst face201aof thelead201. The second connection point at second end205bbetweenwire205 and thefirst face201aof thelead201 is positioned between plane250 and plane280. This positioning of the connection points of thewires205 allows thewires205 to be substantially sandwiched between thedie pad202 and theIC chip203, so as to reduce the size of the overall package profile. The planes270 and280 are typically, but need not be coplanar or parallel to each other. Alternative arrangements would be known and understood by those skilled in the art and are intended to be encompassed by this description.
• According to one aspect of the first exemplary embodiment of the present invention, the[0036]first face202aof the die pad is adapted to direct coupling with a heat sink, which is discussed below, with reference to FIGS. 3 and 4. This adaptation may, for example, involve maintaining thefirst face202aof thedie pad202 from any encapsulant, thus providing a surface for direct coupling with a heat sink.
• According to another aspect of the first exemplary embodiment of the present invention, the IC package further comprises an[0037]encapsulant206 that surrounds the first face203aof the IC chip, thefirst face201aof the leads, thewires205, and the second face202bof the die pad. Theencapsulant206 provides overall protection to the elements it surrounds and gives added strength and support to the package. The encapsulant can be a polymer-based molding compound or any other of many known encapsulant materials. According to this aspect of the first exemplary embodiment, thefirst face202aof thedie pad202 is adapted to direct coupling with a thermal dissipation element, for example, a heat sink. As discussed above, such an adaptation may, for example, involve maintaining thefirst face202aof thedie pad202 exposed and not covered by theencapsulant206. In this way, a heat sink can be coupled directly to thefirst face202aof thedie pad202. Further, aplanar surface207 can be formed comprising thefirst face202aof thedie pad202 and an outer surface of theencapsulant206, that can provide a supporting surface for the thermal dissipation element.
• According to a further aspect of the first exemplary embodiment of the present invention, and with reference to FIGS. 3 and 4 respectively, a thermal dissipation element, such as, but not limited to, for example,[0038]heat sink310 or system-level heat sink410, is coupled to thefirst face202aof the die pad. This coupling allows heat generated within theIC package300 or400, to be dissipated to the external environment through the thermal dissipation element. The thermal dissipation element can be affixed directly to thefirst face202aof thedie pad202, or it can be coupled through a connectinglayer311. The connectinglayer311 may be composed of any form of suitable media, such as film, thermally conductive epoxy, electrically conductive or non-conductive epoxy, or thermal grease, for example. Importantly, the direct coupling of the thermal dissipation element to the first surface of the IC chip provides a highly efficient medium for dissipating heat that is easily and economically achieved.
• FIG. 5 illustrates a cross-section of an IC package according to a second exemplary embodiment of the present invention. As described above with reference to FIG. 2, the[0039]IC package500 of FIG. 5 comprises a plurality ofleads201, adie pad202, anIC chip203, and a plurality ofwires205. These elements are described with reference to FIG. 2, and are disposed and interconnected as therein described.
• The[0040]IC package500 of FIG. 5 further comprises anannular element520.Annular element520 is disposed between the plurality ofleads201 and theIC chip203. In this position, the annular element substantially encirclesIC chip203.IC package500 also comprises at least onesecondary wire521, which links theannular element520 to theintegrated IC chip203. As discussed with reference to the plurality ofwires205, the at least onesecondary wire521 may be composed of gold, gold with some level of impurities, aluminum or copper, for example. Further, as with the plurality ofwires205, the at least onesecondary wire521 is positioned so as to minimize the profile of thetotal package500. As such, the first end521aofsecondary wire521 is electrically conductively joined to the first face203aof theIC chip203 at a first connection point. The first connection point of the first end521ais positioned so that it falls between plane260 and plane270, defined, respectively, by thesecond face202aof the die pad and the first face203aof the IC chip. The second end521bofsecondary wire521 is electrically conductively joined to the first face520aof theannular element520 as a second connection point. The connection point at end521bis positioned so that it falls between plane250 and plane290 defined, respectively, by the first face of thedie pad202aand the first face of the annular element520a.
• According to two aspects of the second exemplary embodiment of the present invention, the[0041]annular element520 can be electrically grounded, or can comprise a power source.Annular element520 can also be shaped in a number of ways. Preferably,annular element520 is shaped so that it is easy to manufacture and so that it contains few, if any, hard corners or edges that would create unwanted anomalies in any electrical field it generates. With these considerations in mind, annular element can be, for example, circular, elliptical, or polygonal.
• The IC package according to the second exemplary embodiment of the present invention can further comprise an[0042]encapsulant206, as described above in reference to the first exemplary embodiment of the present invention.
• The IC package according to the second exemplary embodiment of the present invention can also further comprise a thermal dissipation element, as described above in reference to the first exemplary embodiment of the present invention.[0043]
• FIG. 6 illustrates a cross-section of an IC package according to a third exemplary embodiment of the present invention. As described above in reference to FIG. 2 and the first exemplary embodiment, the IC package[0044]600 comprises a plurality ofleads201, anIC chip203, and a plurality ofwires205. These elements are described in reference to the first exemplary embodiment and are disposed in and interconnected as therein described.
• The IC package[0045]600 of FIG. 6 further comprises athermal dissipation element615, for example, a heat sink, having at least a first face615aand a second face615bopposite to the first face615a.The second face615b,of thethermal dissipation element615, is coupled to the first face203aof the IC chip, through afirst coupling material616. Thefirst coupling material616 is preferably thermally conductive to allow for optimal heat dissipation from theIC chip203 through to thethermal dissipation element615. Thefirst coupling material616 may also be electrically conductive.
• According to an aspect of the third exemplary embodiment, and as illustrated in FIG. 6, the[0046]thermal dissipation element615 may extend laterally to overhang thefirst face201aof theleads201. According to this aspect, the second face615bof the thermal dissipation element may also be coupled to thefirst face201aof theleads201 though asecond coupling material617. Thesecond coupling material617 is preferably thermally conductive to allow for optimal heat dissipation from theleads201 through to thethermal dissipation element615. The second coupling material may be selected so that it is not electrically conductive. Further, if more than one of the leads are to have a common electrical source while others are not, those having a common electrical source may be coupled with an electrically conductive material while the others are coupled with an electrically non-conductive material. An additional benefit of coupling thethermal dissipation element615 to theleads201 is the additional strength and support thus given to the package. According to this aspect, the plurality ofwires205 are sandwiched between thethermal dissipation element615 and theleads201 and theIC chip203.
• According to another aspect, the IC package according to the third exemplary embodiment of the present invention further comprises an[0047]encapsulant206, as described above in reference to the first exemplary embodiment of the present invention. According to this aspect, theencapsulant206 surrounds thefirst face201aof theleads201, the first face203aof theIC circuit203, the plurality ofwires205, and the second face615bof thethermal dissipation element615.
• According to yet another aspect, the IC package according to the third exemplary embodiment of the present invention further comprises the[0048]annular element520 and at least onesecondary wire521, as described above in reference to the second exemplary embodiment of the present invention.
• With reference to FIGS. 10 and 11, the[0049]die pad202 of the above-mentioned exemplary embodiments, can be diepad1002 or diepad1102, respectively.Die pad1002 in FIG. 10 has afirst face1002asimilar to thefirst face202aofdie pad202.Die pad1002 also has asecond face1002bsimilar to the second face202bofdie pad202. However, diepad1002 also has a cut-out portion1035 at the periphery ofsecond face1002bwith an inset surface1002c.The edge formed betweensecond face1002band inset surface1002ccan serve as a reference guide to the dispensing of anadhesive component1004 used to couple thedie pad1002 to another component, such asIC chip203. The inset surface1002cmay further provide overflow space and may prevent the unwanted spread of adhesive in the event that theadhesive component1004 overflows from thesecond face1002. Further, the inset surface1002cis on a different plane from thesecond face1002bso that ifdie pad1002 is made to extend laterally to overlap withwire205, illustrated in FIG. 2,clearance space1035 is provided forwire205 at connection points205aand205b.
• [0050]Die pad1102 in FIG. 11 has afirst face1102asimilar to thefirst face202aofdie pad202.Die pad1102 also has asecond face1102bsimilar to second face202bofdie pad202. However, thesecond face1102bofdie pad1102 has acavity1130. As withdie pad1002, thecavity1130 of thedie pad1102 may serve as a reference guide to the dispensing of anadhesive component1004, and may serve to prevent overflow of theadhesive component1004 into unwanted areas.
• With reference to FIGS. 8 and 9, respectively, the plurality of[0051]leads201 and thedie pad202 of the above-mentioned embodiments can be formed from aleadframe840 or aleadframe940 as shown.Leadframe840 in FIG. 8 comprises anouter frame842, which supports the plurality ofleads201 extending substantially inward from theouter frame842.Leadframe840 further comprises a plurality of tie bars843 securing theouter frame842 to thedie pad202, which is substantially centrally located within theleadframe840. Each of the plurality of tie bars843 has amechanical depression841. Themechanical depression841 creates an orthogonal offset between thedie pad202 and the plurality of leads201.
• With reference to FIG. 9,[0052]leadframe940 can further comprise anannular element520. Theannular element520 is disposed between thedie pad202 and the plurality ofleads201 and is connected to the leadframe through the plurality of tie bars843. Themechanical depressions841 are disposed inside theannular element520. In this way, themechanical depressions841 create an orthogonal offset between thedie pad202 and theannular element520 and the plurality of leads201. Theannular element520 and the plurality ofleads201 can remain coplanar with respect to each other.
• Hereinafter, the elements discussed with respect to the following embodiments and aspects are similar, to those discussed with respect to the aforementioned embodiments and aspects and may comprise the same exemplary materials and constructions as discussed above.[0053]
• According to a fourth exemplary embodiment of the present invention, and with exemplary reference to FIG. 2, a method of assembling an IC package comprises providing a plurality of leads, for example leads[0054]201, each having a first face and a second face opposite to the first face, a die pad, for example diepad202, having a first face and a second face opposite to the first face, an IC chip, forexample IC chip203, having a first face and a second face opposite to the first face, and a plurality of wires, forexample wires205, each having a first end and a second end. The method further comprises orthogonally offsetting the second face of the die pad from the second face of the plurality of leads so that the second face of the die pad and the second face of the plurality of leads are not coplanar. The method further comprises disposing the IC chip substantially laterally between the plurality of leads, as illustrated byIC chip203 and the plurality ofleads201 illustrated in FIG. 2. A further step of this method comprises coupling the first face of the IC chip to the second face of the die pad, through an adhesive or the like, discussed with respect to the first exemplary embodiment. A further step comprises electrically conductively joining the first end of each of the plurality of wires to the first face of the IC chip, as shown withwires205 andIC chip203 in FIG. 2. The step also comprises disposing the first end of each of the plurality of wires between a plane, such as plane260, defined by the second face of the die pad and a plane, such as plane280, defined by the first face of the IC chip. Further, a final step comprises electrically conductively joining the second end of each of the plurality of wires to the first face of one of the plurality of leads, as shown withwires205 and leads201 in FIG. 2. The step also comprises disposing the second end of each of the plurality of wires between a plane, such as plane250, defined by the first face of the die pad and a plane, such as plane270, defined by the first face of the plurality of leads.
• According to the fourth exemplary embodiment, the method further comprises encapsulating the first face of the IC chip, the first face of each of the plurality of leads, the plurality of wires, and the second face of the die pad with an encapsulant, such as[0055]encapsulant206 illustrated in FIG. 2. This aspect further comprises adapting the first face of the die pad to direct coupling with a thermal dissipation element, for example, a heat sink. According to another aspect of the fourth exemplary embodiment, a further step comprises forming a planar surface, for exampleplanar surface207 of FIG. 2, comprising the first face of the die pad and an outer surface of the encapsulant, thus forming a support surface for a heat sink.
• According to another aspect of the fourth exemplary embodiment, a further step comprises coupling a thermal dissipation element to the first face of the die pad. The thermal dissipation element can be, but is not limited to, for example,[0056]heat sink310 of FIG. 3 or system-level heat sink410 of FIG. 4.
• According to a fifth exemplary embodiment of the present invention, and with exemplary reference to FIG. 5, a method of assembling an IC package comprises providing a plurality of leads, for example, leads[0057]201, each having a first face and a second face opposite to the first face, a die pad, for example, diepad202, having a first face and a second face opposite to the first face, an IC chip, for example,IC chip203, having a first face and a second face opposite to the first face, a plurality of wires, forexample wires205, each having a first-end and a second end, an annular element, for exampleannular element520, having a first face and a second face opposite to the first face, and at least one secondary wire, forexample wire521 having a first end and a second end. A further step comprises orthogonally offsetting the second face of the die pad from the second face of the plurality of leads so that the second face of the die pad and the second face of the plurality of leads are not coplanar. The method further comprises disposing the IC chip substantially laterally between the plurality of leads, as illustrated, for example, byIC chip203 and plurality ofleads201 in FIG. 5, and coupling the first face of the IC chip to the second face of the die pad, as illustrated for example byIC chip203 coupled to diepad202. In a following step, the method comprises substantially laterally disposing the annular element between the IC chip and the plurality of leads so that the annular element substantially encircles the IC chip, as shown, for example, byannular element520 illustrated in FIG. 5. Further steps comprise electrically conductively joining the first end of each of the plurality of wires to the first face of the IC chip and electrically conductively joining the second end of each of the plurality of wires to the first face of one of the plurality of leads, as shown, for example, bywires205 illustrated in FIG. 5. Further, the method comprises, electrically conductively joining the first end of each of the at least one secondary wires to the first face of the IC chip, and electrically conductively joining the second end of each of the at least one secondary wires to the first face of the annular element, as shown, for example, bysecondary wire521 illustrated in FIG. 5.
• According to one aspect of the fifth exemplary embodiment, a further step comprises electrically grounding the annular element. In this way, the annular element serves as a ground for the IC chip and any other devices that it may be electrically coupled to.[0058]
• According to another aspect of the fifth exemplary embodiment, a further step comprises coupling the annular element to a power source.[0059]
• According to a sixth exemplary embodiment of the present invention, and with exemplary reference to FIGS. 6 and 7A-[0060]7I, a method of assembling an IC package comprises providing a plurality ofleads201, anIC chip203, athermal dissipation element615, and a plurality ofwires205. FIGS.7A-7I, illustrate consecutive steps in the method according to this exemplary embodiment. In a first step, shown in FIG. 7A, anadhesive layer711 is applied to aleadframe740 forming the plurality ofleads201, and a plurality oflands719, shown in FIG. 7H, for a thermal dissipation element. Theadhesive layer711 is used to support the IC chip during attachment. The adhesive layer can be composed a number of materials as discussed with respect to above-described adhesive layers. Theleadframe740 is created without any obvious die pad portion. In a second step, shown in FIG. 7B, asecond face203bof theIC chip203 is attached to theadhesive layer711. In a third step, shown in FIG. 7C, the plurality ofwires205 are connected to link theIC chip203 to the plurality ofleads201, thus providing the necessary electrical paths. In a fourth step, shown in FIGS. 7D, 7H, and7I, an adhesive616 is disposed on a first face203 a of theIC chip203, and an adhesive617 is disposed on the plurality oflands719. A second face615bof thethermal dissipation element615 is then attached to theIC chip203 and the plurality oflands719 through these adhesive layers. According to one aspect of this exemplary embodiment, the thermal dissipation element can be further attached to the plurality ofleads201 through an electrically non-conductive material. The material can be either thermally conductive, thereby providing added heat dissipation for the plurality ofleads201, or may be thermally non-conductive, providing additional support for the overall structure. In a fifth step, shown in FIG. 7E, anencapsulant606 is applied to the package to encompass theIC chip203, the plurality ofdie pads201, the plurality ofwires205, and all but the first face615aof thethermal dissipation element615. The encapsulant provides protection for the IC chip. In a sixth step, shown in FIG. 7F, theadhesive layer711 is removed. Also,unnecessary material718 from the edges of the package is mechanically removed, thus forming the proper footprint for the package.
• According to one aspect of the present invention according to the sixth exemplary embodiment thereof, the method further comprises providing an[0061]annular element520, as shown in FIG. 6. theannular element520 may be formed as a part of theleadframe740. At least onesecondary wire521 is provided, linking theIC chip203 to theannular element520.
• FIGS. 12 and 13 illustrate IC packages according to alternate embodiments of the present invention. FIG. 12 shows an IC package[0062]1200 comprising adie pad1202 present below achip1203. Thechip1203 is attached to thedie pad1202 with anadhesive component1204, which can be formed of a conductive or non-conductive epoxy, or an adhesive film or tape. Ametal lid1215 is attached to thechip1203 with anadhesive component1211, which can be formed of the same exemplary materials asadhesive component1204.
• FIG. 13 illustrates an[0063]IC package1300, similar to IC package1200.IC package1300 utilizes an alternative attachment of themetal lid1215, positioned up-side-down in comparison to the positioning illustrated in FIG. 12.
• FIG. 14 illustrates an IC package according to another alternative embodiment of the present invention. In comparison to the IC packages of FIGS. 12 and 13, instead of comprising a metal lid,[0064]IC package1400 compriseselement1425, which may be a dummy chip or a glass lid.
• FIG. 15 illustrates an IC package according to yet another alternative embodiment of the present invention.[0065]IC package1500 comprises adie pad1502 formed of a conductive metal attached toleads1501 throughadhesive component1508. AnIC chip1503 is mounted on thedie pad1502 throughadhesive component1504.Wires1505connect IC chip1503 toleads1501, forming an electrical path for signal transmission. An encapsulant1506bseals all the components. An additional encapsulant1506amay be disposed under thedie pad1502 to provide added structure to the overall package.
• Although the above exemplary embodiments of the present invention have been described, it will be understood by those skilled in the art that the present invention should not be limited to the described exemplary embodiments, but that various changes and modifications can be made within the spirit and scope of the present invention. Accordingly, the scope of the present invention is not limited to the described range of the following claims.[0066]

Claims (24)

What is claimed is:

1. An integrated circuit package comprising:

a) a plurality of leads each having a first face and a second face opposite to said first face;

b) a die pad having a first face and a second face opposite to said first face, wherein said second face of said die pad is orthogonally offset from said second face of said leads, such that said second face of said die pad and said second face of said leads are not coplanar;

c) an integrated circuit chip substantially laterally disposed between said plurality of leads and having a first face and a second face opposite to said first face, whereby said first face of said integrated circuit chip is proximate to said second face of said die pad and is coupled to said second face of said die pad; and

d) a plurality of wires linking said plurality of leads to said integrated circuit chip, each of said plurality of wires comprising:

a first end electrically conductively joined to said first face of said IC chip, wherein said first end is disposed between a plane defined by said second face of said die pad and a plane defined by said first face of said integrated circuit chip, and

a second end electrically conductively joined to said first face of one of said plurality of leads, wherein said second end is disposed between a plane defined by said first face of said die pad and a plane defined by said first face of one of said plurality of leads.

2. The integrated circuit package according toclaim 1, wherein said first face of said die pad is adapted to direct coupling with a thermal dissipation element.

3. The integrated circuit package according toclaim 1, further comprising:

e) an encapsulant surrounding said first face of said integrated circuit chip, said first faces of said plurality of leads, said wires, and said second face of said die pad, and wherein said first face of said die pad is adapted to direct coupling with a thermal dissipation element.

4. The integrated circuit package according toclaim 3, wherein said encapsulant is a polymer-based molding compound.

5. The integrated circuit package according toclaim 3, wherein a planar surface is formed comprising said first face of said die pad and an outer surface of said encapsulant.

6. The integrated circuit package according toclaim 1, wherein said plurality of leads and said die pad are composed of a common copper alloy.

7. The integrated circuit package according toclaim 1, wherein said plurality of wires are composed of one of a group comprising: gold, gold with some level of impurities, aluminum, and copper.

8. The integrated circuit package according toclaim 1, further comprising:

e) a thermal dissipation element having a first face and a second face opposite to said first face, wherein said second face of said thermal dissipation element is coupled to said first face of said die pad

9. The integrated circuit package according toclaim 8, wherein said thermal dissipation element comprises a heat sink for a single integrated circuit chip

10. The integrated circuit package according toclaim 8, wherein said thermal dissipation element comprises a heat sink for a plurality of integrated circuit chips.

11. The integrated circuit package according toclaim 1, wherein:

said second face of said die pad comprises:

an inner surface,

a peripheral surface, and

an edge defining the boundary between said inner surface and said peripheral surface; and

wherein the space between said inner surface and said first face is greater than the space between said peripheral surface and said first face, such that said inner portion is offset from said peripheral portion.

12. The integrated circuit according toclaim 1, wherein said second face of said die pad comprises:

an inner surface,

a peripheral surface, and

a reservoir defining the boundary between said inner surface and said peripheral surface.

13. the integrated circuit package according toclaim 1, wherein:

said plurality of leads and said die pad are formed from a leadframe, said leadframe comprising:

an outer frame supporting said plurality of leads extending substantially inward from said outer frame, and

a plurality of tie bars securing said outer frame to said die pad, substantially centrally disposed within said outer frame; and

wherein each of said plurality of tie bars includes a mechanical depression, such that an offset is created between said die pad and said plurality of leads.

14. An integrated circuit package comprising:

a) a plurality of leads each having a first face and a second face opposite to said first face;

b) a die pad having a first face and a second face opposite to said first face, wherein said second face of said die pad is orthogonally offset from said second face of said leads, such that said second face of said die pad and said second face of said leads are not coplanar;

c) an integrated circuit chip substantially laterally disposed between said plurality of leads and having a first face and a second face opposite to said first face, whereby said first face of said integrated circuit chip is proximate to said second face of said die pad and is coupled to said second face of said die pad;

d) a plurality of wires linking said plurality of leads to said integrated circuit chip, each comprising:

a first end electrically conductively joined to said first face of said integrated circuit chip, and

a second end electrically conductively joined to said first face of one of said plurality of leads;

e) an annular element substantially laterally disposed between said integrated circuit chip and said plurality of leads such that said annular element substantially encircles said integrated circuit chip; and

f) at least one secondary wire liking said integrated circuit chip to said annular element, each having:

a first end electrically conductively joined to said first face of said integrated circuit chip, and

a second end electrically conductively joined to said first face of said annular element.

15. The integrated circuit package according toclaim 14, wherein said annular element is electrically grounded.

16. The integrated circuit package according toclaim 14, wherein said annular element comprises a power source.

17. The integrated circuit package according toclaim 14, wherein said annular element is circular.

18. The integrated circuit package according toclaim 14, wherein said annular element is elliptical.

19. The integrated circuit package according toclaim 14, wherein said annular element is a polygon.

20. An integrated circuit package comprising:

a) a plurality of leads each having a first face and a second face opposite to said first face;

b) an integrated circuit chip substantially laterally disposed between said plurality of leads, and having a first face and a second face opposite to said first face;

c) a thermal dissipation element having a first face and a second face opposite to said first face,

wherein said second face of said thermal dissipation element is proximate to said first face of said integrated circuit chip and is coupled to said first face of said integrated circuit chip through a first coupling material, and

wherein said second face of said thermal dissipation element extends laterally such that it overhangs said first face of each of said plurality of leads; and

d) a plurality of wires linking said plurality of leads to said integrated circuit chip, each comprising:

a first end electrically conductively joined to said first face of said integrated circuit chip, wherein said first end is disposed between said second face of said thermal dissipation element and said first face of said integrated circuit chip, and

a second end electrically conductively joined to said first face of one of said plurality of leads, wherein said second end is disposed between said second face of said thermal dissipation element and said first face of said one of said plurality of leads.

21. The integrated circuit package according toclaim 20, wherein said thermal dissipation element comprises a heat sink.

22. The integrated circuit package according toclaim 20, wherein said second face of said thermal dissipation element is further coupled to said first face of each of said plurality of leads through a second coupling material.

23. The integrated circuit package according toclaim 22, wherein said second coupling material is electrically non-conductive.

24. The integrated circuit package according toclaim 22, wherein said second coupling material is thermally conductive.

d) an annular element substantially laterally disposed between said integrated circuit chip and said plurality of leads, such that said annular element substantially encircles said integrated circuit chip; and

e) at least one secondary wire connecting said integrated circuit chip to said annular element, each of said at least one secondary wires comprising:

a first end electrically conductively joined to said first face of said integrated circuit chip, and

a second end electrically conductively joined to said first face of said annular element.

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