US20040114413A1 - Memory and access devices - Google Patents

Abstract

Briefly, in accordance with an embodiment of the invention, a memory is provided. The memory may include a memory element and a first access device coupled to the memory element, wherein the first access device comprises a first chalcogenide material. The memory may further include a second access device coupled to the first access device, wherein the second access device comprises a second chalcogenide material.

Description

BACKGROUND
• Phase change memory devices use phase change materials, i.e., materials that may be electrically switched between a generally amorphous and a generally crystalline state, for electronic memory application. One type of memory element utilizes a phase change material that may be, in one application, electrically switched between a structural state of generally amorphous and generally crystalline local order or between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states. The state of the phase change materials are also non-volatile in that, when set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until changed by another programming event, as that value represents a phase or physical state of the material (e.g., crystalline or amorphous).[0001]
• A transistor or a diode may be connected to the phase change material and may serve as a select device to access the phase change material during programming or read operations. The transistor or diode is typically formed in or on the top surface of a silicon single crystal substrate. Transistors may take up a relatively large portion of the memory chip, and therefore may increase the memory cell size, thereby adversely affecting the memory capacity and cost/bit of a memory chip.[0002]
BRIEF DESCRIPTION OF THE DRAWINGS
• The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The present invention, however, both as to organization and method of operation, together with objects, features, and advantages thereof, may best be understood by reference to the following detailed description when read with the accompanying drawings in which:[0003]
• FIG. 1 is a schematic diagram illustrating a memory in accordance with an embodiment of the present invention;[0004]
• FIG. 2 is a diagram illustrating a current-voltage characteristic of a select device;[0005]
• FIG. 3 is a cross-sectional view of a select device in accordance with an embodiment of the present invention;[0006]
• FIG. 4 is a cross-sectional view of a portion of a memory in accordance with an embodiment of the present invention;[0007]
• FIG. 5 is a cross-sectional view of a portion of the memory of FIG. 1 during fabrication in accordance with an embodiment of the present invention;[0008]
• FIG. 6 is a cross-sectional view of the structure of FIG. 5 at a later stage of fabrication;[0009]
• FIG. 7 is a cross-sectional view of the structure of FIG. 6 at a later stage of fabrication;[0010]
• FIG. 8 is a cross-sectional view of the structure of FIG. 7 at a later stage of fabrication;[0011]
• FIG. 9 is a cross-sectional view of the structure of FIG. 8 at a later stage of fabrication;[0012]
• FIG. 10 is a cross-sectional view of the structure of FIG. 9 at a later stage of fabrication;[0013]
• FIG. 11 is a cross-sectional view of the structure of FIG. 10 at a later stage of fabrication;[0014]
• FIG. 12 is a cross-sectional view of the structure of FIG. 11 at a later stage of fabrication;[0015]
• FIG. 13 is a cross-sectional view illustrating a memory array in accordance with an embodiment of the present invention;[0016]
• FIG. 14 is a schematic diagram illustrating a memory in accordance with an embodiment of the present invention;[0017]
• FIG. 15 is a cross-sectional view illustrating a portion of a memory in accordance with another embodiment of the present invention;[0018]
• FIG. 16 is a cross-sectional view illustrating a memory cell in accordance with an embodiment of the present invention;[0019]
• FIG. 17 is a schematic diagram illustrating a memory in accordance with another embodiment of the present invention; and[0020]
• FIG. 18 is a cross-sectional view of a portion of the memory illustrated in FIG. 17 in accordance with an embodiment of the present invention; and[0021]
• FIG. 19 is a diagram illustrating a current-voltage characteristic of a memory cell; and[0022]
• FIG. 20 is a block diagram illustrating a portion of a system in accordance with an embodiment of the present invention.[0023]
• It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.[0024]
DETAILED DESCRIPTION
• Phase change memory devices use phase change materials, i.e., materials that may be electrically switched between a generally amorphous and a generally crystalline state, for electronic memory application. One type of memory element utilizes a phase change material that may be, in one application, electrically switched between a structural state of generally amorphous and generally crystalline local order or between different detectable states of local order across the entire spectrum between completely amorphous and completely crystalline states. The state of the phase change materials are also non-volatile in that, when set in either a crystalline, semi-crystalline, amorphous, or semi-amorphous state representing a resistance value, that value is retained until changed by another programming event, as that value represents a phase or physical state of the material (e.g., crystalline or amorphous).[0025]
• A transistor or a diode may be connected to the phase change material and may serve as a select device to access the phase change material during programming or read operations. The transistor or diode is typically formed in or on the top surface of a silicon single crystal substrate. Transistors may take up a relatively large portion of the memory chip, and therefore may increase the memory cell size, thereby adversely affecting the memory capacity and cost/bit of a memory chip.[0026]
DETAILED DESCRIPTION
• In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.[0027]
• In the following description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.[0028]
• Turning to FIG. 1, an embodiment of a[0029]memory100 is illustrated.Memory100 may include a 3×3 array of memory cells111-119, wherein memory cells111 -119 each include aselect device120 and amemory element130. Although a 3×3 array is illustrated in FIG. 1, the scope of the present invention is not limited in this respect.Memory100 may have a larger array of memory cells.
• In one embodiment,[0030]memory elements130 may comprise a phase change material. In this embodiment,memory100 may be referred to as a phase change memory. A phase change material may be a material having electrical properties (e.g. resistance, capacitance, etc.) that may be changed through the application of energy such as, for example, heat, light, voltage potential, or electrical current. Examples of a phase change material may include a chalcogenide material or an ovonic material.
• An ovonic material may be a material that undergoes electronic or structural changes and acts as a semiconductor when subjected to application of a voltage potential, an electrical current, light, heat, etc. An ovonic material may be used in a memory element or in an electronic switch. A chalcogenide material may be a material that includes at least one element from column VI of the periodic table or may be a material that includes one or more of the chalcogen elements, e.g., any of the elements of tellurium, sulfur, or selenium.[0031]
• [0032]Memory100 may include column lines141-143 and row lines151-153 to select a particular memory cell of the array during a write or read operation. Column lines141-143 and row lines151-153 may also be referred to as address lines since these lines may be used to address memory cells111-119 during programming or reading. Column lines141-143 may also be referred to as bit lines and row lines151-153 may also be referred to as word lines.
• [0033]Memory elements130 may be connected to row lines151-153 and may be coupled to column lines141-143 viaselect devices120. Therefore, when a particular memory cell (e.g., memory cell115) is selected, voltage potentials may be applied to the memory cell's associated column line (e.g.,142) and row line (e.g.,152) to apply a voltage potential across the memory cell.
• [0034]Select device120 may be used to accessmemory element130 during programming or reading ofmemory element130.Select device120 may operate as a switch that is either “off” or “on” depending on the amount of voltage potential applied across the memory cell. The off state may be a substantially electrically nonconductive state and the on state may be a substantially conductive state. For example,select device120 may have a threshold voltage and if a voltage potential less than the threshold voltage ofselect device120 is applied acrossselect device120, then selectdevice120 may remain “off ” or in a relatively high resistive state so that little or no electrical current passes through the memory cell. Alternatively, if a voltage potential greater than the threshold voltage ofselect device120 is applied acrossselect device120, then selectdevice120 may “turn on,” i.e., operate in a relatively low resistive state so that electrical current passes through the memory cell. In other words,select device120 may be in a substantially electrically nonconductive state if less than a predetermined voltage potential, e.g., the threshold voltage, is applied acrossselect device120.Select device120 may be in a substantially conductive state if greater than the predetermined voltage potential is applied acrossselect device120.Select device120 may also be referred to as an access device, an isolation device, or a switch.
• In one embodiment,[0035]select device120 may comprise a switching material such as, for example, a chalcogenide or an ovonic material, and may be referred to as an ovonic threshold switch, or simply an ovonic switch. The switching material ofselect device120 may be a material in a substantially amorphous state positioned between two electrodes that may be repeatedly and reversibly switched between a higher resistance “off” state (e.g., greater than about ten mega-ohms) and a relatively lower resistance “on” state (e.g., about zero ohms) by application of a predetermined electrical current or voltage potential. In this embodiment,select device120 may be a two terminal device that may have a current-voltage (I-V) characteristic similar to a phase change memory element that is in the amorphous state. However, unlike a phase change memory element, the switching material ofselect device120 may not change phase. That is, the switching material ofselect device120 may not be a programmable material, and as a result,select device120 may not be a memory device capable of storing information. For example, the switching material ofselect device120 may remain permanently amorphous and the I-V characteristic may remain the same throughout the operating life. An example of an I-V characteristic ofselect device120 is shown in FIG. 2.
• Turning to FIG. 2, in the low voltage or low electric field mode, i.e., where the voltage applied across[0036]select device120 is less than a threshold voltage (labeled V_TH),select device120 may be “off” or nonconducting, and exhibit a relatively high resistance, e.g., greater than about 10 mega-ohms.Select device120 may remain in the off state until a sufficient voltage, e.g., V_TH, is applied, or a sufficient current is applied, e.g., I_TH, that may switchselect device120 to a conductive, relatively low resistance on state. After a voltage potential of greater than about V_THis applied acrossselect device120, the voltage potential acrossselect device120 may drop (“snapback”) to a holding voltage potential, labeled V_H. Snapback may refer to the voltage difference between V_THand V_Hof a select device.
• In the on state, the voltage potential across[0037]select device120 may remain close to the holding voltage of V_Has current passing throughselect device120 is increased.Select device120 may remain on until the current throughselect device120 drops below a holding current, labeled I_H. Below this value,select device120 may turn off and return to a relatively high resistance, nonconductive off state until the V_THand I_THare exceeded again.
• Although the scope of the present invention is not limited in this respect, in one embodiment,[0038]select device120 may have a threshold voltage (V_TH) of about 5.3 volts, a holding voltage (V_TH) of about 0.8 volts, a threshold current (I_TH) of about 4 nano-amps, and a holding current (I_H) of about 100 nano-amps. By adjusting the thickness and type of material, the V_THmay be about 2 volts and the holding voltage about one volt. This may allow the snapback to be less than the V_THof the series memory element to avoid the possibility of read disturb if the snapback exceeds V_THof the memory element, encouraging it to turn on and drive the capacitance of the column and row lines, adversely passing current which could reduce the resistance of the memory element when the memory element is in the reset state.
• FIG. 3 illustrates an embodiment of[0039]select device120. In this embodiment,select device120 may include abottom electrode210 and a switchingmaterial220 overlyingbottom electrode210. In other words, switchingmaterial220 may be formed over and contactingbottom electrode210. In addition,select device120 may include atop electrode230overlying switching material220.
• Although the scope of the present invention is not limited in this respect,[0040]bottom electrode210 may be a thin film material having a film thickness ranging from about 20 Angstroms (Å) to about 2000 Å. In one embodiment, the thickness ofelectrode210 may range from about 100 Å to about 1000 Å. In another embodiment, the thickness ofelectrode210 may be about 300 Å. Suitable materials forbottom electrode210 may include a thin film of titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), carbon (C), silicon carbide (SiC), titanium aluminum nitride (TiAIN), titanium silicon nitride (TiSiN), polycrystalline silicon, tantalum nitride (TaN), some combination of these films, or other suitable conductors or resistive conductors compatible with switchingmaterial220.
• Although the scope of the present invention is not limited in this respect, switching[0041]material220 may be a thin film material having a thickness ranging from about 20 Å to about 2000 Å. In one embodiment, the thickness of switchingmaterial220 may range from about 200 Å to about 1000 Å. In another embodiment, the thickness of switchingmaterial220 may be about 500 Å.
• [0042]Switching material220 may be formed overlyingbottom electrode210 using a thin film deposition technique such as, for example, a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD).Switching material220 may be a thin film of a chalcogenide material or an ovonic material in a substantially amorphous state that may be repeatedly and reversibly switched between a higher resistance “off” state and a relatively lower resistance “on” state by application of a predetermined electrical current or voltage potential.Switching material220 may not be a programmable material capable of storing information. In other words, switchingmaterial220 may be a nonprogammable material.
• Although the scope of the present invention is not limited in this respect, switching[0043]material220 may comprise a chalcogen other than oxygen. In one embodiment, switchingmaterial220 may comprise tellurium and/or selenium. In another embodiment, switchingmaterial220 may comprise silicon (Si), tellurium (Te), arsenic (As), and germanium (Ge), or combinations of these elements. In other embodiments, a composition for switchingmaterial220 may include an alloy of silicon (Si), tellurium (Te), arsenic (As), germanium (Ge), and indium (In) or an alloy of Si, Te, As, Ge, and phosphorous (P).
• Although the scope of the present invention is not limited in this respect, in one example, the composition of switching[0044]material220 may comprise a Si concentration of about 14%, a Te concentration of about 39%, an As concentration of about 37%, a Ge concentration of about 9%, and an In concentration of about 1%. In another example, the composition of switchingmaterial220 may comprise a Si concentration of about 14%, a Te concentration of about 39%, an As concentration of about 37%, a Ge concentration of about 9%, and a P concentration of about 1%. In these examples, the percentages are atomic percentages which total 100% of the atoms of the constituent elements.
• In another embodiment, a composition for switching[0045]material220 may include an alloy of arsenic (As), tellurium (Te), sulfur (S), germanium (Ge), selenium (Se), and antimony (Sb) with respective atomic percentages of 10%, 21%, 2%, 15%, 50%, and 2%.
• Although the scope of the present invention is not limited in this respect, in other embodiments, switching[0046]material220 may include Si, Te, As, Ge, sulfur (S), and selenium (Se). As an example, the composition of switchingmaterial220 may comprise a Si concentration of about 5%, a Te concentration of about 34%, an As concentration of about 28%, a Ge concentration of about 11%, a S concentration of about 21%, and a Se concentration of about 1%.
• [0047]Top electrode230 may be a thin film material having a thickness ranging from about 20 angstroms (Å) to about 2000 Å. In one embodiment, the thickness ofelectrode230 may range from about 100 Å to about 1000 Å. In another embodiment, the thickness ofelectrode230 may be about 300 Å. Suitable materials fortop electrode230 may include a thin film of titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), carbon (C), silicon carbide (SiC), titanium aluminum nitride (TiAIN), titanium silicon nitride (TiSiN), polycrystalline silicon, tantalum nitride (TaN), some combination of these films, or other suitable conductors or resistive conductors compatible with switchingmaterial220.
• In one embodiment, top electrode and bottom electrode may comprise carbon and may have a thickness of about 500 Å.[0048]Top electrode230 may also be referred to as an upper electrode andbottom electrode210 may also be referred to as a lower electrode. In this embodiment,select device120 may be referred to as a vertical structure since electrical current may flow vertically through switchingmaterial220 betweentop electrode230 andbottom electrode210.Select device120 may be referred to as a thin film select device if thin films are used for switchingmaterial220 andelectrodes210 and230.
• The threshold current (I[0049]_TH) ofselect device120 may be less than the threshold current for an ovonic memory device set in a high resistance, amorphous state. The threshold voltage (V_TH) ofselect device120 may be altered by changing process variables such as, for example, the thickness or alloy composition of switchingmaterial220. For example, increasing the thickness of switchingmaterial220 may increase the threshold voltage ofselect device120. The holding voltage (V_H) ofselect device120 may be altered or set by the type of contact to switchingdevice120, e.g., the composition ofelectrodes210 and230 may determine the holding voltage ofselect device120.
• For example, in one embodiment, if the thickness of switching[0050]material220 composed of silicon (Si), tellurium (Te), arsenic (As), and germanium (Ge) is about 300 Å, andelectrodes210 and230 are layers of carbon (C), then the threshold voltage ofselect device120 may be about two volts and the holding voltage ofselect device120 may be about one volt. Alternatively, ifelectrodes210 and230 are, layers of TiSiN with a thickness of about 300 Å, then the holding voltage ofselect device120 may be about 0.8 volts. In another embodiment, ifelectrodes210 and230 are layers of TiAIN with a thickness of about 300 Å, then the holding voltage ofselect device120 may be about 0.4 volts. In yet another embodiment, ifelectrodes210 and230 are layers of cobalt silicide, then the holding voltage ofselect device120 may be about 0.15 volts.
• [0051]Select device120 may provide a relatively high “on current” for a given area of a device compared to other switching devices such as, for example, metal-oxide-semiconductor (MOS) transistors or bipolar junction transistors (BJTs). The relatively higher on current ofselect device120 in the on state may allow for a relatively higher programming current available to selectdevice120 to program a memory element (e.g.,130).
• The memory array shown in FIG. 1 using[0052]select device120 illustrated in FIG. 3 may be constructed by stackingselect device120 andmemory element130 in a vertical configuration. An example of a vertical structure comprisingselect device120 formed overmemory element130 is illustrated in FIG. 4.
• Turning to FIG. 4, an embodiment of a portion of[0053]memory100 is illustrated.Memory100 may comprise asubstrate240, an insulatingmaterial260overlying substrate240, and aconductive material270 overlying insulatingmaterial260.Conductive material270 may be an address line (e.g., row line152). Aboveconductive material270, an opening (not shown in FIG. 4) may be formed in an insulatingmaterial280. In the opening, alower electrode340 may be formed. Overelectrode340, sequential layers of amemory material350,electrode material360,barrier material370,electrode210, switchingmaterial220,electrode230, and aconductive material380 may be deposited to form a vertical memory cell structure.Conductive material380 may be an address line (e.g., column line142).
• In the embodiment illustrated in FIG. 4,[0054]memory material350 andelectrodes340 and360 may formmemory element130. Ifmemory material350 is an ovonic material or a chalcogenide material, thenmemory element130 may be referred to as a phase change memory device or an ovonic memory device. Further, in the embodiment illustrated in FIG. 4,select device120 is formed overmemory element130 to form a vertical structure or a vertical stack. In alternate embodiments,memory element130 may be formed aboveselect device120 to form a vertical structure. In the embodiment illustrated in FIG. 4,select device120 andmemory element130 are formed using only thin film materials, and the vertical stack may be referred to as a thin film vertical stack.
• A thin film material may be a particular class of insulating or conducting material deposited onto a substrate or other materials and may have a specified thickness, e.g., thin film materials may refer to materials having a thickness ranging from greater than zero Å to less than about 25,000 Å. In addition, thin film materials may be materials deposited using thin film deposition techniques such as, for example, PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or PECVD (Plasma Enhanced Chemical Vapor Deposition), etc.[0055]
• Other embodiments may include variations in the vertical structure. For example, in one embodiment,[0056]barrier material370 may be eliminated from the vertical structure. In another embodiment,barrier material370 may be eliminated from the vertical structure andelectrode360 may be combined withelectrode210 into a single conductive layer to form a single electrode. Further, in another embodiment,electrode230 may be combined withconductive material380 to form a single conductive layer or single electrode.
• [0057]Memory material350 may be a phase change, programmable material capable of being programmed into one of at least two memory states by applying a current tomemory material350 to alter the phase ofmemory material350 between a substantially crystalline state and a substantially amorphous state, wherein a resistance ofmemory material350 in the substantially amorphous state is greater than the resistance ofmemory material350 in the substantially crystalline state.
• Programming of[0058]memory material350 to alter the state or phase of the material may be accomplished by applying voltage potentials toconductive materials380 and270, thereby generating a voltage potential acrossselect device120 andmemory element130. When the voltage potential is greater than the threshold voltages ofselect device120 andmemory element130, then an electrical current may flow throughmemory material350 in response to the applied voltage potentials, and may result in heating ofmemory material350.
• This heating may alter the memory state or phase of[0059]memory material350. Altering the phase or state ofmemory material350 may alter the electrical characteristic ofmemory material350, e.g., the resistance of the material may be altered by altering the phase of thememory material350.Memory material350 may also be referred to as a programmable resistive material.
• In the “reset” state,[0060]memory material350 may be in an amorphous or semi-amorphous state and in the “set” state,memory material350 may be in an a crystalline or semi-crystalline state. The resistance ofmemory material350 in the amorphous or semi-amorphous state may be greater than the resistance ofmemory material350 in the crystalline or semi-crystalline state. It is to be appreciated that the association of reset and set with amorphous and crystalline states, respectively, is a convention and that at least an opposite convention may be adopted.
• Using electrical current,[0061]memory material350 may be heated to a relatively higher temperature toamorphosize memory material350 and “reset” memory material350 (e.g.,program memory material350 to a logic “0” value). Heating the volume ofmemory material350 to a relatively lower crystallization temperature may crystallizememory material350 and “set” memory material350 (e.g.,program memory material350 to a logic “1” value). Various resistances ofmemory material350 may be achieved to store information by varying the amount of current flow and duration through the volume ofmemory material350.
• [0062]Memory100 shown in FIG. 4 may be referred to as a vertical phase change memory structure since current may flow vertically between address lines throughselect device120 andmemory element130.
• In other embodiments,[0063]memory100 may be arranged differently and include additional layers and structures. For example, it may be desirable to form isolation structures, peripheral circuitry (e.g., addressing circuitry), transistors insubstrate240, etc. It should be understood that the absence of these elements in the drawings is not a limitation of the scope of the present invention.
• It should be noted that the memory structure illustrated in FIG. 4 does not use transistor or diode select devices. The memory structure illustrated in FIG. 4 may be constructed as a standalone array or arrays on a substrate or may be constructed as a process module inserted into a more complex process flow that builds other structures. For example, this module may be integrated into a full complementary metal-oxide-semiconductor (CMOS) process that may also build N-channel and P-channel transistors, their wiring interconnects, and other circuit elements. In such an embodiment, the row and column lines may be respectively driven by N and P channel transistors for reading and writing in ways apparent to one reasonably skilled in the art.[0064]
• Turning back to FIG. 1, an embodiment of an addressing scheme may be illustrated. For a selected memory element (e.g.,[0065]115), a “half select array biasing scheme” may be implemented, wherein a voltage of, for example, V volts, may be applied to the selected column line(e.g.,142) and approximately zero volts may be applied to the selected row line (e.g.,152).
• In one embodiment, termed the “half select array biasing scheme” for the case of programming a memory element, V may be chosen to be greater than the threshold voltage of select device[0066]120 (V_THSD)+the reset threshold voltage of memory element130 (V_THReset), but less than two times V_THSD. In other words (V_THSD+V_THReset) <V<(2*V_THSD). All unselected rows and columns may be biased at V/2. In this approach, there may be no voltage bias between unselected row lines and unselected column lines. This may reduce background leakage current. After successively biasing the memory array in this way, memory elements of the array may be programmed by successively forcing a current sufficient in magnitude and with a fast falling edge of less than about 5 nano-seconds for reset and slow falling edge greater than about 200 nano-seconds for the set state to change phase of the memory material
• For the case of reading a memory element, V may be chosen to be greater than the threshold voltage of select device[0067]120 (V_THSD), but less than the threshold voltage of select device120 (V_THSD)+the reset threshold voltage of memory element130 (V_THReset). In other words (V_THSD)<V<(V_THSD+V_THReset). All unselected rows and unselected columns may be biased at V/2. In this approach, there may be no voltage bias between unselected row lines and unselected column lines. This may reduce background leakage current. After biasing the memory array in this way, memory elements of the array may be successively read by successively forcing a relatively lower current or voltage than that required to write or disturb a bit, to determine resistance of the memory material of the memory elements. A forced voltage is less than the voltage that will exceed the threshold of the memory element yet great enough to result in detectably more current through a set bit than a reset bit. Alternately, a current less than I_THof the memory element may be forced through a bit. This current may cause a detectably smaller voltage drop across a set memory element than a reset memory element. For example, the reset current may be about 1.5 miliamps (ma) and I_THmay be greater than about 0.03 ma. Iread may be about 0.01 ma for a process with Rset less than about 10,000 ohms, so that the maximum drop across a set memory element may be under about 0.1 volts and I_THof the memory element is not exceeded. For a memory device with V_THof about 0.8 volts, the reset device may clamp the voltage across the memory device at about 0.6 volts without thresholding or snapping back. This will provide a read voltage difference between the set and reset state of about 0.6 volts minus about 0.1 or 0.5 volts, that may accommodate the variation in the hold voltages of the device switch and memory element.
• Another embodiment of an addressing scheme may be termed the “one-third select array biasing scheme.” This embodiment may improve deselect margin. In this embodiment, for the case of programming a memory element, a voltage of V volts may be applied to a selected column line and zero volts may be applied to the selected row line. V may be chosen to be greater than the threshold voltage of select device[0068]120 (V_THSD)+the reset threshold voltage of memory element130 (V_THReset), but less than three times V_THSD. In other words (V_THSD+V_THReset)<V<(3*V_THSD). All unselected rows may be biased at (2V)/3. All unselected columns may be biased at V/3. In this approach, there may be a voltage bias between unselected row lines and unselected column lines of approximately +/−V/3. This may provide additional manufacturing margin for variability of threshold voltages ofselect device120 andmemory element130. After biasing the memory array in this manner, memory elements of the array may be programmed by forcing a current sufficient to change the phase of a memory material.
• For the case of reading a memory element, a voltage of V may be chosen to be greater than the threshold voltage of select device[0069]120 (V_THSD), but less than the threshold voltage of select device120 (V_THSD)+the reset threshold voltage of memory element130 (V_THReset). In other words (V_THSD)<V<(V_THSD+V_THReset). All unselected rows may be biased at (2V)/3. All unselected columns may be biased at V/3. In this approach, there may be a voltage bias between unselected row lines and unselected column lines of approximately +/−V/3. This may provide additional manufacturing margin for variability of threshold voltage ofselect device120. After biasing the memory array in this manner, memory elements of the array may be read by forcing a relatively lower current to determine resistance of the memory material of the memory elements such as by the methods used in the V/2 approach discussed above in the half select approach.
• Programming a selected memory cell may include biasing unselected row and unselected column lines as discussed above in the “half select array biasing scheme” and “one-third select array biasing scheme” embodiments. On the selected column line, a current may be forced with a compliance that may be greater than the threshold voltage of selected[0070]device120 and the threshold voltage ofmemory element130. The current amplitude, duration, and pulse shape may be selected to place the memory element in the desired phase or memory state.
• Reading a selected memory cell of the array may include biasing unselected row and column lines as discussed above in the “half select array biasing scheme” and “one-third select array biasing scheme” embodiments. Combinations of these schemes for conventional use that reflect margin needs, array sizes, and leakage requirements in the product may allow one reasonably skilled in the art to determine the appropriate bias voltages that will meet product specifications which may vary by application. Zero volts may be applied to the selected row line and a voltage V applied on the selected column line. The current compliance of this forced voltage may be less than the current that may program or disturb the present phase or memory state of the memory element. If the memory element is in a “reset” state, the memory element may not switch “on” and may present a relatively large voltage, low current condition to a sense amplifier (not shown). The sense amplifier may either compare the resulting column voltage to a reference voltage or compare the resulting column current to a reference current.[0071]
• FIGS.[0072]5-12 may be used to illustrate an embodiment to fabricate or manufacture a portion ofmemory100. In particular, FIGS.5-12 may be used to illustrate an embodiment to fabricateselect device120 andmemory element130.
• Turning to FIG. 5,[0073]memory100 may comprise asubstrate240 that may be, for example, a semiconductor substrate (e.g., a silicon substrate), although the scope of the present invention is not limited in this respect. Other suitable substrates may be, but are not limited to, substrates that contain ceramic material, organic material, or a glass material.
• A layer of insulating[0074]material260 may be formed over and contactingsubstrate240. Insulatingmaterial260 may be a dielectric material that may be a thermally and/or electrically insulating material such as, for example, silicon dioxide, although the scope of the present invention is not limited in this respect. Insulatingmaterial260 may have a thickness ranging from about 300 Å to about 10,000 Å, although the scope of the present invention is not limited in this respect. Insulatingmaterial260 may be planarized using a chemical or chemical-mechanical polish (CMP) technique.
• A thin film of a[0075]conductive material270 may be formed overlying insulatingmaterial270 using, for example, a PVD process.Conductive material270 may be patterned using photolithographic and etch techniques to form a small width in the y-direction (orthogonal to the view shown in FIG. 5). The film thickness ofconductive material270 may range from about 20 Å to about 2000 Å. In one embodiment, the thickness ofconductive material270 may range from about 200 Å to about 1000 Å. In another embodiment, the thickness ofconductive material270 may be about 500 Å.
• [0076]Conductive material270 may be an address line of memory100 (e.g.,row line151,152, or153).Conductive material270 may be, for example, a tungsten (W) film, a doped polycrystalline silicon film, a Ti film, a TiN film, a TiW film, an aluminum (Al) film, a copper (Cu) film, or some combination of these films. In one embodiment,conductive material270 may be a polycrystalline silicon film with a resistance lowering strap of a refractory silicide on its top surface, similar to a poly gate used in CMOS over a thick filed oxide, although the scope of the present invention is not limited in this respect.
• An insulating[0077]material280 may be formed overlyingconductive material270 using, for example, a PECVD (Plasma Enhanced Chemical Vapor Deposition) process, HDP (High Density Plasma) process, or spin-on and bake SOLGEL process. Insulatingmaterial280 may be a dielectric material that may be a thermally and/or electrically insulating material such as, for example, silicon dioxide, although the scope of the present invention is not limited in this respect. Insulatingmaterial280 may have a thickness ranging from about 100 Å to about 4000 Å, although the scope of the present invention is not limited in this respect. In one embodiment, the thickness of insulatingmaterial280 may range from about 500 Å to about 2500 Å. In another embodiment, the thickness of insulatingmaterial280 may be about 1200 Å.
• Although the scope of the present invention is limited in this respect, insulating[0078]material280 may be planarized using a chemical or CMP technique. The resulting thickness of insulatingmaterial280 may range from about 20 Å to about 4000 Å. In one embodiment, after planarizing insulatingmaterial280, the thickness of insulatingmaterial280 may range from about 200 Å to about 2000 Å. In another embodiment, the thickness of insulatingmaterial280 may be about 900 Å.
• A[0079]sacrificial film410 may be deposited overlying insulatingmaterial280.Sacrificial film410 may be, for example, a silicon nitride (SiN) film or a polycrystalline silicon film. The thickness ofsacrificial film410 may range from about 20 Å to about 4000 Å. In one embodiment, the thickness ofsacrificial film410 may range from about 200 Å to about 2000 Å. In another embodiment, the thickness ofsacrificial film410 may be about 1000 Å.
• [0080]Sacrificial film410 may be patterned using photolithographic and etch techniques to formopenings415 havingsidewalls416.Openings415 may be holes, vias or trenches, although the scope of the present invention is not limited in this respect.
• In one embodiment,[0081]openings415 may be formed using photolithographic and etch techniques. As an example,openings415 may be formed by applying a layer of photoresist material (not shown) onsacrificial film410 and exposing this photoresist material to light. A mask (not shown) may be used to expose selected areas of the photoresist material, which defines areas to be removed, i.e., etched. The etch may be a chemical etch, which may be referred to as a wet etch. Or, the etch may be a plasma (ion bombardment) etch, which may be referred to as a dry etch. Ifopenings415 are formed using photolithographic techniques, the diameter or width ofopenings415 may be at least one minimum feature size.
• The minimum feature size of a structure may refer to the minimum dimension achievable using photolithography. For example, the minimum feature size may refer to a width of a material or spacing of materials in a structure. As is understood, photolithography refers to a process of transferring a pattern or image from one medium to another, e.g., as from a mask to a wafer, using a certain wavelength or wavelengths of light. The minimum feature size of the transferred pattern that is available in state of the art IC manufacturing may be limited by the limitations of the wavelength of the light source. Distances, sizes, or dimensions less than the minimum feature size may be referred to as sub-lithographic distances, sizes, or dimensions. For example, some photolithographic processes may have minimum feature sizes of about 2500 angstroms. In this example, a sub-lithographic distance may refer to a feature having a width of less than about 2500 angstroms.[0082]
• Several techniques may be used to achieve sub-lithographic dimensions. Although the scope of the present invention is not limited in this respect, phase shift mask, electron beam lithography, or x-ray lithography may be used to achieve sub-lithographic dimensions. Electron beam lithography may refer to a direct-write lithography technique using a beam of electrons to expose resist on a wafer. X-ray lithography may refer to an advanced lithographic process for transferring patterns to a silicon wafer in which the electromagnetic radiation used is X-ray, rather than longer wavelength radiation. The shorter wavelength for X-rays (e.g., about 10-200 angstroms, versus about 2000-3000 angstroms for ultra-violet radiation) may reduce diffraction, and may be used to achieve feature sizes of about 1000 angstroms and less. Also, sidewall spacers may be used to achieve sub-lithographic dimensions. FIG. 6 may be used to illustrate the use of[0083]sidewall spacers420 to achieve sub-lithographic dimensions.
• FIG. 6 depicts the structure of FIG. 5, through the same cross-sectional view, after forming[0084]sidewall spacers420. In one embodiment,sidewall spacers420 may be formed along sidewalls416 of asacrificial film410. The distance betweensidewalls416 may be one feature size and may be formed using photolithographic and etch techniques.Sidewall spacers420 may be formed by depositing a layer of silicon nitride, poly silicon, or another sacrificial material in the space betweensidewalls416 and patterning this material using a dry etch such as, for example, an anisotropic etch.
• The distance between[0085]sidewall spacers420 may be sub-lithographic. Aftersidewall spacers420 are formed, in one embodiment, another anisotropic etch may be used to form an opening430 (FIG. 7) inthin film280 having a sub-lithographic diameter.
• Turning to FIG. 7, in one embodiment,[0086]sacrificial film410 andspacers420 may be used as a hard mask and insulatingmaterial280 may be anisotropically etched using an etching agent that is selective such that the etching agent stops at, or preserves,conductive material270.
• As shown in FIG. 7, the etching operation exposes a portion of[0087]conductive material270 throughopening430. In one aspect,sidewall spacers420 may serve to reduce the quantity of electrode material (e.g.,340 shown in FIG. 8) formed inopening430. In one embodiment, the diameter ofopening430 may be less than about 1000 angstroms, although the scope of the present invention is not limited in this respect.
• It should be pointed out that the use of[0088]sidewall spacers420 to form opening430 is not a limitation of the present invention. Other sub-lithographic methods, as mentioned above, may be used to form opening430, wherein opening430 may have a sub-lithographic diameter. Or, in alternate embodiments, opening430 may be formed using photolithographic techniques and may therefore, have a diameter of greater than or equal to about one minimum feature size.
• [0089]Sacrificial film410 andspacers420 may be removed after formingopening430. For example,sacrificial film410 andspacers420 may be selectively etched while preserving insulatingmaterial280 andconductive material270.
• FIG. 8 illustrates[0090]memory100 after the conformal deposition of anelectrode material340 over insulatingmaterial280 and in opening430 (FIG. 7).Electrode material340 may be a layer of C, SiC, TiSIN, TIAIN, polycrystalline silicon, TaN, some combination of these, or other suitable resistive conductors. As an example,electrode material340 may be formed using a chemical vapor deposition (CVD) process, however, the scope of the present invention is not limited by the particular process used to formelectrode material340. It should also be understood that alternative processes may be used to formelectrode material340. As an example, ALD (Atomic Layer Deposition) may be used.
• Following introduction of[0091]electrode material340, the structure shown in FIG. 8 may be subjected to a planarization that removes a portion ofelectrode material340 and may remove a portion of insulatinglayer280. Suitable planarization techniques may include a chemical or CMP technique. Other techniques may also be used topattern materials340 and280. For example, a blanket etch may be used to remove portions of insulatinglayer280 andelectrode material340. FIG. 9 illustrates the structure shown in FIG. 8 after patterning ofelectrode material340.
• FIG. 10 illustrates the structure of FIG. 9 at a later stage of fabrication. A thin film of[0092]memory material350 may be deposited overlying insulatingmaterial280 andelectrodes340.
• [0093]Memory material350 may be formed using, for example, a PVD process.Memory material350 may be a programmable material such as, for example, a phase change material.Memory material350 may be an ovonic material or a chalcogenide material. The thickness ofmemory material350 may range from about 20 Å to about 4000 Å. In one embodiment, the thickness ofmemory material350 may range from about 200 Å to about 1000 Å. In another embodiment, the thickness ofmemory material350 may be about 500 Å.
• [0094]Electrode material360 may be depositedoverlying memory material350.Electrode material360 may be formed using, for example, a PVD process.Electrode material360 may be Ti, TiN, TiW, C, SiC, TIAIN, TiSiN, polycrystalline silicon, TaN, some combination of these, or other suitable conductors or resistive conductors. The thickness ofelectrode material360 may range from about 20 Å to about 2000 Å. In one embodiment, the thickness ofelectrode material360 may range from about 100 Å to about 1000 Å. In another embodiment, the thickness ofelectrode material360 may be about 300 Å.
• [0095]Barrier material370 may be deposited overlyingelectrode material360.Barrier material370 may be formed using, for example, a PVD process.Barrier material370 may be Ti, TiN, TiW, C, SiC, TIAIN, TiSiN, polycrystalline silicon, TaN, some combination of these, or other suitable conductors or resistive conductors that provide a barrier betweenelectrode materials360 and210. In one embodiment, barrier material may be composed of TiN and Ti films. The thickness ofbarrier material370 may range from about 20 Å to about 2000 Å. In one embodiment, the thickness ofbarrier material370 may range from about 100 Å to about 1000 Å. In another embodiment, the thickness ofbarrier material370 may be about 300 Å.
• [0096]Electrode210 may be depositedoverlying barrier material370 using, for example, a PVD process.Switching material220 may be depositedoverlying electrode210 using, for example, a PVD process andelectrode230 may be deposited overlying switchingmaterial220 using, for example, a PVD process. Examples of compositions and thicknesses ofelectrode210, switchingmaterial220, andelectrode230 are discussed above with reference to FIG. 3.
• In one embodiment, thin film layers[0097]350,360,370,210,220, and230 or a subset thereof, may be deposited by means of a PVD process, in-situ. That is, all layers may be deposited sequentially in a sputter deposition tool without venting back to atmospheric pressure or exposure to atmospheric gases between each thin film layer deposition.
• FIG. 11 illustrates the structure shown in FIG. 10 after patterning of[0098]materials230,220,210,370,360, and350 using, for example, photolithographic and etch techniques, to form three cylindrical orbox structures500. Cylinder shaped structures may be achieved using a single photo/single etch process. Box shaped structures may be achieved using a dual photo/single etch process. In alternate embodiments, box shaped structures may be achieved using a single photo/single etch/single photo/single etch process. Although three cylindrical or box structures are illustrated, this is not a limitation in the present invention. For example, in other embodiments, more than three cylinder or box shaped structures may be formed.
• In addition, FIG. 11 illustrates[0099]memory100 after the conformal deposition of an insulatingmaterial510 on a portion of a top surface of insulatingmaterial280, and along the sidewalls and top surface ofstructures500. Insulatingmaterial510 may be a silicon dioxide or silicon nitride material. Insulatingmaterial510 may have a thickness ranging from about 20 Å to about 10,000 Å. In one embodiment, the thickness of insulatingmaterial510 may range from about 100 Å to about 1000 Å. In another embodiment, the thickness of insulatingmaterial510 may be about 250 Å. Insulatingmaterial510 may be deposited at a relative cooler temperature, e.g., in the range of 200-600 degrees Celsius, and in one embodiment, at a temperature of about 250 degrees Celsius.
• An[0100]interlayer insulator520 may be deposited overlying insulatingmaterial510.Interlayer insulator520 may be, for example, a silicon dioxide deposited using a high density plasma (HDP) process.Interlayer insulator520 may have a thickness ranging from about300 A to about20,000 A. In one embodiment, the thickness ofinterlayer insulator520 may range from about 2000 Å to about 10,000 Å. In another embodiment, the thickness ofinterlayer insulator520 may be about 6000 Å.
• FIG. 12 illustrates the structure shown in FIG. 11 after planarization of[0101]materials510,520, and possibly230 using, for example, a CMP process.Conductive materials380 may be formed over and contactingelectrodes230 by, for example, depositing a layer of aluminum and patterning this layer using photolithographic and etch techniques to form parallel strips that extend in the y-direction (orthogonal to the x-direction shown in FIG. 12).Conductive materials380 may be address lines such as, for example, column lines141-143 schematically illustrated in FIG. 1. As may be appreciated, column lines141-143 may be orthogonal to row lines151-153.
• Other suitable materials for[0102]conductive layer380 may include a tungsten (W) film, a doped polycrystalline silicon film, a Ti film, a TiN film, a TiW film, a copper film, or some combination of these films. In one embodiment,conductive material380 may be a polycrystalline silicon film with a resistance lowering strap of a cobalt silicide (CoSi₂) on its top surface.Conductive material380 may have a thickness ranging from about 100 Å to about 20,000 Å. In one embodiment, the thickness ofconductive material380 may range from about 300 Å to about 5000 Å. In another embodiment, the thickness ofconductive material380 may be about 2000 Å.
• In the embodiment illustrated in FIG. 12,[0103]memory material350 andelectrodes340 and360 may form memory element130 (FIG. 1).Switching material220 andelectrodes210 and230 may form select device120 (FIG. 1).
• Memory arrays using the structure illustrated in FIG. 12 may be manufactured using thin films for the memory elements and select devices. In this type of an array, single crystal silicon devices such as MOS transistors or BJTs are not used in the memory array. Thus, it may be possible to vertically stack memory arrays on top of one another which may increase memory density with a relatively small increase in wafer processing costs. FIG. 13 illustrates an example of a four layer stack of memory arrays in accordance with an embodiment of the present invention.[0104]
• Although not shown in FIG. 13, on-chip transistors, peripheral circuitry, and/or address circuitry may be positioned under the memory array. This may reduce chip die area. Memory array efficiency may be defined as the percentage of the total product chip area that is made up of memory cells compared to the amount of chip area that is used for other circuitry. In one embodiment, memory efficiency of 90% or higher may be achieved by using the thin film memory structures as discussed above along with placing on-chip transistors, peripheral circuitry, and/or address circuitry underneath the memory array. Alternately, SRAM may be placed under the memory array in available places to increase the bandwidth of writing to the chip for later data placement in the non-volatile memory portion of the chip.[0105]
• Stacked multi-layer arrays may gain access to on chip CMOS transistor pitched array support subcircuits such as, for example, row drivers, column drivers, and sense-amps, as schematically illustrated in FIG. 14. Turning to FIG. 14, a[0106]memory600 is illustrated.
• [0107]Memory600 may includememory cells630 coupled betweenrow lines610 andcolumn lines620 which may run orthogonal to rowlines610.Memory cells630 may include a vertically stacked, thin film select device and a memory element such as a phase change memory element as discussed herein. In other words,memory cells630 may include a vertical structure that includes a select device and a memory element such as a phase change memory element that are formed using thin film materials.
• [0108]Support subcircuits640 may be undermemory cells630 and may be coupled to rowlines610 and column lines620. These subcircuits may comprise drive and sense transistors for the array, and also other support circuits helpful for efficient use of the memory in a system such as, for example, cache SRAM memory. Placingsupport subcircuits640 under the memory array in this manner may increase memory efficiency and may economically allow fewer bits per row line and per column line. This may have the advantage of increasing speed for read and write operations due to reduced parasitic resistance and capacitance and may also provide for more efficient redundancy schemes.
• FIG. 15 illustrates another embodiment of[0109]memory100. In this embodiment, a row line is formed using a salicided single crystal active region of N+ or P+. For example, a row line may be formed using aP region720, anN+ region730, and arefractory salicide strap740 of, for example, CoSi₂, TiSi₂, or NiSi₂. This row line may be coupled toelectrodes340 via conductive plugs710. Conductive plugs710 may be surrounded by an insulatingmaterial750, such as, for example, a silicon dioxide. Conductive plugs710 may be, for example, tungsten, and may include a liner (not shown) of, for example, Ti and/or TiN. In an alternate embodiment, not shown,conductive material380 may be coupled toelectrode230 via a conductive plug.
• FIG. 16 illustrates an alternate embodiment of a memory cell (e.g.,[0110]115) ofmemory100. Although the scope of the present invention is not limited in this respect, in this embodiment,memory cell115 may include anelectrode830, a switchingmaterial820overlying electrode830, and anelectrode810overlying switching material820 to conduct current between the switchingmaterial820 andmemory material850. In addition,memory cell115 may include amemory material850overlying electrode810. In other words,electrode810 may be under and contactingmemory material850. Further,memory cell115 may include anelectrode840overlying memory material850.
• [0111]Memory cell115 is a vertical structure that may be formed of thin film materials and may be formed over a substrate (not shown ).Select device120 may include switchingmaterial820 along with it's upper andlower electrodes810 and830 respectively, andmemory element130 may includememory material850 along with it's upper andlower electrodes840 and810, respectively.
• [0112]Switching material820 may be formed using the same or similar materials, and using the same or similar techniques as described herein for switchingmaterial220. Further,memory material850 may be formed of the same or similar materials, and using the same or similar techniques as described herein formemory material350.
• [0113]Electrodes830 and840 may serve as address lines(e.g., column or row lines).Electrodes830,810, and840 may be composed of materials similar to, or the same as the examples discussed herein formaterials380,370,230,210,360, and340. In one embodiment,electrodes830,810, and840 may be a layer of carbon, although the scope of the present invention is not limited in this respect. In addition, the thickness of, and the techniques used to formmaterials380,370,230,210,360, and340 may be used to formelectrodes830,810, and840.
• FIG. 17 is a schematic diagram illustrating another embodiment of[0114]memory100. In this embodiment, memory cells111-119 each includeselect device120, aselect device125, andmemory element130. In this embodiment, the total snapback may be reduced to allow use of a lower threshold memory element. For example, if the total V_THfor the pair of ovonic switches is about two volts, the individual V_THof each switch may be about one volt by appropriate choice of the switching material thickness. If the V_Hof each is, for example, 0.8 volts, the snapback may be reduced to about 0.4 volts total from about 1.2 volts if a single device is used. Such a stacked series set of switch devices may reduce the tendency to disturb a bit during read. Such a stack may be comprised of one switch, two switches, or more switches in series with the memory element, all placed between the row and column line assisting reliable memory selection and operation.
• As is illustrated,[0115]memory element130 andselect devices120 and125 are connected in a serial arrangement. In one embodiment,select devices120 and125 may be ovonic switches andmemory element130 may be an ovonic memory.
• Turning to FIG. 18, an embodiment of a memory cell (e.g.,[0116]115) ofmemory100 is illustrated in accordance with another embodiment of the present invention.Memory cell115 may comprisesubstrate240, insulatingmaterial260overlying substrate240, andconductive material270 overlying insulatingmaterial260.Conductive material270 may be an address line (e.g., row line152). Aboveconductive material270,electrode340 may be formed between portions of insulatingmaterial280. Overelectrode340, sequential layers of amemory material350,electrode material360, a switchingmaterial920, anelectrode material930, a switchingmaterial940, anelectrode material950, and aconductive material980 may be deposited to form a vertical memory cell structure.Conductive material980 may be an address line (e.g., column line142).
• The embodiment of[0117]memory cell115 illustrated in FIG. 18 may be formed using similar materials and manufacturing techniques as discussed with reference to FIGS.5-12 and15. In the embodiment illustrated in FIG. 18,select devices125 and120 are formed overmemory element130 to form a serially coupled, thin film vertical structure or vertical stack. In alternate embodiments,memory element130 may be formed aboveselect devices120 and125 ormemory element130 may be formed betweenselect devices120 and125 to form a serially coupled, thin film vertical structure. In the embodiment illustrated in FIG. 18,select devices120 and125 andmemory element130 may be formed using thin film materials, and the vertical stack may be referred to as a thin film vertical stack.
• In the embodiment illustrated in FIG. 18,[0118]memory material350 andelectrodes340 and360 may formmemory element130.Memory material350 may be an ovonic material or a chalcogenide material and may be referred to as an ovonic memory.Switching material920 andelectrodes360 and930 may formselect device125.Switching material920 may be formed using similar materials and similar manufacturing techniques used to form switchingmaterial220 described herein.Switching material940 andelectrodes930 and950 may formselect device120.Switching material940 may be formed using similar materials and similar manufacturing techniques used to form switchingmaterial220 described herein. In alternate embodiments, switchingmaterials920 and940 may be composed of the same material or different materials. For example, in one embodiment, switchingmaterial920 may be composed of a chalcogenide material and switchingmaterial940 may be composed of another different chalcogenide material.
• In one embodiment,[0119]select devices120 and125 may be ovonic switches andmemory element130 may be an ovonic memory andmemory cell115 may be referred to as an ovonic memory cell. As discussed above, an example of an I-V characteristic forselect device120 is shown in FIG. 2.Select device125 may have an I-V characteristic similar to that illustrated in FIG. 2.
• Turning to FIG. 19, an example of an I-V characteristic of[0120]memory cell115, which may includememory element130 andselect devices120 and125 in this embodiment, is shown. The holding voltage ofmemory cell115, labeled V_H, may result from the holding voltages ofselect devices120 and125 andmemory element130. The threshold voltage ofmemory cell115 may be equal to the combined threshold voltages ofmemory element130 andselect devices120 and125.
• As may be appreciated from the discussion herein, the threshold voltage of a select device or an ovonic switch may be determined by the thickness or alloy composition of the switching material of the ovonic switch and the holding voltage of an ovonic switch may be determined by the composition of the electrodes contacting the switching material of the ovonic switch. Accordingly, in one embodiment, the snapback voltage, i.e., the voltage difference between the threshold and holding voltages of an ovonic switch, may be reduced by reducing the thickness of the switching material and using a particular type of electrode.[0121]
• For example, referring to select[0122]device120 illustrated in FIG. 18, ifelectrodes930 and950 are carbon layers and if the thickness of switchingmaterial940 is about 200 Å, then the holding voltage ofselect device120 may be about one volt and the threshold voltage ofselect device120 may be about 1.2 volts. In this example, the snapback voltage may be about 0.2 volts, which is the difference between the holding and threshold voltages ofselect device120.
• In the embodiment illustrated in FIG. 18,[0123]memory cell115 may include two ovonic switches serially coupled to an ovonic memory to decrease the voltage difference between the holding voltage and the threshold voltage of a memory cell when higher switching and holding voltages are desired. In other words, rather than using one ovonic switch, two ovonic switches may be serially coupled to an ovonic memory to decrease “snapback” of a memory cell, i.e., reduce the voltage difference between the threshold and holding voltages of an ovonic memory cell when higher switching and holding voltages are desired.
• In one embodiment,[0124]electrodes360,930, and950 may be carbon, the thickness of switchingmaterial920 may be about 200 Å, and the thickness of switchingmaterial940 may be about 200 Å. In this embodiment, the threshold voltage ofselect device120 may be about 1.2 volts and the holding voltage ofselect device120 may be about one volt. The threshold voltage ofselect device125 may be about 1.2 volts and the holding voltage ofselect device125 may be about one volt. If the threshold voltage of reset/setmemory element130 is about 0.8/0.0 volts, then the threshold voltage ofmemory cell115 may be about 3.2/2.4 volts formemory cell115 in a reset state and set state, respectively, which is the combined threshold voltages ofmemory element130 andselect devices120 and125. That is, a voltage potential of greater than about 3.2 volts may be applied acrossmemory cell115 to “turn on”select devices120 and125 and conduct current throughmemory cell115. A voltage of greater than about 3.2 volts may be applied acrossmemory cell115 by applying a voltage potential of greater than about 3.2 volts tocolumn line142 and a voltage potential of about zero volts to rowline152.
• In this example, to program a selected memory cell, e.g.,[0125]memory cell115, a voltage of about 1.8 volts may be applied to unselected column and unselected row lines, e.g.,lines141,143,151, and153. A voltage of greater than about 3.2 volts may be applied to a selected column line, e.g.,142, and zero volts may be applied to a selected row line, e.g.,row line152. In this example, afterselect devices120 and125 “turn on,” then due to snapback, the voltage drop acrossmemory cell115 may be reduced from about 3.2 volts to about 2.0-2.8 volts depending on the cell's memory state and current provided by the column. Then, information may be stored inmemory element130 by forcing current throughmemory cell115 while assuring that the selected column line remains within about 2.4 volts of the unselected row lines biased at about 1.8 volts so that unselected memory cells are not disturbed. That is, the column may not be allowed to be higher than about 4.2 volts during programming.
• FIG. 19 may be used to graphically illustrate this example, wherein for the full memory cell (all 3 components taken together), V[0126]_THis 3.2/2.4 volts for a reset state and set state, respectively, and V_His 2.8 volts. The current throughmemory cell115 is near zero amperes until the threshold voltage, V_TH, of, for example, about 3.2 or 2.4 volts is exceeded, depending on whether the memory cell is in a reset or set state respectively. Then the voltage acrossmemory cell115 drops to (for a reset bit) or climbs to (for a set bit) the holding voltage, V_H, of, for example, about 2.8 volts, as the current is increased.
• To read the value of the information stored in the selected memory cell, in this example, a voltage of about 2.8 volts may be applied across[0127]memory cell115. The resistance ofmemory element130 may be sensed to determine ifmemory element130 is in a low resistance crystalline, “set” state (e.g., less than about 10,000 ohms) or ifmemory element130 is in a high resistance amorphous, “reset” state (e.g., greater than about 10,000 ohms).
• In another embodiment, to read the value of the information stored in the selected memory cell, a voltage of about 2.8 volts may be applied across[0128]memory cell115 by applying 2.8 volts to the selected column and zero volts to the selected row and 1.4 volts to all other unselected rows and columns. The resistance from the selected column to the selected row may be sensed to determine ifmemory element130 is in a low resistance crystalline, “set” state or ifmemory element130 is in a high resistance amorphous, “reset” state. In this embodiment, the series select devices may not “turn on” for the case of a reset state, thus also providing a high resistance between the selected column and selected row.
• It should be understood that the above examples are not a limitation of the present invention. Other holding voltages and threshold voltages may be achieved to alter the snapback of memory cells by altering the thickness of switching[0129]materials920 and940 and the compositions ofelectrodes360,930, and950. One advantage of reducing the snapback of a memory cell is that capacitive displacement current through the memory cell may be reduced, thus reducing the tendency to disturb a bit into a different state while reading.
• In other embodiments,[0130]memory cell115 illustrated in FIG. 18 may be arranged differently and include additional layers and structures. For example, it may be desirable to form isolation structures, barrier layers, peripheral circuitry (e.g., addressing circuitry), etc. The memory cell may instead be a ferro-electric or ferro-magnetic material with different phases programmed by different currents or polarity, and that result in different impedances when programmed to the different states. Alternately, the memory cell may be any other material or device benefiting from a small access device. It should be understood that the absence of these elements is not a limitation of the scope of the present invention.
• Turning to FIG. 20, a portion of a[0131]system860 in accordance with an embodiment of the present invention is described.System860 may be used in wireless devices such as, for example, a personal digital assistant (PDA), a laptop or portable computer with wireless capability, a web tablet, a wireless telephone, a pager, an instant messaging device, a digital music player, a digital camera, or other devices that may be adapted to transmit and/or receive information wirelessly.System860 may be used in any of the following systems: a wireless local area network (WLAN) system, a wireless personal area network (WPAN) system, a cellular network, although the scope of the present invention is not limited in this respect.
• [0132]System860 may include acontroller865, an input/output (I/O) device870 (e.g. a keypad, display), amemory875, and awireless interface880 coupled to each other via abus885. It should be noted that the scope of the present invention is not limited to embodiments having any or all of these components.
• [0133]Controller865 may comprise, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like.Memory875 may be used to store messages transmitted to or bysystem860.Memory875 may also optionally be used to store instructions that are executed bycontroller865 during the operation ofsystem860, and may be used to store user data.Memory875 may be provided by one or more different types of memory. For example,memory875 may comprise any type of random access memory, a volatile memory, a non-volatile memory such as a flash memory and/or a memory such asmemory100 discussed herein.
• I/[0134]O device870 may be used by a user to generate a message.System860 may usewireless interface880 to transmit and receive messages to and from a wireless communication network with a radio frequency (RF) signal. Examples ofwireless interface880 may include an antenna or a wireless transceiver, although the scope of the present invention is not limited in this respect.
• Although the scope of the present invention is not limited in this respect,[0135]system860 may use one of the following communication air interface protocols to transmit and receive messages: Code Division Multiple Access (CDMA), cellular radiotelephone communication systems, Global System for Mobile Communications (GSM) cellular radiotelephone systems, North American Digital Cellular (NADC) cellular radiotelephone systems, Time Division Multiple Access (TDMA) systems, Extended-TDMA (E-TDMA) cellular radiotelephone systems, third generation (3G) systems like Wide-band CDMA (WCDMA), CDMA-2000, or the like.
• It shall be further understood that the ovonic memory has a substantial dynamic range that, with the techniques used above and if necessary with feedback that can be realized by one reasonably skilled in the art, the physical memory cell may store more than one bit by writing and reading more than two non-overlapping ranges of resistance.[0136]
• While certain features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the invention.[0137]

Claims (25)

1. An apparatus, comprising:

a memory element;

a first access device coupled to the memory element, wherein the first access device comprises a first chalcogenide material; and

a second access device coupled to the first access device, wherein the second access device comprises a second chalcogenide material.

2. The apparatus ofclaim 1, further comprising a vertical structure over a substrate, wherein the vertical structure comprises the first access device, the second access device, and the memory element serially coupled to each other.

3. The apparatus ofclaim 1, wherein the first access device, the second access device, and the memory element are formed using thin film materials.

4. The apparatus ofclaim 1, wherein the second access device is over the first access device, and the first access device is over the memory element.

5. The apparatus ofclaim 1, wherein the first select device includes a switching material that is in a substantially amorphous state and is adapted to be repeatedly and reversibly switched between a higher resistance state and a relatively lower resistance state by application of a predetermined voltage or current.

6. The apparatus ofclaim 1, wherein the memory element comprises a phase change material that is capable of being programmed into one of at least two memory states by applying a current to the phase change material to alter the phase of the phase change material between a substantially crystalline state and a substantially amorphous state, wherein a resistance of the phase change material in the substantially amorphous state is greater than the resistance of the phase change material in the substantially crystalline state.

7. The apparatus ofclaim 1, wherein the memory element comprises a memory material over a substrate and wherein the first chalcogenide material is over the memory material and the second chalcogenide material is over the first chalcogenide material.

8. The apparatus ofclaim 7, further comprising:

a first electrode between the memory material and the first chalcogenide material; and

a second electrode between the first chalcogenide material and the second chalcogenide material.

9. The apparatus ofclaim 8, wherein the first electrode and the second electrode are thin films of carbon.

10. The apparatus ofclaim 7, wherein the first chalcogenide material, the second chalcogenide material, and the memory material each comprise tellurium.

11. The apparatus ofclaim 7, wherein the first chalcogenide material is a material selected from the group consisting of silicon, tellurium, arsenic, germanium, and combinations thereof.

12. The apparatus ofclaim 7, wherein the memory material is a tellurium, antimony, germanium alloy.

13. An apparatus, comprising:

a first ovonic switch;

a second ovonic switch coupled to the first ovonic switch; and

a memory element coupled to the second ovonic switch.

14. The apparatus ofclaim 13, wherein the memory element, the first ovonic switch, and the second ovonic switch are formed using thin film materials.

15. The apparatus ofclaim 13, further comprising a vertical structure over a substrate, wherein the vertical structure comprises the first ovonic switch, the second ovonic switch, and the memory element serially coupled to each other.

16. An apparatus, comprising:

a memory material over a substrate;

a first electrode over the memory material;

a first chalcogenide material over the first electrode;

a second electrode over the first chalcogenide material; and

a second chalcogenide material over the second electrode.

17. The apparatus ofclaim 16, wherein the memory material, the first electrode, the first chalcogenide material, the second electrode, and the second chalcogenide material form portions of a vertical stack over the substrate.

18. The apparatus ofclaim 16, wherein the memory material, the first electrode, the first chalcogenide material, the second electrode, and the second chalcogenide material are each thin film materials.

19. An apparatus, comprising:

a memory cell having a holding voltage, wherein the memory cell comprises:

a memory element; and

at least two serially coupled access devices coupled to the memory element to increase the holding voltage of the memory cell.

20. The apparatus ofclaim 19,

wherein the memory element includes a phase change material; and

wherein a first access device of the two serially coupled access devices includes a first chalcogenide material and wherein the second access device of the two serially coupled access devices includes a second chalcogenide material.

21. The apparatus ofclaim 20, wherein the first chalcogenide material is different than the second chalcogenide material.

22. The apparatus ofclaim 19, wherein a first access device of the at least two serially coupled access devices, a second access device of the at least two serially coupled access devices, and the memory element are formed using thin film materials.

23. A system, comprising:

a processor;

a wireless interface coupled to the processor; and

a memory coupled to the processor, the memory including:

a memory element;

a first access device coupled to the memory element, wherein the first access device comprises a first chalcogenide material; and

a second access device coupled to the first access device, wherein the second access device comprises a second chalcogenide material.

24. The system ofclaim 23, wherein the memory element comprises a memory material over a substrate and wherein the first chalcogenide material is over the memory material and the second chalcogenide material is over the first chalcogenide material.

25. The system ofclaim 23, wherein the memory further comprises a vertical structure over a substrate, wherein the vertical structure comprises the first access device, the second access device, and the memory element serially coupled to each other.

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