US20040104486A1 - Electronic apparatus having an adhesive layer from wafer level packaging - Google Patents

Abstract

Flip chip packages formed at a wafer level on semiconductor wafers for electronic systems provide convenient prepackaging. The package, in one embodiment, includes an adhesive layer applied to an active side of the wafer. The adhesive layer has openings to permit access to the conductive pads on each die. A conductive material substantially fills the openings. A pre-packaged die diced from the semiconductor wafer is mounted to a support wherein the conductive material effects electrical interconnection between the conductive pads on the die and receiving conductors on the support. The pre-packaged die can be coupled to a processor for an electronic system. To provide greater mounting densities, two or more dice may be coupled with the adhesive layer providing a covering for the two or more dice. The prepackaged chip with two or more dice may be coupled to a processor reducing the volume needed in an electronic system.

Description

• This application is a Divisional of U.S. application Ser. No. 09/505,018, filed Feb. 16, 2000, which is incorporated herein by reference.[0001]
TECHNICAL FIELD
• This invention relates generally to packaging of semiconductor devices and, more specifically, to an improved flip chip package and method of pre-packaging a flip chip.[0002]
BACKGROUND OF THE INVENTION
• As demand for smaller, more powerful electronic devices grows, semiconductor manufacturers are constantly attempting to reduce the size and cost of not only semiconductor devices themselves but also semiconductor packaging. Smaller packages equate with higher semiconductor mounting densities and higher mounting densities allow for more compact and yet more capable devices.[0003]
• With conventional packaging methods, a semiconductor die or “chip” is singulated from the silicon wafer and is encapsulated in a ceramic or plastic package having a number of electrical leads extending therefrom. The leads permit electrical connection between external components and the circuits on the die. Although these packages have proven reliable, they are generally many times larger than the actual die. In addition, the configuration of these packages typically yields only a limited number of leads. For these reasons, conventional packaging techniques are not particularly adaptable to high density packaging.[0004]
• Accordingly, more efficient chip packages have been developed. One such package is the “pin grid array” or PGA which utilizes a series of pin conductors extending from the face of the package. While PGAs provide increased electrical interconnection density, the pins forming the PGA are fragile and easily bent. In addition, the PGA is relatively expensive to produce and of limited value when the package is to be permanently mounted.[0005]
• Similar to the PGA are various flip chip packages including the “ball grid array” or BGA. Instead of pins, the BGA has an array of solder bumps or balls attached to the active face of the package in a process called “bumping.” The array of solder bumps is adapted to mate with discreet contacts on a receiving component. The package may be subsequently heated to partially liquefy or “reflow” the bumps, thus forming electrical connections at the discreet locations. This technology is frequently referred to as “flip chip” because the solder balls are typically secured to the semiconductor package wherein the package is then “flipped” to secure it to the receiving component. The present invention is directed primarily to flip chip packaging technology and the remainder of this discussion will focus on the same.[0006]
• While flip chip processes have proven effective, problems remain. For instance, conventional flip chip technology requires an underfill layer between the semiconductor package and the receiving substrate. The underfill material reduces stress on the solder bumps caused by thermal mismatch between the semiconductor package and substrate. The underfill layer further provides insulation between the device and substrate and prevents creep flow at the solder interface. Without the underfill layer, repeated thermal cycling constantly stresses the solder interconnections, potentially leading to failure.[0007]
• Unfortunately, the underfill process is time consuming and expensive. For example, the equipment used to dispense the underfill must precisely maintain the viscosity of the material, dispensing it at a particular flow rate and within a predetermined temperature range. Further, the underfill process cannot be applied until the package is secured to its receiving substrate. Accordingly, the chip package and substrate design must permit the dispensing equipment direct access to the package/substrate interface. And still further, since the underfill material is distributed via capillary action, the time required to complete the underfill operation can be significant.[0008]
• One method which avoids the use of underfill material involves the use of a resilient retaining member which supports a series of solder preforms therein. The retaining member is sandwiched between conductive elements such that the preforms effect electrical connection therebetween. Like underfill, however, the retaining member/solder preform is only utilized during actual surface mounting of individual chips.[0009]
• While underfill processes as well as retaining member/preforms are more than adequate in many applications, current trends in IC fabrication favor completing more and more process steps—many of which would not normally occur until after die singulation—at the wafer level. Wafer level processing is advantageous over conventional methods as it allows multiple ICs (equal to the number of die on the wafer face) to be processed simultaneously rather than serially as typically required after die singulation. Accordingly, the time required to produce a given IC device can be dramatically reduced.[0010]
• While some processes lend themselves to wafer level processing, known packaging methods such as underfill and retaining member/preform methods unfortunately do not. Thus, what is needed is a flip chip package that can be assembled at wafer level. What is further needed is a package that avoids the problems with underfill materials including troublesome dispensing and assembly cycle times. The present invention is directed to a package and method that addresses these issues.[0011]
SUMMARY OF THE INVENTION
• To address these problems, an electronic apparatus was devised that, in one embodiment, includes a first semiconductor device having a first side and an opposing second side. The first side of the first device includes a first array of connection pads. Also included is a flip chip adhesive layer covering the first side. The adhesive layer has a first array of openings extending through the layer where the first array of openings is substantially aligned with the first array of connection pads. The apparatus further includes an electrically conductive material substantially filling the first array of openings.[0012]
• Another embodiment relates to a method of packaging a die at wafer level. The method includes applying a flip chip adhesive to a first side of a finished wafer, the wafer having at least one die thereon. An array of openings is then created in the adhesive. The array of openings provides access to an array of connection pads on each die. The array of openings is then substantially filled with an electrically conductive material.[0013]
• In yet another embodiment, an electronic apparatus is provided having a first semiconductor device and a second semiconductor device. The first semiconductor device has a first side and a second side where the first side includes a first array of connection pads. The second semiconductor device also has a first side comprising a second array of connection pads. The second side of the first semiconductor device is coupled to the first side of the second semiconductor device such that the second array of connection pads is adjacent the first array of connection pads.[0014]
• In still yet another embodiment, a semiconductor wafer is provided. The wafer includes at least one die formed on a face of the wafer where the die has an array of connection pads electrically coupled to circuits on the die. Furthermore, the wafer includes an adhesive layer covering the face of the wafer. The adhesive layer has an array of openings where the array of openings are adapted to provide access to the array of connection pads.[0015]
• A method of packaging two or more semiconductor devices is also provided. In this embodiment, a second side of a first semiconductor device is attached to a first side of a second semiconductor device such that a first array of connection pads located on a first side of the first semiconductor device is adjacent to a second array of electrical connection pads located on the first side of the second semiconductor device. An adhesive layer is applied over the first side of the first semiconductor device and the first side of the second semiconductor device.[0016]
• An electronic system is provided in still yet another embodiment. The system includes a processor and a pre-packaged flip chip. The pre-packaged flip chip includes a first semiconductor device having a first side and a second side where the first side comprises a first array of connection pads. In addition, the pre-packaged flip chip includes a second semiconductor device also having a first side comprising a second array of connection pads. The second side of the first semiconductor device is coupled to the first side of the second semiconductor device such that the second array of connection pads is adjacent the first array of connection pads. An adhesive layer covers the first side of the first semiconductor device and the first side of the second semiconductor device. The adhesive layer has an array of openings substantially aligned with one or more connection pads of either the first array of connection pads or the second array of connection pads. A conductive material substantially fills the array of openings.[0017]
• Further embodiments of the invention include apparatus and methods of varying scope.[0018]
• Advantageously, the apparatus and methods of the various embodiments avoid time-consuming underfill operations by prepackaging a die or dice at wafer level. By packaging the die at wafer level, greater manufacturing efficiencies are obtainable due to simultaneous processing of multiple dice across the entire wafer face. In addition, various embodiments are also particularly amenable to pre-packaging multiple chips in a single module, permitting semiconductor packages having increased electronic densities. Since these multi-chip modules can also be packaged at wafer level, similar manufacturing economies are realized.[0019]
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a perspective view of a pre-packaged flip chip in accordance with one embodiment, the chip shown attached to a substrate;[0020]
• FIG. 2 is an exploded perspective view of the flip chip of FIG. 1;[0021]
• FIG. 3 is a partial cut-away perspective view of an active side of a pre-packaged flip chip in accordance with one embodiment (some section lines removed for clarity);[0022]
• FIG. 4 is section view taken along line[0023]4-4 of FIG. 3 illustrating one embodiment (some section lines removed for clarity);
• FIG. 5 is another section view taken along line[0024]4-4 of FIG. 3 illustrating another embodiment (some section lines removed for clarity);
• FIG. 6 is another section view taken along line[0025]4-4 of FIG. 3 illustrating yet another embodiment (some section lines removed for clarity);
• FIG. 7 is another section view taken along line[0026]4-4 of FIG. 3 illustrating still yet another embodiment (some section lines removed for clarity);
• FIGS.[0027]8A-8I illustrate wafers at various processing stages according to one embodiment;
• FIG. 9 is a partial cut-away perspective view of a pre-packaged flip chip in accordance with another embodiment (some section lines removed for clarity);[0028]
• FIG. 10 is a perspective view of a substrate for receiving the pre-packaged flip chip of FIG. 9;[0029]
• FIG. 11 is a section view taken along line[0030]10-10 of FIG. 9 illustrating one embodiment of the flip chip of FIG. 9 (some section lines removed for clarity);
• FIG. 12 is another section view taken along line[0031]10-10 of FIG. 9 illustrating another embodiment of the flip chip of FIG. 9 (some section lines removed for clarity);
• FIGS.[0032]13A-13K illustrate wafers at various processing stages according to another embodiment (some section lines removed for clarity); and
• FIG. 14 illustrates an electronic system incorporating the pre-packaged flip chip in accordance with one embodiment.[0033]
DETAILED DESCRIPTION OF THE EMBODIMENTS
• In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that process, electrical or mechanical changes may be made without departing from the scope of the present invention.[0034]
• The terms wafer and substrate used in the following description include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and terms wafer or substrate include the underlying layers containing such regions/junctions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and their equivalents.[0035]
• Broadly speaking, the instant invention is directed to a “pre-packaged” flip chip integrated circuit (IC) device and method for producing the same. Unlike conventional flip chip packages, the pre-packaged IC described herein eliminates the need for underfill operations by forming a flip chip adhesive layer on the package prior to surface mounting. To maximize throughput, the adhesive layer is, in one embodiment, applied at the wafer level. In this way, multiple dice (as many as the wafer provides) can be processed substantially simultaneously. Further, by packaging the die at wafer level, the bare die is handled less often than with conventional packaging operations, thus reducing the opportunity for damage.[0036]
• Once the adhesive layer is applied, it is processed to produce one or more holes or openings therethrough. In one embodiment, the openings are produced by exposing and patterning a selected photoresist layer and then chemically etching exposed portions of the adhesive layer to produce the openings. However, other methods of creating the openings are also contemplated.[0037]
• The function of the openings is to provide access to connection pads on the face of the IC device. An electrically conductive material is then deposited into the openings in accordance with various methods as further discussed below. The pre-packaged flip chip is then ready for surface mounting to a receiving component which, for simplicity, will hereinafter be referred to as a support. Examples of a support would include a die attach area of a printed circuit board (PCB) or other device. The electrically conductive material is then re-flowed to interconnect the circuits on the IC to conductors on the support.[0038]
• By prepackaging the flip chip, messy, expensive, and time-consuming underfill operations are avoided. In addition, by utilizing various embodiments of the invention, the die may be packaged at wafer level, allowing greater manufacturing efficiencies including simultaneous packaging of multiple dice. Furthermore, as described below, the invention lends itself to multi-chip configurations, permitting packages having even greater mounting densities.[0039]
• With this brief introduction, specific embodiments of the instant invention will now be described. Although the description focuses on particular embodiments, the reader is reminded that such embodiments are exemplary only and are therefore intended merely to teach one of skill in the art how to make and use the invention. Other embodiments are certainly possible without departing from the scope of the invention.[0040]
• FIGS.[0041]1-3 show an electronic apparatus such as anIC package100 according to one embodiment of the invention. The terms “IC package” and “pre-packaged flip chip” are used throughout the specification to refer to an IC device with its protective package and lead system that allows surface mounting of the device to other electronic components such as a receivingsupport102. In the context of chip scale devices (CSD), the IC device will hereinafter be described as a semiconductor device such as a chip or die104 having a first or active side105 (see FIG. 3) and a second or backside103. Theactive side105 has an array of electrical connection points or “pads”107 (see FIG. 3) which allow electrical coupling to theelectronic circuits101 on thedie104. The pads are coupled directly to the circuits or, alternatively, coupled to redistribution traces formed in thedie104 which themselves then connect to the circuits. Thepads107 operatively couple to an array ofmating conductors109 on the support102 (see FIG. 2) via conductive elements112 (see FIG. 3) as further discussed below.
• FIG. 1 shows a flip chip[0042]adhesive layer106 between the die104 and thesupport102. The adhesive layer insulates the conductive elements and prevents damage caused by repeated thermal cycling. For clarity, theadhesive layer106 is partially removed in FIG. 3 to illustrate thepads107 on thedie surface105. Theadhesive layer106 bonds or otherwise adheres to thedie surface105 to form thepackage100.
• One exemplary embodiment of the[0043]pre-packaged flip chip100 is shown in FIG. 3. Here thedie104 is shown with theadhesive layer106 attached to form thepackage100. To provide electrical interconnection to thepads107 on the die, theadhesive layer106 includes an array of holes oropenings108 which are substantially aligned with the pads107 (note that while theholes108 are shown as rectangular, other shapes are equally within the scope of the invention). That is, when theadhesive layer106 is attached, thepads107 are accessible through theopenings108. The adhesive layer further defines asupport mating surface110 which is adapted to adhere to the support102 (see FIG. 2) as further described below.
• The[0044]adhesive layer106 is, in one embodiment, an elastomer applied in fluid form (i.e., applied “wet”) where the fluid is subsequently hardened or cured, or alternatively, in tape-like or film form (i.e., applied “dry”). In one embodiment, the adhesive layer comprises a thermoplastic material that repeatedly becomes sticky under application of heat. In this case, the transition temperature of the thermoplastic material is selected to ensure the material does not soften during solder reflow or other subsequent processing. In another embodiment, the adhesive layer is a thermoset material that permanently sets after initial curing. Alternatively, the thermoset material is a “B-stageable” material (i.e., having an intermediate stage in which the material remains wholly or partially plastic and fusible so that it softens when heated). In still yet another embodiment, the adhesive layer is a pressure-sensitive film that adheres upon contact or under slight application of pressure.
• The material used to form the[0045]adhesive layer106 is selected to adequately protect theflip chip package100 and thesupport102 as the two components experience differential expansion during thermal cycling. In one embodiment, the layer is selected to provide a high modulus, effectively fastening thepackage100 to thesupport102 and significantly prohibiting relative expansion. In another embodiment, thelayer106 is selected to provide a low modulus to allow thepackage102 to expand at a different rate than the support without overstressing either thesupport102 or thepackage100.
• To form the[0046]openings108, various methods are used. For example, where theadhesive layer106 comprises a film, theopenings108 are formed therein by photo-chemical etching, laser cutting, die cutting, or other techniques. One advantage to the film-type adhesive layer106 is that theopenings108 may be formed, if desired, prior to assembly with thedie104. By then precisely locating theadhesive layer106 in registration with thedie104, thepre-cut openings108 are properly aligned with thepads107 on thedie surface105.
• Alternatively, the[0047]openings108 are formed in theadhesive layer106 after assembly to thedie104. This method lends itself to use with either the film-type adhesive or the wet adhesive. With post-formation of theopenings108, the material used to form theadhesive layer106 is selected so that theopenings108 can be formed using standard photolithographic techniques.
• Still referring to FIG. 3, each[0048]opening108 has a conductive material therein which allows electrical connection through theadhesive layer106 to thepads107 on thedie surface105. For simplicity, the conductive material is hereinafter referred to assolder element112. However, those skilled in the art will realize that a variety of conductive materials (e.g., lead-based and lead-free solders, conductive polymers, conductive pastes, etc.) is usable without departing from the scope of the invention.
• The[0049]solder elements112, as described below, take various forms including cylindrical or column-shapedstructures112′ (see FIGS.4-6) and sphere-shaped or ball-like structures112″ (see FIG. 7). FIG. 4 shows one embodiment of thesolder element112 wherein the element forms asolder column112′ that is slightly recessed from themating surface110. In this particular embodiment, theadhesive layer106 includes achamfer114 in the vicinity of theopening108. Thechamfer114 and recessedcolumn112′ are particularly advantageous for surface mounting methods which utilize solder paste or flux on the receiving support102 (see FIG. 2). When thepackage100 is surface mounted, any excess paste/flux is accommodated by the void defined by thechamfer114 and recessedcolumn112′ rather than spreading across thesurface110 where it can interfere with adhesion of thesurface110 to the support102 (see FIG. 2).
• FIG. 4 further illustrates an optional[0050]protective coating116 applied to theback side103 of thedie104. Thecoating116 may be an epoxy or other similar material that hardens to protect theback side103 which would otherwise be exposed after surface mounting as shown in FIG. 1. Additionally, thecoating116 may a single- or multi-layer material, e.g., an adhesive or adhesive-coated film, that is mounted or laminated to theback side103 of thedie104.
• Other embodiments are also possible. For example, in FIG. 5, the conductive material once again forms a[0051]solder column112′. However, in this particular embodiment, thecolumn112′ has a generally convex-shapedhead118 that extends beyond or protrudes from thesurface110. Thesolder column112′ is heated sufficiently to become gel-like during surface mounting. When the package is brought into registration with the support102 (see FIG. 2), theheads118 wet the support conductors109 (see FIG. 2) while thesurface110 bonds to the support102 (see FIG. 2).
• In still another embodiment such as that shown in FIG. 6, the[0052]solder columns112′ are substantially flush with thesurface110. This particular configuration is advantageous when utilizing a pressure sensitive adhesive layer106 (i.e., anadhesive layer106 that comprises a flexible tape which adheres to the support under application of pressure). Because, thesolder columns112′ are flush to thesurface110, theadhesive layer106 makes consistent, uniform contact with the support102 (see FIG. 2). Once secured to thesupport102, the package is heated to reflow thecolumns112′ and form the required electrical interconnection.
• The[0053]solder columns112′ are advantageous as the column height can be adjusted to correspond to the desiredadhesive layer106 thickness. Further, the columns are able to deflect and twist to accommodate relative motion between the die104 and thesupport102.
• While the above-described embodiments utilize[0054]solder columns112′, still yet another embodiment utilizessolder balls112″ as generally shown in FIG. 7. Like the embodiments described in FIGS.4-6, thesolder balls112″ can be recessed within thesurface110, protrude therefrom, or be relatively flush thereto. Thesolder balls112″ are advantageous in that they are cost-efficient to produce and capable of being handled by most semiconductor processing machines. While not shown herein, thesolder columns112′ are, in one embodiment, formed by stackedsolder balls112″.
• Having described various exemplary embodiments of the[0055]pre-packaged flip chip100, a method for producing the package will now be described in accordance with one exemplary embodiment. In describing the method, only those processes necessary for one of ordinary skill in the art to understand the invention are described in detail. Other fabrication processes that are well known or are unnecessary for a complete understanding of the invention are excluded.
• As mentioned above, various embodiments of the invention are perceived to be particularly advantageous for pre-packaging dice at wafer level. Generally speaking, the method, according to one embodiment, comprises applying an adhesive layer to an entire side of a semiconductor wafer (see generally FIG. 8C) wherein the wafer comprises numerous dice thereon. As described above, the adhesive layer either includes or is modifiable to include openings having conductive elements therein. The adhesive layer adheres to each die on the wafer such that a conductive element is aligned and in contact with each pad on each die. The die is then singulated from the wafer to produce a[0056]pre-package flip chip100 as shown in FIG. 3 and discussed above.
• With this general introduction, an exemplary method of making the pre-packaged flip chip in accordance is now described with reference to FIGS.[0057]8A-8I. FIG. 8A shows a finished wafer800 (i.e., a wafer that has substantially completed all fabrication processes) having a first or active side orface802 and a second or backside804. Located on thewafer800 is an array ofdice806. Each die806 has an array ofconductive pads808 as shown in FIG. 8B. Thepads808 permit electrical connection to circuits on each die806.
• FIG. 8C illustrates an[0058]adhesive layer810 placed over theactive side802 of thewafer800. In one embodiment, theadhesive layer810 comprises anadhesive film810′ that bonds to thewafer800. In another embodiment, theadhesive layer810 comprises a fluid810″ applied wet via adispensing apparatus812 and evenly distributed over thefirst side802. The fluid810″, in one embodiment, forms a layer that is hardenable via curing. By controlling the viscosity and volume of theadhesive liquid810″ dispensed, the thickness of theadhesive layer810 is controlled. In one embodiment, thewafer800 is spun to more evenly distribute theliquid adhesive810″. Thewafer800 emerges with a uniformadhesive layer810 covering the entireactive side802.
• To protect the[0059]back side804 of thewafer800, the latter is, in one embodiment, flipped and aprotective coating814 applied to theback side804. In one embodiment, theprotective coating814 comprises afilm814′ that bonds to thewafer800. In another embodiment, theprotective coating814 comprises a fluid814″ applied wet via anotherdispensing apparatus816 and evenly distributed over the back side804 (while theapparatus816 is shown diagrammatically beneath thewafer800, it would actually be oriented above the wafer during dispensing).
• Once the[0060]adhesive layer810 is applied, it is—in one embodiment—cured to securely bond it to thewafer800. Curing may occur via the application of energy such as heat, light, or radiation (as shown by anenergy source818 in FIG. 8D).
• Once cured, the[0061]adhesive layer810 is locally removed, as diagrammatically represented in FIG. 8E, from the area of each pad808 (see FIG. 8B). In other words,openings820 are created in theadhesive layer810, theopenings820 providing access to thepads808 on each die806 as generally shown in FIG. 8F. In one embodiment, theopenings820 are formed by providing a photo-sensitive adhesive layer810. By masking the appropriate areas of theadhesive layer810 and exposing the latter to anenergy source819, such as a high intensity ultra-violet light source, as shown in FIG. 8E, theadhesive layer810 is chemically altered in the area of theopenings820. The alteration permits the areas to be selectively etched and removed to form theopenings820. Other methods of forming theopenings820 are also possible.
• To accurately locate the openings, one or more datums (not shown) are precisely located on the wafer surface. The adhesive layer is chemically or manually removed (in the vicinity of these datums) to expose the datums. The masking apparatus then uses these datums to ensure accurate alignment of the[0062]openings820 with thepads808. Other methods of aligning theopenings820 are also possible within the scope of the invention.
• Once the[0063]openings820 are formed, asolder element822 is inserted therein. In one embodiment, the solder element comprises asolder ball822′ as shown in FIG. 8G. Asolder ball822′ is placed into each opening820 with the use of anapparatus824 such as a pick-and-place machine (hereinafter PNP). The PNP picks up thesolder ball822′ and precisely places it into eachopening820. To form a solder column,multiple balls822′ may be stacked in eachopening820 or, alternatively, the PNP is used to place a column of conductive material. Theapparatus824 is, in another embodiment, a machine similar to the PNP but able to forcefully eject thesolder ball822′ into eachopening820. The latter apparatus is advantageous when thesolder ball822′ is slightly larger than theopening820 diameter.
• In still yet another embodiment, a paste or gel-like[0064]conductive material822″ is placed into each opening820 to form solder columns such ascolumns112 in FIGS.4-6. Thematerial822″ is dispensed directly into theopenings820 with adispensing apparatus826 or, alternatively, applied using stencil/screen techniques (not shown).
• Still other embodiments are possible for securing the adhesive layer and forming the conductive element. For instance, in the case of a wet adhesive layer, the material is a combination of underfill, conductive fillers, and flux components that are spin-coated or stenciled over the wafer. The conductive fillers migrate through the liquid adhesive and accumulate at the connection pads via application of electromagnetic or mechanical energy. This yields a[0065]wafer800 having the required conductive elements without requiring explicit forming of theopenings820.
• While the embodiments described above form the[0066]openings820 and locate thesolder elements822 after theadhesive layer810 is attach to thewafer800, another embodiment of the present invention pre-assembles theadhesive layer810 andsolder elements822. That is, theopenings820 are formed and thesolder elements822 are placed in theadhesive layer810 prior to assembly with thewafer800. For example, in one embodiment, theadhesive layer810 is a film-likeadhesive layer810′ similar to that shown in FIG. 8C. Theopenings820 are formed via laser cutting, chemical etching, die cutting or other methods. Thesolder elements822 are then inserted by any of the methods described above. At this point, theadhesive layer810′ with thepre-assembled solder elements822 is secured to thewafer800. To minimize deformation prior to applying theadhesive layer810′, a removable backing (not shown) may be included with the layer. The removable backing is then removed once thelayer810′ is secured.
• While not shown in the figures, another embodiment of the present invention secures the[0067]solder elements822 to the wafer prior to application of the adhesive layer. For example, a PNP is used to place asolder ball822′ on eachconnection pad808. After placing thesolder balls822, thefluid adhesive810″ is applied. By controlling the volume of the adhesive applied, the thickness of theadhesive layer810 is controlled relative to the size of thesolder balls822′. Accordingly, the order in which the adhesive layer and solder elements are assembled is not perceived to be critical.
• Once the[0068]solder elements822 are positioned and retained within theadhesive layer810 and the adhesive layer is secured to thewafer800, the wafer is singulated intoindividual dice806 by sawing as shown in FIG. 8H. Once singulated, eachindividual die806 with the now integral portion of theadhesive layer810 and the plurality ofsolder elements822 forms apre-packaged flip chip850 as shown in FIG. 8I in accordance with the one embodiment. Thepre-packaged flip chip850 is then attached to asupport102 such as a motherboard (see FIG. 2) where it is, if necessary, reflowed to electrically couple and secure it thereto.
• Accordingly, various embodiments provide semiconductor device packages and methods for making semiconductor device packages that are accomplished at wafer level. While the packaged device and method are useful for packaging single chips, it is perceived to be particularly advantageous for accommodating multiple, stacked devices as further described below, allowing even greater chip mounting densities.[0069]
• One exemplary embodiment of such a pre-packaged multi-flip chip is shown in FIG. 9. Here, a first semiconductor device comprising a[0070]die902 is attached to anactive side903 of a second, larger semiconductor device comprising adie904 over which a flip chipadhesive layer906 is applied to produce a pre-packaged,multi-flip chip900. Themulti-flip chip900, like theflip chip100 illustrated in FIG. 3, is adapted for mounting to a receivingsupport950 having an array ofconductors952 as shown in FIG. 10.
• The first die[0071]902 (see FIG. 9) includes a first array ofconnection pads908 while thesecond die904 includes a second array ofconnection pads910 located along the perimeter of thefirst die902. Thesecond die904 is sized so that when thefirst die902 is secured thereto, thepads910 are still accessible.
• FIG. 11 shows an exemplary embodiment of the[0072]package900 in cross section. Thefirst die902 is precisely secured to thesecond die904 with abonding material912. Theadhesive layer906 is then placed over the combineddice902,904 according to any of the methods already described above. The adhesive layer is sufficiently thick to ensure that adequate adhesive layer thickness exists over thefirst die902. Like the embodiments described above, thepackage900, in one embodiment, includes aprotective covering907 over aback side905 to protect thepackage900 during and after processing.
• As with the embodiments already described herein, the[0073]adhesive layer906 is processed to produce an array ofopenings914 which are generally aligned with thepads908 and910. Within eachopening914 is asolder element916. The particular shape of thesolder elements916 is varied to accommodate the particular application. For instance, in the embodiment illustrated in FIG. 11, the first array ofpads908 utilizesolder balls916″ while the second array ofpads910 utilizesolder columns916′. In FIG. 12, on the other hand, the first array ofpads908 also utilize asolder column916′. In this particular embodiment, thefirst die902 has one ormore pads908 connected directly to thesecond die904 by awire bond918 or similar connection. This allows interconnection between the circuits on thedice902,904 within thepackage900.
• The multi-chip,[0074]flip chip package900 provides increased circuit densities by stacking multiple dice in a single package. Thus, the package occupies less surface area than singularly packaged die and further permits electrical interconnection of the dice within the package, permitting the use of less complex supports950 (see FIG. 10); i.e., the support needs no conductive trace to interconnect the various conductive pads.
• Having described a multi-chip flip chip package according to one embodiment, an exemplary method of making the multi-chip package will now be described with reference to FIGS.[0075]13A-13K. Afirst wafer1300 having a first oractive side1302 and a second or backside1304 is shown in FIG. 13A. Abonding material1310′ is applied to theback side1304 with adispensing apparatus1308 to produce a bonding layer1310 (see FIG. 13B). Thebonding layer1310 may alternatively be applied in the form of a tape or film (not shown). Once thebonding layer1310 is formed, thefirst wafer1300 is diced as shown in FIG. 13B, producing numerousfirst dice1312 as shown in FIG. 13C. Each die1312 has an array ofconnection pads1314 which permit electrical connection to the circuits on thefirst die1312.
• The[0076]first die1312 is then secured to asecond wafer1316 as shown in FIG. 13D. The second wafer also has a first oractive side1318 and a second or backside1320 and numerous, largersecond dice1322 thereon. Thebonding layer1310 permits theback side1304 of eachfirst die1312 to be secured to theactive side1318 of eachsecond die1322. In one embodiment, thebonding layer1310 is a pressure-sensitive material that permits attachment of the dice by application of pressure. In an alternative embodiment, the bonding layer is a heat-sensitive material (i.e., thermoplastic or thermoset) that bonds to thesecond die1322 upon application of heat.
• After securing the[0077]first die1312 to thesecond die1322, thepads1314 of thefirst die1312 are in close proximity and adjacent topads1324 of thesecond die1322. As such, thepads1314 and1324 may be interconnected as shown in FIG. 13E with awire bond1326 or similar connection. After interconnection, anadhesive material1328′ is applied to theactive side1318 of thesecond wafer1316 with adispensing apparatus1329 forming anadhesive layer1328 as shown in FIG. 13F.
• [0078]Openings1330 are then formed within theadhesive layer1328 as also shown in FIG. 13F. As with the embodiments already described herein, theopenings1330 are substantially aligned with thepads1324 and1314 to allow access thereto. The openings may be laser cut, chemically etched, or formed in any one of a variety of ways discussed herein with reference to FIGS.8A-8I.
• Once the[0079]openings1330 are formed, asolder element1332 is placed therein as shown in FIG. 13G. In one embodiment, the solder element is aconductive paste material1332′. In another embodiment, the solder material is asolder ball1332″. The resultingwafer1316, as shown in FIG. 13H, has numeroussecond dice1322 thereon. Each die1322 hassolder elements1332 retained within theadhesive layer1328 formed on theactive side1318 of thesecond wafer1316 as shown in FIG. 131. By then dicing thesecond wafer1316 along the scribe lines as shown in FIG. 13J, numerous individual multi-chipflip chip packages1350 as shown in FIG. 13K are produced.
• Thus, various embodiments can be utilized to package multiple dice at wafer level. By providing multiple dice in one package, higher mounting densities can be achieved. Furthermore, interconnection between multiple dice can be accommodated within the package rather than via the receiving support.[0080]
• FIG. 14 illustrates the[0081]pre-packaged flip chip100 according to one embodiment shown as part of anelectronic system1400 such as a computer. Thesystem1400, in one embodiment, includes aprocessor1402 and an electronic apparatus such as apre-packaged flip chip100. While diagrammatically depicted aspre-packaged flip chip100, other embodiments of thememory component1404 utilize other flip chips (e.g.,flip chip package850,900, or1350) described herein. In addition, the flip chip package is not limited to use with memory components but rather is adapted for use with most any semiconductor device application.
• Advantageously, the packages and methods of the various embodiments avoid time-consuming underfill operations by prepackaging a die or dice at wafer level. By packaging the die at wafer level, greater manufacturing efficiencies are obtainable due to simultaneous processing of multiple dice across the entire wafer face. In addition, the various embodiments are also particularly amenable to pre-packaging multiple chips in a single module, permitting semiconductor packages having increased electronic densities. Since these multi-chip modules can also be packaged at wafer level, similar manufacturing economies are realized.[0082]
• Preferred embodiments of the present invention are described above. Those skilled in the art will recognize that many embodiments are possible within the scope of the invention. Variations, modifications, and combinations of the various parts and assemblies can certainly be made and still fall within the scope of the invention. Thus, the invention is limited only by the following claims, and equivalents thereto.[0083]

Claims (50)

What is claimed is:

1. A semiconductor wafer, comprising:

at least one die having a first side, the at least one die having an array of connection pads thereon, the connection pads electrically coupled to circuits on the at least one die; and

an adhesive layer covering the first side of the at least one die, the adhesive layer having an array of openings, where the array of openings are adapted to provide access to the array of connection pads.

2. The semiconductor wafer ofclaim 1, further comprising a conductive material substantially filling the array of openings, the conductive material adapted to permit electrical interconnection through the adhesive layer to the circuits on the at least one die.

3. The semiconductor wafer ofclaim 2, wherein the conductive material is solder.

4. The semiconductor wafer ofclaim 2, wherein the conductive material is cylindrical in shape.

5. The semiconductor wafer ofclaim 2, wherein the conductive material is sphere-shaped.

6. The semiconductor wafer ofclaim 1, wherein the adhesive layer comprises one or more film layers.

7. The semiconductor wafer ofclaim 1, wherein the adhesive layer substantially covers a face of the semiconductor wafer.

8. A semiconductor wafer, comprising:

at least one die having a first side and a second side, the second side opposite the first side, the at least one die having an array of connection pads thereon, the connection pads electrically coupled to circuits on the at least one die;

an adhesive layer covering the first side of the at least one die, the adhesive layer having an array of openings, where the array of openings provides access to the array of connection pads;

a conductive material substantially filling the array of openings, the conductive material adapted to permit electrical interconnection through the adhesive layer to the array of connection pads; and

a protective coating on the second side of the at least one die.

9. The semiconductor wafer ofclaim 8, wherein the adhesive layer substantially covers a face of the semiconductor wafer.

10. The semiconductor wafer ofclaim 8, wherein the adhesive layer is comprised of one or more film layers.

11. The semiconductor wafer ofclaim 8, wherein the adhesive layer comprises a curable, fluid material.

12. The semiconductor wafer ofclaim 8, wherein the conductive material is solder.

13. An electronic system comprising:

a processor; and

a pre-packaged flip chip coupled to the processor, wherein the flip chip includes:

a first semiconductor device having a first side and a second side, the first side having a first array of connection pads, the connection pads electrically coupled to circuits on the first semiconductor device;

a second semiconductor device having a first side comprising a second array of connection pads, wherein the second side of the first semiconductor device is coupled to the first side of the second semiconductor device such that the second array of connection pads is adjacent the first array of connection pads;

an adhesive layer covering the first side of the first semiconductor device and the first side of the second semiconductor device, the adhesive layer having an array of openings substantially aligned with one or more connection pads of either the first array of connection pads or the second array of connection pads; and

a conductive material substantially filling the array of openings.

14. The electronic system ofclaim 13, wherein the adhesive layer is comprised of one or more film layers.

15. The electronic system ofclaim 13, wherein the adhesive layer includes a curable, fluid material.

16. The electronic system ofclaim 13, wherein the conductive material is solder.

17. The electronic system ofclaim 13, wherein the conductive material is cylindrical in shape.

18. The electronic system ofclaim 13, wherein the conductive material is sphere-shaped.

19. An electronic system comprising:

a processor; and

a pre-packaged flip chip coupled to the processor, wherein the flip chip includes:

a first semiconductor device having a first side and a second side, the first side comprising a first array of connection pads, the connection pads electrically coupled to circuits on the first semiconductor device;

an adhesive layer covering the first side of the first semiconductor device, the adhesive layer having an array of openings substantially aligned with one or more connection pads of the first array of connection pads; and

a conductive material substantially filling the array of openings.

20. The electronic system ofclaim 19, wherein second side of the first semiconductor is opposite the first side and includes a protective material substantially covering the second side.

21. The electronic system ofclaim 19, wherein the adhesive layer is comprised of one or more film layers.

22. The electronic system ofclaim 19, wherein the adhesive layer includes a curable, fluid material.

23. The electronic system ofclaim 19, wherein the conductive material is solder.

24. The electronic system ofclaim 19, wherein the conductive material is cylindrical in shape.

25. The electronic system ofclaim 19, wherein the conductive material is sphere-shaped.

26. An electronic system comprising:

a processor; and

a flip chip coupled to the processor, wherein the flip chip includes:

a die having an active side and a back side, the back side opposite the active side, the active side comprising an array of connection pads, the connection pads electrically coupled to circuits on the die;

an adhesive layer covering the active side of the die, the adhesive layer having an array of openings substantially aligned with one or more connection pads of the array of connection pads;

a conductive material substantially filling the array of openings;

a protective coating on the back side of the die; and

a support coupled to the die, the support having an array of conductors substantially aligned with the one or more connection pads of the array of connection pads.

27. The electronic system ofclaim 26, wherein the adhesive layer is an elastomer.

28. The electronic system ofclaim 26, wherein the adhesive layer is a thermoplastic material.

29. The electronic system ofclaim 26, wherein the adhesive layer is a thermoset material.

30. The electronic system ofclaim 26, wherein the adhesive layer is a pressure-sensitive material.

31. The electronic system ofclaim 26, wherein the protective coating is an epoxy.

32. An electronic system comprising:

a processor; and

a flip chip coupled to the processor, wherein the flip chip includes:

a first die having an active side and a back side, the active side of the first die having a first array of connection pads, the connection pads electrically coupled to circuits on the first die;

a second die having an active side and a back side, the active side of the second die having a second array of connection pads, wherein the back side of the first die is coupled to the active side of the second die such that the second array of connection pads are accessible and the first array of connection pads are accessible;

an adhesive layer covering the active side of the first die and the active side of the second die, the adhesive layer having an array of openings providing access with one or more connection pads of either the first array of connection pads or the second array of connection pads;

a conductive material substantially filling the array of openings; and

a protective coating on the back side of the second die.

33. The electronic system ofclaim 32, wherein the conductive material is conductive paste or conductive gel that hardens upon curing.

34. The electronic system ofclaim 32, wherein the adhesive layer includes a material that is applied as a fluid and hardens upon curing.

35. The electronic system ofclaim 32, wherein the conductive material is column-shaped.

36. The electronic system ofclaim 32, wherein the conductive material comprises one or more sphere-shaped objects.

37. The electronic system ofclaim 32, wherein the back side of the first die includes a bonding layer.

38. An electronic system comprising:

a processor; and

a flip chip coupled to the processor, wherein the flip chip includes:

a first die having a first side and a second side, the first side comprising a first array of connection pads, the connection pads electrically coupled to circuits on the first die;

a second die having a first side comprising a second array of connection pads, wherein the second side of the first die is coupled to the first side of the second die such that the second array of connection pads are accessible and the first array of connection pads are accessible;

an adhesive layer covering the first side of the first die and the first side of the second die, the adhesive layer having an array of openings substantially aligned with both the first array of connection pads and with the second array of connection pads, wherein the adhesive layer forms a mating surface adapted to attach to a support; and

a conductive material substantially filling the array of openings.

39. The electronic system ofclaim 38, wherein each opening of the array of openings is chamfered at the mating surface.

40. The electronic system ofclaim 38, wherein the conductive material is flush with the mating surface.

41. The electronic system ofclaim 38, wherein the conductive material protrudes beyond the mating surface.

42. The electronic system ofclaim 38, wherein the conductive material is recessed within the mating surface.

43. The electronic system ofclaim 38, wherein the conductive material is column-shaped.

44. The electronic system ofclaim 38, wherein the conductive material includes one or more sphere-shaped objects.

45. An electronic system comprising:

a processor; and

a flip chip coupled to the processor, wherein the flip chip includes:

a first die having an active side and a back side, the active side of the first die having a first array of connection pads, the back side of the first die having a bonding layer, the connection pads electrically coupled to circuits on the first die;

a second die having an active side and a back side, the active side of the second die having a second array of connection pads, wherein the bonding layer of the back side of the first die is coupled to the active side of the second die such that the second array of connection pads are accessible and the first array of connection pads are accessible, wherein one or more connection pads of the second array are interconnected with one or more connection pads of the first array;

an adhesive layer covering for the active side of the first die and the active side of the second die, the adhesive layer having an array of openings substantially aligned with both the first array of connection pads and with the second array of connection pads, wherein the adhesive layer forms a mating surface; and

a conductive material substantially filling the array of openings; and a support to which the adhesive attaches.

46. The electronic system ofclaim 45, wherein the conductive material is conductive paste or conductive gel that hardens upon curing.

47. The electronic system ofclaim 45, wherein the adhesive layer includes a material that is applied as a fluid and hardens upon curing.

48. The electronic system ofclaim 45, wherein the conductive material is recessed within the mating surface.

49. The electronic system ofclaim 45, wherein the adhesive layer is a pressure-sensitive material.

50. The electronic system ofclaim 47, wherein the flip chip includes three or more dice, each die having an active side such that the adhesive layer provides a covering for the active side of each die.

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