US20040085292A1 - Head-mounted display system - Google Patents

Abstract

A head mounted display system including a high resolution active matrix display which reduces center of gravity offset in a compact design. The active matrix display can be either a liquid crystal display or a light emitting display.

Description

RELATED APPLICATIONS
• This application is a divisional of U.S. application Ser. No. 09/703,271, filed Oct. 31, 2000, which is a continuation of Ser. No. 08/295,826, filed Feb. 2, 1995, which is a National Phase of PCT/US93/02312 filed Mar. 12, 1993, CIP of Ser. No. 07/851,178 filed Mar. 13, 1992, CIP of Ser. No. 07/874,588 filed Apr. 24, 1992, CIP of Ser. No. 07/971,352 filed Nov. 4, 1992, CIP of Ser. No. 07/985,285, filed Dec. 4, 1992, CIP of PCT/US93/01322 filed Feb. 12, 1993. The entire teachings of the above applications are incorporated herein by reference.[0001]
BACKGROUND OF THE INVENTION
• Head mounted display systems have been developed for a number of different applications including use by aircraft pilots and for simulation. Head mounted displays are generally limited by their resolution and by their size and weight. Existing displays have relatively low resolution and are positioned at a relatively large distance from the eye. Of particular importance, is to keep the center of gravity of the display from extending upward and forward from the center of gravity of the head and neck of the wearer, where it will place a large torque on the wearer's neck and may bump into other instruments during use. There is a continuing need to present images to the wearer of a helmet mounted display in a high-resolution format similar to that of a computer monitor. The display needs to be as non-intrusive as possible, leading to the need for a lightweight and compact system.[0002]
• Head mounted displays can also utilize eye tracking systems in flight control, flight simulation and virtual imaging displays. Eye control systems generate information based on the position of the eye with respect to an image on a display. This information is useful for a variety of applications. It can be used to enable the viewer to control “hands-free” movement of a cursor, such as a cross-hair on the display.[0003]
• Apparatus for detecting the orientation of the eye or determining its line-of-sight (LOS) are called occulometers or eye trackers and are well known in the art. (See for example U.S. Pat. Nos. 4,109,145, 4,034,401 and 4,028,725).[0004]
SUMMARY
• In accordance with the present invention a head mounted display is preferably either an electroluminescent (EL) or an active matrix liquid crystal display (AMLCD) comprising thin film transistor (TFT) driving elements formed of single crystal silicon and then transferred to a transparent glass substrate. Each TFT circuit is connected to an electrode which defines a picture element (pixel) of the display. The head mounted display system can also include a detector array comprising thin film integrated optical diode detectors is formed of III-V materials and transferred directly onto a flat panel active matrix display.[0005]
• In a preferred embodiment of a direct view eye tracking dispaly, the detectors are positioned such that each is completely above the drive transistors of the active matrix circuit i.e., adjacent to the pixel area and therefore do not block any of the display's light output. The light output from the display, either infrared or visible, is used to determine the position of the eye. No additional optics, such as, fiber optics to/from remote displays are required in this approach. The chief advantage is that the integrated eyetracker/display can be inserted in a helmet-mounted optical system without physical modification to the helmet or optics. This advantage results from the fundamental reciprocity of the axial light rays that are used to determine the eye position. An axial ray, is a light ray that emanates from the display and travels through the optical axis of the eye, normal to the retina. These rays, when reflected by the retina, can travel back to the display along the same optical path (in accordance with the optical reciprocity theorem). Except for divergence of the rays, the reflected rays return to the vicinity of the emitting pixel. In this way, the detector can identify the area of the display that is sighted by the user. Software in a computer then provides a cursor at this location.[0006]
• In another alternative embodiment, instead of using the visible scene from the display, some of the frames in the display are used for brief presentation of an interlaced eyetracker pattern. If the repetition rate of the test pattern is sufficiently infrequent, the user (viewer) will not perceive its presence. This pattern can consist of a single pixel being illuminated or can have some other geometric pattern. Light from a single lit pixel enters the eye through the pupil and is reflected from the retina. The path of the reflected light clearly depends on the position of the eye. On the reverse path back to the display panel, the reflected light undergoes spreading or convergence depending upon the optical system. As it returns to the plane of the display, it strikes the photodetectors. A pattern will appear in the output of the photodetector array that depends on the position of the eye and the nature of the optical system. This pattern is interpreted by a computer and correlated to the position of the eye.[0007]
• The present invention uses a single-crystal material to produce a high-density active matrix array in a head mounted optical support system that provides for closeness of the display to the eye, compactness of the array and provides the desired level of resolution. With a density of 400 lines per centimeter, for example, a 1.27 centimeters display in accordance with the invention will fit into a system only 1.52 centimeters in depth. This system is more compact, has lighter weight, and a lower cost than existing head mounted displays.[0008]
• To get the display system as close as possible to the eye and as compact as possible, a short focal length lens system must be used. The focal lengths of simple lenses are limited by lens geometry, where the thickness of the lens is less than the lens diameter. Thus, a simple lens has a shorter focal length as well as a small diameter. For the most compact system, the smallest possible lens that focuses the display image is used. The lens size is defined by the object size, which in this case is the size of the display element.[0009]
• Since resolution needs to be increased while size needs to be decreased, the pixel density of the display needs to increase. Existing displays have pixel densities of about 120 lines per centimeter and are about 4.1 centimeters in diameter. Using a 3.81 centimeter lens, where the minimum focal length for a standard 3.81 centimeter lens is about 3.05 centimeters, results in a lens with a center thickness of over 1.52 centimeters. The use of this lens results in a lens-to-display distance of about 3.3 centimeters, which is the minimum depth of an existing head-mounted display for this geometry.[0010]
• The present system, by increasing the pixel density to at least 200 lines per centimeter, and preferably to over 400 lines per centimeter, provides for a lens-to-display distance of less than one inch. The lens-to-display distance is preferably in the range of 1.0-2.2 centimeters.[0011]
• The display can be a transmission type display with the light source directly adjacent the light valve active matrix or the light source can be positioned above the head or to one or both sides of the head of the user such that the light can be coupled to the light valve active matrix by one or more reflective elements. Fiber optics can also be employed to provide a back light source for the display or to deliver images from the display into the user's field of view.[0012]
• Alternatively, the display can be an emission type device such as an active matrix electroluminescent display or an active matrix of light emitting diodes (LEDs).[0013]
• Additional embodiments of the invention include a projected view active matrix display in which different polarization components of light are separated, one component being directed to the left eye, and another component being directed to the right eye. This provides a more efficient optical system in which more light from the source is used to provide the desired image.[0014]
• Another preferred embodiment utilizes an active matrix display in which the pixel size increases across the display to provide a wide angle field of view display.[0015]
• The display can be fabricated as a visor with a number of displays which are tiled together and positioned on a flat or curved plastic visor.[0016]
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a perspective view of a high density circuit module in the form of an active matrix liquid crystal display (AMLCD).[0017]
• FIG. 2A is a schematic illustrating how two six inch wafers can be used to form tiles for a 4×8 inch AMLCD.[0018]
• FIG. 2B shows the tiles of FIG. 2A applied to a glass substrate for forming an AMLCD.[0019]
• FIG. 3 is a circuit diagram illustrating the driver system for the AMLCD of FIG. 1.[0020]
• FIGS.[0021]4A-4L is a preferred process flow sequence illustrating the fabrication of the a portion of the circuit panel for the AMLCD of FIG. 1.
• FIGS. 5A and 5B are cross-sectional schematic process views of a portion of the AMLCD.[0022]
• FIG. 6 illustrates in a perspective view a preferred embodiment of a system used for recrystallization.[0023]
• FIGS.[0024]7A-7D is a process flow sequence illustrating transfer and bonding of a silicon an oxide (SOI) structure to a glass superstrate and removal of the substrate.
• FIGS. 8A and 8B is a process flow sequence illustrating an alternative transfer process in which a GeSi alloy is used as an intermediate etch step layer.[0025]
• FIG. 9 is a schematic diagram of an eye tracking system of the invention.[0026]
• FIG. 10 is a schematic of an alternate embodiment of an eye tracking system of the invention.[0027]
• FIG. 11 is an exploded view of the integrated display/detector array panel (eye-tracker) of the invention.[0028]
• FIG. 12 is a plan view of a simplified version of the eye tracker in which the matrix array metallization is replaced by a common parallel interconnect.[0029]
• FIGS.[0030]13A-13C are cross-sectioned views showing important steps in the process of forming the eye-tracker device of the invention.
• FIGS.[0031]14A-B are schematic section views of a wafer being processing to form an X-Y addressable LED array.
• FIGS.[0032]14C-E are schematic partial perspectives showing a wafer during successive additional process steps.
• FIGS.[0033]15A-15B is a process flow diagram of the main steps in fabricating an LED bar in accordance with a mesa etch isolation process with a corresponding schematic sectional view of a wafer structure so processed shown beneath each step.
• FIG. 16 is a cross-sectional side view of a wafer during step k of FIG. 15[0034]b.
• FIG. 17 is a process flow diagram of the main steps in fabricating an LED bar in accordance with an alternate process with a correspnding schematic sectional view of a wafer structure so processed shown beneath each step.[0035]
• FIGS.[0036]18A-18B is a process flow diagram of the main steps in fabricating an LED bar in accordance with yet another alternate process with a corresponding schematic sectional view of a wafer structure so processed shown beneath each step.
• FIG. 19 is a plan view of an X-Y addressable LED array mounted on a silicon substrate with associated silicon electronic circuitry.[0037]
• FIG. 20 is a perspective view of a LED pixel from an X-Y addressable LED array embodiment of the invention.[0038]
• FIG. 21 is a schematic side view of an IR to visible light converter embodiment of the invention.[0039]
• FIG. 22 is a schematic diagram of the converter of FIG. 21.[0040]
• FIG. 23 is a side view of an alternate embodiment of FIG. 21.[0041]
• FIG. 24 is a side view of a pixel of a tri-color X-Y addressable LED array.[0042]
• FIG. 25 is a plan view of the array of FIG. 24.[0043]
• FIG. 26 is a schematic diagram of an alternate embodiment of an eye tracking device of the invention.[0044]
• FIG. 27A is an exploded perspective view of an electroluminescent panel display in accordance with the present invention.[0045]
• FIG. 27B is a perspective view of an electroluminescent color display element.[0046]
• FIG. 27C is a circuit diagram illustrating the driver system for the electroluminescent panel display.[0047]
• FIG. 27D is an equivalent circuit for a DMOS transistor of FIG. 16C.[0048]
• FIGS.[0049]28A-28L is a preferred process flow sequency illustrating the fabrication of a circuit panel for an electroluminescent panel display.
• FIGS.[0050]29A-29D is preferred process flow sequence illustrating the fabrication of an electroluminescent color display.
• FIGS.[0051]30A-30B is a preferred process flow sequence illustrating transfer and bonding of an SOI structure to a superstrate and removal of the substrate.
• FIGS.[0052]31A-31B is a preferred process flow sequence illustrating an alternative transfer process in which a GeSi alloy is used as an intermediate etch stop layer.
• FIG. 32 shows a schematic illustration of a head mounted display system.[0053]
• FIG. 33 illustrates a preferred embodiment of a head mounted display where two components of polarized light are separated for improved optical efficiency.[0054]
• FIG. 34 illustrates an active matrix for a wide angle field of view head mounted display system.[0055]
• FIG. 35 provides a detailed view of a portion of the active matrix area of the device shown in FIG. 34.[0056]
• FIG. 36 illustrates an active matrix mounted or tiled onto a visor screen.[0057]
• FIG. 37A-[0058]37C illustrates other preferred embodiments of a direct-view display system.
DETAILED DESCRIPTION
• I. Tiled Active Matrix Liquid Crystal Display[0059]
• A preferred embodiment of the invention for fabricating complex hybrid multi-function circuitry on common module substrates is illustrated in the context of an AMLCD for a head mounted display, as shown in FIG. 1. The basic components of the AMLCD comprise a[0060]light source10, such as a flat fluorescent or incandescent white lamp, or an electroluminescent lamp having white, or red, blue and green phosphors, a firstpolarizing filter12, acircuit panel14, anoptional filter plate16 and a secondpolarizing filter17, which form a layered structure. Note thatfilter plate16 is not needed for a black and white display or where the red, green and blue colors are provided by the lamp at the appropriate pixel. A liquid crystal material23, such as a twisted nematic is placed between thecircuit panel14 and thefilter plate16.
• [0061]Circuit panel14 consists of a transparentcommon module body13 formed, for example, of glass upon which is transferred a plurality of common multifunction circuits comprisingcontrol logic circuits40A and40B and drivecircuits18A and18B,20A and20B, andarray circuit25A and25B. Preferably, the logic and drive circuits which require high speed operation are formed in tiles of x-Si. The array circuits may be formed in -Si material, or poly-Si, or preferably in x-Si, to achieve lower leakage in the resultant TFT's and, hence, better grey scale. Higher speed is also achieved in x-Si. Displays as large as a 4×8 inch active matrix LCD array can be formed from two standard 6-inch diameter Si wafers W1 and W2 as shown in FIG. 2A.Array circuit25A is formed on wafer W1 and 1-inch by 4-inch tiles TA are transferred from the wafer W1 to thesubstrate14. Note that the transfer can be accomplished using either a single or double transfer process, as will be described in detail below. Each tile is registered against another using micropositioning equipment and manipulators capable of micron scale accuracy. Similarly, tiles TB are transferred from wafer W2 to formarray25B on substrate or common module body13 (See FIG. 2B).
• [0062]Logic circuits40A and40B and drivecircuits18A,18B,20A,20B are formed on other suitable substrates (not shown) and tiled and transferred in like manner tocommon substrate13 and registered opposite thearrays25A,25B, as shown in FIG. 1.Conductive interconnections50 are then made between the drive circuits and theindividual pixels22 and thelogic control circuits40A and40B. In this manner, a 1280 by 1024 addressable array ofpixels22 are formed on thesubstrate13 ofcircuit panel14. Eachpixel22 is actuated by voltage from arespective drive circuit18A or B on the X-axis and20A or B on the Y-axis. The X and Y drive circuits are controlled by signals fromcontrol logic circuits40A and B. Eachpixel19 produces an electric field in the liquid crystal material23 disposed between the pixel and a counterelectrode (not shown) formed on the back side of thecolor filter plate16.
• The electric field formed by[0063]pixels22 causes a rotation of the polarization of light being transmitted across the liquid crystal material that results in an adjacent color filter element being illuminated. The color filters offilter plate system16 are arranged into groups of four filter elements, such as blue24, green31, red27, and white29. The pixels associated with filter elements can be selectively actuated to provide any desired color for that pixel group.
• A typical drive and logic circuit that can be used to control the[0064]array pixels22 is illustrated in FIG. 3. Drivecircuit18A receives an incoming signal fromcontrol logic40A and sends a signal to each source electrode of aTFT51 in one of the columns selected bylogic circuit40A throughinterconnect line53. Y-drive circuit20A controlled bylogic circuit40A energizes arow buss59 extending perpendicular tocolumn buss53 and applies a voltage pulse to each gate G of TFT's51 in a selected row. When a TFT has a voltage pulse on both its gate and source electrode current flows through anindividual transistor51, which chargescapacitor56 in arespective pixel22. Thecapacitor56 sustains a charge on the pixel electrode adjacent to the liquid crystal material (shown schematically at 19) until the next scan of thepixel array25. Note that the various embodiments of the invention may, or may not, utilizecapacitors56 with each pixel depending upon the type of display desired.
• II. Transfer Processes[0065]
• The[0066]array circuits25A and25B andlogic40A,40B and drivecircuits18A,18B may be formed and transferred by a number of processes. The basic steps in a single transfer process are: forming of a plurality of thin film Si circuits on Si substrates, dicing the thin film to form tiles, and transferring the tiles to a common module substrate by “tiling.” Tiling can also be employed in fabricating III-V material circuits or hybrid Si and III-V material circuits or circuit components, which can be stacked to provide compact modules.
• Tiling involves the steps of transferring, registering the transferred tiles, and adhering the registered tiles. The Si substrates are then removed and the circuits on the tiles are interconnected. The double transfer approach, described in detail below in connection with FIGS.[0067]4A-4L is similar except that the Si-substrate is removed after dicing and the thin film is transferred to an intermediate transfer body or carrier before ultimate transfer to the common module body.
• Assuming an Isolated Silicon Epitaxy (ISE) process is used, the first step is to form a thin-film precursor structure of silicon-on-insulator (SOI) film. An SOI structure, such as that shown in FIG. 4A, includes a[0068]substrate32 of Si, abuffer layer30, of semi-insulating Si and an oxide34 (such as, for example, SiO2) that is grown or deposited onbuffer layer30, usually by Chemical Vapor Deposition (CVD). Anoptional release layer36 of material which etches slower than theunderlying oxide layer34 is then formed over theoxide34.
• For example, a silicon oxy-nitride release layer, comprising a mixture of silicon nitride (S3N4) and silicon dioxide (SiO2) may be a suitable choice. Such a layer etches more slowly in hydrofluoric acid than does SiO2 alone. This etch rate can be controlled by adjusting the ratio of N and O in the silicon oxy-nitride (SiOxNy) compound.[0069]
• A thin essentially[0070]single crystal layer38 of silicon is then formed over therelease layer36. The oxide (or insulator)34 is thus buried beneath the Si surface layer. For the case of ISE SOI structures, the top layer is essentially single-crystal recrystallized silicon, from which CMOS circuits can be fabricated.
• Note that for the purposes of the present application, the term “essentially” single crystal means a film in which a majority of crystals show a common crystalline orientation and extend over a cross-sectional area in a plane of the film for at least 0.1 cm[0071]², and preferably, in the range of 0.5-1.0 cm2, or more. The term also includes completely single crystal Si. The thin films can have thicknesses in the range of 0.1-20 microns and preferably in the range 0.1-1.0 microns.
• The use of a buried insulator provides devices having higher speeds than can be obtained in conventional bulk (Czochralski) material. Circuits containing in excess of 1.5 million CMOS transistors have been successfully fabricated in ISE material. An optional capping layer (not shown) also of silicon nitride may also be formed over[0072]layer36 and removed when active devices are formed. As shown in FIG. 4B, thefilm38 is patterned to define active circuits, such as a TFT's inregion37 and a pixel electrode region at39 for each display pixel. Note that for simplification, only oneTFT51 and onepixel electrode62 is illustrated (FIG. 4H). It should be understood that an array of 1280 by 1024 such elements can in practice be formed on a single 6-inch wafer.
• A plurality of arrays may be formed on a single six-inch wafer, which can then applied to the display as tiles and interconnected. Alternatively, the plurality of pixel matrices from one wafer can be separated and used in different displays. The plurality may comprise one large rectangular array surrounded by several smaller arrays (to be used in smaller displays). By mixing rectangular arrays of different areas, such an arrangement makes better use of the total available area on a round wafer.[0073]
• An[0074]oxide layer40 is then formed over the patterned regions including aninsulator region48 formed between the tworegions37,39 of each pixel. The intrinsiccrystallized material38 is then implanted44 (at FIG. 4C) with boron or other p-type dopants to provide a n-channel device (or alternatively, an n-type dopant for a p-channel device).
• A[0075]polycrystalline silicon layer42 is then deposited over the pixel and thelayer42 is then implanted46, through a mask as seen in FIG. 4D, with an n-type dopant to lower the resistivity of thelayer42 to be used as the gate of the TFT. Next, thepolysilicon42 is patterned to form agate50, as seen in FIG. 4E, which is followed by alarge implant52 of boron to provide p+ source and drainregions66,64 for the TFT on either side of the gate electrode. As shown in FIG. 4F, anoxide54 is formed over the transistor andopenings60,56,58 are formed through theoxide54 to contact thesource66, thedrain64, and thegate50. A patterned metallization71 of aluminum, tungsten or other suitable metal is used to connect the exposedpixel electrode62 to the source66 (or drain), and to connect the gate and drain to other circuit panel components.
• The devices have now been processed and the circuits may now be tested and repaired, as required, before further processing occurs.[0076]
• The next step in the process is to transfer the silicon pixel circuit film to a common module, either directly, or by a double transfer from substrate to carrier and then to the common module. A double transfer approach is illustrated in FIGS.[0077]4H-4L. To separate a circuit tile from thebuffer30 andsubstrate37, a first opening70 (in FIG. 4H) is etched in an exposed region ofrelease layer36 that occurs between tiles.Oxide layer34 etches more rapidly in HF thannitride layer36, thus a larger portion oflayer34 is removed to formcavity72. A portion oflayer36 thus extends over thecavity72.
• In FIG. 41, a[0078]support post76 of oxide is formed to fillcavity72 andopening70, which extends over a portion oflayer36. Openings or viaholes74 are then provided throughlayer36 such that an etchant can be introduced throughholes74, or throughopenings78 etched beneath therelease layer36, to remove layer34 (See FIG. 4J). The remainingrelease layer36 and the circuitry supported thereon is now held in place relative tosubstrate32 andbuffer30 with support posts76.
• Next, an epoxy[0079]84 that can be cured with ultraviolet light is used to attach an opticallytransmissive superstrate80 to the circuitry, andlayer36. Thebuffer30 andsubstrate32 is then patterned and selectively exposed to light such that regions ofepoxy84′ about theposts76 remain uncured while the remainingepoxy84′ is cured (See FIG. 4K). Thebuffer30 andsubstrate32 andposts76 are removed by cleavage of the oxide post and dissolution of the uncured84 epoxy to provide the thinfilm tile structure141, shown in FIG. 4L mounted oncarrier80.
• To form the final display panel, the edges of the[0080]carrier80 are trimmed to coincide with the tile borders. Thenitride release layer36 is removed by etching.
• As shown in FIG. 5A, a plurality of[0081]tile structures141 are then sequentially registered with one another and adhered to acommon module body110 using a suitable adhesive (not shown).Common module body110 is preferably patterned with interconnect metallization on the surface facing thetile structure141 for interconnecting individual tile circuitry with each other. Next, insulation and alignment layers, spacers, a sealing border and bonding pads for connections (not shown) are bonded onto the periphery of thecommon module body110. A screen printing process can be used to prepare the border. As shown in FIG. 5B, aplate117 containing thecolor filters120 and the counterelectrode (not shown) is bonded to the periphery thinfilm circuit tiles141 with the sealing border after insertion of spacers (not shown). The display is filled with the selectedliquid crystal material116 via a small filling hole or holes extending through the border. This filling hole is then sealed with a resin or epoxy. First andsecond polarizer films118,112 or layers are then bonded to both sides and connectors (not shown) are added. Finally, awhite light source114, or other suitable light source, is bonded topolarizer112.
• [0082]Pixel electrodes62 are laterally spaced from each other. Each pixel has atransistor51 and acolor filter120 or122 associated therewith. A bonding element or adhesive82 and opticallytransmissive superstrate110, such as glass or plastic completes the structure.Body110 is preferably a low temperature glass that can have a thickness preferably of about 200 to 1000 microns.
• In an alternative CLEFT process, thin single-crystal films, are grown by chemical vapor deposition (CVD), and separated from a reusable homoepitaxial substrate.[0083]
• The films removed from the substrate by CLEFT are “essentially” single-crystal, of low defect density, are only a few microns thick, and consequently, circuit panels formed by this process have little weight and good light transmission characteristics.[0084]
• The CLEFT process, illustrated in U.S. Pat. No. 4,727,047, involves the following steps: growth of the desired thin film over a release layer (a plane of weakness), formation of metallization and other coatings, formation of a bond between the film and a second substrate, such as glass (or superstrate), and separation along the built-in-plane of weakness by cleaving. The substrate is then available for reuse.[0085]
• The CLEFT process is used to form sheets of essentially single crystal material using lateral epitaxial growth to form a continuous film on top of a release layer. For silicon, the lateral epitaxy is accomplished either by selective CVD or, preferably, a lateral recrystallization or ISE process, or other recrystallization procedures. Alternatively, other standard deposition techniques can be used to form the necessary thin film of essentially single crystal material.[0086]
• One of the necessary properties of the material that forms the release layer is the lack of adhesion between the layer and the semiconductor film. When a weak plane has been created by the release layer, the film can be cleaved from the substrate without any degradation. As noted in connection with FIGS.[0087]4A-4C, the release layers can comprise multi-layer films of Si3N4 and SiO2. Such an approach permits the SiO2 to be used to passivate the back of the CMOS logic. (The Si3N4 is the layer that is dissolved to produce the plane of weakness.) In the CLEFT approach, the circuits are first bonded to the glass, or other transfer substrate, and then separated, resulting in simpler handling as compared to, for example, UV-cured tape.
• The plane of weakness is key to obtaining uniform cleaving between the circuits and the substrate. This plane may be formed by creating a pattern of carbon on the surface of the wafer so that only a small fraction of the underlying semiconductor surface is exposed. These exposed portions are used as nucleation cites for the epitaxial film. If the growth conditions are properly chosen, the film will grow laterally faster than vertically, leading to laterial overgrowth of the single crystal film. Within 1 m of vertical growth, the film becomes continuous and of high quality. However, the carbon layer is weak and, combined with the small fraction of exposed semiconductor areas where the film is strongly attached to the substrate, creates a plane of weakness. This plane can be used reliably and reproducibly to separate the film from the substrate. The substrate may be reused. These processes have been used to transfer a wide range of GaAs and Si circuits to alternative substrates such as glass, ceramic, and other materials, without harm to the active circuitry.[0088]
• In the ISE process, the oxide film is strongly attached to the substrate and to the top Si film which will contain the circuits. For this reason, it is necessary to reduce the strength of the bond chemically. This requires use of a release layer that is preferentially dissolved with an etchant without complete separation to form a plane of weakness in the release layer. The films can then be separated mechanically after the glass is bonded to the circuits and electrodes.[0089]
• Mechanical separation may be accomplished by bonding the upper surface of the Si film to a superstrate, such as glass, using a transparent epoxy. The film and glass are then bonded with wax to glass plates about 5 mm thick that serve as cleaving supports. A metal wedge is inserted between the two glass plates to force the surfaces apart. Since the mask has low adhesion to the substrate, the film is cleaved from the substrate but remains mounted on the glass. The substrate can then be used for another cycle of the CLEFT process, and the device processing may then be completed on the back surface of the film. Note that since the device remains attached to a superstrate, the back side can be subjected to standard wafer processing, including photolithography.[0090]
• One embodiment of the invention utilizes a recrystallization system, shown schematically in FIG. 6 to form the essentially single crystal Si thin film. A sample wafer[0091]134 is formed of poly Si, formed on SiO2, formed on an Si wafer. Acapping layer138 is formed over the poly Si. The wafer temperature is then elevated to near the melting point by alower heater130. An upper wire orgraphite strip heater132 is then scanned across the top of the sample134 to cause a movingmelt zone136 to recrystallize or further crystallize the polycrystalline silicon. The lateral epitaxy is seeded from small openings formed through the lower oxide. The resultant single crystal film has the orientation of the substrate.
• A number of unique devices and circuits have been formed using the above processing techniques. These techniques have been used to transfer CMOS active matrix LCD circuitry from ISE wafers to glass, and have yielded excellent displays with single crystal Si active matrix circuits. Silicon circuitry has been transferred to glass and shows no important changes in transistor characteristics after transfer. The technique has also been proved with III-V compound semiconductor circuits. For example, GaAs and AlGaAs monolithic series-connected photovoltaic energy converters have been made for power down a fiber application that yield exceptional performance. Also, two-dimensional multiplexed AlGaAs LED arrays (with over 32K pixels) have been made by transfer and two-sided processing and exhibit extremely high LED density as well as performance. The development of this broad range of Si and III-V circuits indicates the general applicability of the transfer process to a wide range of devices and circuits.[0092]
• III. Alternate Adhesion and Transfer Processes[0093]
• FIGS.[0094]7A-7D illustrate an alternate preferred double transfer process for adhering and transferring tiles of circuits of thin films of silicon to a common module body. The starting structure is asilicon wafer118 upon which anoxide layer116 and a thin film of poly-Si, —Si or x-Si114 is formed using any of the previously described processes such as ISE or CLEFT. A plurality of circuits, such as pixel electrodes, TFT's, Si drivers and Si logic circuits, are then formed in the thin film. FIG. 7A shows three such wafers, I, II, III. In wafer I,logic circuits40 are formed. In wafer II,pixel electrodes62 and TFT's51 are formed. In wafer III,driver circuits20 are formed. A wafer, or individual tiles diced from the wafer, is attached to asuperstrate transfer body112, such as glass or other transparent insulator, using an adhesive120. The adhesive can comprise commercially available epoxies.
• The wafer, or tile, is then cleaned and the[0095]native oxide118 is etched off the back surface. Depending on the thickness of the wafer, it may take up to 5 hours to etch theSi118 andoxide116 layers. The solution etches silicon very rapidly, i.e. 2 to 3 microns/min., and uniformly if the wafers are held horizontally in the solution with the etching surface face up. The acid has a very low etch rate on oxide, so that as the substrate is etched away and the buried oxide is exposed, the etching rate goes down. The observer can monitor the process and to stop the etch in the buriedoxide layer116′ without punching through to thethin silicon layer114 above it. Wafers up to 25 mils thick and oxides as thin as 4000 have been successfully etched using this process. An alternative etchant is hydrazine, which has a much higher etch rate selectivity or ethylene diamine pyrocatacol (EDP).
• When the silicon is completely gone, the vigorous bubbling, which is characteristic of silicon etching abruptly stops, signalling that the etching is complete.[0096]
• The[0097]thin films114 transferred to therespective glass superstrates112 are now rinsed and dried. If not already provided withcircuits40,51,62 or20, thefilms114 can be backside circuit processed, if desired.
• After all the necessary circuits are formed, as above, on[0098]transfer bodies112, they may now be diced and tiled onto a common module body13 (FIG. 7D) to perform a combined function, such as an AMLCD. The system can then be mounted on a helmet or head-mountable frame for direct or indirect viewing by the user.
• The[0099]logic circuits40 oftransfer body118 in col. A, FIG. 7C, are transferred to the border ofmodule body13, while thedriver circuits20 from thetransfer body118 in col. C, FIG. 7C, are disposed on the border between thelogic circuits40A and40B.
• Tiles of[0100]pixel electrodes62 and TFT's51 are formed by dicing or etching and are registered with respect to each other andpre-formed wiring50 onmodule body13, as shown in FIG. 7D.
• After all the circuits are registered and adhered to the module body, the[0101]transfer body118 and the epoxy120 is removed using a suitable etchant, such as HF for the case of a glass transfer body.
• Interconnection of circuits is achieved during registration or by direct laser writing where necessary. Also, if desired, the film can be transferred to another[0102]18 substrate and the first glass superstrate and adhesive can be etched off, allowing access to the front side of the wafer for further circuit processing.
• FIGS. 8A and 8B illustrate an alternative one-step silicon thin film transfer process in which GeSi is used as an intermediate etch stop layer. In this process,[0103]Si buffer layer126 is formed on anx-Si substrate128 followed by athin GeSi layer129 and a thin —Si, poly-Si, or x-Si device orcircuit layer132; using well-known CVD or MBE growth systems.
• The[0104]layer132 is then IC processed in the manner previously described in connection with FIGS.4E-H, to form circuits, such as TFT's200 and pixel electrodes202 (FIG. 8A). Next, the processed wafers, or tiles from the wafer, are mounted on a common module glass (or other)support280 using an epoxy adhesive of the type previously mentioned in connection with FIGS.7A-7B. The epoxy fills in the voids formed by the previous processing and adheres the front face to thesuperstrate280.
• Next, the[0105]original Si substrate128 andSi buffer126 are removed by etching, which does not affect the GeSi layer129 (FIGS. 8B). Finally, the GeSi layer124 is removed by brief submersion in a suitable etch.
• IV. Eye Tracker Embodiment[0106]
• Referring now to the schematic diagram of FIG. 9, it may be seen that the present invention relates to an[0107]eye tracking system410 that combines a flatpanel display device412 with an array ofoptical detectors14 to form aneye tracker device500. The flat panel display device is used as a monolithic substrate and light source for determining the position of theeye432. Thedetector array414 is aligned and transferred onto the active matrix electronics of the flat panel device. A test pattern and software incomputer418 analyzes the sensed data generated by the detector on display and determines the position of the eye.
• Light from[0108]display412 is used to project an image ontoviewing screen428 for viewing by the eye(s)432 of a viewer. The image to be displayed is generated incomputer418 and is coupled as an electrical input video signal to display412 alongline424. Image light rays fromdisplay412 pass throughdetector array14 and are projected ontoscreen428 where they may be superimposed on external images from an outside scene formed by light rays C.
• A video signal source provides video signals to the[0109]display device412. The video signal source can be any analog or digital video signal source including a Video Graphics Array (VGA) adaptor, National Television Systems Committee (NTSC) composite video source, high-resolution professional display adapters, Charge-Coupled-Devices (CCD), or other similar sources. In a preferred embodiment a CCD camera is mounted on the head mounted system so as to generate an image of the surroundings of the user and which is linked to the display of the head mounted system. This permits the user to look in a particular direction and receive an image on his/her display or viewing screen from the surrounding area. The display can be programmed to overlay selected images onto the sensed image. The eye tracker can be used to enhance the resolution of the image region that the user's eyes are directed upon. Horizontal and vertical synchronization signals from the video signal source are provided to a video interface. Red-Green-Blue (RGB) video signal components, if supplied by the video signal source, are provided to an encoder. If discrete red, green and blue signals are not supplied by the video source (e.g., NTSC composite video signal), then a single video signal must be supplied by the video source.
• The[0110]display device412 operates as a multi-frequency display device. Typically, video signals from the video signal source will not be synchronized to a fixed frequency. For example, a VGA adaptor generates synchronization signals that vary depending on the particular video mode in which the adaptor is operating. A standard VGA adaptor may generate a vertical synchronization frequency between about 56 and 70 Hz and a horizontal synchronization frequency between about 15 and 35 kHz. For professional display purposes (e.g., CAD/CAM) the vertical and horizontal synchronization frequency may be higher than described. To handle current high resolution displays, thedisplay device412 must adapt to vertical synchronization frequencies up to about 100 Hz and horizontal synchronization frequencies up to about 66 kHz. Consequently, thedisplay device412 adapts to changes in the synchronization frequencies.
• A light ray emanating from a particular pixel of[0111]display412 is shown as line B2. This ray is reflected by the screen428 (line B1) onto the eye optics (not shown) and on to the macula (not shown) ofeye432. The axial rays of greatest importance will impinge on the fovea of the eye, the most sensitive part of the macula. These rays return to the display in the vicinity of the original pixel because reflection from the fovea is approximately normal to the retina and therefore nearly axial. Non-axial rays which will impinge on the retina beyond the fovea will not be reflected back along the axial optical path and will not return to thedetector array414.
• The[0112]viewing screen428 can comprise, for example, the visor of a heads-up helmet mounted optical system for pilots and the integrated detector/display can be inserted in a helmet-mounted optical system without physical modification to the helmet or optics. Additionally, no physical contact with the eye is required.
• Once the axial rays B[0113]1, B2 return to the display, thedetector array14 identifies the portion of the array from which the axial ray emanated, by generating a voltage signal by a detector pixel located in the array nearest the returned ray. That portion of the array is, of course, the part of the display focussed on by the user. A test pattern fromcomputer418 is then interlaced with the display image to enable initial determination of the eye's position. Software, incomputer418, provides a cursor image fordisplay412 which is projected onscreen428 at the line-of-sight location. This cursor is interlaced to provide constant feedback to thedetector array414. The interlace frequency can be adjusted to make the cursor visible or not visible to the user.
• For the case of a partially transparent system of FIG. 9 in which scenes from the surroundings are superimposed on the display image, the[0114]detector array414 is provided with a narrow band pass filter overlay to reject all wavelengths except the wavelength of the cross hair or cursor, which must be one of the display primary colors. Suppose for example that the selected color is primary red. In this case, a narrow bandred rejection filter430 is placed on the outside of thescreen428, and a narrowred bandpass filter416 is placed over the pixels of thedetector array414. In this way, thedetector array414 only receives light originating from the display. A second method of accomplishing the same result is to use polarizing filters as shown in FIG. 10. In this case theflat panel display412 is an AMLCD light valve helmet or head mounted display (HMD), having apolarizer440 on its output face. The polarized nature of the light from thedisplay440, combined with a 90 crossedpolarizer442 on thescreen428, prevents unwanted light from the outside scene from propagating to the detector array. Further partially transparent imaging systems are described below in connection with FIGS.37A-37C.
• Another alternative is to chop or rapidly blink the video signals from[0115]computer418 for the cursor presentation so that software in the computer can subtract the background light. Yet, another alternative that can be used with LCD displays is to use infrared light that can pass through the red filters of the LCD. But this approach requires an IR rejection filter on the front of the viewing screen. It can be seen from the above that there are a number of methods of using thedisplay412 to provide a signal for thedetector array414, without interference from outside light.
• An exploded view of an AMLCD display and[0116]monolithic detector array414 in accordance with the invention is illustrated in FIG. 11. Note that a complete eye-tracker package can be made without substantially changing the overall dimensions of the display. As shown in FIG. 11, adetector array414 is formed of a III-V diode array450 transferred to aglass substrate452 or directly above and onto front glass454 of an activematrix LCD display412. Thedetector pixels462 are positioned so that each is completely above thedrive transistors464 of the active matrix circuit and therefore do not block any of the display's light output frompixel electrodes464. (See FIG. 12). The detector row and column interconnects (not shown) are positioned directly above the display row and columns, so that the interconnect wires do not block any light.
• Note that the cut-out shown in FIG. 12 is not required in practice since the[0117]detector array substrate452 is made of transparent material such as glass or quartz.
• For infrared detection, GaAs appears to be the best choice for the detector elements. The bandgap of GaAs is 1.43 eV, corresponding to an absorption edge of about 0.87 m. This material may also be suitable for visible light; however, if it is desirable to suppress infrared absorption in the detector, the bandgap can be increased to about 1.9 eV (0.65 m) by adding aluminum (Al) to form the ternary compound semiconductor AlxGax-1As. (A bandgap of 1.9 eV is obtained for x=0.38.)[0118]
• The process used to form the detector array is based on an LED array process as a baseline. In this process, the[0119]detector material470 is first grown onsubstrate472 by OMCVD. Arelease layer474 is formed that permits theepitaxial film470 to be separated from thesubstrate472, but separation is deferred until after thefront side metallization476 is formed (FIG. 13A). After metallization of rows of metallization and mesa etching to delineate thepixels462, the surface of the wafer is bonded to a carrier478 (FIG. 13B). This carrier is preferably the front panel454 ofdisplay412. Thesubstrate472 is then removed to yield a partially processeddetector array414 bonded to adisplay array412. The processing is then completed to form a matrix addressed two-dimensional array412 ofdetector pixels462 aligned with the TFT's464 (indicated by X's) but slightly displaced from corresponding pixel electrodes466 (indicated by dots) of the display array412 (FIG. 13C).
• The fabrication of an X-Y multiplexed array, in accordance with the invention, begins with the epitaxial growth of the required hetero-epi-layers of AlGaAs and GaAs layers on a GaAs or Ge substrate. In the case of the[0120]GaAs substrate616, anoptional layer614 of AlAs is formed between the active AlGaAs layers616 and thesubstrate612 to facilitate substrate removal by the etch-off method. The AlAs forms an etch stop layer. [Alternatively, the X-Y array can be removed from the substrate by a CLEFT process or chemical epitaxial lift-off]. In the case of Ge substrates, a layer of AlAs can be used as an etch stop, but AlAs is not really necessary, since the Ge substrate can be dissolved in H202 without harm to the AlGaAs active layers.
• FIG. 14A shows the epitaxial layer structure to comprise a[0121]bottom cladding layer616cof AlGaAs, an active GaAs (or AlGaAs)layer616bin which ap-n junction617 is formed by carbon doping during growth, atop cladding layer616aof AlGaAs and thinGaAs contact layer616d, all formed by OMCVD. A pattern ofcontact pads719 and busbars (not shown) is formed by photolithographic techniques, evaporation, and/or electroplating on the front surface, as shown in FIG. 14B. Next, the p/n junctions617 are isolated by etching part way into the epi-layers616, as shown in FIG. 14B. This step is not absolutely required at this point, however, it simplifies a later etch step in the process.
• The next stage of the process consists of bonding of the wafer to a[0122]support680, such as glass, ceramic, or thin stainless steel. (If the support is transparent to infrared radiation, downstream front-to-back alignments are facilitated, but the alignments can also be carried out by careful registration to the support edges.) The processed front side is bonded to thesupport680 using a suitable adhesive (not shown) (FIG. 14C). After thesupport680 is attached, the wafer orsubstrate612 is etched off (or cleaved off) leaving theLED film616 attached to thesupport680, as shown in FIG. 14D, in which the structure has been flipped over onto the support to expose the backside B for processing.
• Once the backside is exposed, any remaining non-essential material is removed from the back by selective etching in HF to expose a clean GaAs contact layer B. The backside (X-axis)[0123]contacts721 andbusbars721xare now photolithographically patterned and electroplated or evaporated onto thecontact regions616′.
• Finally, the backside is exposed to the mesa etch to totally separate the dots. At this point, all of the epi-material between the pixels is removed (FIG. 14E). Alternately, the isolation may be completed by implant isolation, or by limiting the current spreading. FIGS. 15, 17 and[0124]18 summarize the important steps of three alternate processes for fabricating LED's in accordance with the invention. Beneath each step is the corresponding wafer structure shown in side view.
• Referring now to FIG. 15, a mesa isolation method of dot definition is shown therein. Note that for each process step block, the corresponding structure is illustrated in section below. Step a comprises pre-epitaxial cleaning of[0125]wafer612 using well known techniques, such as soaking in H2SO4/H2O2 and H20 followed by OMCVD deposition of AlGaAs/GaAs epi-layers616, in which a p-n junction is formed in the active GaAs layer (Step b).
• Next, using well known photolithography techniques, individual[0126]dot junction areas640 are defined over the surface of epi-layers616 beneath areas of photoresist705 (Step c). Next, the exposed epi-layers616 are etched away down to just below the p/n junction or alternatively all the way down to substrate612 (Step d). The resist705 is removed and aprotective coating706 of Si3N4 or oxy-nitride (SiON) is formed over the top surface (Step e). Contactareas771 are photolithographically defined by resist715 over the nitride706 (Step f). Thenitride706 is etched away beneath the resist openings (Step g). The resist is stripped away and a “lift-off” photo-resistlayer717 is formed over the top surface, except where the metal contacts will reside (Step h).Front metallization layer719 is evaporated onto the resist contacting the exposed epi-layer surface aligned in the LED dot (Step i).
• The resist[0127]717 withmetallization719 is then removed using well-known photoresist stripper liquids, leavingmetal contacts719′ remaining and applied to each dot716 (Step j). These contacts extend over the nitride716 to the edge of the chip (See FIG. 16) where individual bond pads are formed to address each dot616′.Contact metallization721 is then applied to the back of thesubstrate612.
• FIG. 17 illustrates an alternate dot definition method utilizing ion beam iraplantation. Steps a and b are as set forth in connection with FIG. 15. In step c, an implant mask of[0128]photoresist705 is formed which definesregions641 between LEDs which will be ion bombarded to implant protons711 (Step d) to laterally isolate individual dots orpixels616′, separated by highly resistive bombardedregions641′ (See FIG. 17 notes). Next (Step e), a lift-off photoresist layer715 is formed on the exposed top surface of epi-layers716 with openings left wherecontact metallization719 will be evaporated (Step f). The metallization is removed everywhere, except where desired, to formindividual contacts719′ for each dot616′.Contact metallization721 is then applied to the backside (Step h).
• FIG. 18 depicts an alternate dot definition process that does not require a separate deposit of a dielectric layer with associated photolithography, as in FIG. 15. Steps a-b are as above. In this alternate method, after defining the dot edges (Step c), the cap or[0129]contact layer616dis etched away (Step d). The exposedepilayer surface616 is then anodized to form an insulatingoxide708, thus creating a dielectric in the proper pattern. This method, as in the method of FIG. 15, limits current spreading to the pixel area where it is desirable for uniform current injection. But, by removing the cap layer from regions between dots, illumination within the confines of each dot is maintained. Current spreading is further eliminated by growing an extremely thinupper cladding layer616a, which will have very high lateral resistivity. Conventional cladding layers are 20 microns or higher. OMCVD enables fabrication of 0.5 micron, or less, layers with 0.2 micron being a preferred thickness for layer16a.
• The resist[0130]705 is then removed (Step f) and aphotoresist layer715 formed, except where contacts are desired.Metal719 is evaporated over and between the resist (Step h) and removed (Step leavingcontacts719′ to each dot616′ The structure is then ready forback metallization721, as previously described in connection with FIG. 15 (Step j ).
• In a variation of FIG. 18, the[0131]cap616dandcladding layer616acould both be anodized, eliminating the need for a cap etch step.
• The above processes offer many advantages over other known systems of fabricating LEDs or LED bars. Some of these are the following:[0132]
• Lattice-Matched System. The epitaxy process is very nearly perfectly lattice matched, since it is made in the GaAs/AiGaAs system rather than the GaAs/GaAsP system. Thus, compositional grading to achieve lattice matching is not required. The epi-layers are thin (less than 3 microns) as opposed to 20 to 30 microns in the GaAs/GaAsP system. Since the layers are thinner and are made by OMCVD, the layers yield much more uniform electroluminescence, making the LED bar more uniform. Since the epitaxial layers are lattice matched, it is also a simple matter to change the process to grow LEDs of any wavelength in the range of about 650 nm to 870 nm. The above processes can also utilize GaInP for the active epi layers and AlGaInP for the cladding layers. Another possible lattice matched system is GaInAsP/InP.[0133]
• Better Confinement of Injected Carriers. The beneficial properties of AlGaAs layers can be used to enhance the optical output of the LED devices, in a manner similar to heterojunction lasers. The AlGaAs is used to reflect carriers so that they are confined to the volume In which the optical radiation is to be generated. This enables the generation of much higher efficiency and optical output than believed to be possible in the GaAs/GaAsP system.[0134]
• Epitaxially-grown P/N Junction. The junctions are grown during the OMCVD process. In general, in GaAs/GaAsP technology, the junction is diffused. The epitaxial junctions are of extremely high quality and can be placed anywhere in the structure-Diffused-zinc junctions used in GaAs/GaAsP have the following limitations: the zinc causes p-type doping, so the structure must be p-on-n (whereas epitaxial junctions can be p-on-n or n-on-p); the zinc concentration must be highest at the surface and must have a diffusion profile (whereas epitaxial doping can have any profile), the diffused Junctions are limited to zinc (whereas epitaxial structures can be zinc, or carbon, or other dopant as desired) Implant Isolation. In the FIG. 17 embodiment, the epitaxial wafers are implanted with protons to destroy the crystal quality of the regions between the dots. This isolation is used to prevent the current from spreading beyond the desired dot perimeter. (The GaAs/GaAsP technology uses patterned diffusion.) An additional advantage of implant isolation is that the surface becomes nonconducting so that the metallization can be placed directly-on the semiconductor, without dielectric insulators, and no short circuit will occur.[0135]
• Use of GaAs Cap. A very[0136]thin layer616d, about 1000A thick, of GaAs is provided on the top surface for three reasons: ease of contact, environmental stability, and improvement in current spreading. The GaAs is kept thin to allow most of the generated light to escape. If the cap is much thicker than 1000A, it will absorb a significant amount of light. Environmental stability is a factor because AlGaAs can oxidize in air if left uncoated. The GaAs cap16dprovides the required coating.
• By not removing all of the interpixel material, a path for lateral heat flow out of the pixel is preserved.[0137]
• As shown in FIG. 19, the front and backside processed[0138]X-Y array800 may be mounted directly tosilicon wafer823 in aprecise location810 with X and Ysilicon driver circuits820 and822 formed inwafer823 and coupled to the X andY bonding pads824 and826, respectively. Bonding ofarray800 towafer823 may also be accomplished by having thecontact pads826 replaced by cantilevered bars which extend over to pads onwafer823 which can be trimmed to form circuit bonding pads.
• Suitable[0139]silicon logic circuits830 andinterface circuits832 are formed onwafer823 to control whichpixel616 is illuminated in the X-Y matrix. Note that the driver circuits activate individual pixels by applying a positive voltage to a pixel in a top column, for example,pixel1601 viabus bar826a, while a negative voltage is applied to thesame pixel1601 via Y-driver822 tobottom bus bar824a, thus completing the current circuit through theLED1601.
• It should be noted that the substrate removal methods for fabrication of LED arrays include CLEFT, lift-off, and substrate etch-off. CLEFT and lift-off are appropriate if the substrate is to be reclaimed as a solid wafer. The etch-off process simply comprises the chemical dissolution of the substrate. Note that the substrate material may still be reclaimed in the etch-off process; however, it must be precipitated from the etch solution. The substrate can also be lapped off, as is conventionally done in the industry.[0140]
• Also note that in the first step of the backside process, undesired epitaxial layers are removed; these layers are present to initiate the epitaxy, or may be buffer layers that are not needed in the final device. To make their removal simple, an AlAs etch stop layer (not shown) may be provided in the epitaxy between these layers and the epitaxial device structure. The layers can then be removed in etches that stop at AlAs, such as the well known PA etches. At a pH of about 8, these etches dissolve GaAs 1000 times faster than AlGaAs. After the etch stops at the AlAs, the AlAs can be removed in HF or HCl.[0141]
• In the process described above, the backside of the substrate is provided with multiplex-compatible metallization to contact the back of each pixel. Note that this type of processing requires front-to-back alignment. The pixels are then separated by a mesa etch. Since the films are only about 5 microns thick, the mesa etch is straightforward and quick. The etching may be accomplished with either wet or dry processing. At this point, the exposed semiconductor may be coated with a dielectric to prevent oxidation.[0142]
• Finally, the wafers are formed into individual dice. The dice[0143]800 (See FIG. 19) are mounted in a pin grid array (PGA) or leadless chip carrier socket (neither shown). If the pixel count is sufficiently high (>1000), theX-Y drivers820,822 andlogic multiplexing circuits830 should be mounted within the chip carrier. The reason for this is that the wire count becomes excessive for high pixel numbers. The wire count is approximately the square root of the pixel count. Preferably, the array is mounted on the Si circuitry itself, and interconnected using thin film techniques and photolithographic processing. The circuit and array are then mounted in the leadless chip carrier or PGA.
• As shown in FIG. 20, reflection from the back surface may be used to enhance emission. FIG. 20 is a perspective view of an LED array pixel showing the upper and lower cladding layers[0144]616aand616cwith theactive layer616bbetween them. Thin contact layers616dand616eare formed on the front and back sides, respectively, andconductors719aandbrun orthogonal to each other on the contact layers. The backsurface contact layer616eof GaAs extends across the total pixel surface and serves as a back surface reflector. The back surface reflector reverses the light propagating toward the back of the pixel, so that it is directed toward the front surface. The back surface16emay also serve to scatter light into the escape cone; which is a range of angles that rays, propagating within the LED crystal, must fall within for the ray to propagate beyond the semiconductor/air interface.
• Tuning of individual epi-layers may also be provided to further improve LED efficiency. For example, assume a structure, such as the LED shown in FIG. 20, in which the epi-layers have the following properties:[0145]

  		Refractive	Wavelength	Composition
  	Layer	Index	λ/n(Å)	AlGaAs
  	AIR	1	6500	N/A
  	16d	3.85	1688	0
  	16a	3.24	2006	80%
  	16b	3.60	1806	38%
  	16c	3.24	2006	80%
  	16e	N/A	N/A	Metal

• The active layer[0146]16b, could be made “resonant” by making the active layer thickness a multiple of half the wavelength (i.e., a multiple of 903 Å). For example, an active layer thickness of 4510 Å or 5418 Å would be preferable to 5000 Å. Such a resonant structure could yield superluminescence or stimulated emission which would enhance the optical output. A benefit of stimulated emission in the resonant structure would be that all of the light thus generated would be in the escape cone.
• The front (top)[0147]cladding layer616ais set for maximum transmission (quarterwave or odd multiple). The quarterwave thickness is 503 Å, therefore the top layer should be 0.55 microns, or if better current spreading is needed, 1.05 microns.
• The back cladding layer can be tuned for maximum reflection by using even multiples of 503 Å, such as 10×503 or 5030 Å.[0148]
• Optional front and back Bragg reflector layers[0149]616fand616g, respectively, may be incorporated into the device of FIG. 20 during OMCVD growth, thereby converting the LED into a vertical cavity laser. The laser cavity is bounded by theBragg reflectors616fand616gand the emitted light will be phase coherent. The Bragg reflectors are formed by alternating many AlxGaAs/AlzGaAs layers. A sufficient number of layers will yield a high reflection coefficient. The electrical cavity is formed by the AlGaAs cladding layers. Thus, vertical cavity lasers can be in an X-Y array, or may be formed in a laser bar. The feature that makes this possible is the double-sided processing approach, which permits a wide range of pixel structures, including LEDs, lasers and detectors.
• A light detector array[0150]945 can be formed in a similar manner. To form a light detector array, the epitaxial films are doped so as to form a p-i-n structure, rather than an LED. The active layer comprises a semiconductor chosen for absorption over the wavelength range of interest. For example, long wavelength detection could utilize InAs grown on an InAs substrate. Alternatively, InGaAs grown on InP or GaAs could be utilized for mid-IR detection. Near IR is detected with GaAs or AlGaAs. The fabrication of the detector must include edge passivation to maintain minimal dark current, but is otherwise the same as the LED array processing previously described.
• The multiplexing electronic detector circuitry is somewhat different than the LED driver circuit, since it must sense the current generated in each pixel in sequence, rather than supply current. The electronics is nevertheless straightforward, and is similar to charge coupled device (CCD) circuitry. In fact, the device could be formed using a CCD array instead of a p-i-n array.[0151]
• An infrared-to-visible digital image converter can be formed from a[0152]detector950 and light emitting diode array800 (as shown in FIG. 22). The converter is useful for night vision devices, as well as for digital processing of IR and visible video data.
• Current image converters utilize a photocathode based system that converts IR radiation to visible. The conversion process is a direct analog process. Owing to this design, the direct analog process is not particularly amenable to digital image enhancement. There are also various displays that could be superimposed over the night vision display to provide the user with communication or computer data. However, the photocathode display is not easily adaptable to display applications.[0153]
• A digital pixel-based system, in accordance with FIGS. 21 and 22, functions both as an IR image converter, an image enhancing device, and a display.[0154]
• The converter invention consists of three main elements' the[0155]IR detector array950, the multiplexingelectronics970, and the light emitting diode (LED)array800. A diagram of the IR image converter is shown in FIG. 22. An IR image is focused by lens946 on a multiplexedX-Y array950 of IR detectors. The pixel data from the detectors is processed by theelectronics970, which then drives a synchronous multiplexedLED array800. Note that the processor can accept external data viadata port972 to add to or subtract from the image. In this way, image enhancement can be accomplished, or communications or other data can be superimposed on thedisplay800.
• As noted above, the[0156]detector array950 can comprise a Si charge coupled device, or if longer wavelength detection is required, can be made from p-i-n diodes formed from material in the InGaAs system. Thearray950 is fabricated using substrate etch-off or lift-off processing. along with backside processing. to form very thin structures with metallization on both sides, as more fully described above in connection with theLED array800.
• The intensity of the image produced by array[0157]300 may be controlled by varying the duty cycle timing or modulating the drive current of the LED pixels.
• The[0158]electronics970 consists of a multiplexing and sequencing circuit that first detects the charge or current in each IR detector and then couples this input data to a current amplifier that drives the corresponding LED pixel in theoutput array800. Theelectronic processor970 also accepts signals from an external source, such as a microprocessor that can be displayed on the LED array. Moreover, the electronics can supply that video data to the microprocessor for image enhancement and can accept a return signal to be displayed on the LED array300.
• The LED array consists of multiplexed thin film LED pixels formed from material in the AIGaInP′ family, and more particularly, AlGaAs for bright red displays. The array is formed using the previously described processing array steps. The pixel size can be as small as 25 microns square and, consequently, the display can offer extremely high resolution or alternatively, fairly low cost.[0159]
• As shown in FIG. 23, the[0160]detector950 andLED array800 can be stacked into a hybrid assembly comprised of a top thin film IRX-Y detector array950 affixed by light transparent glue to lower thinfilm LED array800 mounted onglass substrate620. Aglass lens960 is affixed to the top surface ofdetector950 andheat transfer openings960 provided as necessary for cooling purposes. The entire structure can be quite thin (1 mil), with theelectronics970 provided around the periphery. Ultimately, the monolithic thin array can be mounted on ordinary glasses for image enhancement of visible light, as well as for display of data superimposed on video images.
• The applications of the device of FIGS.[0161]21-23 include military night vision systems, range finders, advanced military avionics, personal communications systems, and medical systems In which real-time image enhancement is useful.
• As shown schematically in FIGS. 24 and 25, X-Y arrays can also be used to form a multicolor display. To make such a display, individual X-Y arrays labelled LED[0162]1, LED2 and LED3, are formed from two or more different epitaxial structures. The primary difference in the structure is in the active layer material761,762 and763. which must have different band gaps to create different colors. For example, red763 can be created with AlGaAs, and green762 can be created with InAiGaP. The top device LED1 may be a blue LED formed of II-VI material, such as ZnSe, ZnSSe or a group IV alloy such as SiC.
• The arrays must be stacked with the larger bandgap LED[0163]1 closer to the observer. The material with £he larger bandgap will be transparent to the radiation from the smaller bandgap. Thus, in this way, the observer will be able to see both colors.
• The creation of the stack of three LEDs is as follows: First, the three separate LED arrays LED[0164]1, LED2 and LED3 are formed, as previously described. Next, they are stacked together withglass600 between them.
• Transparent glue or[0165]epoxy900 is used to bond the stacks on top of each other. The upper and lower bonding pads P1 and P2 on each LED are laterally staggered with respect to other LEDs, so that individual LED pixels may be addressed (See plan view FIG. 25).
• Several points need to be emphasized regarding the formation of the[0166]integrated detector array414 anddisplay412. First, the matrix metallization (not shown) of the detector must be positioned over the metallization of the display. In this way, no decrease in the optical aperture of the display is introduced by the metal interconnects of thedetector array414. Second, thedetector pixels462 can be made as small as a few microns square provided the detector sensitivity is high enough. Since the TFT's are also in the order of a few microns wide, detector pixels of such size would not block light. Third, thedetector array414 does not need to use an active matrix, because III-IV materials, such as, GaAs and AlGaAs are extremely fast detectors (<1 s decay time) and so the detector array can be scanned as fast or faster than the display. Since the detector pixels are small, they can be placed over the transistors in the active matrix display, resulting in very little reduction in optical aperture of the display.
• The integrated[0167]eyetracker device500 can consist of a pair of units that can be simultaneously scanned bycomputer418 to obtain real time correlation between the probe or cursor signal and the detected LOS signal. This real-time signal correlation can be used to eliminate the complicated image processing software that is ordinarily needed to analyze a CCD dark pupil image.
• The line-of-sight information obtained may be processed in[0168]computer418 and coupled to controldevice420 alongline422 to execute functions, or to display412 alongline424 to present various images or for generating a high resolution image only in the line-of-sight vicinity.
• The detector array may alternatively be mounted on the back panel of the[0169]display412 or preferably integrated with the formation of the display array. In this integrated embodiment, the detector pixels are formed of Si on the TFT substrate in the same process in which the TFT's are formed. Each detector pixel is located adjacent a corresponding TFT pixel.
• The display array may be comprised of an EL panel. As stated previously, other preferred embodiments employ an emissive material such as an electroluminescent film, light emitting diodes, porous silicon or any light emitting material to form each pixel element of the display. To that end, another preferred embodiment of the present invention is illustrated in the perspective view of an electroluminescent (EL) panel display in FIG. 27A. The basic components of the EL display include an active[0170]matrix circuit panel1414, abottom insulator1423, anelectroluminescent structure1416, atop insulator1417 and an opticallytransparent electrode1419, which are secured in a layered structure. TheEL structure1416 is positioned between the two planar insulatinglayers1417 and1423 which prevent destructive electrical breakdown by capacitively limiting direct current flow through the EL structure and also serve to enhance reliability. Theinsulators1417 and1423 have high electrical breakdown so that they can remain useful at high fields which are required to create hot electrons in the EL phosphor layers. The capacitive structure of the display is completed by producing thin-film electrodes adjacent to each insulator. One of these electrodes is formed within thepixel array1422 and the other electrode is the opticallytransparent electrode1419 which allows light to exit the display.
• The array of[0171]pixels1422 formed on thecircuit panel1414 are individually actuated by a drive circuit. The circuit has first1418 and second1420 circuit components that are positioned adjacent to the array such that eachpixel1422 can produce an electric field in theelectroluminescent structure1416 between the pixel electrode and an element of theelectrode1419. The electric field causes anEL element1424 to be illuminated.
• The[0172]electroluminescent structure1416 may be formed of a single phosphor layer for a preferred embodiment having a monochrome EL display. In another preferred embodiment, theEL structure1416 is formed of a plurality of patterned phosphor layers for providing color display. The phosphor layers are patterned such that each color pixel includes red, green and blue phosphor elements. The EL color display can be formed based on the EL display formation process disclosed in international application PCT/US88/01680 to Barrow et al. Referring to FIG. 27B, eachEL element1424 is divided into single color elements such as red1476 and1482, green1478 and blue1480.
• To illuminate a single color element for a given[0173]EL element1424, the drive circuit causes an electric field to be formed between one of thebottom electrodes1462 and thetransparent electrode1419. For a selected illuminated single color element, the light emitting centers of the phosphor are impact excited by the flow of hot electrons through the phosphor layer when the electric field exceeds a known threshold. As such, thepixels1422 can be selectively actuated to provide any illuminated color for that pixel group.
• The active matrix pixel array employs transistors (TFTs) colocated with each pixel in the display to control the function of the pixel. As applied to EL displays, the active matrix approach offers significant advantages including reduced power dissipation in the circuit panel and increased frequency at which the AC resonant driver can operate. The formation of a useful EL active matrix requires TFTs that can operate at high voltages and high speeds. Single crystal silicon is preferred for achieving high resolution in a small (6in×6in or less) active matrix EL display.[0174]
• In an EL display, one or more pixels are energized by alternating current (AC) which is provided to each pixel by row and column interconnects connected to the drive circuitry. The efficient conduction of AC by the interconnects is limited by parasitic capacitance. The use of an active matrix, however, provides a large reduction of the interconnect capacitance and can enable the use of high frequency AC to obtain more efficient electroluminescence in the pixel phosphor and increased brightness. In accordance with the present invention, the TFTs that provide this advantage are formed in a single crystal wafer, such as bulk Si wafers, or thin-films of single crystal or essentially single crystal silicon. These high quality TFTs are employed in an EL panel display, providing high speed and low leakage as well as supporting the high voltage levels needed for electroluminescence.[0175]
• In preferred embodiments, single crystal silicon formed on an insulator (SOI) is processed to permit the formation of high voltage circuitry necessary to drive the EL display. More specifically, thin-film single crystal silicon formed by the ISE process or other SOI processes allows for fabrication of high voltage DMOS circuitry for the TFTs as well as low voltage CMOS circuitry for the drivers and other logic elements.[0176]
• The DMOS/CMOS drive circuitry configuration for controlling an EL monochrome display is illustrated in FIGS.[0177]27C-27D. Each active matrixEL pixel circuit1425 includes a CMOS and DMOS transistor (TFTs)1421aand1421brespectively. Thecapacitors1426a,1426band1426crepresent the parasitic and blocking capacitors normally present in an AC EL structure. Despite its complicated appearance, eachpixel circuit1425 should actually occupy only a small fraction of the pixel area even with array densities of up to 1000 lines/inch. The drive circuitry for an EL monochrome display is shown for simplicity purposes only. For an EL color display, the drive circuitry for each pixel would comprise threepixel circuits1425 selectively activated to drive the red, green or blue color elements.
• Referring to FIG. 27C, there are two unique aspects of the[0178]pixel circuit1425. The first is that the use of theDMOS transistor1421bon the output of the drive circuit allows the EL display to be driven with an AC drive signal at1428. This feature can be appreciated by considering just the DMOS transistor.
• Referring to FIG. 27D, an equivalent circuit for a[0179]DMOS transistor1421bincludes an NMOS device Xi with a shunting diode D1. If the gate on the NMOS transistor Xi is raised to the threshold voltage above the source, current will flow through the transistor XI during the positive AC drive pulse. The presence of the shunt diode D1 allows current to flow in the reverse direction regardless of the gate voltage, so that with a high gate voltage, current flows through the transistor Xi during both the positive and negative transitions. TheEL layer1429 is therefore being excited and will be illuminated as long as the gate is held high. If the gate is held low, that is at a voltage below the threshold voltage Vt, then the transistor X1 will not conduct during the positive drive pulse. Thus, theEL layer1429 will only see a series of negative pulse and will charge to the pulse potential during the first negative pulses and be prevented from discharging during the positive pulse by the rectifying behavior of the diode D1. Therefore, after a single brief illumination period, theEL layer1429 will remain passive since the total voltage across it and itsisolation capacitors1426band1426cremains constant.
• Referring back to FIG. 27C, the second unique feature of the[0180]circuit1425 is that it can be controlled by only two wires. The second feature is achieved in the present invention through the use of a p-channel MOS transistor1421a, and adiode1427. Thediode1427 may be fabricated as a lateral or vertical structure and would not add significantly to the overall area or complexity. Thediode1427 is needed because theNMOS transistor1421ais a symmetric device and would otherwise discharge thecapacitor1426aduring the illuminate period rendering the circuit and display inoperable.
• To insure the performance of the[0181]circuit1425, a circuit analysis was performed. Thecircuit1425 operates by first charging thecapacitors1426aby applying a low signal to the select line1413 (0 volts) in the analysis and then raising thedata line1411 to the desired voltage (in a range from 0.5 to 2 volts in this analysis). After the charging sequence, thecapacitor1426awill be charged to a voltage approximately equal to the difference between the data and select line signal levels and minus thediode1427 forward voltage drop. To turn on theoutput transistor1421b, theselect line1413 is first increased to about 1 volt and thedata line1411 is ramped from −2 volts to 0 volts. Theoutput transistor1421bremains on for a time which is directly proportional to the voltage that was stored on thecapacitor1426a. In this way, grey scale is achieved by thecircuit1425.
• A preferred EL display formation process includes the formation of a single crystal silicon film, fabrication of active matrix circuitry on the silicon film and integration of EL materials to form the emissive elements. To that end, FIGS.[0182]28A-28K illustrate the Isolated Silicon Epitaxy (ISE) process to form a silicon-on-insulator (SOI) film as well as a process for fabricating high voltage DMOS devices and low voltage CMOS devices on the ISE film to form circuit panel circuitry. Note that while the ISE process is shown herein, any number of techniques can be employed to provide a thin-film of single crystal Si.
• An SOI structure, such as that shown in FIG. 28A, includes a[0183]substrate1430 and an oxide1432 (such as, for example SiO2) that is grown or deposited on thesubstrate1430. A polycrystalline silicon film is deposited on theoxide1432, and the poly-Si film is capped with a capping layer1436 (such as for example, SiO2). The structure is the heated near melting point, and a thin movable strip heater (FIG. 6) is scanned above the top surface of the wafer. The heater melts and recrystallizes the silicon film that is trapped between the oxide layers, resulting in a full area single crystal silicon film1434.
• A thin single crystal layer of silicon[0184]434 is thus formed over theoxide1432 such that the oxide (or insulator) is buried beneath the Si surface layer. For the case of ISE SOI structures, after the capping layer is removed, the top layer is essentially single-crystal recrystallized silicon, from which CMOS circuits can be fabricated. The use of a buried insulator provides devices having higher speeds than can be obtained in conventional bulk material. Circuits containing in excess of 1.5 million CMOS transistors have been successfully fabricated in ISE material.
• As shown in FIG. 28B, the silicon film[0185]1434 is patterned to definediscrete islands1437 and1438 for each pixel. Anoxide layer1435 is then formed over the patterned regions including channels1448 between theislands1437 and1438. A twin well diffusion process is then employed to form both p and n wells. To form n wells,silicon nitride islands1439 are formed to isolate thoseislands1438 designated to be p wells (FIG. 17C). The remaining islands1437 are subsequently implanted with an n-type dopant1440 to formn wells1441. To form p wells, athick oxide layer1442 is grown over the n wells to isolate those islands from the p-type dopant1443, and the silicon nitride islands are removed (FIG. 28D). The non-isolated islands are then implanted with the p-type dopant443 to formp wells1444.
• Following the twin well formation, a thick oxide film is grown over the surface of the[0186]silicon islands1441 and1444 to form active area regions. More specifically, theoxide layer1446 is etched to a relatively even thickness andsilicon nitride islands1447 are deposited thereon (FIG. 28E). Next, a thick oxide film is grown around the surface of thesilicon islands1441 and1444 to formactive area regions1450 between the thick LOCOS field oxide regions1451 (FIG. 28F). Polysilicon is then deposited and patterned to form thegates1453 of the high voltage DMOS devices and thegates1454 of the low voltage CMOS devices (FIG. 28G). Note that thegate1453 of the DMOS device extends from theactive area region1450 over thefield oxide region1451. The edge of thegate1453 which is over theactive region1450 is used as a diffusion edge for the p-channel diffusion, while the portion of the gate which is over thefield oxide region1451 is used to control the electric field in the n well drift region.
• Following the channel diffusion, the n-channel and p-[0187]channel source1456,1459 anddrain regions1457,1460 are formed using arsenic and boron implantation (FIGS.28H-28J). Next, a borophosphorosilicate glass (BPSG)flow layer1458 is formed and openings are formed through theBPSG layer1458 to contact thesource1456, thedrain1457 and thegate1453 of the DMOS device as well as thesource1459 and thedrain1460 of the CMOS device (FIG. 28K). Further, a patternedmetallization1462 of aluminum, tungsten or other suitable metal is used to connect the devices to other circuit panel components. The preferred process comprises nine masks and permits fabrication of both high voltage DMOS and low voltage CMOS devices.
• The high voltage characteristics of the DMOS devices depend on several dimensions of the structure as well as the doping concentrations of both the diffused p-channel and n-well drift region. The important physical dimensions are the length of the n-well drift region, the spacing between the edge of the polysilicon gate in the active region and the edge of the underlying field oxide, and the amount of overlap between the polysilicon gate over the field oxide and the edge of the field oxide. The degree of current handling in the DMOS devices is also a function of some of these parameters as well as a function of the overall size of the device. Since a preferred embodiment includes a high density array (1M pixels/in2), the pixel area, and hence the transistor size, is kept as small as possible. Referring to FIG. 28L, the circuit panel can optionally be removed from the[0188]substrate1430 and transferred to a glass plate1431 upon which EL phosphors have been formed. The removal process can comprise CEL, CLEFT or back etching and/or lapping.
• FIGS.[0189]28A-29D illustrate the details of the fabrication process of an electroluminescent color display. As stated earlier, this fabrication process is based on the EL color display formation process disclosed in international application PCT/US8801680 to Barrows et al. The EL display formation process, whether for a monochrome or color display, comprises the sequential deposition of layers of an emissive thin-film stack. The phosphor layers are patterned such that each color pixel includes red, green and blue phosphor elements. The red color is obtained by filtering a yellow ZnS:Mn phosphor layer so as to only select the red component. The green and blue phosphor elements have components other than Mn for emitting in the desired spectral regions.
• The first layer of the EL display is the bottom electrode. In a preferred EL display formation process, the bottom electrode comprises the source or drain metallization of the transistor in the drive circuit. This electrode may be optimized for high reflection of the desired wavelength to increase the luminous efficiency of the EL panel. Referring to FIG. 29A, the fabrication process begins with the deposition of the[0190]bottom insulator1423, preferably covering the entire surface of the active matrix of thecircuit panel1414. The firstcolor phosphor layer1476 is then deposited onto the active matrix and patterned. A firstetch stop layer1477 is deposited, and a secondcolor phosphor layer1478 is deposited and patterned over the stop layer (FIG. 28B). A secondetch stop layer1479 is deposited, and a thirdcolor phosphor layer1480 is deposited and patterned over the second stop layer.
• Referring to FIG. 29C, the array of patterned[0191]phosphor layers1416 is then coated with thetop insulator1417. The twoinsulating layers1417 and1423 are then patterned to expose the connection points between the top electrodes and the active matrix circuit panel, and also to remove material from areas which external connections will be made to the drive logic. Thetop electrode1419 formed of an optically transparent material such as indium tin oxide is then deposited and patterned over the top insulator1417 (FIG. 29D). The deposition of the top electrode serves to complete the circuit between thephosphors1416 and theactive matrix circuitry1414. Ared filter1482 is then deposited and patterned over the red pixels, or alternatively is incorporated on a seal cover plate if a cover is used. Thered filter1482 transmits the desired red portion of the ZnS:Mn phosphor (yellow) output to produce the desired red color.
• Alternatively, the EL thin-film stack may be formed on a glass or other substrate to which the active matrix circuit panel is transferred by the aforementioned transfer processes. Yet another option comprises the transfer of both the circuit panel and the EL stack to another material such as a curved surface of a helmet-mounted visor. In a single-step transfer, the circuit is transferred to a flexible substrate. The flexible substrate is then bent to form a curved display. In a double-step transfer, the circuit is first bent to form a curved circuit and double transferred to a fixed curvature substrate. The curved direct view display makes use of the intrinsic stress on the silicon. The curved surface releases the stress on the circuit and may improve circuit performance.[0192]
• A preferred process for transferring and adhering thin-films of silicon from its support substrate to a different material is illustrated in FIGS.[0193]30A-30B. This process may be employed for transferring a circuit panel formed in thin-film silicon (FIGS.28A-28L) or an entire EL display (FIGS.29A-29D) and adhering it to a different material such as glass or a curved surface of a material.
• Referring to FIG. 30A, the starting structure is a silicon wafer[0194]1500 upon which anoxide layer1516 an a thin film ofsingle crystal silicon1514 is formed using any of the previously described techniques, such as ISE or CLEFT. A plurality ofcircuits1511 such as pixel electrodes, TFTs, drivers and logic circuits are then formed in the thin-film silicon1514. The SOI processed wafer is then attached to asuperstrate1512, such as glass or other transparent insulator or a curved surface of a material, using an adhesive1520.
• The wafer is then cleaned and the native oxide is etched off the[0195]back surface1518. The wafer is put into a solution. The etchant has a very low etch rate on oxide, so that as the substrate is etched away and the buried oxide is exposed, the etching rate goes down. The selectivity of the silicon etch rate versus the oxide etch rate can be very high (200:1). This selectivity, combined with the uniformity of the silicon etching, allows the etcher to observe the process and to stop in the buriedoxide layer1516′ without punching through to thethin silicon layer1514 above it. Wafers up to 25 mils thick and oxides as thin as 4000 Å have been successfully etched using this process. One such etchant is hydrazine.
• The thin film[0196]514 transferred to theglass1512 is now rinsed and dried. If not already provided with thecircuitry1511, it can be backside circuit processed. Also, if desired, the film can be transferred to another substrate and the glass superstrate can be etched off, allowing access to the front side of the wafer for further circuit processing.
• FIGS.[0197]31A-31B illustrate an alternative silicon thin-film transfer process in which GeSi is used as an intermediate etch stop layer. Referring to FIG. 31A, in this process, asilicon buffer layer1526 is formed on a singlecrystal silicon substrate1528 followed by athin GeSi layer1524 and a thin single crystal silicon device orcircuit layer1532; using well-known CVD or MBE growth systems.
• The[0198]layer1532 is then IC processed in a manner previously described to form circuits such asTFTs1600 orpixel electrodes1602. Next, the processed wafer is mounted on a glass orother support1680 using an epoxy adhesive. The epoxy fills in the voids formed by the previous processing and adheres the front face to thesuperstrate1680.
• Next, the[0199]original silicon substrate1528 and thesilicon buffer1526 are removed by etching with KOH, which does not affect the GeSi layer1524 (FIG. 31B). Finally, theGeSi layer1524 is selectively etched away which does not affect the silicon film1522.
• In this case, the detector array would be transferred to the[0200]EL panel1419.
• The eye tracking device of the invention offers numerous system simplifications. One simplification is made possible by the use of the high speed III-[0201]V detector array414. Scanning of the array can be synchronized with the display scan. This eliminates the complex software needed for pattern recognition in the typical CCD approach. This is because the reflected light can be analyzed pixel-by-pixel in real time to determine the area on which the viewer is focusing. Moreover, depending on the angular resolution needed, it may be possible to replace the detector matrix array with a much simpler array of pixels interconnected in a common parallel circuit, as shown in FIG. 12 comprisinganode plane482 and cathode plane480. Only two terminals are used for connection to thedetector plane482. Light reflection from the non-macular portion of the retina largely falls beyond thedetector array414 and macular reflection returns to some location on thearray414. The display413 is scanned row by row while the computer simultaneously monitors the reflected signal at the detector. The row yielding the highest signal is the row upon which the viewer is focused. A similar scan is performed for the columns to determine the column pixels upon which the viewer is focused.
• Referring now to the schematic diagram of FIG. 26, an alternate embodiment of the present invention will now be described. This embodiment relates to a direct viewing[0202]eye tracking system530 that combines a flatpanel display device492 with a substantially transparent array ofoptical detectors494 to form aneye tracker device520. As in FIG. 9, flatpanel display device492 is used as a monolithic substrate for the detector array and as a light source for determining the position of theeye496. Thedetector array494 anddisplay492 are preferably formed as described above. The array is aligned and transferred onto the active matrix electronics of theflat panel display492. A test pattern and software incomputer498 analyzes the sensed data generated by theindividual detectors502 of thearray494 and determines the position of the eye based upon which detector(s) senses light reflected from the eye.
• Light from[0203]display492 is used to project an image for viewing by the eye(s)492 of a viewer. The image to be displayed is generated incomputer498 and is coupled as an electrical input video signal to display492 alongline506. Image light rays fromdisplay492 pass throughdetector array494 and are viewed by theeye496.
• A light ray emanating from a particular pixel P[0204]1 ofdisplay492 is shown as line L1. This ray impinges on the fovea of theeye496 and is reflected back along line L1. The ray returns to thedisplay492 in the vicinity of the original pixel because reflection from the fovea is approximately normal to the retina and therefore nearly axial. Non-axial rays which impinge on the retina beyond the fovea will not be reflected back along the axial optical path.
• Once the axial ray L[0205]1 returns to thedisplay492, thedetector array494 identifies the portion of the array at which the axial ray returns by generating a voltage signal from a detector pixel P2 located in the array nearest the returned ray. That portion of the array is, of course, the part of the display focussed upon by theeye496 of the user. This voltage signal, indicative of eye position, is coupled online508 tocomputer498. A test pattern from computer98 is then generated bycomputer418 and interlaced with the display image to indicate to the user the eye's position. Software, incomputer418, provides a test pattern in the form of cursor image ondisplay492 which is formed at the line-of-sight location. The cursor is interlaced to provide constant feedback to thedetector array494. The interlace frequency can be adjusted to make the cursor visible or not visible to the user. Anoptional lens system495 may be employed between the eye and array to enhance the image projected from thedisplay492. The line-of-sight information obtained inarray494 may be processed incomputer498 and coupled to controldevice490 to execute functions or may be coupled to present various images, such as, the previously mentioned cursor.
• V. Optics For Head-Mounted System[0206]
• A preferred embodiment of the invention is illustrated in the direct view, helmet mounted display system of FIG. 32. An active matrix single crystal[0207]silicon display device2010 is mounted in close proximity to theeye2012. Alens2014 is used to deliver a focussed image to the eye.Lens2014 has a given thickness and a diameter d. Table 1 lists characteristics of commercially available lens including diameter, F# and center thickness. Other lenses having the desired dimensions are easily manufactured to provide the thickness and focal length necessary.

  	TABLE 1
  		Nom.	Nom.
  	Diam.	f	BFL		Ctr.	Edge
  	in.	@589 nm	@589 nm		Thk.	Thk.
  	(mm)	(mm)	(mm)	F/#	(mm)	(mm)

  	0.5	11	9	0.8	5.7	1.34
  	(12.7)	13.7	12.2	1.0	4.3	1.1
  		16.6	15.4	1.3	3.6	1.1
  		20.5	19.5	1.5	3.1	1.1
  		26.4	25.6	2.0	2.6	1.1
  		38.4	37.7	3.0	2.1	1.1
  		51.3	50.7	4.0	2.0	1.2
  	1.0	20	18	0.8	11.0	2.3
  	(25.4)	27.4	24.6	1.0	8.2	1.8
  		33	30.7	1.3	6.7	1.6
  		39	37	1.5	5.8	1.6
  		51.7	50.2	2.0	4.7	1.6
  		63.6	62.3	2.5	4.0	1.6
  		76.6	75.2	3.0	4.0	1.9
  		101.6	100.3	4.0	4.0	2.4
  	1.5	34.4	29.4	0.85	14.0	1.9
  	(38.1)	40	36	1.0	12.0	2.1
  		52.5	49.4	1.3	9.1	2.0
  		64.2	61.7	1.7	7.5	1.8
  		77	74.8	2.0	6.5	1.8
  		101.8	100	2.6	5.3	1.8
  		127.2	125.6	3.3	5.0	2.2
  	2.0	42	34.2	0.8	21.0	2.4
  	(50.8)	53.6	48.4	1.0	15.0	2.0
  		65	61	1.2	12.0	1.7
  		77.8	74	1.5	11.0	2.6
  		102	100	2.0	8.3	2.0
  		127.6	125.3	2.5	7.0	2.0
  		176.5	174.4	3.5	6.4	2.8

• The distance from the[0208]center axis2018 oflens2014 to thedisplay2010 is denoted by P. The active matrix display has a high pixel density so as to match the resolution of the human eye. By increasing the resolution, or the density of pixels in theactive matrix display2010, and at the same time reduce the size of the display it is possible to position the display closer to the eye.
• Where the distance P is less than 2.5 centimeters, the pixel density is at least 200 lines per centimeter and preferably over 400 lines per centimeter to provide the desired resolution.[0209]
• Where P=1.5 centimeters, the[0210]display10 is about 1.27 centimeters in diameter and has a pixel density of about 400 lines per centimeter. The focal length FL between thelens2014 and focal point F is generally defined by the Expression:$\frac{1}{F_L}=\frac{1}{P}+\frac{1}{D_{\mathrm{IMAGE}}}$

  
• Solving for the distance to the image we obtain[0211]$D_{\mathrm{image}}={\left(\frac{1}{F_L}-\frac{1}{P}\right)}^{-1}$

  
• As the human eye will optimally focus an image at a distance of about 400 centimeters (about 15 feet), and as the focal length of the lens is preferably small enough to focus the image onto the eye over a short distance, the diameter of the lens should be less than 3 centimeters and preferably under 2.0 centimeters.[0212]
• Table 2 defines the relationship between lens diameter d, and the distance between the lens and the display P in accordance with the invention where DIMAGE is about 400 centimeters:[0213]

  	TABLE 2
  	Lens Diameter, d	Object Distance P (all in cm)

  	0.6	0.48
  	0.8	0.64
  	1	0.80
  	1.2	0.96
  	1.4	1.12
  	1.6	1.28
  	1.8	1.43
  	2	1.59
  	2.2	1.75
  	2.4	1.91
  	2.6	2.07
  	2.8	2.23
  	3	2.39

• The above summarizes the preferred elements of a head mounted display where the active matrix display and lens system are mounted in close proximity to the eye. Note that the lens need not be circular in shape, however, but can be of a different shape to provide more peripheral information to the eye.[0214]
• The following embodiment comprises a simple optical approach to attain a brightness increase of up to 100% by reducing a common parasitic loss. This loss obtains in all liquid crystal display light valves at the first polarizing filter, which attenuates one half of the unpolarized light emanating from the lamp. In other words, the light source of the display generates light of two polarizations; one polarization (half of the light) is absorbed by the polarizing filter to make it suitable for modulation by the liquid crystal.[0215]
• In this embodiment, as shown in FIG. 33, the light from[0216]source30 is polarized, not by a polarizing filter, but by a Brewsterpolarizing window2032 which passes onepolarization2033 only tolight valve2036. Theother polarization2034 is reflected, atwindow2032 and reflected again atmirror2037 and directed to asecond light valve2038. There are at least two implementations of this invention, as follows:
• In a head-mounted display the[0217]Brewster window2032 can be used to pass polarized light, TE polarized for example, to theright eye2035 light valveliquid crystal display2036. The reflected light, TM polarized in this example, is passed to theleft eye2039 light valveliquid crystal display2038. Neither light valve requires a “first” polarizer, although the presence of one introduces only a slight reduction in fluence since the light is already polarized. Thus, substantially all of the incident light is passed to the liquid crystal, leading to near doubling of the optical efficiency. Of course, the liquid crystal in the left and right liquid crystal display must be rotated 90 with respect to each other to account for the polarization of the TE and TM polarizations of the light. The absence of a “first” polarizing filter can reduce the cost of the display.
• Another preferred embodiment of the invention is illustrated in FIG. 34. In this embodiment the[0218]active matrix2050 is fabricated where the pixel geometry and pixel area is variable as a function of the position of the pixel within the matrix. This provides a wide angle field of view image that can be projected onto the internal surface of theface shield2054 of the head mounted display. This visual effect can also be done electronically by transforming the video input such that the intensity of appropriate pixels is adjusted to conform to the viewer's perception. The eye tracking system described previously can be used to adjust intensity depending upon the direction in which each eye is looking.
• FIG. 35 illustrates a detailed view of a portion of the active matrix surface area.[0219]Pixels2060,2062,2064 and2068 have an increasing surface area as the distance from the pixel to thematrix center2066 axis is increased. The distance between adjacent column lines and between adjacent row lines also increases as a function of the distance fromcenter axis2066. The matrix can be a backlit transmission display or an emission type display. The active matrix can be formed on a first substrate and transferred onto either a flat or curved substrate prior to mounting onto the optical support assembly of the helmet. The active matrix can also be transferred to a flat substrate that is subjected to a low temperature anneal in the range of 300-400° F. and preferably at about 350° F. that will provide a desired curvature to the active matrix.
• A further embodiment is illustrated in FIG. 36 wherein separate active[0220]matrix display elements2070,2072,2074 etc. are mounted or tiled onto aplastic visor screen2076. The visor screen can be polycarbonate, polyethylene or polyester material. Eachdisplay element2070,2072,2074 can havedriver circuitry2082,2080,2078, respectively, formed separately on the edge.
• FIGS.[0221]37A-37C illustrate other preferred embodiments of a direct-view display system. Light from adisplay device1610 is represented bylight ray1615. Thelight ray1615 from thedisplay1610 may pass through an optical system orlens1620. The ray of light1615 from thedisplay1610 is combined with ambient light1690 before becoming incident on a viewer'seye1600. Thus, the image created by thedisplay device1610 appears to the viewer to float in the viewer's field of vision.
• There are various means of combining the[0222]display image1615 with theambient image1690, which will now be described. FIG. 37A illustrates a preferred embodiment of the invention using aprism1710 to combine the images. The hypotenuse of the prism may be coated with a partial reflector orelectrochromatic material1712 to attenuateambient light1690. FIG. 37B illustrates a preferred embodiment of the invention using alenticular structure1720 as an image combiner. The gradings are spaced such that theeye1600 cannot distinguish lines in thestructure1620. In a preferred embodiment, the grating density is greater than or equal to 150 per inch. FIG. 37C is similar to the lenticular structure in FIG. 37B except that a Fresnellenticular structure1730 is used. In bothlenticular structures1720,1730, theflat surface1722,1732 may also be coated with a partial reflector or electrochromatic material. In either of FIGS.37A-37C, thedisplay system1610 may be mounted adjacent to the viewer's head. In a preferred embodiment of the invention, thedisplay device1610 is mounted adjacent to the sides of the viewer's head, such as on the sides of a viewer. The head mounted systems described herein utilize audio circuitry and acoustic speakers to deliver sounds to the user's ears and can employ sensor systems such as cameras, magnetic position sensors, LED's or ultrasound for determining the position of the user's head. Additional sensors on a user's glove or other actuators can be electronically connected to a system data processor to provide interactive capabilities.
• Equivalents[0223]
• The preceding description is particular to the preferred embodiments and may be changed or modified without substantially changing the nature of the invention. For example, while the invention has been illustrated primarily by use of a passive substantially transparent LCD display, other type displays both active and passive are within the contemplation of the invention; such as, without limitation, the following: active displays, e.g., plasma display panels, electroluminescent displays, vacuum fluorescent displays and light emitting diode displays; passive displays: electrophoretic image displays, suspended particle displays, twisting ball displays or transparent ceramic displays. In each case, the eye tracking photodetector system can be formed in the same film as the display pixel or monolithically formed above or below the pixel to sense which pixel or group of pixels receive eye reflected light. While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.[0224]

Claims (8)

1. A method of determining the direction in which an eye of a viewer is looking comprising:

a) forming an image on a viewing screen for viewing by the eye of a viewer by projecting light from a display onto said screen; and

b) detecting light reflected from the eye of the viewer, the light emanating from the display and reflected by the eye along an optical path.

2. The method ofclaim 1 wherein the viewing screen comprises a visor through which the viewer can see an external scene and the image is superimposed upon the viewing screen.

3. The method ofclaim 1 wherein the image comprises a cursor and the image is projected at a predetermined frequency and further comprising the steps of filtering frequencies other than the projected image frequency for viewing on the viewing screen.

4. The method ofclaim 2 further comprising the steps of polarizing the projected light in one plane and polarizing the light from the external scene in an opposite plane.

5. The method ofclaim 1 further comprising determining the direction of the eye by sensing which detectors detect the reflected light.

6. The method ofclaim 5 wherein the image comprises a cursor and the image is projected at a predetermined frequency and further comprising the steps of filtering frequencies other than the projected image frequency for viewing by the viewer.

7. The method ofclaim 6 further comprising the steps of polarizing the projected light in one plane and polarizing the light from an external scene in a opposite plane.

8. The method ofclaim 1 for revising said image in response to eye position determinations comprising the steps of:

a) projecting said image for viewing by the eye using a display comprising an array of pixels;

b) providing an array of photodetectors with each photodetector aligned with a respective pixel, and converting light from the pixles reflected by the eye into a electrical signal indicative of line-of-sight position; and

c) generating signal for revising said image.

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