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US20040068602A1 - Apparatus, method and system for accelerated graphics port bus bridges - Google Patents

Apparatus, method and system for accelerated graphics port bus bridgesDownload PDF

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US20040068602A1
US20040068602A1US10/679,734US67973403AUS2004068602A1US 20040068602 A1US20040068602 A1US 20040068602A1US 67973403 AUS67973403 AUS 67973403AUS 2004068602 A1US2004068602 A1US 2004068602A1
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agp
queue
read
result
write
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Sompong Olarig
Usha Rajagopalan
Ronald Horan
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Hewlett Packard Development Co LP
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Assigned to HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.reassignmentHEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).Assignors: COMPAQ INFORMATION TECHNOLOGIES GROUP LP
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Abstract

A computer system having at least one central processing unit, system memory, and a core logic capable of accepting an AGP bus is provided with an AGP to AGP bridge connected to the standard AGP bus. The AGP to AGP bridge can accommodate two or more AGP-compatible devices that can be accessed through the standard AGP bus via the AGP to AGP bridge. A PCI to memory bridge is also provided within the AGP to AGP bridge so that PCI devices may be connected to the AGP to AGP bridge. The AGP to AGP bridge is fitted with an overall flow control logic that controls the transfer of data to or from the various AGP devices and the standard AGP bus that is connected to the core logic of the computer system. The AGP to AGP Bridge can utilize a standard 32-bit AGP bus as well as (two) dual 32-bit buses to enhance bandwidth. In an alternate embodiment of the invention, the dual 32-bit buses can be combined to form a single 64-bit bus to increase the available bandwidth. Alternate embodiments of the AGP to AGP Bridge can accommodate the single 64-bit AGP bus for increased performance. Another alternate embodiment can accommodate peer-to-peer transfer of data between AGP busses on the bridge.

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Claims (46)

What is claimed is:
1. A computer system, said computer system having a central processing unit, a core logic connected to said central processing unit, system random access memory connected to said core logic, and a first AGP bus connected to said core logic, said apparatus further comprising:
an AGP to AGP bridge, said AGP to AGP bridge constructed and arranged to connect at least two AGP-compatible devices to said computer system via said first AGP bus.
2. A computer system as inclaim 1, wherein said first AGP bus is a 32-bit bus.
3. A computer system as inclaim 2, said AGP to AGP bridge further comprising:
a first interface target and arbiter connected to said first AGP bus;
a first read data return queue connected to said first interface target and arbiter;
a first read and write request queue connected to said first interface target and arbiter;
a first write data queue connected to said first interface target and arbiter;
a second interface target and arbiter connected to a second AGP bus;
a second read data return queue connected to said second interface target and arbiter, said second read data return queue further connected to said first read data return queue;
a second read and write request queue connected to said second interface target and arbiter, said second read and write request queue further connected to said first read and write request queue;
a second write data queue connected to said second interface target and arbiter, said second write data queue further connected to said first write data queue;
a third interface target and arbiter connected to a third AGP bus;
a third read data return queue connected to said third interface target and arbiter, said third read data return queue further connected to said first read data return queue;
a third read and write request queue connected to said third interface target and arbiter, said third read and write request queue further connected to said first read and write request queue;
a third write data queue connected to said third interface target and arbiter, said third write data queue further connected to further connected to said first write data queue; and
a flow control logic, said flow control logic connected to said first read data return queue, said first read and write request queue, said first write data queue, said first interface target and arbiter, said second read data return queue, said second read and write request queue, said second write data queue, said second interface target and arbiter, said third read data return queue, said third read and write request queue, said third write data queue, and said third interface target and arbiter;
wherein said flow control logic regulates the transfer of requests, replies, and data between said first AGP bus, said second AGP bus and said third AGP bus.
4. A computer system as inclaim 3, wherein said AGP to AGP bridge has a PCI interface.
5. A computer system as inclaim 4, wherein said PCI interface comprises:
a first PCI master/target interface connected to said first AGP bus;
a first PCI target state machine connected to said first PCI master/target interface;
a first PCI master state machine connected to said first PCI master/target interface;
a second PCI master/target arbiter connected to said second AGP bus;
a second PCI target state machine connected to said second PCI master/target arbiter and to said first PCI target state machine;
a second PCI master state machine connected to said second PCI master/target arbiter and to said first PCI master state machine;
a third PCI master/target arbiter connected to said third AGP bus;
a third PCI target state machine connected to said third PCI master/target arbiter and to said first PCI target state machine; and
a third PCI master state machine connected to said third PCI master/target arbiter and to said first PCI master state machine;
wherein said PCI interface handles request, reply, and data transfers between said first AGP bus, said second AGP bus and said third AGP bus within the PCI protocol.
6. A computer system as inclaim 1, wherein said first AGP bus is a 64-bit bus acting as a first 32-bit AGP bus and a second 32-bit AGP bus, said first and said second 32-bit AGP buses capable of operating concurrently.
7. A computer system as inclaim 1, wherein said first AGP bus is a 64-bit bus and said AGP to AGP bridge is an ASIC that interfaces directly with said core logic, said first AGP bus behaves as a superset of the standard 32-bit AGP bus.
8. A computer system as inclaim 7, wherein said AGP to AGP bridge further comprises an REQ64#, an ACK64#, a C/BE[7:4]#, an AD[63:32], and an ST[3:2].
9. A computer system, said computer system having a central processing unit, a core logic connected to said central processing unit, system random access memory connected to said core logic, and a first AGP bus connected to said core logic, said apparatus further comprising:
a first AGP bus connected to said core logic, said first AGP bus consisting of a 64-bit bus that is configured as two 32-bit buses, each of said 32-bit buses acts as a standard AGP bus to said core logic, each of said 32-bit bus can operate concurrently with the other of said 32-bit bus.
10. A computer system as inclaim 9, wherein said AGP to AGP bridge has a PCI interface.
11. A computer system, said computer system having a central processing unit, a core logic connected to said central processing unit, and system random access memory connected to said core logic, said apparatus further comprising:
a first AGP bus connected to said core logic, said first AGP bus being a 64-bit bus.
12. A computer system as inclaim 11, wherein an AGP to AGP bridge is connected to said first AGP bus, said AGP to AGP bridge being an ASIC that interfaces directly with said core logic.
13. A computer system as inclaim 1, said computer system further comprising a geometry processor connected to said AGP to AGP bridge.
14. A computer system as inclaim 1, said computer system further comprising a rendering processor connected to said AGP to AGP bridge.
15. A computer system as inclaim 1, said computer system further comprising a geometry processor and a rendering processor, each of said processors connected to said AGP to AGP bridge.
16. A computer system as inclaim 15, wherein said geometry processor and said rendering processor can communicate without using said core logic.
17. A computer system as inclaim 15, wherein said geometry process and said rendering processor reside on a printed circuit board.
18. A computer system as inclaim 13, wherein said geometry processor resides on a geometry processor board.
19. A computer system as inclaim 14, wherein said rendering processor resides on a rendering processor board.
20. A method of transferring data within a computer system, said computer system having a central processing unit, a core logic connected to said central processing unit, system random access memory connected to said core logic, and a first AGP bus connected to said core logic, said computer system further having an AGP to AGP bridge, said AGP to AGP bridge constructed and arranged to connect at least two AGP-compatible devices to said computer system via said first AGP bus, said AGP to AGP bridge further having a first interface target and arbiter connected to said first AGP bus, a first read data return queue connected to said first interface target and arbiter, a first read and write request queue connected to said first interface target and arbiter, a first write data queue connected to said first interface target and arbiter, a second interface target and arbiter connected to a second AGP bus, a second read data return queue connected to said second interface target and arbiter, said second read data return queue further connected to said first read data return queue, a second read and write request queue connected to said second interface target and arbiter, said second read and write request queue further connected to said first read and write request queue, a second write data queue connected to said second interface target and arbiter, said second write data queue further connected to said first write data queue, a third interface target and arbiter connected to a third AGP bus, a third read data return queue connected to said third interface target and arbiter, said third read data return queue further connected to said first read data return queue, a third read and write request queue connected to said third interface target and arbiter, said third read and write request queue further connected to said first read and write request queue, a third write data queue connected to said third interface target and arbiter, said third write data queue further connected to said first write data queue, and a flow control logic, said flow control logic connected to said first read data return queue, said first read and write request queue, said first write data queue, said first interface target and arbiter, said second read data return queue, said second read and write request queue, said second write data queue, said second interface target and arbiter, said third read data return queue, said third read and write request queue, said third write data queue, and said third interface target and arbiter, said method comprising the steps of:
(a) transferring data between said first AGP bus and said second AGP bus.
21. A method of transferring data within a computer system, said computer system having a central processing unit, a core logic connected to said central processing unit, system random access memory connected to said core logic, and a first AGP bus connected to said core logic, said computer system further having an AGP to AGP bridge, said AGP to AGP bridge constructed and arranged to connect at least two AGP-compatible devices to said computer system via said first AGP bus, said AGP to AGP bridge further having a first interface target and arbiter connected to said first AGP bus, a first read data return queue connected to said first interface target and arbiter, a first read and write request queue connected to said first interface target and arbiter, a first write data queue connected to said first interface target and arbiter, a second interface target and arbiter connected to a second AGP bus, a second read data return queue connected to said second interface target and arbiter, said second read data return queue further connected to said first read data return queue, a second read and write request queue connected to said second interface target and arbiter, said second read and write request queue further connected to said first read and write request queue, a second write data queue connected to said second interface target and arbiter, said second write data queue further connected to said first write data queue, a third interface target and arbiter connected to a third AGP bus, a third read data return queue connected to said third interface target and arbiter, said third read data return queue further connected to said first read data return queue, a third read and write request queue connected to said third interface target and arbiter, said third read and write request queue further connected to said first read and write request queue, a third write data queue connected to said third interface target and arbiter, said third write data queue further connected to said first write data queue, and a flow control logic, said flow control logic connected to said first read data return queue, said first read and write request queue, said first write data queue, said first interface target and arbiter, said second read data return queue, said second read and write request queue, said second writ data queue, said second interface target and arbiter, said third read data return queue, said third read and write request queue, said third write data queue, and said third interface target and arbiter, said method comprising the steps of:
(a) transferring data between said first AGP bus and said third AGP bus.
22. A method of transferring data within a computer system, said computer system having a central processing unit, a core logic connected to said central processing unit, system random access memory connected to said core logic, and a first AGP bus connected to said core logic, said computer system further having an AGP to AGP bridge, said AGP to AGP bridge constructed and arranged to connect at least two AGP-compatible devices to said computer system via said first AGP bus, said AGP to AGP bridge further having a first interface target and arbiter connected to said first AGP bus, a first read data return queue connected to said first interface target and arbiter, a first read and write request queue connected to said first interface target and arbiter, a first write data queue connected to said first interface target and arbiter, a second interface target and arbiter connected to a second AGP bus, a second read data return queue connected to said second interface target and arbiter, said second read data return queue further connected to said first read data return queue, a second read and write request queue connected to said second interface target and arbiter, said second read and write request queue further connected to said first read and write request queue, a second write data queue connected to said second interface target and arbiter, said second write data queue further connected to said first write data queue, a third interface target and arbiter connected to a third AGP bus, a third read data return queue connected to said third interface target and arbiter, said third read data return queue further connected to said first read data return queue, a third read and write request queue connected to said third interface target and arbiter, said third read and write request queue further connected to said first read and write request queue, a third write data queue connected to said third interface target and arbiter, said third write data queue further connected to said first write data queue, and a flow control logic, said flow control logic connected to said first read data return queue, said first read and write request queue, said first write data queue, said first interface target and arbiter, said second read data return queue, said second read and write request queue, said second write data queue, said second interface target and arbiter, said third read data return queue, said third read and write request queue, said third write data queue, and said third interface target and arbiter, said method comprising the steps of:
(a) transferring data between said second AGP bus and said third AGP bus.
23. The method ofclaim 20, wherein said step (a) further comprises the steps of:
(a1) if the request is on said second AGP bus, then adding said request to said second AGP read and write request queue; and
(a2) reorder request according to a set of ordering rules.
24. The method ofclaim 20, wherein said step (a) further comprises the steps of:
(a1) issuing a signal from said overall flow control logic to start a transaction;
(a2) arbitrating and starting a read reply transaction;
(a3) getting data from said second AGP read data return queue; and
(a4) inserting wait states upon instructions from said flow control logic.
25. The method ofclaim 21, wherein said step (a) further comprises the steps of:
(a1) if the request is on said third AGP bus, then adding said request to said third AGP read and write request queue; and
(a2) reorder requests according to a set of ordering rules.
26. The method ofclaim 21, wherein said step (a) further comprises the steps of:
(a1) issuing a signal from said flow control logic to start a transaction;
(a2) arbitrating and starting a read reply transaction;
(a3) getting data from said third AGP read data return queue; and
(a4) inserting wait states upon instructions from said flow control logic.
27. The method ofclaim 20, wherein said step (a) further comprises the steps of:
(a1) if a request is in said first AGP read and write request queue and if further requests can be queued to said first AGP bus target, then arbitrating and queuing said requests; and
(a2) changing the status of said request in said first AGP read and write request queue.
28. The method ofclaim 21, wherein said step (a) further comprises the steps of:
(a1) if a request is in said first AGP read and write request queue and if further requests can be queued to said first AGP bus target, then arbitrating and queuing said requests; and
(a2) changing the status of said request in said first AGP read and write request queue.
29. The method ofclaim 22, wherein said step (a) further comprises the steps of:
(a1) if the request is in said first AGP read and write request queue and if further requests can be queued to said first AGP bus target, then arbitrating and queuing said requests; and
(a2) changing the status of said request in said first AGP read and write request queue.
30. The method ofclaim 20, wherein said step (a) further comprising the steps of:
(a1) checking to determine if a reply is in said first AGP bus;
(a2) if the result of said step (a1) is positive, then checking to see if said reply is a write;
(a3) if the result of said step (a2) is positive, then supplying data from said first AGP write data queue, and retiring from said first AGP read and write request queue and from said first AGP read data return queue and repeating said step (a1);
(a4) if the result of said step (a2) is negative, then checking to see if said reply is a read;
(a5) if the result of said step (a4) is negative, then checking to see if said reply is a fence;
(a6) if the result of said step (a5) is positive, then completing the access and triggering said flow control logic and repeating said step (a1);
(a7) if the result of said step (a4) is positive, then storing data in said first AGP read data return queue, moving corresponding read request into said first AGP read data return queue, triggering said flow control logic to start moving said data towards either to said second AGP bus or to said third AGP bus;
(a8) inserting at least one wait state at a subsequent block if said first AGP read data return queue is full until complete access has been completed on said first AGP bus;
(a9) checking to determine if an RBF# has been asserted;
(a10) if the result of said step (a9) is negative, then performing said step (a5); and
(a11) if the result of said step (a9) is positive, then utilizing a spillover buffer space and inserting wait state on a subsequent boundary, and performing said step (a1).
31. The method ofclaim 21, wherein said step (a) further comprising the steps of:
(a1) checking to determine if a reply is in said first AGP bus;
(a2) if the result of said step (a1) is positive, then checking to see if said reply is a write;
(a3) if the result of said step (a2) is positive, then supplying data from said first AGP write data queue, and retiring from said first AGP read and write request queue and from said first AGP read data return queue and repeating said step (a1);
(a4) if the result of said step (a2) is negative, then checking to see if said reply is a read;
(a5) if the result of said step (a4) is negative, then checking to see if said reply is a fence;
(a6) if the result of said step (a5) is positive, then completing the access and triggering said flow control logic and repeating said step (a1);
(a7) if the result of said step (a4) is positive, then storing data in said first AGP read data return queue, moving corresponding read request into said first AGP read data return queue, triggering said flow control logic to start moving said data towards either to said second AGP bus or to said third AGP bus;
(a8) inserting at least one wait state at a subsequent block if said first AGP read data return queue is full until complete access has been completed on said first AGP bus;
(a9) checking to determine if an RBF# has been asserted;
(a10) if the result of said step (a9) is negative, then performing said step (a5); and
(a11) if the result of said step (a9) is positive, then utilizing a spillover buffer space and inserting wait state on a subsequent boundary, and performing said step (a1).
32. The method ofclaim 22, wherein said step (a) further comprising the steps of:
(a1) checking to determine if a reply is in said first AGP bus;
(a2) if the result of said step (a1) is positive, then checking to see if said reply is a write;
(a3) if the result of said step (a2) is positive, then supplying data from said first AGP write data queue, and retiring from said first AGP read and write request queue and from said first AGP read data return queue and repeating said step (a1);
(a4) if the result of said step (a2) is negative, then checking to see if said reply is a read;
(a5) if the result of said step (a4) is negative, then checking to see if said reply is a fence;
(a6) if the result of said step (a5) is positive, then completing the access and triggering said flow control logic and repeating said step (a1);
(a7) if the result of said step (a4) is positive, then storing data in said first AGP read data return queue, moving corresponding read request into said first AGP read data return queue, triggering said flow control logic to start moving said data towards either to said second AGP bus or to said third AGP bus;
(a8) inserting at least one wait state at a subsequent block if said first AGP read data return queue is full until complete access has been completed on said first AGP bus;
(a9) checking to determine if an RBF# has been asserted;
(a10) if the result of said step (a9) is negative, then performing said step (a5); and
(a11) if the result of said step (a9) is positive, then utilizing a spillover buffer space and inserting wait state on a subsequent boundary, and performing said step (a1).
33. The method ofclaim 20, wherein said step (a) further comprises the steps of
(a1) checking to determine if a request is in said second AGP read and write request queue;
(a2) if the result of said step (a1) is negative, then handling said request as being in said third AGP read and write request queue;
(a3) if the result of said step (a1) is positive, then checking to determine if said request is a write;
(a4) if the result of said step (a3) is positive, then checking to determine if said write request is complete in said second AGP bus;
(a5) if said result of said step (a4) is positive, then handling said request as being in said third AGP read and write request queue;
(a6) if the result of said step (a4) is negative, then checking to determine if there is space in said second AGP write data queue for an entire access;
(a7) if the result of said step (a6) is negative, then handling said request as being in said third AGP read and write request queue;
(a8) if said result of said step (a6) is positive, then running a write cycle on said second AGP bus and storing write data in said second AGP write data queue, and marking said request as completed on said second AGP bus;
(a9) after said step (a8), or if said result of said step (a2) is negative, then checking to determine if space is available in said first AGP read and write request queue;
(a10) if said result of said step (a9) is negative, then executing said step (a1);
(a11) if said result of said step (a9) is positive, then checking to determine if said request is a write;
(a12) if the result of said step (a11) is negative, then transferring said request to said first AGP read and write request queue and re-ordering said first AGP read and write request queue according to a set of ordering rules and then handling said request as being in said third AGP read and write request queue;
(a13) if said result of said step (a11) is positive, then checking to determine if there is space available in said first AGP write data queue;
(a14) if the result of said step (a13) is negative, then executing said step (a1); and
(a15) if said result of said step (a13) is positive, then transferring data and transferring said request to said first AGP write data queue, reording said first AGP write data queue according to a set of ordering rules, and then handling said request as being in said third AGP read and write request queue.
34. The method ofclaim 21, wherein said step (a) further comprises the steps of
(a1) checking to determine if a request is in said second AGP read and write request queue;
(a2) if the result of said step (a1) is negative, then handling said request as being in said third AGP read and write request queue;
(a3) if the result of said step (a1) is positive, then checking to determine if said request is a write;
(a4) if the result of said step (a3) is positive, then checking to determine if said write request is complete in said second AGP bus;
(a5) if said result of said step (a4) is positive, then handling said request as being in said third AGP read and write request queue;
(a6) if the result of said step (a4) is negative, then checking to determine if there is space in said second AGP write data queue for an entire access;
(a7) if the result of said step (a6) is negative, then handling said request as being in said third AGP read and write request queue;
(a8) if said result of said step (a6) is positive, then running a write cycle on said second AGP bus and storing write data in said second AGP write data queue, and marking said request as completed on said second AGP bus;
(a9) after said step (a8), or if said result of said step (a2) is negative, then checking to determine if space is available in said first AGP read and write request queue;
(a10) if said result of said step (a9) is negative, then executing said step (a1);
(a11) if said result of said step (a9) is positive, then checking to determine if said request is a write;
(a12) if the result of said step (a11) is negative, then transferring said request to said first AGP read and write request queue and re-ordering said first AGP read and write request queue according to a set of ordering rules and then handling said request as being in said third AGP read and write request queue;
(a13) if said result of said step (a11) is positive, then checking to determine if there is space available in said first AGP write data queue;
(a14) if the result of said step (a13) is negative, then executing said step (a1); and
(a15) if said result of said step (a13) is positive, then transferring data and transferring said request to said first AGP write data queue, reording said first AGP write data queue according to a set of ordering rules, and then handling said request as being in said third AGP read and write request queue.
35. The method ofclaim 20, wherein said step (a) further comprises the steps of:
(a1) checking to determine if a request is in said third AGP read and write request queue;
(a2) if the result of said step (a1) is negative, then handling said request as being in said second AGP read and write request queue;
(a3) if the result of said step (a1) is positive, then checking to determine if said request is a write;
(a4) if the result of said step (a3) is positive, then checking to determine if said write request is complete in said second AGP bus;
(a5) if the result of said step (a4) is negative, then checking to determine if there is space in said third AGP write data queue for an entire access;
(a6) if the result of said step (a5) is negative, then executing said step (a1);
(a7) if said result of said step (a5) is positive, then running a write cycle on said third AGP bus and storing write data in said third AGP write data queue, and marking said request as completed on said third AGP bus;
(a8) after said step (a7), or if said result of said step (a3) is negative, or if said result of said step (a4) is positive, then checking to determine if space is available in said first AGP read and write request queue;
(a9) if said result of said step (a8) is negative, then executing said step (a1);
(a10) if said result of said step (a8) is positive, then checking to determine if said request is a write;
(a11) if the result of said step (a10) is negative, then transferring said request to said first AGP read and write request queue and re-ordering said first AGP read and write request queue according to a set of ordering rules and then handling said request as being in said second AGP read and write request queue;
(a12) if said result of said step (a10) is positive, then checking to determine if there is space available in said first AGP write data queue;
(a13) if the result of said step (a12) is negative, then executing said step (a1); and
(a14) if said result of said step (a12) is positive, then transferring data and transferring said request to said first AGP write data queue, reording said first AGP write data queue according to a set of ordering rules, and then handling said request as being in said second AGP read and write request queue.
36. The method ofclaim 21, wherein said step (a) further comprises the steps of:
(a1) checking to determine if a request is in said third AGP read and write request queue;
(a2) if the result of said step (a1) is negative, then handling said request as being in said second AGP read and write request queue;
(a3) if the result of said step (a1) is positive, then checking to determine if said request is a write;
(a4) if the result of said step (a3) is positive, then checking to determine if said write request is complete in said second AGP bus;
(a5) if the result of said step (a4) is negative, then checking to determine if there is space in said third AGP write data queue for an entire access;
(a6) if the result of said step (a5) is negative, then executing said step (a1);
(a7) if said result of said step (a5) is positive, then running a write cycle on said third AGP bus and storing write data in said third AGP write data queue, and marking said request as completed on said third AGP bus;
(a8) after said step (a7), or if said result of said step (a3) is negative, or if said result of said step (a4) is positive, then checking to determine if space is available in said first AGP read and write request queue;
(a9) if said result of said step (a8) is negative, then executing said step (a1);
(a10) if said result of said step (a8) is positive, then checking to determine if said request is a write;
(a11) if the result of said step (a10) is negative, then transferring said request to said first AGP read and write request queue and re-ordering said first AGP read and write request queue according to a set of ordering rules and then handling said request as being in said second AGP read and write request queue;
(a12) if said result of said step (a10) is positive, then checking to determine if there is space available in said first AGP write data queue;
(a13) if the result of said step (a12) is negative, then executing said step (a1); and
(a14) if said result of said step (a12) is positive, then transferring data and transferring said request to said first AGP write data queue, reording said first AGP write data queue according to a set of ordering rules, and then handling said request as being in said second AGP read and write request queue.
37. The method according toclaim 20, wherein said step (a) further comprises the steps of:
(a1) checking to determine if a next read request on said first AGP read and write request queue is small enough to fit within an internal buffer space within said AGP to AGP bridge;
(a2) if the result of said step (a1) is positive, then executing said step (a1);
(a3) if said result of said step (a1) is negative, then checking to determine if said next read request is from said second AGP bus;
(a4) if said result of said step (a3) is positive, then checking to determine if an RBF# has been asserted on said second AGP bus;
(a5) if the result of said step (a4) is negative, then executing said step (a1);
(a6) if the result of said step (a4) is positive, then asserting an RBF# on said first AGP bus;
(a7) checking to determine if said RBF# on said second AGP bus is deasserted;
(a8) if the result of step (a7) is negative, then executing step (a7);
(a9) if said result of step (a7) is positive, then deasserting said RBF# of said first AGP bus and then executing said step (a1);
(a10) if said result of said step (a3) is negative, then checking to determine if said next read request is from said third AGP bus;
(a11) if the result of said step (a10) is positive, then checking to determine if an RBF# on said third AGP bus has been asserted;
(a12) if the result of said step (a11) is negative then executing said step (a1);
(a13) if said result of said step (a11) is positive, then asserting said RBF# of said first AGP bus;
(a14) checking to determine if said RBF# of said third AGP bus is deasserted;
(a15) if the result of said step (a14) is negative, then executing said step (a14); and
(a16) if said result of said step (a14) is positive, then deasserting said RBF# of said first AGP bus and executing said step (a1).
38. The method according toclaim 21, wherein said step (a) further comprises the steps of:
(a1) checking to determine if a next read request on said first AGP read and write request queue is small enough to fit within an internal buffer space within said AGP to AGP bridge;
(a2) if the result of said step (a1) is positive, then executing said step (a1);
(a3) if said result of said step (a1) is negative, then checking to determine if said next read request is from said second AGP bus;
(a4) if said result of said step (a3) is positive, then checking to determine if an RBF# has been asserted on said second AGP bus;
(a5) if the result of said step (a4) is negative, then executing said step (a1);
(a6) if the result of said step (a4) is positive, then asserting an RBF# on said first AGP bus;
(a7) checking to determine if said RBF# on said second AGP bus is deasserted;
(a8) if the result of step (a7) is negative, then executing step (a7);
(a9) if said result of step (a7) is positive, then deasserting said RBF# of said first AGP bus and then executing said step (a1);
(a10) if said result of said step (a3) is negative, then checking to determine if said next read request is from said third AGP bus;
(a11) if the result of said step (a10) is positive, then checking to determine if an RBF# on said third AGP bus has been asserted;
(a12) if the result of said step (a11) is negative then executing said step (a1);
(a13) if said result of said step (a11) is positive, then asserting said RBF# of said first AGP bus;
(a14) checking to determine if said RBF# of said third AGP bus is deasserted;
(a15) if the result of said step (a14) is negative, then executing said step (a14); and
(a16) if said result of said step (a14) is positive, then deasserting said RBF# of said first AGP bus and executing said step (a1).
39. The method ofclaim 20, wherein said step (a) further comprises the steps of:
(a1) checking to determine if a reply in said first AGP read data return queue;
(a2) if the result of said step (a1) is positive, then checking to determine if said replay is for said second AGP bus;
(a3) if the result of said step (a2) is positive, then checking to determine if sufficient space exists within said second AGP read data queue;
(a4) if the result of said step (a3) is positive, then transferring data to said second read data return queue, triggering said second AGP bus interface to start transacting on said second AGP bus, completing said transfer of said request, otherwise waiting for said second AGP read data return queue to empty in order to complete said transfer, and then executing said step (a1);
(a5) if said result of said step (a2) is negative, then checking to determine if said reply is for said third AGP bus;
(a6) if the result of said step (a5) is positive, then checking to determine if space is available to fulfill said request in said third read data return queue; and
(a7) if the result of said step (a6) is positive, then transferring data to said third read data return queue, triggering said third AGP bus interface to start transacting on said third AGP bus, completing said transfer of said request, and then executing said step (a1).
40. The method ofclaim 21, wherein said step (a) further comprises the steps of:
(a1) checking to determine if a reply in said first AGP read data return queue;
(a2) if the result of said step (a1) is positive, then checking to determine if said replay is for said second AGP bus;
(a3) if the result of said step (a2) is positive, then checking to determine if sufficient space exists within said second AGP read data queue;
(a4) if the result of said step (a3) is positive, then transferring data to said second read data return queue, triggering said second AGP bus interface to start transacting on said second AGP bus, completing said transfer of said request, otherwise waiting for said second AGP read data return queue to empty in order to complete said transfer, and then executing said step (a1);
(a5) if said result of said step (a2) is negative, then checking to determine if said reply is for said third AGP bus;
(a6) if the result of said step (a5) is positive, then checking to determine if space is available to fulfill said request in said third read data return queue; and
(a7) if the result of said step (a6) is positive, then transferring data to said third read data return queue, triggering said third AGP bus interface to start transacting on said third AGP bus, completing said transfer of said request, and then executing said step (a1).
41. The method ofclaim 22, wherein said step (a) further comprises the steps of:
(a1) checking to determine if a request in said second AGP read and write request queue;
(a2) if the result of said step (a1) is negative, then executing said step (a1);
(a3) if said result of said step (a1) is positive, then checking to determine if said request is a peer-to-peer request;
(a4) if the result of said step (a3) is negative, then transferring said request to said first AGP read and write request queue; and
(a5) if said result of said step (a3) is positive, then transferring said request to said third APG read and write request queue.
42. The method ofclaim 22, wherein said step (a) further comprises the steps of:
(a1) checking to determine if a request in said third AGP read and write request queue;
(a2) if the result of said step (a1) is negative, then executing said step (a1);
(a3) if said result of said step (a1) is positive, then checking to determine if said request is a peer-to-peer request;
(a4) if the result of said step (a3) is negative, then transferring said request to said first AGP read and write request queue; and
(a5) if said result of said step (a3) is positive, then transferring said request to said second APG read and write request queue.
43. The method ofclaim 22, wherein said step (a) further comprises the steps of:
(a1) checking to determine if a reply is in said second AGP read data return queue;
(a2) if the result of said step (a1) is negative, then executing said step (a1); and
(a3) if said result of said step (a1) is positive, then transferring data to said third AGP read data return queue.
44. The method ofclaim 22, wherein said step (a) further comprises the steps of:
(a1) checking to determine if a reply is in said third AGP read data return queue;
(a2) if the result of said step (a1) is negative, then executing said step (a1); and
(a3) if said result of said step (a1) is positive, then transferring data to said second AGP read data return queue.
45. The method ofclaim 22, wherein said step (a) further comprises the steps of:
(a1) checking to determine if a request is in said second AGP write data queue;
(a2) if the result of said step (a1) is negative, then executing said step (a1);
(a3) if said result of said step (a1) is positive, then transferring data to said third AGP write data queue.
46. The method ofclaim 22, wherein said step (a) further comprises the steps of:
(a1) checking to determine if a request is in said third AGP write data queue;
(a2) if the result of said step (a1) is negative, then executing said step (a1);
(a3) if said result of said step (a1) is positive, then transferring data to said second AGP write data queue.
US10/679,7341998-09-242003-10-06Apparatus, method and system for accelerated graphics port bus bridgesAbandonedUS20040068602A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US20150149673A1 (en)*2013-11-252015-05-28Apple Inc.Fence management over multiple busses

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US6456502B1 (en)1998-09-212002-09-24Compaq Computer CorporationIntegrated circuit device/circuit board connection apparatus
US6167476A (en)*1998-09-242000-12-26Compaq Computer CorporationApparatus, method and system for accelerated graphics port bus bridges
US6308237B1 (en)*1998-10-192001-10-23Advanced Micro Devices, Inc.Method and system for improved data transmission in accelerated graphics port systems
US6304935B1 (en)*1998-10-192001-10-16Advanced Micro Devices, Inc.Method and system for data transmission in accelerated graphics port systems
US6301627B1 (en)*1998-12-182001-10-09International Business Machines CorporationMethod/system for identifying delayed predetermined information transfer request as bypassable by subsequently-generated information transfer request using bypass enable bit in bridge translation control entry
US6545683B1 (en)*1999-04-192003-04-08Microsoft CorporationApparatus and method for increasing the bandwidth to a graphics subsystem
US6567883B1 (en)*1999-08-272003-05-20Intel CorporationMethod and apparatus for command translation and enforcement of ordering of commands
JP2001134752A (en)*1999-11-052001-05-18Mitsubishi Electric Corp Graphic processor and data processing method in graphic processor
US6624817B1 (en)*1999-12-312003-09-23Intel CorporationSymmetrical accelerated graphics port (AGP)
US6760031B1 (en)1999-12-312004-07-06Intel CorporationUpgrading an integrated graphics subsystem
JP2001256176A (en)*2000-03-132001-09-21Mitsubishi Electric Corp Bridge device
US6670958B1 (en)*2000-05-262003-12-30Ati International, SrlMethod and apparatus for routing data to multiple graphics devices
US6633296B1 (en)*2000-05-262003-10-14Ati International SrlApparatus for providing data to a plurality of graphics processors and method thereof
US6789154B1 (en)*2000-05-262004-09-07Ati International, SrlApparatus and method for transmitting data
US6954209B2 (en)*2000-12-062005-10-11Hewlett-Packard Development Company, L.P.Computer CPU and memory to accelerated graphics port bridge having a plurality of physical buses with a single logical bus number
US6826645B2 (en)*2000-12-132004-11-30Intel CorporationApparatus and a method to provide higher bandwidth or processing power on a bus
US6907490B2 (en)*2000-12-132005-06-14Intel CorporationMethod and an apparatus for a re-configurable processor
US6950897B2 (en)*2001-02-232005-09-27Hewlett-Packard Development Company, L.P.Method and apparatus for a dual mode PCI/PCI-X device
DE10139387A1 (en)2001-08-102003-02-20Siemens Ag Data processing system with at least one computer module and associated further computer or other self-sufficient modules
US7079149B2 (en)*2001-10-092006-07-18Texas Instruments IncorporatedSystem, method, and device for accelerated graphics port linking
US6973525B2 (en)2002-03-192005-12-06Dell Products L.P.System and method for managing bus numbering
US20030188080A1 (en)*2002-03-282003-10-02Olarig Sompong PaulApparatus, method and system for remote registered peripheral component interconnect bus
TWI237765B (en)*2003-11-032005-08-11Via Tech IncAdapting device for use in a computer system
US7345689B2 (en)*2003-12-192008-03-18Intel CorporationInterfacing a digital display card through PCI express connector
JP4912299B2 (en)*2004-06-252012-04-11エヌヴィディア コーポレイション Individual graphics system and method
US8446417B2 (en)*2004-06-252013-05-21Nvidia CorporationDiscrete graphics system unit for housing a GPU
US8411093B2 (en)*2004-06-252013-04-02Nvidia CorporationMethod and system for stand alone graphics independent of computer system form factor
US8941668B2 (en)*2004-06-252015-01-27Nvidia CorporationMethod and system for a scalable discrete graphics system
KR100706246B1 (en)*2005-05-242007-04-11삼성전자주식회사 Memory card can improve read performance
TWI273423B (en)*2005-07-152007-02-11Via Tech IncComputer system with multi-port bridge and an operating method of the same
CN100403287C (en)*2005-11-072008-07-16威盛电子股份有限公司Bridging device with multiple connection ports, system and method using the bridging device

Citations (16)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US5479627A (en)*1993-09-081995-12-26Sun Microsystems, Inc.Virtual address to physical address translation cache that supports multiple page sizes
US5524235A (en)*1994-10-141996-06-04Compaq Computer CorporationSystem for arbitrating access to memory with dynamic priority assignment
US5664161A (en)*1989-10-161997-09-02Hitachi, Ltd.Address-translatable graphic processor, data processor and drawing method with employment of the same
US5740381A (en)*1995-12-221998-04-14United Microelectronics CorporationExpandable arbitration architecture for sharing system memory in a computer system
US5740409A (en)*1996-07-011998-04-14Sun Microsystems, Inc.Command processor for a three-dimensional graphics accelerator which includes geometry decompression capabilities
US5793995A (en)*1996-07-191998-08-11Compaq Computer CorporationBus system for shadowing registers
US5793996A (en)*1995-05-031998-08-11Apple Computer, Inc.Bridge for interconnecting a computer system bus, an expansion bus and a video frame buffer
US5802568A (en)*1996-06-061998-09-01Sun Microsystems, Inc.Simplified least-recently-used entry replacement in associative cache memories and translation lookaside buffers
US5812789A (en)*1996-08-261998-09-22Stmicroelectronics, Inc.Video and/or audio decompression and/or compression device that shares a memory interface
US5835962A (en)*1995-03-031998-11-10Fujitsu LimitedParallel access micro-TLB to speed up address translation
US5857086A (en)*1997-05-131999-01-05Compaq Computer Corp.Apparatus method and system for peripheral component interconnect bus using accelerated graphics port logic circuits
US5859989A (en)*1997-05-131999-01-12Compaq Computer Corp.Apparatus method and system for 64 bit peripheral component interconnect bus using accelerated graphics port logic circuits
US5889970A (en)*1997-05-091999-03-30Compaq Computer Corp.Dual purpose apparatus, method and system for accelerated graphics port and peripheral component interconnect
US5892964A (en)*1997-06-301999-04-06Compaq Computer Corp.Computer bridge interfaces for accelerated graphics port and peripheral component interconnect devices
US5986663A (en)*1997-10-101999-11-16Cirrus Logic, Inc.Auto level of detail-based MIP mapping in a graphics processor
US6633944B1 (en)*2001-10-312003-10-14Lsi Logic CorporationAHB segmentation bridge between busses having different native data widths

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US5734850A (en)*1995-07-051998-03-31National Semiconductor CorporationTransparent bridge between of a computer system and a method of interfacing the buses to operate as a single logical bus
US5632021A (en)*1995-10-251997-05-20Cisco Systems Inc.Computer system with cascaded peripheral component interconnect (PCI) buses
US6134622A (en)*1995-12-272000-10-17Intel CorporationDual mode bus bridge for computer system
US5828865A (en)*1995-12-271998-10-27Intel CorporationDual mode bus bridge for interfacing a host bus and a personal computer interface bus
US5911051A (en)*1996-03-291999-06-08Intel CorporationHigh-throughput interconnect allowing bus transactions based on partial access requests
DE69721474T2 (en)*1996-10-312004-04-08Texas Instruments Inc., Dallas A configurable expansion bus control unit
US5937173A (en)*1997-06-121999-08-10Compaq Computer Corp.Dual purpose computer bridge interface for accelerated graphics port or registered peripheral component interconnect devices
US6057863A (en)*1997-10-312000-05-02Compaq Computer CorporationDual purpose apparatus, method and system for accelerated graphics port and fibre channel arbitrated loop interfaces
US6006291A (en)*1997-12-311999-12-21Intel CorporationHigh-throughput interface between a system memory controller and a peripheral device
US6230223B1 (en)*1998-06-012001-05-08Compaq Computer CorporationDual purpose apparatus method and system for accelerated graphics or second memory interface
US6223239B1 (en)*1998-08-122001-04-24Compaq Computer CorporationDual purpose apparatus, method and system for accelerated graphics port or system area network interface
US6167476A (en)*1998-09-242000-12-26Compaq Computer CorporationApparatus, method and system for accelerated graphics port bus bridges

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US5664161A (en)*1989-10-161997-09-02Hitachi, Ltd.Address-translatable graphic processor, data processor and drawing method with employment of the same
US5479627A (en)*1993-09-081995-12-26Sun Microsystems, Inc.Virtual address to physical address translation cache that supports multiple page sizes
US5524235A (en)*1994-10-141996-06-04Compaq Computer CorporationSystem for arbitrating access to memory with dynamic priority assignment
US5835962A (en)*1995-03-031998-11-10Fujitsu LimitedParallel access micro-TLB to speed up address translation
US5793996A (en)*1995-05-031998-08-11Apple Computer, Inc.Bridge for interconnecting a computer system bus, an expansion bus and a video frame buffer
US5740381A (en)*1995-12-221998-04-14United Microelectronics CorporationExpandable arbitration architecture for sharing system memory in a computer system
US5802568A (en)*1996-06-061998-09-01Sun Microsystems, Inc.Simplified least-recently-used entry replacement in associative cache memories and translation lookaside buffers
US5740409A (en)*1996-07-011998-04-14Sun Microsystems, Inc.Command processor for a three-dimensional graphics accelerator which includes geometry decompression capabilities
US5793995A (en)*1996-07-191998-08-11Compaq Computer CorporationBus system for shadowing registers
US5812789A (en)*1996-08-261998-09-22Stmicroelectronics, Inc.Video and/or audio decompression and/or compression device that shares a memory interface
US5889970A (en)*1997-05-091999-03-30Compaq Computer Corp.Dual purpose apparatus, method and system for accelerated graphics port and peripheral component interconnect
US5857086A (en)*1997-05-131999-01-05Compaq Computer Corp.Apparatus method and system for peripheral component interconnect bus using accelerated graphics port logic circuits
US5859989A (en)*1997-05-131999-01-12Compaq Computer Corp.Apparatus method and system for 64 bit peripheral component interconnect bus using accelerated graphics port logic circuits
US5892964A (en)*1997-06-301999-04-06Compaq Computer Corp.Computer bridge interfaces for accelerated graphics port and peripheral component interconnect devices
US5986663A (en)*1997-10-101999-11-16Cirrus Logic, Inc.Auto level of detail-based MIP mapping in a graphics processor
US6633944B1 (en)*2001-10-312003-10-14Lsi Logic CorporationAHB segmentation bridge between busses having different native data widths

Cited By (2)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US20150149673A1 (en)*2013-11-252015-05-28Apple Inc.Fence management over multiple busses
US9495318B2 (en)*2013-11-252016-11-15Apple Inc.Synchronizing transactions for a single master over multiple busses

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