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US20040064794A1 - Symbolic model checking with dynamic model pruning - Google Patents

Symbolic model checking with dynamic model pruning
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Publication number
US20040064794A1
US20040064794A1US10/666,619US66661903AUS2004064794A1US 20040064794 A1US20040064794 A1US 20040064794A1US 66661903 AUS66661903 AUS 66661903AUS 2004064794 A1US2004064794 A1US 2004064794A1
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property
assumption
state
predicate
transition
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US10/666,619
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Jin Yang
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Abstract

Formal verification methods provide for improved efficiency of popular binary decision diagram (BDD) based algorithms. A lazy pre-image computation method builds new transition relation partitions on-demand for relevant internal variables of a state predicate, and conjoins only next state relations for relevant internal variables to a pre-image including the state predicate. A lazy fixpoint computation method makes iterative use of lazy pre-image computation to compute conditions that must be satisfied to produce a given set of states. A forward assumption propagation method generates assumptions to characterize a set of interesting states for a property being evaluated at one or more evaluation stages. A dynamic transition relation reduction improves the efficiency for symbolic model checking by reducing transition relations under assumptions dynamically generated from properties being evaluated. These methods provide symbolic model checking of circuits and other finite state systems previously too large to be completed successfully using BDD based algorithms.

Description

Claims (19)

What is claimed is:
1. A computer software product having one or more recordable medium having executable instructions stored thereon which, when executed by a processing device, causes the processing device to:
generate, from a first property, a first assumption including a first state predicate;
generate, for a model, a first transition relation that includes the first state predicate; and
reduce the first transition relation according to the first assumption.
2. The computer software product recited inclaim 1 wherein reducing the first transition relation reduces the size of the model.
3. The computer software product recited inclaim 1 wherein reducing the first transition relation reduces the computational complexity of evaluating the first property.
4. The computer software product recited inclaim 1 wherein reducing the first transition relation reduces the number of variables in the model.
5. The computer software product recited inclaim 1 wherein reducing the first transition relation reduces the number of variables in the first transition relation.
6. The computer software product recited inclaim 1 wherein the first assumption is generated from an implication structure of the first property.
7. The computer software product recited inclaim 6 which, when executed by a processing device, further causes the processing device to:
propagate the first assumption to generate a second assumption according to a second property.
8. The computer software product recited inclaim 7 wherein the second property is a sub-property of the first property.
9. The computer software product recited inclaim 7 wherein the second property is to be evaluated under the first assumption.
10. The computer software product recited inclaim 7 wherein the first assumption is propagated only one transition stage to generate the second assumption.
11. A verification system comprising:
means for producing, from a first property, a first assumption including a first state predicate; and
means for producing a reduced next state function from a first next state function involving the first state predicate by applying the first assumption.
12. The verification system ofclaim 11 wherein the first assumption is produced from the structure of the first property.
13. The verification system ofclaim 12 further comprising:
means for propagating the first assumption according to a second property to generate a second assumption; and
means for producing, for a model, a transition relation that includes the reduced next state function.
14. The verification system ofclaim 13 wherein the second property is a sub-property of the first property.
15. The verification system ofclaim 14 wherein the first assumption is propagated only one transition stage to generate the second assumption.
16. A verification system comprising:
a recordable medium to store executable instructions;
a processing device to execute executable instruction; and
a plurality of executable instructions to cause the processing device to:
produce, from a first property, a first assumption including a first state predicate;
produce, for a model, a first transition relation that includes the first state predicate; and
reduce the first transition relation according to the first assumption.
17. The verification system ofclaim 16 wherein the first assumption is produced from the logical structure of the first property.
18. The verification system recited inclaim 17, the plurality of executable instructions further comprising instructions to cause the processing device to:
propagate the first assumption to generate a second assumption according to a second state predicate.
19. The computer software product recited inclaim 18 wherein the second property is a sub-property of the first property.
US10/666,6192000-09-302003-09-17Symbolic model checking with dynamic model pruningAbandonedUS20040064794A1 (en)

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US7076407B2 (en)*2001-08-242006-07-11Wayne Biao LiuSpace reduction in compositional state systems
US7310790B2 (en)*2002-12-032007-12-18Intel CorporationAutomatic symbolic indexing methods for formal verification on a symbolic lattice domain
US20040107174A1 (en)*2002-12-032004-06-03Jones Robert B.Parametric representation methods for formal verification on a symbolic lattice domain
US6957404B2 (en)*2002-12-202005-10-18International Business Machines CorporationModel checking with layered localization reduction
US7742907B2 (en)*2003-04-152010-06-22Nec Laboratories America, Inc.Iterative abstraction using SAT-based BMC with proof analysis
US7246331B2 (en)*2004-10-152007-07-17International Business Machines CorporationMethod for optimizing integrated circuit device design and service
US7290230B2 (en)*2005-03-172007-10-30Fujitsu LimitedSystem and method for verifying a digital design using dynamic abstraction
US7930659B2 (en)*2005-06-032011-04-19Nec Laboratories America, Inc.Software verification
US7788646B2 (en)*2005-10-142010-08-31International Business Machines CorporationMethod for optimizing integrated circuit device design and service
US8244516B2 (en)2008-06-302012-08-14International Business Machines CorporationFormal verification of models using concurrent model-reduction and model-checking
US8201115B2 (en)*2008-08-142012-06-12International Business Machines CorporationScalable reduction in registers with SAT-based resubstitution

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US7231621B1 (en)2004-04-302007-06-12Xilinx, Inc.Speed verification of an embedded processor in a programmable logic device
US7269805B1 (en)2004-04-302007-09-11Xilinx, Inc.Testing of an integrated circuit having an embedded processor
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US20070299793A1 (en)*2006-06-212007-12-27Microsoft CorporationComputer implemented cover process approximating quantifier elimination
US7606774B2 (en)*2006-06-212009-10-20Microsoft CorporationComputer implemented cover process approximating quantifier elimination
US20110071809A1 (en)*2009-09-232011-03-24International Business Machines CorporationModel generation based on a constraint and an initial model
US8352234B2 (en)*2009-09-232013-01-08International Business Machines CorporationModel generation based on a constraint and an initial model

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