US20040012097A1 - Structure and method for fine pitch flip chip substrate - Google Patents
Structure and method for fine pitch flip chip substrateDownload PDFInfo
- Publication number
- US20040012097A1 US20040012097A1US10/197,066US19706602AUS2004012097A1US 20040012097 A1US20040012097 A1US 20040012097A1US 19706602 AUS19706602 AUS 19706602AUS 2004012097 A1US2004012097 A1US 2004012097A1
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- layer
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Definitions
- the inventionrelates to a structure and a method of manufacturing of a substrate in the semiconductor packaging process, and more particularly to fine pitch flip chip substrates that demand high packaging precision.
- BGABall Grid Array
- PGAis a through hole packaging technology that is restricted by the pitch between the separate areas on the printed board.
- BGAis a surface packaging technology without such restriction.
- FCBGAFlip Chip Ball Grid Array
- a conventional Flip Chip Substrateincludes 4 to 8 layers of printed circuit boards.
- the substratecould be made of ceramic or organic material.
- the communication between the layers of boardsis through the tiny holes drilled mechanically or with laser. Wires are extended through the tiny holes and made into bump pads for connecting the IC bumps.
- the conventional approachusually requires a larger space; hence, restricts the density and the flexibility of routing. It is desirable to device a technology to fill the tiny laser-drilled holes with plating copper in order to form the communication between the layers of boards. This will improve the density and the flexibility of routing.
- the substratesare treated with a high temperature step which could sometimes deform the substrates.
- the deformed substrates, warped or twisted,are difficult for the IC chips to be adhered on.
- the present inventionprovides a Fine Pitch flip chip substrate with a mesh pattern to increase the stiffness of the substrates.
- the mesh patternimproves the resistance to heat deformation.
- the flip chip substratesis coated with a photo solder resist made of Epoxy to prevent short-circuit of the tin bridge due to the flowing of melted soldering tin during the solder reflow.
- a bump padis formed at the area for connecting each solder bump of I/O on the IC chips in the packaging process. This step is difficult for the flip chip substrate that requires its alignment precision to be within 25 ⁇ m. Meanwhile, the thickness of the solder resist are usually controlled between 15 to 45 ⁇ m during manufacturing. Therefore, the bump pads buried in the solder resist will degrade the connection between the IC bumps and the pads on the substrate.
- the present inventionprovides a Fine Pitch flip chip substrate structure, as shown in FIG. 1B.
- a black oxide damis formed on the metal wires between the bump pads to replace the conventional solder resist.
- the thickness of the damcan be easily controlled between 1-3 ⁇ m such that the bump pads will not be buried in the solder resist.
- the present inventionis no longer constrained by the alignment precision imposed by the solder resist in the IC connection area, it solves the misalignment problem faced by the conventional technology.
- a similar technology to the present inventionis to electro-plate a NiO layer to form the black oxide resist layer.
- the thickness of the NiOhas to be controlled below 5 ⁇ m.
- the inherent shortcoming of this methodis that the metal wires are not well adherent to the underfill, which is a glue used at the bottom of IC during the FCBGA process. Thus, the reliability is reduced.
- the present inventiongrows fur-shaped black oxide dam directly on the wire. This will enhance the adhesion to the underfill, and improve the long term reliability of the circuits.
- the use of NiOprovides no such capability.
- the present inventionrelates to a method comprising the following steps:
- Step 1providing a substrate:
- a first metal plated layeris formed on the first metal layer and the through holes.
- Step 2forming an inner circuit:
- Step 3black oxide inner circuit:
- Step 4forming a mediate layer and a second metal layer
- Step 5forming vias in the dielectric layer by laser beams:
- [0018]Form a laser mask by transferring an image on the dry film. Vias are drilled by laser drilling at the opening of the laser mask to form a plurality of dielectric layer vias. A second metal plated layer is formed in the dielectric layer vias, which are plated and filled by copper to form the surface of the second metal plated layer.
- Step 6forming a circuit layer:
- Step 7forming a plurality of solder resist areas:
- Step 8forming a plurality of black oxide dams:
- Step 9packaging flip chip process:
- the primary object of the present inventionis to provide a method that improves the routing flexibility on the substrates and reduces the misalignment problem in manufacturing.
- FIG. 1Ashows the conventional flip chip substrate
- FIG. 1Bshows the fine pitch flip chip substrate of the present invention
- FIGS. 2A to 2 Ushow the steps of the method for making the fine pitch flip chip substrate of the present invention
- FIG. 3shows the flip chip substrate of the present invention.
- FIGS. 2A to 2 Tshow the steps of the method for making a flip chip substrate and includes the following steps:
- FIG. 2Ashows a substrate 201 which may be a flip chip substrate and is made of Bismaleimide Triazine (BT), other organic material, or even ceramics.
- the thickness of 201is about 0.1 to 0.4 mm.
- a first metal layer 202is made on the substrate 201 .
- the first metal layercan be made of Copper (Cu) with a thickness of 12 ⁇ m.
- FIG. 2Bshows a plurality of through holes 203 are drilled on the substrate 201 by mechanical or laser drilling. Each of the through holes 203 has a diameter of 100 to 250 ⁇ m.
- FIG. 2Cshows that a first metal plated layer 204 is formed on the first metal layer 202 and the through holes 203 .
- the first metal plated layer 204can be made of Copper (Cu) with a thickness of 15 ⁇ m.
- FIGS. 2D to 2 Eshow a step of forming an inner circuit.
- FIG. 2Duses a dry film 205 containing an image to be transferred as the inner circuit, and the dry film is used as a mask.
- a part of the first metal plated layer 204 and the first metal layer 202are etched to form traces 206 .
- FIG. 2Ethe remained portions of the first metal plated layer 204 and the first metal layer 202 are left as the inner circuit.
- FIG. 2Fshows a step of black-oxidizing the inner circuit.
- a black oxide inner circuit 207is formed in the inner circuit by oxidizing the inner circuit.
- FIGS. 2G to 2 Hshow a step of forming a dielectric layer and a second metal layer.
- FIG. 2Gshows the lamination of the dielectric material into the traces and the through holes of the substrate by heat pressing and fusion to form a dielectric layer 208 which is coated on the entire inner circuit.
- the dielectric layer 208is made of Bismaleimide Triazing (BT) or other dielectric material.
- a metal foil 209is formed on the dielectric layer 208 .
- the metal foil 209can be made of Copper (Cu) with a thickness of 12 ⁇ m.
- FIG. 2Gshows the foil 209 is laminated to form the second metal layer 209 a with a thickness of 7 to 9 ⁇ m.
- FIGS. 21 to 2 Mshow the step of forming vias in the dielectric layer by laser beams.
- FIG. 2Ishows that the dry film 210 used as a laser mask 211 as shown in FIG. 2J by image transferring.
- a plurality of dielectric layer vias 212 with a diameter of 100 ⁇ mare drilled by laser drilling at the laser openings of the laser mask as shown in FIG. 2K.
- a second metal plated layer 213is formed in the dielectric layer vias 212 and the second metal plated layer 213 , as shown in FIG. 2L.
- the dielectric layer vias 212are filled with plating filled copper 214 .
- FIG. 2Mshows that the second metal plated layer 213 is laminated and the second metal layer 209 a has a thickness of 7 to 9 ⁇ m.
- FIGS. 2N to 2 Rshow a step of forming a circuit layer.
- FIG. 2Nshows the dry film 214 is used as a mask
- FIG. 2Oshows that a Ni/Au layer 215 is coated on the portion that is not covered by the image on dry film 214 .
- the Ni/Au layer 215is formed by way of electro-plating and has a thickness of 5 ⁇ m.
- the Ni/Au layer 215is used as the connection area of flip chip bumps.
- FIG. 2Pshows a liquid photo resist agent or dry film pressing process is used as a mask 216 .
- FIG. 2Qshows the process of image transferring 217
- FIG. 2Rshows the etching on the second metal layer 218 wherein the remained portion is the circuit layer.
- a mesh patternis designed in the circuit layer to reinforce the stiffness of the substrate and reduce the heat deformation that could cause substrate warpage or twist.
- FIG. 2Sshows a step of forming a plurality of solder resist areas.
- the solder resist areas 219are formed on the second metal layer, excluding the bump pads area for IC connection.
- the solder resist 219can be a photo solder resist coated with Epoxy.
- FIG. 2Tshows a step of forming a plurality of black oxide dams.
- the black oxide dams 220are formed, by way of oxidization, on the second metal layer 209 a wherein no etching is applied.
- the thickness of the black oxide dams 220is below 1-3 ⁇ m.
- FIG. 2Ushows the step of packaging flip chip. This includes the step of underfilling 223 to the bottom of IC 222 .
- the flip chip bumps 221are connected to the Ni/Au layer 215 .
- the through holes of the flip chip substrateare electrically connected to the mediate layer through holes and the BGA tin balls 224 .
- FIG. 3shows the structure of the flip chip substrate and includes a substrate 301 with a first metal layer 302 on the surface of the substrate and the thickness of the first metal layer 302 is 12 ⁇ m.
- a plurality of through holes 303are drilled on the substrate and each has a diameter of 100 to 250 ⁇ m.
- the first metal plated layer 304is formed on the surface of the first metal layer 302 and the through holes 303 of the substrate.
- the thickness of the first metal plated layer 304is about 15 ⁇ m.
- An inner circuitis the remained portion of the first metal plated layer 304 and the first metal layer 302 by an etching process. The etching results into traces 306 .
- a black oxide inner circuit 307is formed on the surface of the inner circuit.
- a dielectric layer 308is formed by laminating dielectric material into the traces 306 and the through holes 303 of the substrate and is coated on the entire inner circuit.
- a metal foil 309 with a thickness of 12 ⁇ mis formed on the dielectric layer 308 .
- the metal foil 309is laminated to form a second metal layer 309 a which has a thickness of 7-9 ⁇ m.
- a plurality of dielectric layer vias 312are made by drilling holes at 100 ⁇ m in diameter with laser.
- a second metal plated layer 313is formed in the dielectric layer vias 312 which are filled with plating filled copper.
- a circuit layeris made by forming a Ni/Au layer 315 on the second metal layer 309 a and is used to connect the Ni/Au layer and the bumps.
- the thickness of the Ni/Auis about 5 ⁇ m.
- the circuit layerwhich has a mesh pattern to reinforce the stiffness of the substrate and reduces the heat deformation which could cause substrate warpage and twist.
- a plurality of solder resist areas 319are formed on the areas of the second metal layer 309 a excluding bump pads area for IC connection.
- a plurality of black oxide dams 320are formed on the second metal layer 209 a and each black oxide dams 320 has a thickness of 1-3 ⁇ m.
- the present inventionhas the following advantages in comparison with the current technologies:
- the black oxide dams on the circuit of non-bump padsare able to reduce the thickness of the solder resists, which is a common problem for using the conventional solder resists.
- the present inventionmay have an alignment tolerance up to 50 ⁇ m.
- the plating filled copperreduces the number of the wires and the bump pads pitch is reduced to be 50 ⁇ m so as to increase the density of the wires. Therefore, there is enough space for the mesh pattern to improve the packaging quality.
- the thickness of the black oxide layer of the present inventionis about 1-3 ⁇ m. In comparison with the conventional requirement of the thickness of the solder resist 25 ⁇ m, the clearer shape and the better resolution enable the alignment precision of the present invention to be easily controlled under 20 ⁇ m.
- the conventional photo solder resistusually forms a deep well in the manufacturing process, debris is left at the bottom of the bump pads and affects the quality of packaging.
- the present inventionsolves the problem.
- the high density flip chip bumpsare replaced with the black oxide dams in the soldering of the packaging process.
- the thickness of the plated Ni/Au layer on the bump padis about 5 ⁇ m and the black oxide dam is lower than the bump pad.
- the conventional solder resist having a thickness of 25 ⁇ m, which is higher than the bump padit is advantageous for the high quality and reliability of the flip chip bumping packaging.
- the conventional packagingemploys a tin-lead solder bump which does not meet the trend of un-leaded environmental green requirement.
- the present inventionmeets the requirement.
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Abstract
Description
- The invention relates to a structure and a method of manufacturing of a substrate in the semiconductor packaging process, and more particularly to fine pitch flip chip substrates that demand high packaging precision.[0001]
- Due to the increase of the number of I/Os in modern electronic products, the packaging technology has evolved from the early Plug-In method to the more advanced Surface Mounting Technology (SMT) in order to meet the new demands. There are two representative SMT, the Dual-In-Line Package (DIP), by Fairchild, and Flat Package (FP), by Texas Instrument Institute. Another packaging method drawing much attention is the Ball Grid Array (BGA), which uses protruding poles arranged in an array to replace the pins of conventional Pin Grid Array (PGA). PGA is a through hole packaging technology that is restricted by the pitch between the separate areas on the printed board. On the other hand, BGA is a surface packaging technology without such restriction. Thus, BGA is suitable for packaging compact products with high density of I/Os. With the emergence of Flip Chip used in high-level products, BGA is becoming the technology of choice in the modern packaging industry. However, in practice, when applying Flip Chip Ball Grid Array (FCBGA) on Flip Chip Substrate, the current BGA technology suffers from the problems of crowed routing space, substrate warpage, and the solder resist too thick to adhere the IC devices. It is necessary to develop a different packaging structure and method for solving the aforementioned problems.[0002]
- As shown in FIG. 1A, a conventional Flip Chip Substrate includes 4 to 8 layers of printed circuit boards. The substrate could be made of ceramic or organic material. The communication between the layers of boards is through the tiny holes drilled mechanically or with laser. Wires are extended through the tiny holes and made into bump pads for connecting the IC bumps. The conventional approach usually requires a larger space; hence, restricts the density and the flexibility of routing. It is desirable to device a technology to fill the tiny laser-drilled holes with plating copper in order to form the communication between the layers of boards. This will improve the density and the flexibility of routing.[0003]
- In the IC packaging process, the substrates are treated with a high temperature step which could sometimes deform the substrates. The deformed substrates, warped or twisted, are difficult for the IC chips to be adhered on. To avoid heat deformation, the present invention provides a Fine Pitch flip chip substrate with a mesh pattern to increase the stiffness of the substrates. The mesh pattern improves the resistance to heat deformation.[0004]
- In a conventional IC packaging process, the flip chip substrates is coated with a photo solder resist made of Epoxy to prevent short-circuit of the tin bridge due to the flowing of melted soldering tin during the solder reflow. Also, a bump pad is formed at the area for connecting each solder bump of I/O on the IC chips in the packaging process. This step is difficult for the flip chip substrate that requires its alignment precision to be within 25 μm. Meanwhile, the thickness of the solder resist are usually controlled between 15 to 45 μm during manufacturing. Therefore, the bump pads buried in the solder resist will degrade the connection between the IC bumps and the pads on the substrate.[0005]
- The present invention provides a Fine Pitch flip chip substrate structure, as shown in FIG. 1B. A black oxide dam is formed on the metal wires between the bump pads to replace the conventional solder resist. The thickness of the dam can be easily controlled between 1-3 μm such that the bump pads will not be buried in the solder resist. As the present invention is no longer constrained by the alignment precision imposed by the solder resist in the IC connection area, it solves the misalignment problem faced by the conventional technology.[0006]
- A similar technology to the present invention is to electro-plate a NiO layer to form the black oxide resist layer. The thickness of the NiO has to be controlled below 5 μm. The inherent shortcoming of this method is that the metal wires are not well adherent to the underfill, which is a glue used at the bottom of IC during the FCBGA process. Thus, the reliability is reduced. On the other hand, the present invention grows fur-shaped black oxide dam directly on the wire. This will enhance the adhesion to the underfill, and improve the long term reliability of the circuits. The use of NiO provides no such capability.[0007]
- The present invention relates to a method comprising the following steps:[0008]
- Step 1: providing a substrate:[0009]
- Form a first metal layer on the substrate, on which a plurality of through holes are drilled. A first metal plated layer is formed on the first metal layer and the through holes.[0010]
- Step 2: forming an inner circuit:[0011]
- Transfer image on the dry film and to etch the first metal layer and the first metal plated layer according the image to form a plurality of traces, the remained portion becomes the inner circuit.[0012]
- Step 3: black oxide inner circuit:[0013]
- Form a black oxide inner circuit in the inner circuit by oxidizing the inner circuit.[0014]
- Step 4: forming a mediate layer and a second metal layer;[0015]
- Introduce dielectric substance into the traces and the through holes of the substrate and coat the entire inner circuit. A metal foil is formed on the dielectric layer and is laminated to become the second metal layer.[0016]
- Step 5: forming vias in the dielectric layer by laser beams:[0017]
- Form a laser mask by transferring an image on the dry film. Vias are drilled by laser drilling at the opening of the laser mask to form a plurality of dielectric layer vias. A second metal plated layer is formed in the dielectric layer vias, which are plated and filled by copper to form the surface of the second metal plated layer.[0018]
- Step 6: forming a circuit layer:[0019]
- Make a Ni/Au layer on the second metal layer by using a dry film as a mask and etch the second metal layer according to the image. The remained portion is the circuit layer.[0020]
- Step 7: forming a plurality of solder resist areas:[0021]
- Form the solder resist areas on the second metal layer excluding the bump pad area for IC connection.[0022]
- Step 8: forming a plurality of black oxide dams:[0023]
- Form the black oxide dams on the second metal layer by way of oxidization.[0024]
- Step 9: packaging flip chip process:[0025]
- Underfill the bottom of IC and connect the flip chip bumps with the Ni/Au layer. The through holes of the flip chip substrate is electrically connected to the mediate layer vias.[0026]
- The primary object of the present invention is to provide a method that improves the routing flexibility on the substrates and reduces the misalignment problem in manufacturing.[0027]
- The present invention will become more obvious from the following description when taken in connection with the accompanying drawings which show, for purposes of illustration only, a preferred embodiment in accordance with the present invention.[0028]
- FIG. 1A shows the conventional flip chip substrate;[0029]
- FIG. 1B shows the fine pitch flip chip substrate of the present invention;[0030]
- FIGS. 2A to[0031]2U show the steps of the method for making the fine pitch flip chip substrate of the present invention;
- FIG. 3 shows the flip chip substrate of the present invention.[0032]
- FIGS. 2A to[0033]2T show the steps of the method for making a flip chip substrate and includes the following steps:
- FIGS. 2A to[0034]2C show a process of providing a substrate. FIG. 2A shows a
substrate 201 which may be a flip chip substrate and is made of Bismaleimide Triazine (BT), other organic material, or even ceramics. The thickness of201 is about 0.1 to 0.4 mm. Afirst metal layer 202 is made on thesubstrate 201. The first metal layer can be made of Copper (Cu) with a thickness of 12 μm. FIG. 2B shows a plurality of throughholes 203 are drilled on thesubstrate 201 by mechanical or laser drilling. Each of the throughholes 203 has a diameter of 100 to 250 μm. FIG. 2C shows that a first metal platedlayer 204 is formed on thefirst metal layer 202 and the throughholes 203. The first metal platedlayer 204 can be made of Copper (Cu) with a thickness of 15 μm. - FIGS. 2D to[0035]2E show a step of forming an inner circuit. FIG. 2D uses a
dry film 205 containing an image to be transferred as the inner circuit, and the dry film is used as a mask. A part of the first metal platedlayer 204 and thefirst metal layer 202 are etched to form traces206. As shown in FIG. 2E, the remained portions of the first metal platedlayer 204 and thefirst metal layer 202 are left as the inner circuit. - FIG. 2F shows a step of black-oxidizing the inner circuit. A black oxide[0036]
inner circuit 207 is formed in the inner circuit by oxidizing the inner circuit. - FIGS. 2G to[0037]2H show a step of forming a dielectric layer and a second metal layer. FIG. 2G shows the lamination of the dielectric material into the traces and the through holes of the substrate by heat pressing and fusion to form a
dielectric layer 208 which is coated on the entire inner circuit. Thedielectric layer 208 is made of Bismaleimide Triazing (BT) or other dielectric material. Ametal foil 209 is formed on thedielectric layer 208. Themetal foil 209 can be made of Copper (Cu) with a thickness of 12 μm. FIG. 2G shows thefoil 209 is laminated to form thesecond metal layer 209awith a thickness of 7 to 9 μm. - FIGS.[0038]21 to2M show the step of forming vias in the dielectric layer by laser beams. FIG. 2I shows that the
dry film 210 used as alaser mask 211 as shown in FIG. 2J by image transferring. A plurality of dielectric layer vias212 with a diameter of 100 μm are drilled by laser drilling at the laser openings of the laser mask as shown in FIG. 2K. A second metal platedlayer 213 is formed in thedielectric layer vias 212 and the second metal platedlayer 213, as shown in FIG. 2L. Thedielectric layer vias 212 are filled with plating filledcopper 214. FIG. 2M shows that the second metal platedlayer 213 is laminated and thesecond metal layer 209ahas a thickness of 7 to 9 μm. - FIGS. 2N to[0039]2R show a step of forming a circuit layer. FIG. 2N shows the
dry film 214 is used as a mask, and FIG. 2O shows that a Ni/Au layer 215 is coated on the portion that is not covered by the image ondry film 214. The Ni/Au layer 215 is formed by way of electro-plating and has a thickness of 5 μm. The Ni/Au layer 215 is used as the connection area of flip chip bumps. FIG. 2P shows a liquid photo resist agent or dry film pressing process is used as amask 216. FIG. 2Q shows the process of image transferring217, and FIG. 2R shows the etching on thesecond metal layer 218 wherein the remained portion is the circuit layer. A mesh pattern is designed in the circuit layer to reinforce the stiffness of the substrate and reduce the heat deformation that could cause substrate warpage or twist. - FIG. 2S shows a step of forming a plurality of solder resist areas. The solder resist[0040]
areas 219 are formed on the second metal layer, excluding the bump pads area for IC connection. The solder resist219 can be a photo solder resist coated with Epoxy. - FIG. 2T shows a step of forming a plurality of black oxide dams. The[0041]
black oxide dams 220 are formed, by way of oxidization, on thesecond metal layer 209awherein no etching is applied. The thickness of theblack oxide dams 220 is below 1-3 μm. - FIG. 2U shows the step of packaging flip chip. This includes the step of[0042]
underfilling 223 to the bottom ofIC 222. The flip chip bumps221 are connected to the Ni/Au layer 215. The through holes of the flip chip substrate are electrically connected to the mediate layer through holes and theBGA tin balls 224. - FIG. 3 shows the structure of the flip chip substrate and includes a[0043]
substrate 301 with afirst metal layer 302 on the surface of the substrate and the thickness of thefirst metal layer 302 is 12 μm. A plurality of throughholes 303 are drilled on the substrate and each has a diameter of 100 to 250 μm. The first metal platedlayer 304 is formed on the surface of thefirst metal layer 302 and the throughholes 303 of the substrate. The thickness of the first metal platedlayer 304 is about 15 μm. An inner circuit is the remained portion of the first metal platedlayer 304 and thefirst metal layer 302 by an etching process. The etching results intotraces 306. A black oxideinner circuit 307 is formed on the surface of the inner circuit. Adielectric layer 308 is formed by laminating dielectric material into thetraces 306 and the throughholes 303 of the substrate and is coated on the entire inner circuit. A metal foil309 with a thickness of 12 μm is formed on thedielectric layer 308. The metal foil309 is laminated to form asecond metal layer 309awhich has a thickness of 7-9 μm. A plurality ofdielectric layer vias 312 are made by drilling holes at 100 μm in diameter with laser. A second metal platedlayer 313 is formed in the dielectric layer vias312 which are filled with plating filled copper. A circuit layer is made by forming a Ni/Au layer 315 on thesecond metal layer 309aand is used to connect the Ni/Au layer and the bumps. The thickness of the Ni/Au is about 5 μm. By etching part of thesecond metal layer 309a, it forms the circuit layer which has a mesh pattern to reinforce the stiffness of the substrate and reduces the heat deformation which could cause substrate warpage and twist. A plurality of solder resistareas 319 are formed on the areas of thesecond metal layer 309aexcluding bump pads area for IC connection. A plurality ofblack oxide dams 320 are formed on thesecond metal layer 209aand eachblack oxide dams 320 has a thickness of 1-3 μm. - The present invention has the following advantages in comparison with the current technologies:[0044]
- 1. The black oxide dams on the circuit of non-bump pads are able to reduce the thickness of the solder resists, which is a common problem for using the conventional solder resists. In comparison with the requirement of the conventional alignment precision of ±25 μm, the present invention may have an alignment tolerance up to 50 μm. The plating filled copper reduces the number of the wires and the bump pads pitch is reduced to be 50 μm so as to increase the density of the wires. Therefore, there is enough space for the mesh pattern to improve the packaging quality.[0045]
- 2. The thickness of the black oxide layer of the present invention is about 1-3 μm. In comparison with the conventional requirement of the thickness of the solder resist 25 μm, the clearer shape and the better resolution enable the alignment precision of the present invention to be easily controlled under 20 μm.[0046]
- 3. The conventional photo solder resist usually forms a deep well in the manufacturing process, debris is left at the bottom of the bump pads and affects the quality of packaging. The present invention solves the problem.[0047]
- 4. The high density flip chip bumps are replaced with the black oxide dams in the soldering of the packaging process. The thickness of the plated Ni/Au layer on the bump pad is about 5 μm and the black oxide dam is lower than the bump pad. In comparison with the conventional solder resist having a thickness of 25 μm, which is higher than the bump pad, it is advantageous for the high quality and reliability of the flip chip bumping packaging.[0048]
- 5. The conventional packaging employs a tin-lead solder bump which does not meet the trend of un-leaded environmental green requirement. The present invention meets the requirement.[0049]
- While we have shown and described the embodiment in accordance with the present invention, it should be clear to those skilled in the art that further embodiments may be made without departing from the scope of the present invention.[0050]
Claims (27)
1. A method for making a fine pitch flip chip substrate, comprising the steps of:
providing a substrate, with a first metal layer, the said substrate having a plurality of through holes, a first metal plated layer on the first metal layer and the through holes;
forming an inner circuit on said substrate;
forming a black oxide inner circuit by oxidizing said inner circuit;
forming a dielectric layer and a second metal layer on said substrate;
forming vias in the dielectric layer by drilling to form a plurality of dielectric layer vias, and a second metal plated layer formed in said vias, which are plated and filled to form the surface of the second metal plated layer;
forming a circuit layer on said second metal layer;
forming a plurality of solder resist opening areas on said second metal layer excluding IC bump pad area;
forming a plurality of black oxide dams on said second metal layer by oxidization;
packaging flip chip by under g said IC bumping area, connecting the through holes of the flip chip substrate and said vias of the dielectric layer.
2. The method as claimed inclaim 1 , wherein in the step of providing a substrate which is made of Bismaleimide Triazine (BT), other organic material, or even ceramics. The thickness of substrate is about 0.1 to 0.4 mm.
3. The method as claimed inclaim 1 , wherein in the step of providing a substrate, the first metal layer is made of Copper (Cu) with a thickness of 12 μm.
4. The method as claimed inclaim 1 , wherein in the step of providing a substrate, a plurality of through holes on the substrate is drilled by mechanical or laser drilling. Each of the through holes203 has a diameter of 100 to 250 μm.
5. The method as claimed inclaim 1 , wherein in the step of providing a substrate, a first metal plated layer forming on the first metal layer and the through holes is made of Copper (Cu) with a thickness of 15 μm.
6. The method as claimed inclaim 1 , wherein in the step of forming a dielectric layer and a second metal layer, the dielectric layer is made of Bismaleimde Triazing (BT or other dielectric material.
7. The method as claimed inclaim 1 , wherein in the step of forming a dielectric layer and a second metal layer, the metal foil is made of Copper (Cu) with a thickness of 12 μm.
8. The method as claimed inclaim 7 , wherein in the step of forming a dielectric layer and a second metal layer, the foil is laminated to form the second metal layer with a thickness of 7 to 9 μm.
9. The method as claimed inclaim 1 , wherein in the step of forming vias in the dielectric layer by laser beams, a plurality of dielectric layer vias with a diameter of 100 μm are drilled by laser drilling and the second metal plated layer is laminated to a thickness of 7 to 9 μm.
10. The method as claimed inclaim 1 , wherein in the step of forming a circuit layer, the Ni/Au layer is formed by way of electro-plating and has a thickness of 5 μm. The Ni/Au layer is used as the connection area of flip chip bumps.
11. The method as claimed inclaim 1 , wherein in the step of forming a circuit layer, a, liquid photo resist agent or dry film pressing process is used as a mask.
12. The method as claimed inclaim 1 , wherein in the step of forming a circuit layer, a mesh pattern is designed in the circuit layer to reinforce the stiffness of the substrate and reduce the heat deformation that could cause substrate warpage or twist.
13. The method as claimed inclaim 1 , wherein in the step of forming a plurality of solder resist areas, the solder resist is a photo solder resist coated with Epoxy.
14. The method as claimed inclaim 1 , wherein in the step of forming a plurality of black oxide dams, the thickness of the black oxide dams is below 1-3 μm.
15. A fine pitch flip chip substrate comprising:
a fist metal layer formed on the substrate, a plurality of through holes defined through the substrate, a first metal plated layer being made on the first metal layer and the through holes;
an inner layer circuit, etching the first metal layer and the fiat metal plated layer according to the mask to form a plurality of traces, the remained metal portion becoming the inner layer circuit;
black oxide inner layer circuit formed at the surface of the metal circuit of the inner layer circuit;
a dielectric layer being formed by laminating dielectric material on the though holes of the substrate and cover the entire inner layer circuit, a metal foil formed on the dielectric layer and laminated to be the second metal layer;
vias in the dielectric layer and a second metal plated layer formed in the dielectric layer vias which are plated and filled by copper;
a circuit layer formed by plating Ni/Au layer on the second metal layer;
a plurality of solder resist opening areas formed on the second metal layer excluding IC bump pad area;
a plurality of black oxide dams being formed dams on the surface of the IC bump pad connected trace.
16. The substrate claimed as inclaim 15 , wherein the substrate which is made of Bismaleimide Triazine (BT), other organic material, or even ceramics. The thickness of substrate is about 0.1 to 0.4 mm.
17. The substrate claimed as inclaim 15 , wherein the first metal layer is made of Copper (Cu) with a thickness of 12 μm.
18. The substrate claimed as inclaim 15 , wherein a plurality of through holes on the substrate are drilled by mechanical or laser drilling. Each of the through holes203 has a diameter of 100 to 250 μm.
19. The substrate claimed as inclaim 15 , wherein a first metal plated layer forming on the first metal layer and the through holes is made of Copper (Cu) with a thickness of 15 μm.
20. The substrate claimed as inclaim 15 , wherein the dielectric layer is made of Bismaleimide Triazing (BT) or other dielectric material.
21. The substrate claimed as inclaim 15 , wherein a plurality of dielectric layer vias with a diameter of 100 μm are drilled by laser drilling and the metal foil may be made of Copper (Cu) with a thickness of 12 μm.
22. The substrate as claimed inclaim 21 , wherein the foil is laminated to form the second metal layer with a thickness of 7 to 9 μm.
23. The substrate as claimed inclaim 21 , wherein the Ni/Au layer is formed by way of electroplating and has a thickness of 5 μm. The Ni/Au layer is used as the connection area of flip chip bumps.
24. The substrate as claimed inclaim 21 , wherein a liquid photo resist agent or dry film pressing process is used as a mask.
25. The substrate as claimed inclaim 21 , wherein a mesh pattern is designed in the circuit layer to reinforce the stiffness of the substrate and reduce the heat deformation that cause substrate warpage or twist.
26. The substrate as claimed inclaim 21 , wherein the solder resist is a photo solder resist coated with Epoxy.
27. The substrate as claimed inclaim 21 , wherein the thickness of the black oxide dams is below 1-3 μm.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/197,066US20040012097A1 (en) | 2002-07-17 | 2002-07-17 | Structure and method for fine pitch flip chip substrate |
| US10/932,874US6969674B2 (en) | 2002-07-17 | 2004-09-01 | Structure and method for fine pitch flip chip substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/197,066US20040012097A1 (en) | 2002-07-17 | 2002-07-17 | Structure and method for fine pitch flip chip substrate |
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| US10/932,874DivisionUS6969674B2 (en) | 2002-07-17 | 2004-09-01 | Structure and method for fine pitch flip chip substrate |
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| US20040012097A1true US20040012097A1 (en) | 2004-01-22 |
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| US10/197,066AbandonedUS20040012097A1 (en) | 2002-07-17 | 2002-07-17 | Structure and method for fine pitch flip chip substrate |
| US10/932,874Expired - LifetimeUS6969674B2 (en) | 2002-07-17 | 2004-09-01 | Structure and method for fine pitch flip chip substrate |
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| Application Number | Title | Priority Date | Filing Date |
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| US10/932,874Expired - LifetimeUS6969674B2 (en) | 2002-07-17 | 2004-09-01 | Structure and method for fine pitch flip chip substrate |
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| US20070080449A1 (en)* | 2005-10-07 | 2007-04-12 | Nec Electronics Corporation | Interconnect substrate and electronic circuit device |
| CN100403504C (en)* | 2006-07-25 | 2008-07-16 | 威盛电子股份有限公司 | Packaging substrate process and chip packaging body |
| US20090001606A1 (en)* | 2007-06-27 | 2009-01-01 | Shinko Electric Industries Co., Ltd. | Semiconductor package and semiconductor device using the same |
| US20100236822A1 (en)* | 2009-03-23 | 2010-09-23 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
| CN103050475A (en)* | 2012-12-18 | 2013-04-17 | 苏州日月新半导体有限公司 | Anti-warping packaging substrate |
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| CN100403504C (en)* | 2006-07-25 | 2008-07-16 | 威盛电子股份有限公司 | Packaging substrate process and chip packaging body |
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| US20140035130A1 (en)* | 2012-08-06 | 2014-02-06 | Samsung Electro-Mechanics Co., Ltd. | Packaging method using solder coating ball and package manufactured thereby |
| US8952531B2 (en)* | 2012-08-06 | 2015-02-10 | Samsung Electro-Mechanics Co., Ltd. | Packaging method using solder coating ball and package having solder pattern including metal pattern |
| CN103050475A (en)* | 2012-12-18 | 2013-04-17 | 苏州日月新半导体有限公司 | Anti-warping packaging substrate |
| CN104995731A (en)* | 2013-03-29 | 2015-10-21 | 三菱综合材料株式会社 | Power module |
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| CN104752234A (en)* | 2014-12-17 | 2015-07-01 | 安捷利电子科技（苏州）有限公司 | Micro blind hole manufacturing method for flexible packaging substrate |
| CN109727965A (en)* | 2017-10-27 | 2019-05-07 | 三星电机株式会社 | Fan-out semiconductor package module and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| US20050032273A1 (en) | 2005-02-10 |
| US6969674B2 (en) | 2005-11-29 |
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| AS | Assignment | Owner name:KINSUS INTERCONNECT TECHNOLOGY CORP., TAIWAN Free format text:ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHANG, CHIEN-WEI;HUANG, SHENG-CHUAN;REEL/FRAME:013115/0387 Effective date:20020712 | |
| STCB | Information on status: application discontinuation | Free format text:ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |