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US20040002215A1 - Whole wafer MEMS release process - Google Patents

Whole wafer MEMS release process
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Publication number
US20040002215A1
US20040002215A1US10/608,288US60828803AUS2004002215A1US 20040002215 A1US20040002215 A1US 20040002215A1US 60828803 AUS60828803 AUS 60828803AUS 2004002215 A1US2004002215 A1US 2004002215A1
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United States
Prior art keywords
lines
wafer
devices
width
layer
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Abandoned
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US10/608,288
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Andrew Dewa
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Individual
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Individual
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Priority to US10/608,288priorityCriticalpatent/US20040002215A1/en
Publication of US20040002215A1publicationCriticalpatent/US20040002215A1/en
Abandonedlegal-statusCriticalCurrent

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Abstract

A process for manufacturing a wafer having a multiplicity of MEMS devices such as mirrors with gimbals formed thereon is disclosed. The devices on the wafer include features defined by a wide line between features which extend completely through the wafer, and have a ratio of greater than about 4:1 with respect to the narrow lines which separate individual devices. Each individual device is separated by narrow gaps or line widths which are, for example, about 10 μm. Thus, the etching process is controlled such that the features defined by the wide lines are etched completely through, whereas the individual devices are separated by narrow lines which are not etched completely through the wafer. Therefore, the multiplicity of devices remain attached together even after the wafer is released from a backing wafer. Thus, the wafer with the many devices still attached together allows further processing such as packaging, testing, transport, etc. without the required handling of individual devices.

Description

Claims (21)

I claim:
1. A process for manufacturing a plurality of MEMS devices on a first layer of material of a selected thickness comprising:
attaching said first layer of material to a backing layer of material;
defining features on each individual ones of said plurality of MEMS devices with first lines having at least a first selected width;
defining boundary lines between individual ones of said plurality of MEMS devices with second lines having a width that is less than said first selected width;
simultaneously etching said first lines and said second lines until said first lines defining device features are etched through said selected thickness;
stopping said etching before said second lines defining boundaries are etched through said first selected thickness; and
separating said first layer with said plurality of devices attached together from said backing layer.
2. The process ofclaim 1 and comprising further processing of said separated first layer.
3. The process ofclaim 2 when said further processing comprising testing said devices while still attached together on said first layer.
4. The process ofclaim 2 wherein said further processing comprises separating each individual device of said first layer from each other.
5. The process ofclaim 1 wherein said further processing comprises cleaning said devices while still attached together subsequent to said separation step.
6. The process ofclaim 1 and further comprising packing said separated wafer with said devices still attached together for storage or shipping.
7. The process ofclaim 1 wherein said first width of said first lines have a ratio greater than 4:1 with respect to said width of said second lines.
8. The process ofclaim 1 wherein said first selected width is at least about 50 μm and said second width is about 10 μm.
9. The process ofclaim 1 wherein said first layer of material is selected from the group consisting of silicon, gallium arsenide, quartz and silicon carbide.
10. The process ofclaim 9 wherein said first layer of material is silicon.
11. A process for manufacturing a plurality of gimbal mirror devices on a first layer of material of a selected thickness comprising:
attaching said first layer of material to a backing layer of material;
defining features on each individual ones of said plurality of gimbal mirror devices with first lines having at least a first selected width;
defining boundary lines between individual ones of said plurality of gimbal mirror devices with second lines having a width that is less than said first selected width;
simultaneously etching said first lines and said second lines until said first lines defining gimbal mirror features are etched through said first selected thickness;
stopping said etching before said second lines defining boundaries are etched through said first selected thickness; and
separating said first layer with said plurality of gimbal mirror devices attached together from said backing layer.
12. The process ofclaim 11 further comprising testing individual devices defined on said first layer.
13. The process ofclaim 11 further comprising separating each individual gimbal mirror device from said first layer.
14. The process ofclaim 11 wherein said further processing comprises cleaning said gimbal mirror while still attached together subsequent to said step of separating said first layer from said backing layer.
15. The process ofclaim 11 and further comprising packing said separated wafer with said devices still attached together for storage or shipping.
16. The process ofclaim 11 wherein said first lines have a width at least equal to about 50 μm and said second lines have a width of about 10 μm.
17. The process ofclaim 11 wherein said first layer is a silicon wafer.
18. A wafer defining a plurality of MEMS devices attached together comprising:
at least two features of said MEMS devices separated by first lines etched completely through said wafer, said first line having at least a first selected width;
second lines etched part way through said wafer defining individual ones of said plurality of MEMS devices, said second lines having a second width which is less than said first selected width.
19. The wafer ofclaim 18 wherein said width of said first lines have a ratio greater than 4:1 with respect to said width of said second lines.
20. The wafer ofclaim 18 wherein said first selected width is at least about 50 μm and said second width is about 10 μm.
21. A wafer defining a plurality of gimbal mirror devices attached together comprising:
at least two features of said gimbal mirror devices separated by first lines etched completely through said wafer, said first lines having at least a first selected width;
second lines etched part way through said wafer defining individual ones of said plurality of gimbal mirror devices, said second lines having a second width which is less than said first selected width.
US10/608,2882001-12-212003-06-27Whole wafer MEMS release processAbandonedUS20040002215A1 (en)

Priority Applications (1)

Application NumberPriority DateFiling DateTitle
US10/608,288US20040002215A1 (en)2001-12-212003-06-27Whole wafer MEMS release process

Applications Claiming Priority (3)

Application NumberPriority DateFiling DateTitle
US34224801P2001-12-212001-12-21
US10/076,222US6586315B1 (en)2001-12-212002-02-14Whole wafer MEMS release process
US10/608,288US20040002215A1 (en)2001-12-212003-06-27Whole wafer MEMS release process

Related Parent Applications (1)

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US10/076,222DivisionUS6586315B1 (en)2001-12-212002-02-14Whole wafer MEMS release process

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US20040002215A1true US20040002215A1 (en)2004-01-01

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US10/076,222Expired - LifetimeUS6586315B1 (en)2001-12-212002-02-14Whole wafer MEMS release process
US10/608,288AbandonedUS20040002215A1 (en)2001-12-212003-06-27Whole wafer MEMS release process

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US10/076,222Expired - LifetimeUS6586315B1 (en)2001-12-212002-02-14Whole wafer MEMS release process

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US20060027522A1 (en)*2004-08-092006-02-09Martin John RMethod of producing a MEMS device
US20060027885A1 (en)*2004-08-092006-02-09Martin John RMEMS device with non-standard profile
US10611632B1 (en)*2018-12-292020-04-07Texas Instruments IncorporatedSingulation of wafer level packaging

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US6962514B2 (en)*2002-08-082005-11-08Applied Materials, Inc.Method and apparatus used in fabrication of MEMS stacks
US7041579B2 (en)*2003-10-222006-05-09Northrop Grumman CorporationHard substrate wafer sawing process
KR101263276B1 (en)*2004-10-212013-05-10후지필름 디마틱스, 인크.Sacrificial substrate for etching
US7534822B2 (en)*2004-11-222009-05-19Sabic Innovative Plastics Ip B.V.Method of making a flame retardant poly(arylene ether)/polyamide composition
US20060111548A1 (en)*2004-11-222006-05-25Mark ElkovitchMethod of making a flame retardant poly(arylene ether)/polyamide composition and the composition thereof
US20070042563A1 (en)*2005-08-192007-02-22Honeywell International Inc.Single crystal based through the wafer connections technical field
US7932182B2 (en)*2005-08-192011-04-26Honeywell International Inc.Creating novel structures using deep trenching of oriented silicon substrates
JP4812512B2 (en)*2006-05-192011-11-09オンセミコンダクター・トレーディング・リミテッド Manufacturing method of semiconductor device
US7767483B1 (en)*2006-07-252010-08-03The United States Of America As Represented By The Secretary Of The NavyDual-suspension system for MEMS-based devices and method for fabricating same

Citations (3)

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Publication numberPriority datePublication dateAssigneeTitle
US20020181886A1 (en)*2001-06-042002-12-05Fischer Kevin J.Bi-directional micromechanical latching linear actuator
US20030002802A1 (en)*2001-06-292003-01-02John TrezzaMulti-piece fiber optic component and manufacturing technique
US6685844B2 (en)*2001-02-142004-02-03Delphi Technologies, Inc.Deep reactive ion etching process and microelectromechanical devices formed thereby

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US6444138B1 (en)*1999-06-162002-09-03James E. MoonMethod of fabricating microelectromechanical and microfluidic devices
US6387778B1 (en)*2000-02-112002-05-14Seagate Technology LlcBreakable tethers for microelectromechanical system devices utilizing reactive ion etching lag
US6383833B1 (en)*2000-05-232002-05-07Silverbrook Research Pty Ltd.Method of fabricating devices incorporating microelectromechanical systems using at least one UV curable tape

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US6685844B2 (en)*2001-02-142004-02-03Delphi Technologies, Inc.Deep reactive ion etching process and microelectromechanical devices formed thereby
US20020181886A1 (en)*2001-06-042002-12-05Fischer Kevin J.Bi-directional micromechanical latching linear actuator
US20030002802A1 (en)*2001-06-292003-01-02John TrezzaMulti-piece fiber optic component and manufacturing technique

Cited By (9)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US20060027522A1 (en)*2004-08-092006-02-09Martin John RMethod of producing a MEMS device
US20060027885A1 (en)*2004-08-092006-02-09Martin John RMEMS device with non-standard profile
WO2006022956A1 (en)*2004-08-092006-03-02Analog Devices, Inc.Mems device with non-standard profile
US7416984B2 (en)2004-08-092008-08-26Analog Devices, Inc.Method of producing a MEMS device
US20080225505A1 (en)*2004-08-092008-09-18Analog Devices, Inc.Method of producing a MEMS device
US7521363B2 (en)2004-08-092009-04-21Analog Devices, Inc.MEMS device with non-standard profile
US8343369B2 (en)2004-08-092013-01-01Analog Devices, Inc.Method of producing a MEMS device
US10611632B1 (en)*2018-12-292020-04-07Texas Instruments IncorporatedSingulation of wafer level packaging
US11235971B2 (en)2018-12-292022-02-01Texas Instruments IncorporatedSingulation of wafer level packaging

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Publication numberPublication date
US6586315B1 (en)2003-07-01
US20030116815A1 (en)2003-06-26

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STCBInformation on status: application discontinuation

Free format text:ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION


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