US20030234443A1 - Low profile stacking system and method - Google Patents
Low profile stacking system and methodDownload PDFInfo
- Publication number
- US20030234443A1 US20030234443A1US10/457,608US45760803AUS2003234443A1US 20030234443 A1US20030234443 A1US 20030234443A1US 45760803 AUS45760803 AUS 45760803AUS 2003234443 A1US2003234443 A1US 2003234443A1
- Authority
- US
- United States
- Prior art keywords
- csp
- contacts
- flex
- circuit
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0657—Stacked arrangements of devices
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5387—Flexible insulating substrates
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13116—Lead [Pb] as principal constituent
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
- H01L2224/81011—Chemical cleaning, e.g. etching, flux
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/8121—Applying energy for connecting using a reflow oven
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06579—TAB carriers; beam leads
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
- H01L2225/06586—Housing with external bump or bump-like connectors
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01051—Antimony [Sb]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/05—Flexible printed circuits [FPCs]
- H05K2201/056—Folded around rigid support or component
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/361—Assembling flexible printed circuits with other printed circuits
- H05K3/363—Assembling flexible printed circuits with other printed circuits by soldering
Definitions
- the present inventionrelates to mounting integrated circuit devices on substrates and to mounting integrated circuits on substrates employed in stacked modules.
- solder pasteis selectively applied to the integrated circuit device or substrate to which the IC is to be attached.
- the device and substrateare exposed to reflow temperatures of approximately 220° C.
- the deviceis, consequently, soldered to the substrate.
- solder jointswill re-melt during subsequent processing.
- Common tin-lead soldersstart to melt at 183° C. and, when exposed to such temperatures and higher, the exposed joint may re-melt and become unreliable.
- the present inventionprovides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules.
- the contact pads of a packaged integrated circuit deviceare substantially exposed.
- a solder paste that includes higher temperature solder paste alloyis applied to a substrate or the contacts of the packaged device.
- the integrated circuit deviceis positioned to contact the contacts of the substrate with the higher temperature solder alloy paste between.
- Heatis applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints.
- the formed jointsare less subject to re-melting in subsequent processing steps.
- the methodmay be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile.
- a first solder used to construct a stacked modulehas a higher melting point than a second solder used to populate a board with that module.
- FIG. 1depicts a typical prior art packaged integrated circuit device.
- FIG. 2depicts the device of FIG. 1 from which the solder ball contacts have been removed.
- FIG. 3depicts a set of substrate contacts upon which a high temperature solder paste has been applied in accordance with a preferred embodiment of the present invention.
- FIG. 4depicts portions of two flexible circuit connectors prepared for mounting of an integrated circuit device in accordance with a preferred embodiment of the present invention.
- FIG. 5depicts a device-substrate assembly in accordance with a preferred embodiment of the present invention.
- FIG. 6depicts a two-high integrated circuit module mounted to the two flexible circuit connectors depicted in FIG. 4 in accordance with a preferred embodiment of the present invention.
- FIG. 7depicts a four-high stacked module devised in accordance with a preferred embodiment of the present invention.
- FIG. 1depicts an exemplar integrated circuit device 10 having upper surface 11 and lower surface 13 .
- Device 10is an example of one type of the general class of devices commonly known in the art as chip-scale-packaged integrated circuits (“CSPs”).
- CSPschip-scale-packaged integrated circuits
- the present inventionmay employed with a wide variety of integrated circuit devices and is not, as those of skill in the art will understand, limited to devices having the profile depicted in FIG. 1. Further, although its preferred use is with plastic-bodied CSP devices, the invention provides advantages in mounting a variety of packaged integrated circuit devices in a wide variety of configurations including leaded and CSP topologies.
- Exemplar integrated circuit device 10may include one or more integrated circuit die and body 12 and a set of contacts 14 .
- the illustrated integrated circuit device 10has CSP ball contacts 14 arrayed along surface 13 of its body 12 .
- CSP ball contacts 14are, as depicted, balls that are a mixture of tin and lead with a common relative composition of 63% tin and 37% lead.
- Such contactstypically have a melting point of about 183° C.
- Other contactsare sometimes found along a planar surface of integrated circuit devices and such other contacts may also be treated in accordance with the present invention where the opportunity arises as will be understood after gaining familiarity with the present disclosure.
- CSP ball contacts 14have been removed, leaving CSP pads 16 arrayed along lower surface 13 .
- CSP pads 16will typically exhibit a residual thin layer of tin/lead mixture after removal of CSP ball contacts 14 .
- CSPsmay be received without attached balls and the process and structures described herein will then not require “removal” of balls. Further, embodiments of the present invention may be implemented with CSPs already bearing ball contacts comprised of high temperature solders.
- FIG. 3depicts exemplar substrate 18 on which are disposed contacts 20 .
- Substrate 18is depicted as a rigid board such as a PWB or PCB such as are known in the art.
- a solder paste 22is applied to substrate contacts 20 .
- solder paste 22is applied to the CSP pads 16 and not the substrate contacts 20 .
- solder paste 22may applied to both substrate contacts 20 and CSP pads 16 (or a set of contacts of other configuration when devices that are not CSP are used in accordance with the invention.)
- solder pasteis a mixture of solder particles and flux.
- solder alloy employed in solder paste 22exhibits a melting point equal to or greater than 235° C. and, preferably between 235° C. and 312° C.
- the alloy chosenshould not have a melting point so high that the IC package is adversely affected, but it should also not be so low as to remelt during board assembly operations.
- lead-free soldersSuch lead-free solders will typically have melting points higher than those found in lead inclusive solders. Typically, those who use lead-free solders to populate boards with stacked modules will, for example, employ temperatures up to 240° C. in the process of attachment of stacked modules to boards. Consequently, a HT joint implemented with a lead-free alloy will, in conformity with preferred embodiments of the present invention, exhibit a melting point greater than those lead-free solders used to populate boards. Consequently, a preferred implementation of the HT joints of the present invention will have a melting point range of between 245° C. and 265° C.
- the lead-free solder alloy employed in such HT jointswill be comprised of at least two of the following elements: tin, silver, copper, or indium.
- an alloy used as a solder in the present inventionwill melt over a narrow temperature range. Disintegration of the module during board attachment or population will be less likely if the melt range is narrow. Most preferably, the top of the melting point range of the solder used in board attachment should be exceeded by 15° C. by the melting point of the solder used to manufacture the stacked module although in the case of lead-free solders, this is reduced to ameliorate issues that could arise from exposure of the package to high temperatures.
- solder alloysappropriate for use in the present invention.
- these examplesare instructive in selecting other preferred particular combinations of lead, tin, silver, copper, antimony, and indium that are readily employed to advantage in the present invention so as to arrive at alloys of at least two of the following solder elements: lead, tin, silver, copper, antimony, and indium that have in their combined mixture, a preferred melting point between 235° C. to 312° C. inclusive.
- a combination of 95% Sn and 5% Sbmelts over a range of 235° C. to 240° C.
- solder alloys or mixturesmay also be employed in embodiments of the present invention that exhibit melting points lower than 235° C., as would be exhibited for example with a 97% Sn and a 3% Sb alloy, but preferred embodiments will employ solder mixtures or alloys that melt between 235° C. and 312° C. inclusive.
- FIG. 4depicts portions of two flexible circuit connectors 24 A and 24 B prepared for mounting of a device 10 in accordance with a preferred embodiment of the present invention.
- Exemplar flex circuits 24 A and 24 Bmay be simple flex circuitry or may exhibit the more sophisticated designs of flex circuitry such as those that would be constructed in accordance with the detailed descriptions provided in U.S. Patent Application Ser. No. 10/005,581 which has been made part of this application by incorporation by reference.
- depicted flex circuits 24 A and 24 Bexhibit a single conductive layer 26 and a first outer layer 28 .
- Conductive layer 26is supported by substrate layer 30 , which, in a preferred embodiment, is a polyimide.
- Outer layer 32resides along the lower surface of the flex circuits 24 A and 24 B.
- Optional outer layers 28 and 32when present, are typically a covercoat or solder mask material. Windows 34 are created through outer layer 32 and intermediate layer 30 to expose flex contacts 36 .
- solder paste 22is applied to flex contacts 36 which are demarked at the level of conductive layer 26 .
- Solder paste 22may also alternatively or in addition, be applied to the CSP pads 16 of a CSP.
- Windows 34provide openings through which module contacts may be disposed in a later stacked module assembly step.
- FIG. 5depicts a device-substrate assembly in accordance with a preferred embodiment of the present invention as may be employed in the construction of a low profile stacked module.
- the features depicted in FIG. 5are not drawn to scale, and show various features in an enlarged aspect for purposes of illustration.
- integrated circuit device 10is disposed upon flex circuits 24 A and 24 B which have been, in a preferred embodiment of the method of the present invention, previously prepared as shown in earlier FIG. 4.
- Module contacts 40have been appended to flex circuits 24 A and 24 B to provide connective facility for the device-flex combination whether as part of a stacked module or otherwise.
- High temperature joint contacts 38(“HT joints”) are formed by the melting of the lead alloy in previously applied solder paste 22 and the application of a selected heat range appropriate for the solder mixtures identified previously.
- HT joints 38will, after solidification, typically not re-melt unless exposed subsequently to such temperature ranges.
- the temperature range applied in this step of assemblywill not typically be subsequently encountered in a later assembly operation such as, for example, the application of a stacked module to a DIMM board. Consequently, in one embodiment, the present invention is articulated as a stacked module having HT joints that is appended to a DIMM board with traditional lower melting point solder.
- FIG. 6depicts a two-high stacked module devised in accordance with a preferred embodiment of the present invention.
- Stacked module 50 shown in FIG. 6includes lower integrated circuit device 52 and upper integrated circuit device 54 .
- a stacked module 50may be devised in accordance with the present invention that includes more than two packaged integrated circuit devices.
- Flex circuits 56 A and 56 Bare depicted connecting lower integrated circuit device 52 and upper integrated circuit device 54 .
- module 50may be implemented with a single flexible circuit connector. Further, the flexible circuit connectors employed in accordance with the invention may exhibit one or more conductive layers. Flex circuits 56 A and 56 B may be any circuit connector structure that provides connective facility between two integrated circuits having a contact array.
- flexible circuits 56 A and 56 Bmay exhibit single conductive layers (such as, for example, the flexible circuit connectors earlier illustrated herein and identified for descriptive purposes as flex circuits 24 A and 24 B in FIG. 5) or may exhibit multiple conductive layers. Examples of other preferred flexible circuit structures are found in U.S. Application Ser. No. 10/005,581 which has been incorporated by reference and those of skill will readily appreciate how a variety of circuit structures may be employed in preferred embodiments. Further, the connective structures used to connect lower integrated circuit 52 with upper integrated circuit 54 need not literally be flexible circuit connectors but may be flexible in portions and rigid in other portions.
- HT contacts 38are employed in the preferred embodiment of FIG. 6 to provide connective facility between the respective integrated circuits and contacts borne by the flex circuits 56 A and 56 B.
- HT joints 38will exhibit a height dimension smaller than that of CSP ball contacts 14 shown earlier as part of typical CSPs in FIG. 1.
- HT joints 38are depicted in a scale that is enlarged relative to joint sizes that would typically be encountered in actual practice of preferred modes of the invention.
- module 50will preferably present a lower profile than stacked modules created employing typical CSP contacts 14 on each of the constituent integrated circuit packages employed in a stacked module 50 .
- FIG. 7depicts module 60 as having lower integrated circuit element 52 , upper IC element 54 , 3 rd IC element 58 , and 4 th IC element 62 .
- some embodimentswill present HT contacts that have minimal heights that do not cause appreciable separation between the flex circuitry associated IC 52 and IC 54 , for example, or between IC 54 and IC 62 , for example.
- the apparent height for illustrated HT joints 39particularly, that lie between respective layers of flex circuitry will be understood to be exaggerated in the depiction of FIG. 7.
- Three sets of flex circuitry pairs 56 A and 56 Bare also shown but, as in other embodiments, the invention may be implemented with a variety of substrates including single flex circuits in place of the depicted pair and with flexible circuits that have one or plural conductive layers.
- the HT jointsprovide connections between integrated circuit devices and substrates and the overall profile of module 60 is reduced by use of the present invention that provides advantages in subsequent processing steps such as, for example, affixation of module 60 to DIMM boards, for example.
- CSP contacts 16that typically exhibit a residual layer of solder.
- a high temperature solder pastecomposed from a lead alloy or mixture that has a preferable melting point equal to or higher than 235° C. and preferably less than 312° C. is applied to substrate contacts 20 of a substrate such as a flexible circuit and/or the substrate contacts to which it is to be mounted.
- the CSPis positioned to place the CSP pads 16 and substrate contacts 22 in appropriate proximity. Heat is applied sufficient to melt the lead solder alloy of solder paste 22 thus forming HT joints 38 .
- the flexible circuitis positioned to place portions of the flexible circuit connector between the first CSP and a second CSP that is connected to the substrate with HT joints created using the process described for creating HT joints.
- the present inventionwill provide a stacked high module that is assembled using the HT joints that exhibit melting point ranges between X and Y degrees where X is less than Y. Attachment of the stacked module to a board is then implemented with a solder having a melting point between A and B degrees where A and B are less than X.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Combinations Of Printed Boards (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
- The present application is a continuation-in-part of U.S. Patent Application Ser. No. 10/005,581, filed Oct. 26, 2001, pending, which is hereby incorporated by reference.[0001]
- The present invention relates to mounting integrated circuit devices on substrates and to mounting integrated circuits on substrates employed in stacked modules.[0002]
- A variety of methods are used to mount integrated circuit devices to substrates such as PWBs and flex circuitry. Solder paste is selectively applied to the integrated circuit device or substrate to which the IC is to be attached. The device and substrate are exposed to reflow temperatures of approximately 220° C. The device is, consequently, soldered to the substrate.[0003]
- Typically, however, the formed solder joints will re-melt during subsequent processing. Common tin-lead solders start to melt at 183° C. and, when exposed to such temperatures and higher, the exposed joint may re-melt and become unreliable.[0004]
- What is needed, therefore, is a technique and system for mounting integrated circuit devices on substrates that provides an efficient and readily implemented technique to create structures that reliably withstand subsequent exposure to typical tin-lead solder melting point temperatures.[0005]
- The present invention provides a system and method that mounts integrated circuit devices onto substrates and a system and method for employing the method in stacked modules. The contact pads of a packaged integrated circuit device are substantially exposed. A solder paste that includes higher temperature solder paste alloy is applied to a substrate or the contacts of the packaged device. The integrated circuit device is positioned to contact the contacts of the substrate with the higher temperature solder alloy paste between. Heat is applied to create high temperature joints between the contacts of the substrate and the integrated circuit device resulting in a device-substrate assembly with high temperature joints. The formed joints are less subject to re-melting in subsequent processing steps. The method may be employed in devising stacked module constructions such as those disclosed herein as preferred embodiments in accordance with the invention. Typically, the created joints are low in profile. In a method in accordance with the present invention, a first solder used to construct a stacked module has a higher melting point than a second solder used to populate a board with that module.[0006]
- FIG. 1 depicts a typical prior art packaged integrated circuit device.[0007]
- FIG. 2 depicts the device of FIG. 1 from which the solder ball contacts have been removed.[0008]
- FIG. 3 depicts a set of substrate contacts upon which a high temperature solder paste has been applied in accordance with a preferred embodiment of the present invention.[0009]
- FIG. 4 depicts portions of two flexible circuit connectors prepared for mounting of an integrated circuit device in accordance with a preferred embodiment of the present invention.[0010]
- FIG. 5 depicts a device-substrate assembly in accordance with a preferred embodiment of the present invention.[0011]
- FIG. 6 depicts a two-high integrated circuit module mounted to the two flexible circuit connectors depicted in FIG. 4 in accordance with a preferred embodiment of the present invention.[0012]
- FIG. 7 depicts a four-high stacked module devised in accordance with a preferred embodiment of the present invention.[0013]
- FIG. 1 depicts an exemplar integrated[0014]
circuit device 10 havingupper surface 11 andlower surface 13.Device 10 is an example of one type of the general class of devices commonly known in the art as chip-scale-packaged integrated circuits (“CSPs”). The present invention may employed with a wide variety of integrated circuit devices and is not, as those of skill in the art will understand, limited to devices having the profile depicted in FIG. 1. Further, although its preferred use is with plastic-bodied CSP devices, the invention provides advantages in mounting a variety of packaged integrated circuit devices in a wide variety of configurations including leaded and CSP topologies. - Exemplar[0015]
integrated circuit device 10 may include one or more integrated circuit die andbody 12 and a set of contacts14. The illustratedintegrated circuit device 10 has CSP ball contacts14 arrayed alongsurface 13 of itsbody 12. Typically, when integratedcircuit device 10 is a CSP device, CSP ball contacts14 are, as depicted, balls that are a mixture of tin and lead with a common relative composition of 63% tin and 37% lead. Such contacts typically have a melting point of about 183° C. Other contacts are sometimes found along a planar surface of integrated circuit devices and such other contacts may also be treated in accordance with the present invention where the opportunity arises as will be understood after gaining familiarity with the present disclosure. - In the depiction of FIG. 2, CSP ball contacts[0016]14 have been removed, leaving CSP pads16 arrayed along
lower surface 13. CSP pads16 will typically exhibit a residual thin layer of tin/lead mixture after removal of CSP ball contacts14. As those of skill will know, CSPs may be received without attached balls and the process and structures described herein will then not require “removal” of balls. Further, embodiments of the present invention may be implemented with CSPs already bearing ball contacts comprised of high temperature solders. - FIG. 3 depicts[0017]
exemplar substrate 18 on which are disposedcontacts 20.Substrate 18 is depicted as a rigid board such as a PWB or PCB such as are known in the art. In accordance with a preferred embodiment of the present invention, asolder paste 22 is applied tosubstrate contacts 20. In accordance with an alternative preferred embodiment of the invention,solder paste 22 is applied to the CSP pads16 and not thesubstrate contacts 20. However, as those of skill will recognize,solder paste 22 may applied to bothsubstrate contacts 20 and CSP pads16 (or a set of contacts of other configuration when devices that are not CSP are used in accordance with the invention.) As those of skill understand, solder paste is a mixture of solder particles and flux. - Two or more of the elements lead, tin, silver, copper, antimony or indium may be employed in a variety of combinations to devise a solder to be employed in[0018]
solder paste 22 in accordance with the present invention. Therefore, in accordance with preferred embodiments of the present invention, a solder alloy employed insolder paste 22 exhibits a melting point equal to or greater than 235° C. and, preferably between 235° C. and 312° C. The alloy chosen should not have a melting point so high that the IC package is adversely affected, but it should also not be so low as to remelt during board assembly operations. - Some market participants are starting to implement lead-free solders. Such lead-free solders will typically have melting points higher than those found in lead inclusive solders. Typically, those who use lead-free solders to populate boards with stacked modules will, for example, employ temperatures up to 240° C. in the process of attachment of stacked modules to boards. Consequently, a HT joint implemented with a lead-free alloy will, in conformity with preferred embodiments of the present invention, exhibit a melting point greater than those lead-free solders used to populate boards. Consequently, a preferred implementation of the HT joints of the present invention will have a melting point range of between 245° C. and 265° C. The lead-free solder alloy employed in such HT joints will be comprised of at least two of the following elements: tin, silver, copper, or indium.[0019]
- Preferably, an alloy used as a solder in the present invention will melt over a narrow temperature range. Disintegration of the module during board attachment or population will be less likely if the melt range is narrow. Most preferably, the top of the melting point range of the solder used in board attachment should be exceeded by 15° C. by the melting point of the solder used to manufacture the stacked module although in the case of lead-free solders, this is reduced to ameliorate issues that could arise from exposure of the package to high temperatures.[0020]
- The following combinations have been found to exhibit the following melting points, and the below recited combinations are merely a representative, but not exhaustive, list of examples of solder alloys appropriate for use in the present invention. As those of skill will recognize, these examples are instructive in selecting other preferred particular combinations of lead, tin, silver, copper, antimony, and indium that are readily employed to advantage in the present invention so as to arrive at alloys of at least two of the following solder elements: lead, tin, silver, copper, antimony, and indium that have in their combined mixture, a preferred melting point between 235° C. to 312° C. inclusive.[0021]
- a. A combination of 95% Sn and 5% Sb melts over a range of 235° C. to 240° C.[0022]
- b. A combination of 83% Pb and 10% Sb and 5% Sn and 2% Ag melts over a range of 237° C. to 247° C.[0023]
- c. A combination of 85% Pb and 10% Sb and 5% Sn melts over a range of 245° C. to 255° C.[0024]
- d. A combination of 90% Pb and 10% Sb melts over a range of 252° C. to 260° C.[0025]
- e. A combination of 92.5% Pb, 5% Sn and 2.5% Ag melts over a range of 287° C. to 296° C.[0026]
- f. A combination of 90% Pb and 10% Sn melts over a range of 275° C. to 302° C.[0027]
- g. A combination of 95% Pb and 5% Sn melts over a range of 308° C. to 312° C.[0028]
- h. A combination of 75% Pb and 25% Indium melts over a range of 240° C. to 260° C.[0029]
- Those of skill will note that solder alloys or mixtures may also be employed in embodiments of the present invention that exhibit melting points lower than 235° C., as would be exhibited for example with a 97% Sn and a 3% Sb alloy, but preferred embodiments will employ solder mixtures or alloys that melt between 235° C. and 312° C. inclusive.[0030]
- FIG. 4 depicts portions of two[0031]
flexible circuit connectors 24A and24B prepared for mounting of adevice 10 in accordance with a preferred embodiment of the present invention.Exemplar flex circuits 24A and24B may be simple flex circuitry or may exhibit the more sophisticated designs of flex circuitry such as those that would be constructed in accordance with the detailed descriptions provided in U.S. Patent Application Ser. No. 10/005,581 which has been made part of this application by incorporation by reference. For clarity of exposition, depictedflex circuits 24A and24B exhibit a singleconductive layer 26 and a firstouter layer 28.Conductive layer 26 is supported bysubstrate layer 30, which, in a preferred embodiment, is a polyimide.Outer layer 32 resides along the lower surface of theflex circuits 24A and24B. Optionalouter layers Windows 34 are created throughouter layer 32 andintermediate layer 30 to exposeflex contacts 36. - As depicted in FIG. 4,[0032]
solder paste 22 is applied to flexcontacts 36 which are demarked at the level ofconductive layer 26.Solder paste 22 may also alternatively or in addition, be applied to the CSP pads16 of a CSP.Windows 34 provide openings through which module contacts may be disposed in a later stacked module assembly step. Those of skill will recognize that the method of the present invention is applicable to a wide variety of substrates including solid PWB's, rigid flex, and flexible substrates such as flexible circuits, for example, and the substrate employed can be prepared in accordance with the present invention in a manner appropriate for the intended application. Where the invention is employed with rigid substrates such as a PWB, multilayer strategies and windowing in substrate layers are techniques which are useful in conjunction with the present invention, but not essential. - FIG. 5 depicts a device-substrate assembly in accordance with a preferred embodiment of the present invention as may be employed in the construction of a low profile stacked module. The features depicted in FIG. 5 are not drawn to scale, and show various features in an enlarged aspect for purposes of illustration. As shown, integrated[0033]
circuit device 10 is disposed uponflex circuits 24A and24B which have been, in a preferred embodiment of the method of the present invention, previously prepared as shown in earlier FIG. 4.Module contacts 40 have been appended to flexcircuits 24A and24B to provide connective facility for the device-flex combination whether as part of a stacked module or otherwise. - High temperature joint contacts[0034]38 (“HT joints”) are formed by the melting of the lead alloy in previously applied
solder paste 22 and the application of a selected heat range appropriate for the solder mixtures identified previously. Thus, HT joints38 will, after solidification, typically not re-melt unless exposed subsequently to such temperature ranges. The temperature range applied in this step of assembly will not typically be subsequently encountered in a later assembly operation such as, for example, the application of a stacked module to a DIMM board. Consequently, in one embodiment, the present invention is articulated as a stacked module having HT joints that is appended to a DIMM board with traditional lower melting point solder. - FIG. 6 depicts a two-high stacked module devised in accordance with a preferred embodiment of the present invention.[0035]
Stacked module 50 shown in FIG.6 includes lower integrated circuit device52 and upper integrated circuit device54. A stackedmodule 50 may be devised in accordance with the present invention that includes more than two packaged integrated circuit devices.Flex circuits module 50 may be implemented with a single flexible circuit connector. Further, the flexible circuit connectors employed in accordance with the invention may exhibit one or more conductive layers.Flex circuits flexible circuits flex circuits 24A and24B in FIG. 5) or may exhibit multiple conductive layers. Examples of other preferred flexible circuit structures are found in U.S. Application Ser. No. 10/005,581 which has been incorporated by reference and those of skill will readily appreciate how a variety of circuit structures may be employed in preferred embodiments. Further, the connective structures used to connect lower integrated circuit52 with upper integrated circuit54 need not literally be flexible circuit connectors but may be flexible in portions and rigid in other portions. - [0036]
HT contacts 38 are employed in the preferred embodiment of FIG. 6 to provide connective facility between the respective integrated circuits and contacts borne by theflex circuits module 50 will preferably present a lower profile than stacked modules created employing typical CSP contacts14 on each of the constituent integrated circuit packages employed in a stackedmodule 50. - FIG. 7 depicts[0037]
module 60 as having lower integrated circuit element52, upper IC element54, 3rdIC element58, and 4thIC element 62. When the present invention is employed between flex circuits in stacking multiple levels of CSPs, as for example in FIG. 7, some embodiments will present HT contacts that have minimal heights that do not cause appreciable separation between the flex circuitry associated IC52 and IC54, for example, or between IC54 andIC 62, for example. For such embodiments, the apparent height for illustrated HT joints39, particularly, that lie between respective layers of flex circuitry will be understood to be exaggerated in the depiction of FIG. 7. Three sets of flex circuitry pairs56A and56B are also shown but, as in other embodiments, the invention may be implemented with a variety of substrates including single flex circuits in place of the depicted pair and with flexible circuits that have one or plural conductive layers. - As shown, the HT joints provide connections between integrated circuit devices and substrates and the overall profile of[0038]
module 60 is reduced by use of the present invention that provides advantages in subsequent processing steps such as, for example, affixation ofmodule 60 to DIMM boards, for example. - To construct a stacked module in accordance with a preferred embodiment of the present invention, if present, ball contacts[0039]14 are removed from a CSP leaving CSP contacts16 that typically exhibit a residual layer of solder. A high temperature solder paste composed from a lead alloy or mixture that has a preferable melting point equal to or higher than 235° C. and preferably less than 312° C. is applied to
substrate contacts 20 of a substrate such as a flexible circuit and/or the substrate contacts to which it is to be mounted. The CSP is positioned to place the CSP pads16 andsubstrate contacts 22 in appropriate proximity. Heat is applied sufficient to melt the lead solder alloy ofsolder paste 22 thus forming HT joints38. The flexible circuit is positioned to place portions of the flexible circuit connector between the first CSP and a second CSP that is connected to the substrate with HT joints created using the process described for creating HT joints. - In understanding the present invention, it may be helpful to articulate the relative melting points in terms of variables to illustrate the relationships between the HT joints used to construct a stacked module and the solders used to populate a board with such a HT joint-implemented stacked module. In use in board population, the present invention will provide a stacked high module that is assembled using the HT joints that exhibit melting point ranges between X and Y degrees where X is less than Y. Attachment of the stacked module to a board is then implemented with a solder having a melting point between A and B degrees where A and B are less than X.[0040]
- Although the present invention has been described in detail, it will be apparent to those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.[0041]
Claims (32)
1. A stacked circuit module comprising:
a first integrated circuit element;
a second integrated circuit element;
a flexible circuit connector connecting the first and second integrated circuit elements, the first and second integrated circuits being connected to the flexible circuit connector by a plurality of high temperature joints, each of the plurality of high temperature joints having melting points between 232° C. and 312° C. inclusive.
2. A high temperature joint in a stacked circuit module in which a first integrated circuit element is disposed above a second integrated circuit element, the high temperature joint comprising:
an alloy comprised of lead and antimony having the proportion of no more than 95% tin and at least 5% antimony, the alloy having a melting point between 235° C. to 260° C.
3. A high temperature joint in a stacked circuit module in which a first integrated circuit element is disposed above a second integrated circuit element, the high temperature joint comprising:
an alloy comprised of lead and tin, the alloy having a melting point between 275° C. and 312° C.
4. A high temperature joint in a stacked circuit module in which a first integrated circuit element is disposed above a second integrated circuit element, the high temperature joint comprising:
an alloy comprised of lead, the alloy having a melting point of between 235° C. and 312° C.
5. A stacked circuit module comprising:
a first integrated circuit;
a second integrated circuit disposed above the first integrated circuit;
a flex circuit connecting the first and second integrated circuits, the first integrated circuit and the second integrated circuit being connected to the flex circuit through high temperature joints devised in accordance withclaim 4 and the flex circuit comprising;
first and second outer layers;
first and second conductive layers, between which there is an intermediate layer, the first and second conductive layers and the intermediate layer being interior to the first and second outer layers, the second conductive layer having demarked first and second flex contacts, the first flex contacts being accessible through first windows through the second outer layer and the second flex contacts being accessible through second windows through the first outer layer, the first conductive layer, and the intermediate layer.
6. The stacked circuit module ofclaim 5 in which the second flex contacts are accessible through module windows through the second outer layer.
7. The stacked circuit module ofclaim 5 in which the first and second conductive layers are metal.
8. The stacked circuit module ofclaim 5 in which selected ones of the first flex contacts are connected to selected ones of the second flex contacts.
9. The stacked circuit module ofclaim 5 in which selected ones of the first flex contacts are connected to the first conductive layer.
10. The stacked circuit module flex circuit ofclaim 7 in which the metal of the first and second conductive layers is alloy 110.
11. The flex circuit ofclaim 8 in which the connected selected ones of the first and second flex contacts are connected with traces.
12. The flex circuit ofclaim 5 in which selected ones of the first flex contacts and selected ones of the second flex contacts are connected to the first conductive layer with vias.
13. The flex circuit ofclaim 12 in which selected ones of the first flex contacts are connected to the first conductive layer with on-pad vias.
14. The flex circuit ofclaim 12 in which selected ones of the second flex contacts are connected to the first conductive layer with off-pad vias.
15. A stacked circuit module comprising:
a first flex circuit having first and second conductive layers;
a second flex circuit having first and second conductive layers;
a first integrated circuit element and a second integrated circuit element, each of the first and second integrated circuit elements being connected to the first flex circuit and the second flex circuit with solder joints having a melting point equal to or greater than 235° C.
16. A method of constructing a stacked circuit module comprising the steps of:
providing a first CSP having a plurality of ball contacts;
removing the plurality of ball contacts from the first CSP leaving a plurality of CSP pads on the first CSP;
providing a substrate having a plurality of substrate contacts;
applying a solder paste to the plurality of substrate contacts of the substrate, the solder paste being comprised of an alloy of lead having a melting point, the melting point being equal to or greater than 235° C.;
positioning the first CSP and the substrate relative to each other to place the CSP pads of the first CSP in contact with the substrate contacts of the substrate to which the solder paste has been applied;
heating the first CSP and the substrate to cause the temperature at the CSP contacts and substrate contacts to reach the melting point.
17. The method ofclaim 16 in which solder remains upon the plurality of CSP contacts after the removal of the ball contacts from the first CSP.
18. The method ofclaim 16 in which the substrate is a flexible circuit.
19. The method ofclaim 16 further comprising the step of connecting a second CSP to the substrate.
20. The method ofclaim 16 in which the substrate is a flexible circuit and further comprising the step of connecting a second CSP to the flexible circuit with an alloy of lead having a second CSP melting point equal to or greater than 235° C. and disposing the second CSP above the first CSP.
21. The method ofclaim 20 in which portions of the flexible circuit are disposed between the first and second CSPs.
22. A method of constructing a stacked circuit module comprising the steps of:
providing a first CSP having a plurality of ball contacts;
removing the plurality of ball contacts from the first CSP leaving a plurality of CSP pads on the first CSP;
providing a substrate having a plurality of substrate contacts;
applying a solder paste to the plurality of CSP pads, the solder paste being comprised of an alloy of lead having a melting point, the melting point being equal to or greater than 235° C.;
positioning the first CSP and the substrate relative to each other to place the CSP pads to which the solder paste has been applied in contact with the substrate contacts of the substrate;
heating the first CSP and the substrate to cause the temperature at the CSP contacts and substrate contacts to reach the melting point.
23. A circuit board to which is connected a stacked circuit module devised in accordance with claims16 or22.
24. The circuit board ofclaim 23 in which the stacked circuit module devised in accordance with claims16 or22 is connected to the board with a solder having a melting point below 235° C.
25. A stacked circuit module comprising:
a first integrated circuit;
a second integrated circuit in stacked disposition relative to the first integrated circuit;
a substrate through which the first and second integrated circuits are connected;
a plurality of high temperature joints that connect the first integrated circuit to the substrate and the second integrated circuit to the substrate, the high temperature joints each having a melting point greater than 230° C.
26. A high-density circuit module comprising:
a first CSP having first and second lateral sides and upper and lower major surfaces and a set of CSP pads along the lower major surface;
a second CSP having first and second lateral sides and upper and lower major surfaces and a set of CSP pads along the lower major surface, the first CSP being disposed above the second CSP;
a pair of flex circuits, each of which pair having a first conductive layer and a second conductive layer, both said conductive layers being interior to first and second outer layers, and demarcated at the second conductive layer of each flex circuit there being upper and lower flex contacts, the upper flex contacts being connected to the CSP pads of the first CSP with first high temperature joints and the lower flex contacts being connected to the CSP pads of the second CSP with second high temperature joints, the first and second high temperature joints each having melting points above 230° C.
27. The high-density circuit module ofclaim 26 in which:
a chip-enable module contact is connected to an enable lower flex contact that is connected to a chip select CSP pad of the first CSP.
28. The high-density circuit module ofclaim 27 in which the connection between the enable lower flex contact and the chip select CSP contact of the first CSP is through an enable connection at the first conductive layer.
29. The high-density circuit module ofclaim 26 in which a first one of the flex circuit pair is partially wrapped about the first lateral side of the second CSP and a second one of the flex circuit pair is partially wrapped about the second lateral side of the second CSP to dispose the upper flex contacts above the upper major surface of the second CSP and beneath the lower major surface of the first CSP.
30. The high-density circuit module ofclaim 26 in which the first CSP expresses an n-bit datapath and the second CSP expresses an n-bit datapath, each of the flex circuits of the flex circuit pair having supplemental lower flex contacts which, in combination with the lower flex contacts, provide connection for the set of module contacts and a set of supplemental module contacts to express a 2n-bit module datapath that combines the n-bit datapath expressed by the first CSP and the n-bit datapath expressed by the second CSP.
31. A method of populating a circuit board comprising the steps of:
obtaining a high-density circuit module comprised of: two or more packaged integrated circuits;
a flexible circuit for connection between the two or more packaged integrated circuits, the connection between the two or more packaged integrated circuits being implemented through HT joints, the HT joints having a melting point range of between X and Y degrees Centigrade, where X is less than Y;
attaching the high-density circuit module to the circuit board with solder joints, the solder joints having a melting point range of between A and B degrees Centigrade, where A is less than B and A and B are both less than X.
32. A method of populating a circuit board comprising the steps of:
constructing a high-density circuit module having two or more integrated circuits with one integrated circuit disposed above another, the construction being implemented with a first solder having a melting point of X degrees; and
attaching the stacked circuit module to a circuit board with a second solder having a melting point of Y degrees where Y is less than X.
Priority Applications (16)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/457,608US20030234443A1 (en) | 2001-10-26 | 2003-06-09 | Low profile stacking system and method |
| US10/631,886US7026708B2 (en) | 2001-10-26 | 2003-07-14 | Low profile chip scale stacking system and method |
| PCT/US2004/016347WO2004112128A2 (en) | 2003-06-09 | 2004-05-25 | Low profile stacking system and method |
| US10/873,847US7094632B2 (en) | 2001-10-26 | 2004-06-22 | Low profile chip scale stacking system and method |
| US11/011,469US7180167B2 (en) | 2001-10-26 | 2004-12-14 | Low profile stacking system and method |
| US11/263,627US7656678B2 (en) | 2001-10-26 | 2005-10-31 | Stacked module systems |
| US11/403,081US20060255446A1 (en) | 2001-10-26 | 2006-04-12 | Stacked modules and method |
| US11/432,206US20080211077A1 (en) | 2001-10-26 | 2006-05-11 | Low profile chip scale stacking system and method |
| US11/626,316US20070117262A1 (en) | 2001-10-26 | 2007-01-23 | Low Profile Stacking System and Method |
| US11/626,318US20070114649A1 (en) | 2001-10-26 | 2007-01-23 | Low Profile Stacking System and Method |
| US11/873,355US20080120831A1 (en) | 2001-10-26 | 2007-10-16 | Stacked Modules and Method |
| US11/873,351US7719098B2 (en) | 2001-10-26 | 2007-10-16 | Stacked modules and method |
| US11/874,795US20080088032A1 (en) | 2001-10-26 | 2007-10-18 | Stacked Modules and Method |
| US11/874,775US20080090329A1 (en) | 2001-10-26 | 2007-10-18 | Stacked Modules and Method |
| US12/356,432US7626273B2 (en) | 2001-10-26 | 2009-01-20 | Low profile stacking system and method |
| US12/437,340US20090273069A1 (en) | 2001-10-26 | 2009-05-07 | Low profile chip scale stacking system and method |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/005,581US6576992B1 (en) | 2001-10-26 | 2001-10-26 | Chip scale stacking system and method |
| US10/457,608US20030234443A1 (en) | 2001-10-26 | 2003-06-09 | Low profile stacking system and method |
Related Parent Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/005,581Continuation-In-PartUS6576992B1 (en) | 2001-10-26 | 2001-10-26 | Chip scale stacking system and method |
| US10/453,398Continuation-In-PartUS6914324B2 (en) | 2001-10-26 | 2003-06-03 | Memory expansion and chip scale stacking system and method |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/631,886Continuation-In-PartUS7026708B2 (en) | 2001-10-26 | 2003-07-14 | Low profile chip scale stacking system and method |
| US11/011,469DivisionUS7180167B2 (en) | 2001-10-26 | 2004-12-14 | Low profile stacking system and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US20030234443A1true US20030234443A1 (en) | 2003-12-25 |
Family
ID=34713105
Family Applications (5)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/457,608AbandonedUS20030234443A1 (en) | 2001-10-26 | 2003-06-09 | Low profile stacking system and method |
| US11/011,469Expired - Fee RelatedUS7180167B2 (en) | 2001-10-26 | 2004-12-14 | Low profile stacking system and method |
| US11/626,316AbandonedUS20070117262A1 (en) | 2001-10-26 | 2007-01-23 | Low Profile Stacking System and Method |
| US11/626,318AbandonedUS20070114649A1 (en) | 2001-10-26 | 2007-01-23 | Low Profile Stacking System and Method |
| US12/356,432Expired - LifetimeUS7626273B2 (en) | 2001-10-26 | 2009-01-20 | Low profile stacking system and method |
Family Applications After (4)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US11/011,469Expired - Fee RelatedUS7180167B2 (en) | 2001-10-26 | 2004-12-14 | Low profile stacking system and method |
| US11/626,316AbandonedUS20070117262A1 (en) | 2001-10-26 | 2007-01-23 | Low Profile Stacking System and Method |
| US11/626,318AbandonedUS20070114649A1 (en) | 2001-10-26 | 2007-01-23 | Low Profile Stacking System and Method |
| US12/356,432Expired - LifetimeUS7626273B2 (en) | 2001-10-26 | 2009-01-20 | Low profile stacking system and method |
Country Status (1)
| Country | Link |
|---|---|
| US (5) | US20030234443A1 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060125067A1 (en)* | 2004-09-03 | 2006-06-15 | Staktek Group L.P. | Flex circuit constructions for high capacity circuit module systems and methods |
| US7442050B1 (en) | 2005-08-29 | 2008-10-28 | Netlist, Inc. | Circuit card with flexible connection for memory module with heat spreader |
| US7480152B2 (en)* | 2004-09-03 | 2009-01-20 | Entorian Technologies, Lp | Thin module system and method |
| US20090046431A1 (en)* | 2004-09-03 | 2009-02-19 | Staktek Group L.P. | High Capacity Thin Module System |
| US7511968B2 (en)* | 2004-09-03 | 2009-03-31 | Entorian Technologies, Lp | Buffered thin module system and method |
| US7619893B1 (en) | 2006-02-17 | 2009-11-17 | Netlist, Inc. | Heat spreader for electronic modules |
| US7630202B2 (en) | 2004-04-09 | 2009-12-08 | Netlist, Inc. | High density module having at least two substrates and at least one thermally conductive layer therebetween |
| US20110197438A1 (en)* | 2010-02-17 | 2011-08-18 | Masashi Kikuchii | Method of manufacturing semiconductor device |
| US8018723B1 (en) | 2008-04-30 | 2011-09-13 | Netlist, Inc. | Heat dissipation for electronic modules |
Families Citing this family (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7485951B2 (en)* | 2001-10-26 | 2009-02-03 | Entorian Technologies, Lp | Modularized die stacking system and method |
| US6576992B1 (en)* | 2001-10-26 | 2003-06-10 | Staktek Group L.P. | Chip scale stacking system and method |
| US7026708B2 (en)* | 2001-10-26 | 2006-04-11 | Staktek Group L.P. | Low profile chip scale stacking system and method |
| US6940729B2 (en)* | 2001-10-26 | 2005-09-06 | Staktek Group L.P. | Integrated circuit stacking system and method |
| US7656678B2 (en)* | 2001-10-26 | 2010-02-02 | Entorian Technologies, Lp | Stacked module systems |
| US7371609B2 (en)* | 2001-10-26 | 2008-05-13 | Staktek Group L.P. | Stacked module systems and methods |
| US7760513B2 (en)* | 2004-09-03 | 2010-07-20 | Entorian Technologies Lp | Modified core for circuit module system and method |
| US20060261449A1 (en)* | 2005-05-18 | 2006-11-23 | Staktek Group L.P. | Memory module system and method |
| US7289327B2 (en)* | 2006-02-27 | 2007-10-30 | Stakick Group L.P. | Active cooling methods and apparatus for modules |
| US7606040B2 (en)* | 2004-09-03 | 2009-10-20 | Entorian Technologies, Lp | Memory module system and method |
| US7542297B2 (en) | 2004-09-03 | 2009-06-02 | Entorian Technologies, Lp | Optimized mounting area circuit module system and method |
| US7446410B2 (en)* | 2004-09-03 | 2008-11-04 | Entorian Technologies, Lp | Circuit module with thermal casing systems |
| US20060053345A1 (en)* | 2004-09-03 | 2006-03-09 | Staktek Group L.P. | Thin module system and method |
| US7606049B2 (en)* | 2004-09-03 | 2009-10-20 | Entorian Technologies, Lp | Module thermal management system and method |
| US7579687B2 (en)* | 2004-09-03 | 2009-08-25 | Entorian Technologies, Lp | Circuit module turbulence enhancement systems and methods |
| US7324352B2 (en)* | 2004-09-03 | 2008-01-29 | Staktek Group L.P. | High capacity thin module system and method |
| US7522421B2 (en) | 2004-09-03 | 2009-04-21 | Entorian Technologies, Lp | Split core circuit module |
| US20060049513A1 (en)* | 2004-09-03 | 2006-03-09 | Staktek Group L.P. | Thin module system and method with thermal management |
| US7606050B2 (en)* | 2004-09-03 | 2009-10-20 | Entorian Technologies, Lp | Compact module system and method |
| US7423885B2 (en)* | 2004-09-03 | 2008-09-09 | Entorian Technologies, Lp | Die module system |
| US7468893B2 (en)* | 2004-09-03 | 2008-12-23 | Entorian Technologies, Lp | Thin module system and method |
| FR2889405B1 (en)* | 2005-07-29 | 2010-12-10 | Thales Sa | METHOD FOR ASSEMBLING ELECTRONIC COMPONENTS WITH BALL GRID CONTACTS, IN PARTICULAR ALLOY, SILVER AND COPPER, AND PROCESS FOR PRODUCING SUCH COMPONENTS |
| US7511969B2 (en)* | 2006-02-02 | 2009-03-31 | Entorian Technologies, Lp | Composite core circuit module system and method |
| KR100780691B1 (en)* | 2006-03-29 | 2007-11-30 | 주식회사 하이닉스반도체 | Folding Chip Planar Stack Package |
| US8031475B2 (en)* | 2007-07-12 | 2011-10-04 | Stats Chippac, Ltd. | Integrated circuit package system with flexible substrate and mounded package |
| US8278141B2 (en)* | 2008-06-11 | 2012-10-02 | Stats Chippac Ltd. | Integrated circuit package system with internal stacking module |
| TWI406376B (en)* | 2010-06-15 | 2013-08-21 | Powertech Technology Inc | Semiconductor chip package |
| US8884420B1 (en)* | 2013-07-12 | 2014-11-11 | Infineon Technologies Austria Ag | Multichip device |
| JP6513465B2 (en)* | 2015-04-24 | 2019-05-15 | 日本航空電子工業株式会社 | Lead connection structure |
| CN111093316B (en)* | 2018-10-24 | 2021-08-24 | 鹏鼎控股(深圳)股份有限公司 | Circuit board and manufacturing method thereof |
| US10999938B1 (en)* | 2020-04-29 | 2021-05-04 | Raytheon Company | Method of wire bonding a first and second circuit card |
| US12266629B2 (en) | 2021-02-05 | 2025-04-01 | Raytheon Company | Ball bond impedance matching |
Citations (61)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3654394A (en)* | 1969-07-08 | 1972-04-04 | Gordon Eng Co | Field effect transistor switch, particularly for multiplexing |
| US4513368A (en)* | 1981-05-22 | 1985-04-23 | Data General Corporation | Digital data processing system having object-based logical memory addressing and self-structuring modular memory |
| US4645944A (en)* | 1983-09-05 | 1987-02-24 | Matsushita Electric Industrial Co., Ltd. | MOS register for selecting among various data inputs |
| US4654944A (en)* | 1985-09-13 | 1987-04-07 | Graf Richard W | Overhead cam valve spring compressor adapter |
| US4763188A (en)* | 1986-08-08 | 1988-08-09 | Thomas Johnson | Packaging system for multiple semiconductor devices |
| US4985703A (en)* | 1988-02-03 | 1991-01-15 | Nec Corporation | Analog multiplexer |
| US5117282A (en)* | 1990-10-29 | 1992-05-26 | Harris Corporation | Stacked configuration for integrated circuit devices |
| US5224023A (en)* | 1992-02-10 | 1993-06-29 | Smith Gary W | Foldable electronic assembly module |
| US5239198A (en)* | 1989-09-06 | 1993-08-24 | Motorola, Inc. | Overmolded semiconductor device having solder ball and edge lead connective structure |
| US5289062A (en)* | 1991-03-18 | 1994-02-22 | Quality Semiconductor, Inc. | Fast transmission gate switch |
| US5428190A (en)* | 1993-07-02 | 1995-06-27 | Sheldahl, Inc. | Rigid-flex board with anisotropic interconnect and method of manufacture |
| US5448511A (en)* | 1994-06-01 | 1995-09-05 | Storage Technology Corporation | Memory stack with an integrated interconnect and mounting structure |
| US5523695A (en)* | 1994-08-26 | 1996-06-04 | Vlsi Technology, Inc. | Universal test socket for exposing the active surface of an integrated circuit in a die-down package |
| US5642055A (en)* | 1990-02-14 | 1997-06-24 | Particle Interconnect, Inc. | Electrical interconnect using particle enhanced joining of metal surfaces |
| US5764497A (en)* | 1995-11-13 | 1998-06-09 | Minolta Co, Ltd. | Circuit board connection method and connection structure |
| US5776797A (en)* | 1995-12-22 | 1998-07-07 | Fairchild Space And Defense Corporation | Three-dimensional flexible assembly of integrated circuits |
| US5917709A (en)* | 1997-06-16 | 1999-06-29 | Eastman Kodak Company | Multiple circuit board assembly having an interconnect mechanism that includes a flex connector |
| US5949657A (en)* | 1997-12-01 | 1999-09-07 | Karabatsos; Chris | Bottom or top jumpered foldable electronic assembly |
| US5953215A (en)* | 1997-12-01 | 1999-09-14 | Karabatsos; Chris | Apparatus and method for improving computer memory speed and capacity |
| US6028365A (en)* | 1998-03-30 | 2000-02-22 | Micron Technology, Inc. | Integrated circuit package and method of fabrication |
| US6072233A (en)* | 1998-05-04 | 2000-06-06 | Micron Technology, Inc. | Stackable ball grid array package |
| US6097087A (en)* | 1997-10-31 | 2000-08-01 | Micron Technology, Inc. | Semiconductor package including flex circuit, interconnects and dense array external contacts |
| US6121676A (en)* | 1996-12-13 | 2000-09-19 | Tessera, Inc. | Stacked microelectronic assembly and method therefor |
| US6208521B1 (en)* | 1997-05-19 | 2001-03-27 | Nitto Denko Corporation | Film carrier and laminate type mounting structure using same |
| US6222737B1 (en)* | 1999-04-23 | 2001-04-24 | Dense-Pac Microsystems, Inc. | Universal package and method of forming the same |
| US6233650B1 (en)* | 1998-04-01 | 2001-05-15 | Intel Corporation | Using FET switches for large memory arrays |
| US6266252B1 (en)* | 1997-12-01 | 2001-07-24 | Chris Karabatsos | Apparatus and method for terminating a computer memory bus |
| US6265660B1 (en)* | 1997-07-09 | 2001-07-24 | Micron Technology, Inc. | Package stack via bottom leaded plastic (BLP) packaging |
| US6281577B1 (en)* | 1996-06-28 | 2001-08-28 | Pac Tech-Packaging Technologies Gmbh | Chips arranged in plurality of planes and electrically connected to one another |
| US6300679B1 (en)* | 1998-06-01 | 2001-10-09 | Semiconductor Components Industries, Llc | Flexible substrate for packaging a semiconductor component |
| US20010040793A1 (en)* | 2000-02-01 | 2001-11-15 | Tetsuya Inaba | Electronic device and method of producing the same |
| US6323060B1 (en)* | 1999-05-05 | 2001-11-27 | Dense-Pac Microsystems, Inc. | Stackable flex circuit IC package and method of making same |
| US20020006032A1 (en)* | 2000-05-23 | 2002-01-17 | Chris Karabatsos | Low-profile registered DIMM |
| US6351029B1 (en)* | 1999-05-05 | 2002-02-26 | Harlan R. Isaak | Stackable flex circuit chip package and method of making same |
| US6376769B1 (en)* | 1999-05-18 | 2002-04-23 | Amerasia International Technology, Inc. | High-density electronic package, and method for making same |
| US6392162B1 (en)* | 2000-11-10 | 2002-05-21 | Chris Karabatsos | Double-sided flexible jumper assembly and method of manufacture |
| US6410857B1 (en)* | 2001-03-01 | 2002-06-25 | Lockheed Martin Corporation | Signal cross-over interconnect for a double-sided circuit card assembly |
| US20020101261A1 (en)* | 2001-02-01 | 2002-08-01 | Chris Karabatsos | Tri-directional, high-speed bus switch |
| US6433418B1 (en)* | 1998-07-24 | 2002-08-13 | Fujitsu Limited | Apparatus for a vertically accumulable semiconductor device with external leads secured by a positioning mechanism |
| US6444921B1 (en)* | 2000-02-03 | 2002-09-03 | Fujitsu Limited | Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like |
| US6446158B1 (en)* | 1999-05-17 | 2002-09-03 | Chris Karabatsos | Memory system using FET switches to select memory banks |
| US20020139577A1 (en)* | 2001-03-27 | 2002-10-03 | Miller Charles A. | In-street integrated circuit wafer via |
| US6462412B2 (en)* | 2000-01-18 | 2002-10-08 | Sony Corporation | Foldable, flexible laminate type semiconductor apparatus with reinforcing and heat-radiating plates |
| US6465893B1 (en)* | 1990-09-24 | 2002-10-15 | Tessera, Inc. | Stacked chip assembly |
| US20020164838A1 (en)* | 2001-05-02 | 2002-11-07 | Moon Ow Chee | Flexible ball grid array chip scale packages and methods of fabrication |
| US6486544B1 (en)* | 1998-09-09 | 2002-11-26 | Seiko Epson Corporation | Semiconductor device and method manufacturing the same, circuit board, and electronic instrument |
| US20020180022A1 (en)* | 1999-10-20 | 2002-12-05 | Seiko Epson Corporation | Semiconductor device |
| US6552910B1 (en)* | 2000-06-28 | 2003-04-22 | Micron Technology, Inc. | Stacked-die assemblies with a plurality of microelectronic devices and methods of manufacture |
| US6560117B2 (en)* | 2000-06-28 | 2003-05-06 | Micron Technology, Inc. | Packaged microelectronic die assemblies and methods of manufacture |
| US6572387B2 (en)* | 1999-09-24 | 2003-06-03 | Staktek Group, L.P. | Flexible circuit connector for stacked chip module |
| US6590282B1 (en)* | 2002-04-12 | 2003-07-08 | Industrial Technology Research Institute | Stacked semiconductor package formed on a substrate and method for fabrication |
| US6600222B1 (en)* | 2002-07-17 | 2003-07-29 | Intel Corporation | Stacked microelectronic packages |
| US6614664B2 (en)* | 2000-10-24 | 2003-09-02 | Samsung Electronics Co., Ltd. | Memory module having series-connected printed circuit boards |
| US20030168725A1 (en)* | 1996-12-13 | 2003-09-11 | Tessera, Inc. | Methods of making microelectronic assemblies including folded substrates |
| US6620651B2 (en)* | 2001-10-23 | 2003-09-16 | National Starch And Chemical Investment Holding Corporation | Adhesive wafers for die attach application |
| US6627984B2 (en)* | 2001-07-24 | 2003-09-30 | Dense-Pac Microsystems, Inc. | Chip stack with differing chip package types |
| US6660561B2 (en)* | 2000-06-15 | 2003-12-09 | Dpac Technologies Corp. | Method of assembling a stackable integrated circuit chip |
| US6677670B2 (en)* | 2000-04-25 | 2004-01-13 | Seiko Epson Corporation | Semiconductor device |
| US6683377B1 (en)* | 2000-05-30 | 2004-01-27 | Amkor Technology, Inc. | Multi-stacked memory package |
| US20040021211A1 (en)* | 2002-08-05 | 2004-02-05 | Tessera, Inc. | Microelectronic adaptors, assemblies and methods |
| US20040150107A1 (en)* | 2002-12-31 | 2004-08-05 | Cha Ki Bon | Stack package and fabricating method thereof |
Family Cites Families (292)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3411122A (en) | 1966-01-13 | 1968-11-12 | Ibm | Electrical resistance element and method of fabricating |
| US3436604A (en) | 1966-04-25 | 1969-04-01 | Texas Instruments Inc | Complex integrated circuit array and method for fabricating same |
| US3436804A (en)* | 1968-04-23 | 1969-04-08 | Olin Mathieson | Process for forming composite aluminum alloy |
| US3772776A (en) | 1969-12-03 | 1973-11-20 | Thomas & Betts Corp | Method of interconnecting memory plane boards |
| US3727064A (en) | 1971-03-17 | 1973-04-10 | Monsanto Co | Opto-isolator devices and method for the fabrication thereof |
| US3746934A (en) | 1971-05-06 | 1973-07-17 | Siemens Ag | Stack arrangement of semiconductor chips |
| US3766439A (en) | 1972-01-12 | 1973-10-16 | Gen Electric | Electronic module using flexible printed circuit board with heat sink means |
| US3806767A (en)* | 1973-03-15 | 1974-04-23 | Tek Wave Inc | Interboard connector |
| US3983547A (en) | 1974-06-27 | 1976-09-28 | International Business Machines - Ibm | Three-dimensional bubble device |
| US4079511A (en) | 1976-07-30 | 1978-03-21 | Amp Incorporated | Method for packaging hermetically sealed integrated circuit chips on lead frames |
| US4103318A (en) | 1977-05-06 | 1978-07-25 | Ford Motor Company | Electronic multichip module |
| US4288841A (en) | 1979-09-20 | 1981-09-08 | Bell Telephone Laboratories, Incorporated | Double cavity semiconductor chip carrier |
| US4381421A (en)* | 1980-07-01 | 1983-04-26 | Tektronix, Inc. | Electromagnetic shield for electronic equipment |
| US4398235A (en) | 1980-09-11 | 1983-08-09 | General Motors Corporation | Vertical integrated circuit package integration |
| US4437235A (en) | 1980-12-29 | 1984-03-20 | Honeywell Information Systems Inc. | Integrated circuit package |
| JPS57181146A (en) | 1981-04-30 | 1982-11-08 | Hitachi Ltd | Resin-sealed semiconductor device |
| US4406508A (en) | 1981-07-02 | 1983-09-27 | Thomas & Betts Corporation | Dual-in-line package assembly |
| US4420794A (en) | 1981-09-10 | 1983-12-13 | Research, Incorporated | Integrated circuit switch |
| US4712129A (en) | 1983-12-12 | 1987-12-08 | Texas Instruments Incorporated | Integrated circuit device with textured bar cover |
| KR890004820B1 (en) | 1984-03-28 | 1989-11-27 | 인터내셔널 비지네스 머신즈 코포레이션 | Memory module and board with double storage density and method of forming the same |
| US4587596A (en) | 1984-04-09 | 1986-05-06 | Amp Incorporated | High density mother/daughter circuit board connector |
| EP0213205B1 (en) | 1984-12-28 | 1992-12-09 | Micro Co., Ltd. | Method of stacking printed circuit boards |
| EP0218796B1 (en) | 1985-08-16 | 1990-10-31 | Dai-Ichi Seiko Co. Ltd. | Semiconductor device comprising a plug-in-type package |
| US4696525A (en) | 1985-12-13 | 1987-09-29 | Amp Incorporated | Socket for stacking integrated circuit packages |
| US4722691A (en) | 1986-02-03 | 1988-02-02 | General Motors Corporation | Header assembly for a printed circuit board |
| JPS62162891U (en)* | 1986-04-03 | 1987-10-16 | ||
| US4839717A (en) | 1986-12-19 | 1989-06-13 | Fairchild Semiconductor Corporation | Ceramic package for high frequency semiconductor devices |
| US4821007A (en) | 1987-02-06 | 1989-04-11 | Tektronix, Inc. | Strip line circuit component and method of manufacture |
| US5159535A (en) | 1987-03-11 | 1992-10-27 | International Business Machines Corporation | Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate |
| US4862249A (en) | 1987-04-17 | 1989-08-29 | Xoc Devices, Inc. | Packaging system for stacking integrated circuits |
| US4855810A (en) | 1987-06-02 | 1989-08-08 | Gelb Allan S | Thermoelectric heat pump |
| IT1214254B (en) | 1987-09-23 | 1990-01-10 | Sgs Microelettonica S P A | SEMICONDUCTOR DEVICE IN PLASTIC OR CERAMIC CONTAINER WITH "CHIPS" FIXED ON BOTH SIDES OF THE CENTRAL ISLAND OF THE "FRAME". |
| US5016138A (en) | 1987-10-27 | 1991-05-14 | Woodman John K | Three dimensional integrated circuit package |
| US4983533A (en) | 1987-10-28 | 1991-01-08 | Irvine Sensors Corporation | High-density electronic modules - process and product |
| US5198888A (en) | 1987-12-28 | 1993-03-30 | Hitachi, Ltd. | Semiconductor stacked device |
| US4833568A (en) | 1988-01-29 | 1989-05-23 | Berhold G Mark | Three-dimensional circuit component assembly and method corresponding thereto |
| US4891789A (en) | 1988-03-03 | 1990-01-02 | Bull Hn Information Systems, Inc. | Surface mounted multilayer memory printed circuit board |
| US5138434A (en) | 1991-01-22 | 1992-08-11 | Micron Technology, Inc. | Packaging for semiconductor logic devices |
| US4911643A (en) | 1988-10-11 | 1990-03-27 | Beta Phase, Inc. | High density and high signal integrity connector |
| US4956694A (en) | 1988-11-04 | 1990-09-11 | Dense-Pac Microsystems, Inc. | Integrated circuit chip stacking |
| WO1990006609A1 (en) | 1988-11-16 | 1990-06-14 | Motorola, Inc. | Flexible substrate electronic assembly |
| EP0382203B1 (en) | 1989-02-10 | 1995-04-26 | Fujitsu Limited | Ceramic package type semiconductor device and method of assembling the same |
| DE69006609T2 (en) | 1989-03-15 | 1994-06-30 | Ngk Insulators Ltd | Ceramic lid for closing a semiconductor element and method for closing a semiconductor element in a ceramic package. |
| JP2647194B2 (en) | 1989-04-17 | 1997-08-27 | 住友電気工業株式会社 | Semiconductor package sealing method |
| US4953060A (en) | 1989-05-05 | 1990-08-28 | Ncr Corporation | Stackable integrated circuit chip package with improved heat removal |
| US5104820A (en) | 1989-07-07 | 1992-04-14 | Irvine Sensors Corporation | Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting |
| US5057903A (en) | 1989-07-17 | 1991-10-15 | Microelectronics And Computer Technology Corporation | Thermal heat sink encapsulated integrated circuit |
| DE68925727T2 (en)* | 1989-09-15 | 1996-07-04 | Hewlett Packard Gmbh | Method for determining the optimal working conditions in an electrochemical detector and electrochemical detector using this method |
| US5068708A (en) | 1989-10-02 | 1991-11-26 | Advanced Micro Devices, Inc. | Ground plane for plastic encapsulated integrated circuit die packages |
| US5012323A (en) | 1989-11-20 | 1991-04-30 | Micron Technology, Inc. | Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe |
| US5229641A (en) | 1989-11-25 | 1993-07-20 | Hitachi Maxell, Ltd. | Semiconductor card and manufacturing method therefor |
| US5041902A (en) | 1989-12-14 | 1991-08-20 | Motorola, Inc. | Molded electronic package with compression structures |
| JPH03227541A (en) | 1990-02-01 | 1991-10-08 | Hitachi Ltd | Semiconductor device |
| US5041015A (en) | 1990-03-30 | 1991-08-20 | Cal Flex, Inc. | Electrical jumper assembly |
| US5345205A (en) | 1990-04-05 | 1994-09-06 | General Electric Company | Compact high density interconnected microwave system |
| US5261068A (en) | 1990-05-25 | 1993-11-09 | Dell Usa L.P. | Dual path memory retrieval system for an interleaved dynamic RAM memory unit |
| US5050039A (en) | 1990-06-26 | 1991-09-17 | Digital Equipment Corporation | Multiple circuit chip mounting and cooling arrangement |
| CA2022304C (en)* | 1990-07-30 | 1994-04-26 | Jonathan Willner | Miniaturized ground fault circuit interrupter |
| US5446620A (en) | 1990-08-01 | 1995-08-29 | Staktek Corporation | Ultra high density integrated circuit packages |
| US5475920A (en) | 1990-08-01 | 1995-12-19 | Burns; Carmen D. | Method of assembling ultra high density integrated circuit packages |
| US5377077A (en) | 1990-08-01 | 1994-12-27 | Staktek Corporation | Ultra high density integrated circuit packages method and apparatus |
| US5499160A (en) | 1990-08-01 | 1996-03-12 | Staktek Corporation | High density integrated circuit module with snap-on rail assemblies |
| EP0509065A1 (en) | 1990-08-01 | 1992-10-21 | Staktek Corporation | Ultra high density integrated circuit packages, method and apparatus |
| US5852326A (en) | 1990-09-24 | 1998-12-22 | Tessera, Inc. | Face-up semiconductor chip assembly |
| JP3242101B2 (en) | 1990-10-05 | 2001-12-25 | 三菱電機株式会社 | Semiconductor integrated circuit |
| JPH04162556A (en) | 1990-10-25 | 1992-06-08 | Mitsubishi Electric Corp | Lead frame and its manufacturing method |
| US5289346A (en)* | 1991-02-26 | 1994-02-22 | Microelectronics And Computer Technology Corporation | Peripheral to area adapter with protective bumper for an integrated circuit chip |
| JPH04284661A (en) | 1991-03-13 | 1992-10-09 | Toshiba Corp | Semiconductor device |
| US5219794A (en) | 1991-03-14 | 1993-06-15 | Hitachi, Ltd. | Semiconductor integrated circuit device and method of fabricating same |
| US5099393A (en) | 1991-03-25 | 1992-03-24 | International Business Machines Corporation | Electronic package for high density applications |
| US5158912A (en) | 1991-04-09 | 1992-10-27 | Digital Equipment Corporation | Integral heatsink semiconductor package |
| US5138430A (en) | 1991-06-06 | 1992-08-11 | International Business Machines Corporation | High performance versatile thermally enhanced IC chip mounting |
| JPH0513666A (en) | 1991-06-29 | 1993-01-22 | Sony Corp | Complex semiconductor device |
| US5214307A (en) | 1991-07-08 | 1993-05-25 | Micron Technology, Inc. | Lead frame for semiconductor devices having improved adhesive bond line control |
| US5311401A (en) | 1991-07-09 | 1994-05-10 | Hughes Aircraft Company | Stacked chip assembly and manufacturing method therefor |
| US5252857A (en) | 1991-08-05 | 1993-10-12 | International Business Machines Corporation | Stacked DCA memory chips |
| US5448450A (en) | 1991-08-15 | 1995-09-05 | Staktek Corporation | Lead-on-chip integrated circuit apparatus |
| JP2967621B2 (en) | 1991-08-27 | 1999-10-25 | 日本電気株式会社 | Method of manufacturing package for semiconductor device |
| US5168926A (en) | 1991-09-25 | 1992-12-08 | Intel Corporation | Heat sink design integrating interface material |
| IT1252136B (en) | 1991-11-29 | 1995-06-05 | St Microelectronics Srl | SEMICONDUCTOR DEVICE STRUCTURE WITH METALLIC DISSIPATOR AND PLASTIC BODY, WITH MEANS FOR AN ELECTRICAL CONNECTION TO THE HIGH RELIABILITY DISSIPATOR |
| US5281852A (en) | 1991-12-10 | 1994-01-25 | Normington Peter J C | Semiconductor device including stacked die |
| US5397916A (en) | 1991-12-10 | 1995-03-14 | Normington; Peter J. C. | Semiconductor device including stacked die |
| US5198965A (en) | 1991-12-18 | 1993-03-30 | International Business Machines Corporation | Free form packaging of specific functions within a computer system |
| US5919231A (en) | 1992-01-10 | 1999-07-06 | Hansa Medical Products, Inc. | Delivery system for voice prosthesis |
| US5241454A (en) | 1992-01-22 | 1993-08-31 | International Business Machines Corporation | Mutlilayered flexible circuit package |
| US5262927A (en) | 1992-02-07 | 1993-11-16 | Lsi Logic Corporation | Partially-molded, PCB chip carrier package |
| US5243133A (en) | 1992-02-18 | 1993-09-07 | International Business Machines, Inc. | Ceramic chip carrier with lead frame or edge clip |
| US5222014A (en) | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
| US5229916A (en) | 1992-03-04 | 1993-07-20 | International Business Machines Corporation | Chip edge interconnect overlay element |
| US5259770A (en) | 1992-03-19 | 1993-11-09 | Amp Incorporated | Impedance controlled elastomeric connector |
| US5438224A (en) | 1992-04-23 | 1995-08-01 | Motorola, Inc. | Integrated circuit package having a face-to-face IC chip arrangement |
| US5361228A (en) | 1992-04-30 | 1994-11-01 | Fuji Photo Film Co., Ltd. | IC memory card system having a common data and address bus |
| MY109101A (en)* | 1992-05-25 | 1996-12-31 | Hitachi Ltd | Thin type semiconductor device, module structure using the device and method of mounting the device on board |
| US5247423A (en) | 1992-05-26 | 1993-09-21 | Motorola, Inc. | Stacking three dimensional leadless multi-chip module and method for making the same |
| EP0597087B1 (en)* | 1992-06-02 | 1999-07-28 | Hewlett-Packard Company | Computer-aided design method for multilevel interconnect technologies |
| US5343366A (en) | 1992-06-24 | 1994-08-30 | International Business Machines Corporation | Packages for stacked integrated circuit chip cubes |
| US5702985A (en) | 1992-06-26 | 1997-12-30 | Staktek Corporation | Hermetically sealed ceramic integrated circuit heat dissipating package fabrication method |
| US5804870A (en) | 1992-06-26 | 1998-09-08 | Staktek Corporation | Hermetically sealed integrated circuit lead-on package configuration |
| US5729894A (en) | 1992-07-21 | 1998-03-24 | Lsi Logic Corporation | Method of assembling ball bump grid array semiconductor packages |
| US5854534A (en) | 1992-08-05 | 1998-12-29 | Fujitsu Limited | Controlled impedence interposer substrate |
| US5432630A (en) | 1992-09-11 | 1995-07-11 | Motorola, Inc. | Optical bus with optical transceiver modules and method of manufacture |
| JP3105089B2 (en) | 1992-09-11 | 2000-10-30 | 株式会社東芝 | Semiconductor device |
| US5731633A (en) | 1992-09-16 | 1998-03-24 | Gary W. Hamilton | Thin multichip module |
| US5402006A (en) | 1992-11-10 | 1995-03-28 | Texas Instruments Incorporated | Semiconductor device with enhanced adhesion between heat spreader and leads and plastic mold compound |
| US5313097A (en) | 1992-11-16 | 1994-05-17 | International Business Machines, Corp. | High density memory module |
| US5375041A (en) | 1992-12-02 | 1994-12-20 | Intel Corporation | Ra-tab array bump tab tape based I.C. package |
| US5347428A (en) | 1992-12-03 | 1994-09-13 | Irvine Sensors Corporation | Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip |
| US6205654B1 (en) | 1992-12-11 | 2001-03-27 | Staktek Group L.P. | Method of manufacturing a surface mount package |
| US5484959A (en) | 1992-12-11 | 1996-01-16 | Staktek Corporation | High density lead-on-package fabrication method and apparatus |
| US5455740A (en) | 1994-03-07 | 1995-10-03 | Staktek Corporation | Bus communication system for stacked high density integrated circuit packages |
| US5801437A (en) | 1993-03-29 | 1998-09-01 | Staktek Corporation | Three-dimensional warp-resistant integrated circuit module method and apparatus |
| US5541812A (en) | 1995-05-22 | 1996-07-30 | Burns; Carmen D. | Bus communication system for stacked high density integrated circuit packages having an intermediate lead frame |
| US5644161A (en) | 1993-03-29 | 1997-07-01 | Staktek Corporation | Ultra-high density warp-resistant memory module |
| US5384690A (en)* | 1993-07-27 | 1995-01-24 | International Business Machines Corporation | Flex laminate package for a parallel processor |
| US5396573A (en)* | 1993-08-03 | 1995-03-07 | International Business Machines Corporation | Pluggable connectors for connecting large numbers of electrical and/or optical cables to a module through a seal |
| US5337388A (en) | 1993-08-03 | 1994-08-09 | International Business Machines Corporation | Matrix of pluggable connectors for connecting large numbers of clustered electrical and/or opticcal cables to a module |
| US5386341A (en) | 1993-11-01 | 1995-01-31 | Motorola, Inc. | Flexible substrate folded in a U-shape with a rigidizer plate located in the notch of the U-shape |
| US5523619A (en) | 1993-11-03 | 1996-06-04 | International Business Machines Corporation | High density memory structure |
| KR970000214B1 (en) | 1993-11-18 | 1997-01-06 | 삼성전자 주식회사 | Semiconductor device and method of producing the same |
| US5477082A (en) | 1994-01-11 | 1995-12-19 | Exponential Technology, Inc. | Bi-planar multi-chip module |
| US5744627A (en)* | 1994-01-28 | 1998-04-28 | Prolinx, Inc. | Boronic compound complexing reagents and complexes |
| US5502333A (en) | 1994-03-30 | 1996-03-26 | International Business Machines Corporation | Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit |
| JPH088389A (en) | 1994-04-20 | 1996-01-12 | Fujitsu Ltd | Semiconductor device and semiconductor device unit |
| JPH07312469A (en)* | 1994-05-16 | 1995-11-28 | Nippon Mektron Ltd | Structure of bent part of multilayer flexible circuit board |
| US5509197A (en)* | 1994-06-10 | 1996-04-23 | Xetel Corporation | Method of making substrate edge connector |
| US5644839A (en) | 1994-06-10 | 1997-07-08 | Xetel Corporation | Surface mountable substrate edge terminal |
| KR970005644B1 (en) | 1994-09-03 | 1997-04-18 | 삼성전자 주식회사 | Multi-block erase and verify device and method of non-volatile semiconductor memory device |
| JP2570628B2 (en) | 1994-09-21 | 1997-01-08 | 日本電気株式会社 | Semiconductor package and manufacturing method thereof |
| KR0147259B1 (en) | 1994-10-27 | 1998-08-01 | 김광호 | Stack type semiconductor package and method for manufacturing the same |
| US5592364A (en) | 1995-01-24 | 1997-01-07 | Staktek Corporation | High density integrated circuit module with complex electrical interconnect rails |
| US5588205A (en) | 1995-01-24 | 1996-12-31 | Staktek Corporation | Method of manufacturing a high density integrated circuit module having complex electrical interconnect rails |
| US5514907A (en) | 1995-03-21 | 1996-05-07 | Simple Technology Incorporated | Apparatus for stacking semiconductor chips |
| US5612570A (en) | 1995-04-13 | 1997-03-18 | Dense-Pac Microsystems, Inc. | Chip stack and method of making same |
| JP2606177B2 (en)* | 1995-04-26 | 1997-04-30 | 日本電気株式会社 | Printed wiring board |
| US5657537A (en) | 1995-05-30 | 1997-08-19 | General Electric Company | Method for fabricating a stack of two dimensional circuit modules |
| US5872051A (en)* | 1995-08-02 | 1999-02-16 | International Business Machines Corporation | Process for transferring material to semiconductor chip conductive pads using a transfer substrate |
| US6025642A (en) | 1995-08-17 | 2000-02-15 | Staktek Corporation | Ultra high density integrated circuit packages |
| US5922061A (en) | 1995-10-20 | 1999-07-13 | Iq Systems | Methods and apparatus for implementing high speed data communications |
| US6002167A (en) | 1995-09-22 | 1999-12-14 | Hitachi Cable, Ltd. | Semiconductor device having lead on chip structure |
| SG45122A1 (en) | 1995-10-28 | 1998-01-16 | Inst Of Microelectronics | Low cost and highly reliable chip-sized package |
| US6013948A (en)* | 1995-11-27 | 2000-01-11 | Micron Technology, Inc. | Stackable chip scale semiconductor package with mating contacts on opposed surfaces |
| KR0184076B1 (en) | 1995-11-28 | 1999-03-20 | 김광호 | Three-dimensional stacked package |
| US5719440A (en) | 1995-12-19 | 1998-02-17 | Micron Technology, Inc. | Flip chip adaptor package for bare die |
| JPH09260568A (en) | 1996-03-27 | 1997-10-03 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method thereof |
| US5789815A (en) | 1996-04-23 | 1998-08-04 | Motorola, Inc. | Three dimensional semiconductor package having flexible appendages |
| JP2810647B2 (en) | 1996-04-30 | 1998-10-15 | 山一電機株式会社 | IC package |
| US5778522A (en) | 1996-05-20 | 1998-07-14 | Staktek Corporation | Method of manufacturing a high density integrated circuit module with complex electrical interconnect rails having electrical interconnect strain relief |
| AU5866596A (en) | 1996-05-20 | 1997-12-09 | Morris Anschel | High-density, integrated circuit chip package |
| JP2794558B2 (en)* | 1996-06-27 | 1998-09-10 | 日本航空電子工業株式会社 | Electronics |
| US5822856A (en) | 1996-06-28 | 1998-10-20 | International Business Machines Corporation | Manufacturing circuit board assemblies having filled vias |
| US6247228B1 (en) | 1996-08-12 | 2001-06-19 | Tessera, Inc. | Electrical connection with inwardly deformable contacts |
| US6336262B1 (en) | 1996-10-31 | 2002-01-08 | International Business Machines Corporation | Process of forming a capacitor with multi-level interconnection technology |
| US5729896A (en) | 1996-10-31 | 1998-03-24 | International Business Machines Corporation | Method for attaching a flip chip on flexible circuit carrier using chip with metallic cap on solder |
| JP3695893B2 (en) | 1996-12-03 | 2005-09-14 | 沖電気工業株式会社 | Semiconductor device, manufacturing method and mounting method thereof |
| US6225688B1 (en) | 1997-12-11 | 2001-05-01 | Tessera, Inc. | Stacked microelectronic assembly and method therefor |
| JP3455040B2 (en) | 1996-12-16 | 2003-10-06 | 株式会社日立製作所 | Source clock synchronous memory system and memory unit |
| US5959839A (en) | 1997-01-02 | 1999-09-28 | At&T Corp | Apparatus for heat removal using a flexible backplane |
| US5933712A (en) | 1997-03-19 | 1999-08-03 | The Regents Of The University Of California | Attachment method for stacked integrated circuit (IC) chips |
| US6084778A (en) | 1997-04-29 | 2000-07-04 | Texas Instruments Incorporated | Three dimensional assembly using flexible wiring board |
| JP3011233B2 (en) | 1997-05-02 | 2000-02-21 | 日本電気株式会社 | Semiconductor package and its semiconductor mounting structure |
| US6114763A (en) | 1997-05-30 | 2000-09-05 | Tessera, Inc. | Semiconductor package with translator for connection to an external substrate |
| US6028352A (en) | 1997-06-13 | 2000-02-22 | Irvine Sensors Corporation | IC stack utilizing secondary leadframes |
| US6014316A (en) | 1997-06-13 | 2000-01-11 | Irvine Sensors Corporation | IC stack utilizing BGA contacts |
| US5895705A (en)* | 1997-07-11 | 1999-04-20 | Highland Industries, Inc. | Awning and backlit sign fabric having a selectively eradicable ink layer and a process for producing same |
| US6234820B1 (en) | 1997-07-21 | 2001-05-22 | Rambus Inc. | Method and apparatus for joining printed circuit boards |
| US6002589A (en) | 1997-07-21 | 1999-12-14 | Rambus Inc. | Integrated circuit package for coupling to a printed circuit board |
| JPH1197619A (en) | 1997-07-25 | 1999-04-09 | Oki Electric Ind Co Ltd | Semiconductor device, manufacture thereof and mounting thereof |
| JP3294785B2 (en) | 1997-09-01 | 2002-06-24 | シャープ株式会社 | Heat dissipation structure of circuit element |
| US6040624A (en) | 1997-10-02 | 2000-03-21 | Motorola, Inc. | Semiconductor device package and method |
| US6313402B1 (en) | 1997-10-29 | 2001-11-06 | Packard Hughes Interconnect Company | Stress relief bend useful in an integrated circuit redistribution patch |
| US5869353A (en) | 1997-11-17 | 1999-02-09 | Dense-Pac Microsystems, Inc. | Modular panel stacking process |
| US5899705A (en) | 1997-11-20 | 1999-05-04 | Akram; Salman | Stacked leads-over chip multi-chip module |
| DE19754874A1 (en)* | 1997-12-10 | 1999-06-24 | Siemens Ag | Converting substrate with edge contacts into ball grid array |
| US5963427A (en) | 1997-12-11 | 1999-10-05 | Sun Microsystems, Inc. | Multi-chip module with flexible circuit board |
| US6186106B1 (en)* | 1997-12-29 | 2001-02-13 | Visteon Global Technologies, Inc. | Apparatus for routing electrical signals in an engine |
| DE19758197C2 (en) | 1997-12-30 | 2002-11-07 | Infineon Technologies Ag | Stack arrangement for two semiconductor memory chips and printed circuit board, which is equipped with a plurality of such stack arrangements |
| JP3097644B2 (en) | 1998-01-06 | 2000-10-10 | 日本電気株式会社 | Semiconductor device connection structure and connection method |
| US5926369A (en) | 1998-01-22 | 1999-07-20 | International Business Machines Corporation | Vertically integrated multi-chip circuit package with heat-sink support |
| US6172874B1 (en) | 1998-04-06 | 2001-01-09 | Silicon Graphics, Inc. | System for stacking of integrated circuit packages |
| US6226862B1 (en) | 1998-04-30 | 2001-05-08 | Sheldahl, Inc. | Method for manufacturing printed circuit board assembly |
| JP3055619B2 (en) | 1998-04-30 | 2000-06-26 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
| US6329709B1 (en) | 1998-05-11 | 2001-12-11 | Micron Technology, Inc. | Interconnections for a semiconductor device |
| KR100285664B1 (en) | 1998-05-15 | 2001-06-01 | 박종섭 | Stack Package and Manufacturing Method |
| US6329705B1 (en) | 1998-05-20 | 2001-12-11 | Micron Technology, Inc. | Leadframes including offsets extending from a major plane thereof, packaged semiconductor devices including same, and method of designing and fabricating such leadframes |
| US6300687B1 (en) | 1998-06-26 | 2001-10-09 | International Business Machines Corporation | Micro-flex technology in semiconductor packages |
| US6272741B1 (en) | 1998-07-24 | 2001-08-14 | Autosplice, Inc. | Hybrid solder ball and pin grid array circuit board interconnect system and method |
| DE19833713C1 (en) | 1998-07-27 | 2000-05-04 | Siemens Ag | Laminate or stacked package arrangement based on at least two integrated circuits |
| JP2000068444A (en) | 1998-08-26 | 2000-03-03 | Mitsubishi Electric Corp | Semiconductor device |
| JP2000088921A (en)* | 1998-09-08 | 2000-03-31 | Sony Corp | Semiconductor device |
| US6187652B1 (en) | 1998-09-14 | 2001-02-13 | Fujitsu Limited | Method of fabrication of multiple-layer high density substrate |
| US6239485B1 (en) | 1998-11-13 | 2001-05-29 | Fujitsu Limited | Reduced cross-talk noise high density signal interposer with power and ground wrap |
| US6310392B1 (en) | 1998-12-28 | 2001-10-30 | Staktek Group, L.P. | Stacked micro ball grid array packages |
| GB9900396D0 (en) | 1999-01-08 | 1999-02-24 | Danionics As | Arrangements of electrochemical cells |
| US6360935B1 (en)* | 1999-01-26 | 2002-03-26 | Board Of Regents Of The University Of Texas System | Apparatus and method for assessing solderability |
| US6965166B2 (en) | 1999-02-24 | 2005-11-15 | Rohm Co., Ltd. | Semiconductor device of chip-on-chip structure |
| US6130477A (en) | 1999-03-17 | 2000-10-10 | Chen; Tsung-Chieh | Thin enhanced TAB BGA package having improved heat dissipation |
| US6313998B1 (en) | 1999-04-02 | 2001-11-06 | Legacy Electronics, Inc. | Circuit board assembly having a three dimensional array of integrated circuit packages |
| JP3602000B2 (en)* | 1999-04-26 | 2004-12-15 | 沖電気工業株式会社 | Semiconductor device and semiconductor module |
| JP2000353767A (en)* | 1999-05-14 | 2000-12-19 | Universal Instr Corp | Board for mounting electronic component, package, mounting method, and method for housing integrated circuit chip in package |
| DE19923523B4 (en) | 1999-05-21 | 2004-09-30 | Infineon Technologies Ag | Semiconductor module with semiconductor chips arranged one above the other and connected to one another |
| TW409377B (en)* | 1999-05-21 | 2000-10-21 | Siliconware Precision Industries Co Ltd | Small scale ball grid array package |
| JP3526788B2 (en)* | 1999-07-01 | 2004-05-17 | 沖電気工業株式会社 | Method for manufacturing semiconductor device |
| DE19933265A1 (en)* | 1999-07-15 | 2001-02-01 | Siemens Ag | TSOP memory chip package assembly |
| JP2001053243A (en) | 1999-08-06 | 2001-02-23 | Hitachi Ltd | Semiconductor storage device and memory module |
| US6675469B1 (en) | 1999-08-11 | 2004-01-13 | Tessera, Inc. | Vapor phase connection techniques |
| US6670700B1 (en) | 1999-08-19 | 2003-12-30 | Seiko Epson Corporation | Interconnect substrate and semiconductor device electronic instrument |
| US6111761A (en) | 1999-08-23 | 2000-08-29 | Motorola, Inc. | Electronic assembly |
| US6303981B1 (en) | 1999-09-01 | 2001-10-16 | Micron Technology, Inc. | Semiconductor package having stacked dice and leadframes and method of fabrication |
| US6285560B1 (en) | 1999-09-20 | 2001-09-04 | Texas Instruments Incorporated | Method for increasing device reliability by selectively depopulating solder balls from a foot print of a ball grid array (BGA) package, and device so modified |
| US6689634B1 (en)* | 1999-09-22 | 2004-02-10 | Texas Instruments Incorporated | Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability |
| KR100344927B1 (en) | 1999-09-27 | 2002-07-19 | 삼성전자 주식회사 | Stack package and method for manufacturing the same |
| JP3633559B2 (en) | 1999-10-01 | 2005-03-30 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus |
| KR100530911B1 (en)* | 1999-10-01 | 2005-11-23 | 세이코 엡슨 가부시키가이샤 | Wiring board, semiconductor device and method of producing, testing and packaging the same, and circuit board and electronic equipment |
| KR100925361B1 (en)* | 1999-10-22 | 2009-11-09 | 소니 케미카루 앤드 인포메이션 디바이스 가부시키가이샤 | Low temperature-curable connecting material for anisotropically electroconductive connection |
| DE19954888C2 (en) | 1999-11-15 | 2002-01-10 | Infineon Technologies Ag | Packaging for a semiconductor chip |
| JP2001177051A (en) | 1999-12-20 | 2001-06-29 | Toshiba Corp | Semiconductor device and system device |
| TW434664B (en) | 1999-12-29 | 2001-05-16 | Advanced Semiconductor Eng | Lead-bond type chip package and method for making the same |
| US6262895B1 (en) | 2000-01-13 | 2001-07-17 | John A. Forthun | Stackable chip package with flex carrier |
| US6489178B2 (en) | 2000-01-26 | 2002-12-03 | Texas Instruments Incorporated | Method of fabricating a molded package for micromechanical devices |
| US6528870B2 (en) | 2000-01-28 | 2003-03-04 | Kabushiki Kaisha Toshiba | Semiconductor device having a plurality of stacked wiring boards |
| US6487078B2 (en) | 2000-03-13 | 2002-11-26 | Legacy Electronics, Inc. | Electronic module having a three dimensional array of carrier-mounted integrated circuit packages |
| US6437990B1 (en) | 2000-03-20 | 2002-08-20 | Agere Systems Guardian Corp. | Multi-chip ball grid array IC packages |
| US6320137B1 (en) | 2000-04-11 | 2001-11-20 | 3M Innovative Properties Company | Flexible circuit with coverplate layer and overlapping protective layer |
| US6833984B1 (en) | 2000-05-03 | 2004-12-21 | Rambus, Inc. | Semiconductor module with serial bus connection to multiple dies |
| US6449159B1 (en) | 2000-05-03 | 2002-09-10 | Rambus Inc. | Semiconductor module with imbedded heat spreader |
| US6624507B1 (en) | 2000-05-09 | 2003-09-23 | National Semiconductor Corporation | Miniature semiconductor package for opto-electronic devices |
| US6522018B1 (en)* | 2000-05-16 | 2003-02-18 | Micron Technology, Inc. | Ball grid array chip packages having improved testing and stacking characteristics |
| US6778404B1 (en) | 2000-06-02 | 2004-08-17 | Micron Technology Inc | Stackable ball grid array |
| US6236565B1 (en) | 2000-06-15 | 2001-05-22 | Mark G. Gordon | Chip stack with active cooling system |
| US7104804B2 (en) | 2000-07-03 | 2006-09-12 | Advanced Interconnect Solutions | Method and apparatus for memory module circuit interconnection |
| JP3390412B2 (en) | 2000-08-07 | 2003-03-24 | 株式会社キャットアイ | head lamp |
| JP4397109B2 (en) | 2000-08-14 | 2010-01-13 | 富士通株式会社 | Information processing apparatus and crossbar board unit / back panel assembly manufacturing method |
| US6462423B1 (en) | 2000-08-31 | 2002-10-08 | Micron Technology, Inc. | Flip-chip with matched lines and ground plane |
| US6717241B1 (en) | 2000-08-31 | 2004-04-06 | Micron Technology, Inc. | Magnetic shielding for integrated circuits |
| US6608763B1 (en) | 2000-09-15 | 2003-08-19 | Staktek Group L.P. | Stacking system and method |
| KR100402391B1 (en) | 2000-10-26 | 2003-10-22 | 삼성전자주식회사 | Memory card system |
| KR100400765B1 (en) | 2000-11-13 | 2003-10-08 | 엘지.필립스 엘시디 주식회사 | Method for forming thin-film and liquid crystal display device fabricated by the same method |
| US6414384B1 (en) | 2000-12-22 | 2002-07-02 | Silicon Precision Industries Co., Ltd. | Package structure stacking chips on front surface and back surface of substrate |
| EP1306900A3 (en) | 2000-12-28 | 2005-07-06 | Texas Instruments Incorporated | Chip-scale packages stacked on folded interconnector for vertical assembly on substrates |
| KR100355032B1 (en) | 2001-01-08 | 2002-10-05 | 삼성전자 주식회사 | High density package memory device, memory module using this device, and control method of this module |
| US6707664B2 (en)* | 2001-02-11 | 2004-03-16 | Micron Technology, Inc. | Expandable keyboard for portable computers |
| WO2002069374A2 (en) | 2001-02-27 | 2002-09-06 | Chippac, Inc. | Tape ball grid array semiconductor package structure and assembly process |
| US20020126951A1 (en) | 2001-03-12 | 2002-09-12 | Sutherland Robert A. | Optical converter flex assemblies |
| US6884653B2 (en) | 2001-03-21 | 2005-04-26 | Micron Technology, Inc. | Folded interposer |
| US6462408B1 (en) | 2001-03-27 | 2002-10-08 | Staktek Group, L.P. | Contact member stacking system and method |
| SG108245A1 (en) | 2001-03-30 | 2005-01-28 | Micron Technology Inc | Ball grid array interposer, packages and methods |
| US6707684B1 (en) | 2001-04-02 | 2004-03-16 | Advanced Micro Devices, Inc. | Method and apparatus for direct connection between two integrated circuits via a connector |
| US6588095B2 (en) | 2001-04-27 | 2003-07-08 | Hewlett-Packard Development Company, Lp. | Method of processing a device by electrophoresis coating |
| US6532162B2 (en)* | 2001-05-26 | 2003-03-11 | Intel Corporation | Reference plane of integrated circuit packages |
| KR100415279B1 (en) | 2001-06-26 | 2004-01-16 | 삼성전자주식회사 | Chip stack package and manufacturing method thereof |
| JP2003031885A (en) | 2001-07-19 | 2003-01-31 | Toshiba Corp | Semiconductor laser device |
| US6451626B1 (en) | 2001-07-27 | 2002-09-17 | Charles W.C. Lin | Three-dimensional stacked semiconductor package |
| US7605479B2 (en) | 2001-08-22 | 2009-10-20 | Tessera, Inc. | Stacked chip assembly with encapsulant layer |
| US6927471B2 (en) | 2001-09-07 | 2005-08-09 | Peter C. Salmon | Electronic system modules and method of fabrication |
| KR100429878B1 (en) | 2001-09-10 | 2004-05-03 | 삼성전자주식회사 | Memory module and printed circuit board for the same |
| US6977440B2 (en) | 2001-10-09 | 2005-12-20 | Tessera, Inc. | Stacked packages |
| WO2003032370A2 (en) | 2001-10-09 | 2003-04-17 | Tessera, Inc. | Stacked packages |
| KR20030029743A (en) | 2001-10-10 | 2003-04-16 | 삼성전자주식회사 | Stack package using flexible double wiring substrate |
| US6940729B2 (en) | 2001-10-26 | 2005-09-06 | Staktek Group L.P. | Integrated circuit stacking system and method |
| US6914324B2 (en) | 2001-10-26 | 2005-07-05 | Staktek Group L.P. | Memory expansion and chip scale stacking system and method |
| US6576992B1 (en) | 2001-10-26 | 2003-06-10 | Staktek Group L.P. | Chip scale stacking system and method |
| US6657134B2 (en) | 2001-11-30 | 2003-12-02 | Honeywell International Inc. | Stacked ball grid array |
| US7081373B2 (en) | 2001-12-14 | 2006-07-25 | Staktek Group, L.P. | CSP chip stack with flex circuit |
| US20030113998A1 (en) | 2001-12-17 | 2003-06-19 | Ross Andrew C. | Flex tab for use in stacking packaged integrated circuit chips |
| US6891276B1 (en) | 2002-01-09 | 2005-05-10 | Bridge Semiconductor Corporation | Semiconductor package device |
| US6762769B2 (en) | 2002-01-23 | 2004-07-13 | Microsoft Corporation | System and method for real-time texture synthesis using patch-based sampling |
| SG121707A1 (en) | 2002-03-04 | 2006-05-26 | Micron Technology Inc | Method and apparatus for flip-chip packaging providing testing capability |
| US6707148B1 (en)* | 2002-05-21 | 2004-03-16 | National Semiconductor Corporation | Bumped integrated circuits for optical applications |
| US6873039B2 (en) | 2002-06-27 | 2005-03-29 | Tessera, Inc. | Methods of making microelectronic packages including electrically and/or thermally conductive element |
| TW565918B (en)* | 2002-07-03 | 2003-12-11 | United Test Ct Inc | Semiconductor package with heat sink |
| WO2004017399A1 (en) | 2002-08-16 | 2004-02-26 | Tessera, Inc. | Microelectronic packages with self-aligning features |
| JP4085788B2 (en)* | 2002-08-30 | 2008-05-14 | 日本電気株式会社 | SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD, CIRCUIT BOARD, ELECTRONIC DEVICE |
| US7246431B2 (en) | 2002-09-06 | 2007-07-24 | Tessera, Inc. | Methods of making microelectronic packages including folded substrates |
| US6821029B1 (en) | 2002-09-10 | 2004-11-23 | Xilinx, Inc. | High speed serial I/O technology using an optical link |
| US6737742B2 (en) | 2002-09-11 | 2004-05-18 | International Business Machines Corporation | Stacked package for integrated circuits |
| US7071547B2 (en) | 2002-09-11 | 2006-07-04 | Tessera, Inc. | Assemblies having stacked semiconductor chips and methods of making same |
| US6838761B2 (en) | 2002-09-17 | 2005-01-04 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield |
| KR100616435B1 (en) | 2002-11-28 | 2006-08-29 | 삼성전자주식회사 | Semiconductor Package and Laminated Package |
| US6869825B2 (en)* | 2002-12-31 | 2005-03-22 | Intel Corporation | Folded BGA package design with shortened communication paths and more electrical routing flexibility |
| US6762495B1 (en) | 2003-01-30 | 2004-07-13 | Qualcomm Incorporated | Area array package with non-electrically connected solder balls |
| US6879047B1 (en) | 2003-02-19 | 2005-04-12 | Amkor Technology, Inc. | Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor |
| US20040217471A1 (en) | 2003-02-27 | 2004-11-04 | Tessera, Inc. | Component and assemblies with ends offset downwardly |
| US6841855B2 (en)* | 2003-04-28 | 2005-01-11 | Intel Corporation | Electronic package having a flexible substrate with ends connected to one another |
| DE10319984B4 (en) | 2003-05-05 | 2009-09-03 | Qimonda Ag | Device for cooling memory modules |
| US20040245617A1 (en) | 2003-05-06 | 2004-12-09 | Tessera, Inc. | Dense multichip module |
| US6940158B2 (en) | 2003-05-30 | 2005-09-06 | Tessera, Inc. | Assemblies having stacked semiconductor chips and methods of making same |
| US7269481B2 (en) | 2003-06-25 | 2007-09-11 | Intel Corporation | Method and apparatus for memory bandwidth thermal budgetting |
| KR100592786B1 (en) | 2003-08-22 | 2006-06-26 | 삼성전자주식회사 | Laminated package and its manufacturing method using surface-mount semiconductor package |
| US7078793B2 (en) | 2003-08-29 | 2006-07-18 | Infineon Technologies Ag | Semiconductor memory module |
| KR100535181B1 (en) | 2003-11-18 | 2005-12-09 | 삼성전자주식회사 | Semiconductor chip package having decoupling capacitor and manufacturing method thereof |
| KR100575590B1 (en) | 2003-12-17 | 2006-05-03 | 삼성전자주식회사 | Heat-Resistant Stacking Packages and Modules with They |
| US20050018495A1 (en) | 2004-01-29 | 2005-01-27 | Netlist, Inc. | Arrangement of integrated circuits in a memory module |
- 2003
- 2003-06-09USUS10/457,608patent/US20030234443A1/ennot_activeAbandoned
- 2004
- 2004-12-14USUS11/011,469patent/US7180167B2/ennot_activeExpired - Fee Related
- 2007
- 2007-01-23USUS11/626,316patent/US20070117262A1/ennot_activeAbandoned
- 2007-01-23USUS11/626,318patent/US20070114649A1/ennot_activeAbandoned
- 2009
- 2009-01-20USUS12/356,432patent/US7626273B2/ennot_activeExpired - Lifetime
Patent Citations (67)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3654394A (en)* | 1969-07-08 | 1972-04-04 | Gordon Eng Co | Field effect transistor switch, particularly for multiplexing |
| US4513368A (en)* | 1981-05-22 | 1985-04-23 | Data General Corporation | Digital data processing system having object-based logical memory addressing and self-structuring modular memory |
| US4645944A (en)* | 1983-09-05 | 1987-02-24 | Matsushita Electric Industrial Co., Ltd. | MOS register for selecting among various data inputs |
| US4654944A (en)* | 1985-09-13 | 1987-04-07 | Graf Richard W | Overhead cam valve spring compressor adapter |
| US4763188A (en)* | 1986-08-08 | 1988-08-09 | Thomas Johnson | Packaging system for multiple semiconductor devices |
| US4985703A (en)* | 1988-02-03 | 1991-01-15 | Nec Corporation | Analog multiplexer |
| US5239198A (en)* | 1989-09-06 | 1993-08-24 | Motorola, Inc. | Overmolded semiconductor device having solder ball and edge lead connective structure |
| US5642055A (en)* | 1990-02-14 | 1997-06-24 | Particle Interconnect, Inc. | Electrical interconnect using particle enhanced joining of metal surfaces |
| US6465893B1 (en)* | 1990-09-24 | 2002-10-15 | Tessera, Inc. | Stacked chip assembly |
| US5117282A (en)* | 1990-10-29 | 1992-05-26 | Harris Corporation | Stacked configuration for integrated circuit devices |
| US5289062A (en)* | 1991-03-18 | 1994-02-22 | Quality Semiconductor, Inc. | Fast transmission gate switch |
| US5224023A (en)* | 1992-02-10 | 1993-06-29 | Smith Gary W | Foldable electronic assembly module |
| US5428190A (en)* | 1993-07-02 | 1995-06-27 | Sheldahl, Inc. | Rigid-flex board with anisotropic interconnect and method of manufacture |
| US5448511A (en)* | 1994-06-01 | 1995-09-05 | Storage Technology Corporation | Memory stack with an integrated interconnect and mounting structure |
| US5523695A (en)* | 1994-08-26 | 1996-06-04 | Vlsi Technology, Inc. | Universal test socket for exposing the active surface of an integrated circuit in a die-down package |
| US5764497A (en)* | 1995-11-13 | 1998-06-09 | Minolta Co, Ltd. | Circuit board connection method and connection structure |
| US5776797A (en)* | 1995-12-22 | 1998-07-07 | Fairchild Space And Defense Corporation | Three-dimensional flexible assembly of integrated circuits |
| US6281577B1 (en)* | 1996-06-28 | 2001-08-28 | Pac Tech-Packaging Technologies Gmbh | Chips arranged in plurality of planes and electrically connected to one another |
| US20030168725A1 (en)* | 1996-12-13 | 2003-09-11 | Tessera, Inc. | Methods of making microelectronic assemblies including folded substrates |
| US6121676A (en)* | 1996-12-13 | 2000-09-19 | Tessera, Inc. | Stacked microelectronic assembly and method therefor |
| US6208521B1 (en)* | 1997-05-19 | 2001-03-27 | Nitto Denko Corporation | Film carrier and laminate type mounting structure using same |
| US5917709A (en)* | 1997-06-16 | 1999-06-29 | Eastman Kodak Company | Multiple circuit board assembly having an interconnect mechanism that includes a flex connector |
| US6265660B1 (en)* | 1997-07-09 | 2001-07-24 | Micron Technology, Inc. | Package stack via bottom leaded plastic (BLP) packaging |
| US6465877B1 (en)* | 1997-10-31 | 2002-10-15 | Micron Technology, Inc. | Semiconductor package including flex circuit, interconnects and dense array external contacts |
| US6368896B2 (en)* | 1997-10-31 | 2002-04-09 | Micron Technology, Inc. | Method of wafer level chip scale packaging |
| US6097087A (en)* | 1997-10-31 | 2000-08-01 | Micron Technology, Inc. | Semiconductor package including flex circuit, interconnects and dense array external contacts |
| US6266252B1 (en)* | 1997-12-01 | 2001-07-24 | Chris Karabatsos | Apparatus and method for terminating a computer memory bus |
| US5949657A (en)* | 1997-12-01 | 1999-09-07 | Karabatsos; Chris | Bottom or top jumpered foldable electronic assembly |
| US5953215A (en)* | 1997-12-01 | 1999-09-14 | Karabatsos; Chris | Apparatus and method for improving computer memory speed and capacity |
| US6028365A (en)* | 1998-03-30 | 2000-02-22 | Micron Technology, Inc. | Integrated circuit package and method of fabrication |
| US6233650B1 (en)* | 1998-04-01 | 2001-05-15 | Intel Corporation | Using FET switches for large memory arrays |
| US6072233A (en)* | 1998-05-04 | 2000-06-06 | Micron Technology, Inc. | Stackable ball grid array package |
| US6300679B1 (en)* | 1998-06-01 | 2001-10-09 | Semiconductor Components Industries, Llc | Flexible substrate for packaging a semiconductor component |
| US6433418B1 (en)* | 1998-07-24 | 2002-08-13 | Fujitsu Limited | Apparatus for a vertically accumulable semiconductor device with external leads secured by a positioning mechanism |
| US6486544B1 (en)* | 1998-09-09 | 2002-11-26 | Seiko Epson Corporation | Semiconductor device and method manufacturing the same, circuit board, and electronic instrument |
| US6360433B1 (en)* | 1999-04-23 | 2002-03-26 | Andrew C. Ross | Universal package and method of forming the same |
| US6222737B1 (en)* | 1999-04-23 | 2001-04-24 | Dense-Pac Microsystems, Inc. | Universal package and method of forming the same |
| US6351029B1 (en)* | 1999-05-05 | 2002-02-26 | Harlan R. Isaak | Stackable flex circuit chip package and method of making same |
| US6514793B2 (en)* | 1999-05-05 | 2003-02-04 | Dpac Technologies Corp. | Stackable flex circuit IC package and method of making same |
| US6323060B1 (en)* | 1999-05-05 | 2001-11-27 | Dense-Pac Microsystems, Inc. | Stackable flex circuit IC package and method of making same |
| US6426549B1 (en)* | 1999-05-05 | 2002-07-30 | Harlan R. Isaak | Stackable flex circuit IC package and method of making same |
| US6426240B2 (en)* | 1999-05-05 | 2002-07-30 | Harlan R. Isaak | Stackable flex circuit chip package and method of making same |
| US6446158B1 (en)* | 1999-05-17 | 2002-09-03 | Chris Karabatsos | Memory system using FET switches to select memory banks |
| US6376769B1 (en)* | 1999-05-18 | 2002-04-23 | Amerasia International Technology, Inc. | High-density electronic package, and method for making same |
| US6572387B2 (en)* | 1999-09-24 | 2003-06-03 | Staktek Group, L.P. | Flexible circuit connector for stacked chip module |
| US20020180022A1 (en)* | 1999-10-20 | 2002-12-05 | Seiko Epson Corporation | Semiconductor device |
| US6462412B2 (en)* | 2000-01-18 | 2002-10-08 | Sony Corporation | Foldable, flexible laminate type semiconductor apparatus with reinforcing and heat-radiating plates |
| US20010040793A1 (en)* | 2000-02-01 | 2001-11-15 | Tetsuya Inaba | Electronic device and method of producing the same |
| US6444921B1 (en)* | 2000-02-03 | 2002-09-03 | Fujitsu Limited | Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like |
| US6677670B2 (en)* | 2000-04-25 | 2004-01-13 | Seiko Epson Corporation | Semiconductor device |
| US20020006032A1 (en)* | 2000-05-23 | 2002-01-17 | Chris Karabatsos | Low-profile registered DIMM |
| US6683377B1 (en)* | 2000-05-30 | 2004-01-27 | Amkor Technology, Inc. | Multi-stacked memory package |
| US6660561B2 (en)* | 2000-06-15 | 2003-12-09 | Dpac Technologies Corp. | Method of assembling a stackable integrated circuit chip |
| US6552910B1 (en)* | 2000-06-28 | 2003-04-22 | Micron Technology, Inc. | Stacked-die assemblies with a plurality of microelectronic devices and methods of manufacture |
| US6560117B2 (en)* | 2000-06-28 | 2003-05-06 | Micron Technology, Inc. | Packaged microelectronic die assemblies and methods of manufacture |
| US6614664B2 (en)* | 2000-10-24 | 2003-09-02 | Samsung Electronics Co., Ltd. | Memory module having series-connected printed circuit boards |
| US6392162B1 (en)* | 2000-11-10 | 2002-05-21 | Chris Karabatsos | Double-sided flexible jumper assembly and method of manufacture |
| US20020101261A1 (en)* | 2001-02-01 | 2002-08-01 | Chris Karabatsos | Tri-directional, high-speed bus switch |
| US6410857B1 (en)* | 2001-03-01 | 2002-06-25 | Lockheed Martin Corporation | Signal cross-over interconnect for a double-sided circuit card assembly |
| US20020139577A1 (en)* | 2001-03-27 | 2002-10-03 | Miller Charles A. | In-street integrated circuit wafer via |
| US20020164838A1 (en)* | 2001-05-02 | 2002-11-07 | Moon Ow Chee | Flexible ball grid array chip scale packages and methods of fabrication |
| US6627984B2 (en)* | 2001-07-24 | 2003-09-30 | Dense-Pac Microsystems, Inc. | Chip stack with differing chip package types |
| US6620651B2 (en)* | 2001-10-23 | 2003-09-16 | National Starch And Chemical Investment Holding Corporation | Adhesive wafers for die attach application |
| US6590282B1 (en)* | 2002-04-12 | 2003-07-08 | Industrial Technology Research Institute | Stacked semiconductor package formed on a substrate and method for fabrication |
| US6600222B1 (en)* | 2002-07-17 | 2003-07-29 | Intel Corporation | Stacked microelectronic packages |
| US20040021211A1 (en)* | 2002-08-05 | 2004-02-05 | Tessera, Inc. | Microelectronic adaptors, assemblies and methods |
| US20040150107A1 (en)* | 2002-12-31 | 2004-08-05 | Cha Ki Bon | Stack package and fabricating method thereof |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7630202B2 (en) | 2004-04-09 | 2009-12-08 | Netlist, Inc. | High density module having at least two substrates and at least one thermally conductive layer therebetween |
| US8345427B2 (en) | 2004-04-09 | 2013-01-01 | Netlist, Inc. | Module having at least two surfaces and at least one thermally conductive layer therebetween |
| US7839645B2 (en) | 2004-04-09 | 2010-11-23 | Netlist, Inc. | Module having at least two surfaces and at least one thermally conductive layer therebetween |
| US7511968B2 (en)* | 2004-09-03 | 2009-03-31 | Entorian Technologies, Lp | Buffered thin module system and method |
| US7480152B2 (en)* | 2004-09-03 | 2009-01-20 | Entorian Technologies, Lp | Thin module system and method |
| US7616452B2 (en)* | 2004-09-03 | 2009-11-10 | Entorian Technologies, Lp | Flex circuit constructions for high capacity circuit module systems and methods |
| US20060125067A1 (en)* | 2004-09-03 | 2006-06-15 | Staktek Group L.P. | Flex circuit constructions for high capacity circuit module systems and methods |
| US7626259B2 (en) | 2004-09-03 | 2009-12-01 | Entorian Technologies, Lp | Heat sink for a high capacity thin module system |
| US20090046431A1 (en)* | 2004-09-03 | 2009-02-19 | Staktek Group L.P. | High Capacity Thin Module System |
| US7811097B1 (en) | 2005-08-29 | 2010-10-12 | Netlist, Inc. | Circuit with flexible portion |
| US8033836B1 (en) | 2005-08-29 | 2011-10-11 | Netlist, Inc. | Circuit with flexible portion |
| US7442050B1 (en) | 2005-08-29 | 2008-10-28 | Netlist, Inc. | Circuit card with flexible connection for memory module with heat spreader |
| US8864500B1 (en) | 2005-08-29 | 2014-10-21 | Netlist, Inc. | Electronic module with flexible portion |
| US7619893B1 (en) | 2006-02-17 | 2009-11-17 | Netlist, Inc. | Heat spreader for electronic modules |
| US7839643B1 (en) | 2006-02-17 | 2010-11-23 | Netlist, Inc. | Heat spreader for memory modules |
| US8488325B1 (en) | 2006-02-17 | 2013-07-16 | Netlist, Inc. | Memory module having thermal conduits |
| US8018723B1 (en) | 2008-04-30 | 2011-09-13 | Netlist, Inc. | Heat dissipation for electronic modules |
| US8705239B1 (en) | 2008-04-30 | 2014-04-22 | Netlist, Inc. | Heat dissipation for electronic modules |
| US20110197438A1 (en)* | 2010-02-17 | 2011-08-18 | Masashi Kikuchii | Method of manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| US20090124045A1 (en) | 2009-05-14 |
| US20070117262A1 (en) | 2007-05-24 |
| US7626273B2 (en) | 2009-12-01 |
| US20050146031A1 (en) | 2005-07-07 |
| US20070114649A1 (en) | 2007-05-24 |
| US7180167B2 (en) | 2007-02-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7626273B2 (en) | Low profile stacking system and method | |
| US7094632B2 (en) | Low profile chip scale stacking system and method | |
| EP0527044B1 (en) | Memory package | |
| US5796591A (en) | Direct chip attach circuit card | |
| JP4938980B2 (en) | Non-eutectic solder composition | |
| US6994243B2 (en) | Low temperature solder chip attach structure and process to produce a high temperature interconnection | |
| JPH098451A (en) | Method of manufacturing chip mounting circuit card | |
| JPH04273453A (en) | Method for direct chip mounting | |
| WO2021012228A1 (en) | Electronic packaging assembly, camera, movable platform, and preparation method for electronic packaging assembly | |
| JP2008210993A (en) | Printed wiring board and method of manufacturing the same | |
| JP2008205132A (en) | Printed wiring board, and solder connection structure and method between the structure and flexible printed board | |
| US7488896B2 (en) | Wiring board with semiconductor component | |
| WO2007001598A2 (en) | Lead-free semiconductor package | |
| JP2000151095A (en) | Method of soldering part on printed wiring board and manufacture of printed wiring board | |
| JP2002359462A (en) | Electronic component mounting method, mounting structure, and metal mask | |
| US20070007323A1 (en) | Standoff structures for surface mount components | |
| US6802119B2 (en) | Conductive pedestal on pad for leadless chip carrier (LCC) standoff | |
| US20060049238A1 (en) | Solderable structures and methods for soldering | |
| JP2011249457A (en) | Wiring board having embedded component, and manufacturing method for the same | |
| JP2008140868A (en) | Multilayer wiring board and semiconductor device | |
| JP2008171975A (en) | Mounting method and mounting structure of semiconductor component | |
| JP2007141973A (en) | Wiring circuit board with semiconductor components | |
| JP4667208B2 (en) | Wiring board with semiconductor parts | |
| JP2025031250A (en) | Control board and manufacturing method thereof | |
| JP2005197403A (en) | Surface-mounted electronic circuit arrangement |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AS | Assignment | Owner name:STAKTEK GROUP L.P., TEXAS Free format text:ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PARTRIDGE, JULIAN;CADY, JAMES W.;WILDER, JAMES;AND OTHERS;REEL/FRAME:014161/0950;SIGNING DATES FROM 20030605 TO 20030606 | |
| AS | Assignment | Owner name:COMERICA BANK, AS AGENT, MICHIGAN Free format text:SECURITY AGREEMENT;ASSIGNOR:STAKTEK GROUP L.P.;REEL/FRAME:014546/0001 Effective date:20030819 | |
| STCB | Information on status: application discontinuation | Free format text:ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION | |
| AS | Assignment | Owner name:STAKTEK GROUP L.P. NOW KNOWN AS ENTORIAN TECHNOLOG Free format text:RELEASE BY SECURED PARTY;ASSIGNOR:COMERICA BANK, AS AGENT;REEL/FRAME:023985/0954 Effective date:20040219 |