US20030214800A1 - System and method for processor power delivery and thermal management - Google Patents

Abstract

A power interconnection system comprising a plurality of z-axis compliant connectors passing power and ground signals between a first circuit board to a second circuit board is disclosed. The interconnection system provides for an extremely low impedance through a broad range of frequencies and allows for large amounts of current to pass from one substrate to the next either statically or dynamically. The interconnection system may be located close to the die or may be further away depending upon the system requirements. The interconnection may also be used to take up mechanical tolerances between the two substrates while providing a low impedance. interconnect.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• This application is a continuation of U.S. patent application Ser. No. 10/036,957, entitled “ULTRA-LOW IMPEDANCE POWER INTERCONNECTION SYSTEM FOR ELECTRONIC PACKAGES,” filed Dec. 20, 2001, hereby incorporated herein by reference.[0001]
• Application Ser. No. 10/036,957 is a continuation in part of U.S. patent application Ser. No. 09/885,780, entitled “INTER-CIRCUIT ENCAPSULATED PACKAGING,” filed Jun. 19, 2001, now abandoned, which is a continuation of U.S. patent application Ser. No. 09/353,428, entitled “INTER-CIRCUIT ENCAPSULATED PACKAGING,” filed Jul. 15, 1999, now U.S. Pat. No. 6,304,450.[0002]
• Application Ser. No. 10/036,957 is a continuation in part of U.S. patent application Ser. No. 09/432,878, entitled “INTER-CIRCUIT ENCAPSULATED PACKAGING FOR POWER DELIVERY,” filed Nov. 2, 1999, now U.S. Pat. No. 6,356,448.[0003]
• Application Ser. No. 10/036,957 is a continuation in part of U.S. patent application Ser. No. 09/785,892, entitled “APPARATUS FOR PROVIDING POWER TO A MICROPROCESSOR WITH INTEGRATED THERMAL AND EMI MANAGEMENT,” filed Feb. 16, 2001, now U.S. Pat. No. 6,452,113.[0004]
• Application Ser. No. 10/036,957 is a continuation in part of U.S. patent application Ser. No. 09/727,016, entitled “EMI CONTAINMENT USING INTER-CIRCUIT ENCAPSULATED PACKAGING TECHNOLOGY,” filed Nov. 28, 2000, now abandoned, which claims the benefit of the following applications:[0005]
• Provisional Patent Application No. 60/167,792, entitled “EMI CONTAINMENT USING INTER-CIRCUIT ENCAPSULATED PACKAGING TECHNOLOGY,” filed Nov. 29, 1999;[0006]
• Provisional Patent Application No. 60/171,065, entitled “INTER-CIRCUIT ENCAPSULATED PACKAGING TECHNOLOGY,” filed Dec. 16, 1999;[0007]
• Provisional Patent Application No. 60/183,474, entitled “DIRECT ATTACH POWER/THERMAL WITH INCEP TECHNOLOGY,” filed Feb. 18, 2000;[0008]
• Provisional Patent Application No. 60/187,777, entitled “NEXT GENERATION PACKAGING FOR EMI CONTAINMENT, POWER DELIVERY, AND THERMAL DISSIPATION USING INTER-CIRCUIT ENCAPSULATED PACKAGING TECHNOLOGY,” filed Mar. 8, 2000;[0009]
• Provisional Patent Application No. 60/196,059, entitled “EMI FRAME WITH POWER FEED-THROUGHS AND THERMAL INTERFACE MATERIAL IN AN AGGREGATE DIAMOND MIXTURE,” filed Apr. 10, 2000;[0010]
• Provisional Patent Application No. 60/219,813, entitled “HIGH-CURRENT MICROPROCESSOR POWER DELIVERY SYSTEMS,” filed Jul. 21, 2000; and[0011]
• Provisional Patent Application No. 60/232,971, entitled “INTEGRATED POWER DISTRIBUTION AND SEMICONDUCTOR PACKAGE,” filed Sep. 14, 2000.[0012]
• Application Ser. No. 10/036,957 is a continuation in part of U.S. patent application Ser. No. 09/798,541, entitled “THERMAL/MECHANICAL SPRINGBEAM MECHANISM FOR HEAT TRANSFER FROM HEAT SOURCE TO HEAT DISSIPATING DEVICE,” filed Mar. 2, 2001, now abandoned, which claims the benefit of Provisional Patent Application No. 60/186,769, entitled “THERMACEP SPRING BEAM,” filed Mar. 3, 2000.[0013]
• Application Ser. No. 10/036,957 is a continuation in part of U.S. patent application Ser. No. 09/910,524, entitled “HIGH PERFORMANCE THERMAL/MECHANICAL INTERFACE FOR FIXED GAP REFERENCES FOR HIGH HEAT FLUX AND POWER SEMICONDUCTOR APPLICATIONS,” filed Jul. 20, 2001, now abandoned, which claims the benefit of Provisional Patent Application No. 60/219,506, entitled “HIGH PERFORMANCE THERMAL/MECHANICAL INTERFACE,” filed Jul. 20, 2000.[0014]
• Application Ser. No. 10/036,957 is a continuation in part of U.S. patent application Ser. No. 09/921,153, entitled “VAPOR CHAMBER WITH INTEGRATED PIN ARRAY,” filed Aug. 2, 2001, now U.S. Pat. No. 6,490,160, which claims the benefit of the following applications:[0015]
• Provisional Patent Application No. 60/222,386, entitled “HIGH DENSITY CIRCULAR ‘PIN’ CONNECTOR FOR HIGH SPEED SIGNAL INTERCONNECT,” filed Aug. 2, 2000; and[0016]
• Provisional Patent Application No. 60/222,407, entitled “VAPOR HEATSINK COMBINATION FOR HIGH EFFICIENCY THERMAL MANAGEMENT,” filed Aug. 2, 2000.[0017]
• The following patents and applications are hereby incorporated herein by reference in their entirety:[0018]
• U.S. patent application Ser. No. 09/353,428, entitled “INTER-CIRCUIT ENCAPSULATED PACKAGING,” filed Jul. 15, 1999, now U.S. Pat. No. 6,304,450;[0019]
• U.S. patent application Ser. No. 09/432,878, entitled “INTER-CIRCUIT ENCAPSULATED PACKAGING FOR POWER DELIVERY,” filed Nov. 2, 1999, now U.S. Pat. No. 6,356,448;[0020]
• U.S. patent application Ser. No. 09/785,892, entitled “APPARATUS FOR PROVIDING POWER TO A MICROPROCESSOR WITH INTEGRATED THERMAL AND EMI MANAGEMENT,” filed Feb. 16, 2001, now U.S. Pat. No. 6,452,113;[0021]
• Provisional Patent Application No. 60/167,792, entitled “EMI CONTAINMENT USING INTER-CIRCUIT ENCAPSULATED PACKAGING TECHNOLOGY,” filed Nov. 29, 1999;[0022]
• Provisional Patent Application No. 60/171,065, entitled “INTER-CIRCUIT ENCAPSULATED PACKAGING TECHNOLOGY,” filed Dec. 16, 1999;[0023]
• Provisional Patent Application No. 60/183,474, entitled “DIRECT ATTACH POWER/THERMAL WITH INCEP TECHNOLOGY,” filed Feb. 18, 2000;[0024]
• Provisional Patent Application No. 60/186,769, entitled “THERMACEP SPRING BEAM,” filed Mar. 3, 2000;[0025]
• Provisional Patent Application No. 60/187,777, entitled “NEXT GENERATION PACKAGING FOR EMI CONTAINMENT, POWER DELIVERY, AND THERMAL DISSIPATION USING INTER-CIRCUIT ENCAPSULATED PACKAGING TECHNOLOGY,” filed Mar. 8, 2000;[0026]
• Provisional Patent Application No. 60/196,059, entitled “EMI FRAME WITH POWER FEED-THROUGHS AND THERMAL INTERFACE MATERIAL IN AN AGGREGATE DIAMOND MIXTURE,” filed Apr. 10, 2000;[0027]
• Provisional Patent Application No. 60/219,506, entitled “HIGH PERFORMANCE THERMAL/MECHANICAL INTERFACE,” filed Jul. 20, 2000;[0028]
• Provisional Patent Application No. 60/219,813, entitled “HIGH-CURRENT MICROPROCESSOR POWER DELIVERY SYSTEMS,” filed Jul. 21, 2000;[0029]
• Provisional Patent Application No. 60/222,386, entitled “HIGH DENSITY CIRCULAR ‘PIN’ CONNECTOR FOR HIGH SPEED SIGNAL INTERCONNECT,” filed Aug. 2, 2000;[0030]
• Provisional Patent Application No. 60/222,407, entitled “VAPOR HEATSINK COMBINATION FOR HIGH EFFICIENCY THERMAL MANAGEMENT,” filed Aug. 2, 2000; and[0031]
• Provisional Patent Application No. 60/232,971, entitled “INTEGRATED POWER DISTRIBUTION AND SEMICONDUCTOR PACKAGE,” filed Sep. 14, 2000.[0032]
FIELD OF THE INVENTION
• The present invention relates generally to systems and methods for interconnecting electronic packages and in particular to a power interconnection system mating between substrates to enable a low impedance disconnectable power delivery path between the power source and the load of an electronic package.[0033]
DESCRIPTION OF THE RELATED ART
• High-speed microprocessor packaging must be designed to provide increasingly small form-factors. Meeting end user performance requirements with minimal form-factors while increasing reliability and manufacturability presents significant challenges in the areas of power distribution, thermal management, and electromagnetic interference (EMI) containment.[0034]
• To increase reliability and reduce thermal dissipation requirements, newer generation processors are designed to operate with reduced voltage and higher current. Unfortunately, this creates a number of design problems.[0035]
• First, the lowered operating voltage of the processor places greater demands on the power regulating circuitry and the conductive paths providing power to the processor. Typically, processors require supply voltage regulation to within 10% of nominal. In order to account for impedance variations in the path from the power supply to the processor itself, this places greater demands on the power regulating circuitry, which must then typically regulate power supply voltages to within 5% of nominal.[0036]
• Lower operating voltages have also lead engineers away from centralized power supply designs to distributed power supply architectures in which power is bused where required at high voltages and low current, where it is converted to the low-voltage, high-current power required by the processor from nearby power conditioning circuitry.[0037]
• While it is possible to place power conditioning circuitry on the processor package itself, this design is difficult to implement because of the unmanageable physical size of the components in the power conditioning circuitry (e.g. capacitors and inductors), and because the addition of such components can have a deleterious effect on processor reliability. Such designs also place additional demands on the assembly and testing of the processor packages as well.[0038]
• Further exacerbating the problem are the transient currents that result from varying demands on the processor itself. Processor computing demands vary widely over time, and higher clock speeds and power conservation techniques such as clock gating and sleep mode operation give rise to transient currents in the power supply. Such power fluctuations can require changes of thousands of amps within a few microseconds. The resulting current surge between the processor and the power regulation circuitry can create unacceptable spikes in the power supply voltage[0039]$\left(e.g.\mathrm{dv}=\mathrm{IR}+L\frac{i}{t}\right).$

  
• The package on which the device (die) typically resides must be connected to other circuitry in order for it to communicate and get power into and out of the device. Because the current slew-rates may be very high, a low impedance interconnection system is often needed to reduce voltage excursions between the power source and load which, if left unchecked, may cause false switching due to the reduced voltage seen at the load from a large voltage drop across the interconnect.[0040]
• The technology of vertically stacking electronic substrates has been utilized for a number of years. As one example, U.S. Pat. No. 5,734,555, issued to McMahon (which is hereby incorporated by reference herein) discloses a method by which a circuit board containing power conversion elements is coplanar located over a circuit board containing an integrated circuit. The interconnect between the power conversion substrate and the integrated circuit substrate utilizes pins which do not provide a low impedance power path to the integrated circuit. Further, the McMahon device cannot be easily disassembled because the pins are permanently connected to the substrates. As another example, U.S. Pat. No. 5,619,339, (which is hereby incorporated by reference herein) issued to Mok discloses a printed circuit board (PCB) is vertically displaced over a multi-chip module (MCM) with electrical communication between the two substrates (the PCB and the MCM) established by a compliant interposer which contains “fizz buttons” which communicate with pads located on each substrate. Although such an approach does provide for disassembly of the two substrates, e.g., the MCM and the PCB, the approach does not provide for large ‘Z’ axis compliance to accommodate manufacturing tolerances, and does not teach the use of a contact design that is capable of handling large amounts of DC current. Further, this design requires the use of a compliant interposer. In order to handle such large amounts of current, the number of contacts would have to be increased dramatically, which would increase the inductance between the source and the load device. Furthermore, such a large array of such contacts would require a large amount of force to be applied to maintain contact and will not result in a space-efficient design.[0041]
• From the foregoing, it can be seen that there is a need for a low impedance power interconnect between the power dissipating device and the power source. It can also be seen that this impedance must be low in inductance and resistance throughout a wide frequency band in order to ensure that the voltage drops across the interconnect are mitigated across it during dynamic switching of power. It can also be seen that the interconnect should provide large ‘z’ axis compliance and permit separation of the assembly without desoldering or similar measures.[0042]
SUMMARY OF THE INVENTION
• To address the requirements described above, the present invention discloses an apparatus for providing power to a power dissipating device. The apparatus comprises a first circuit board and a second circuit board, and a plurality of compliant conductors disposed between first circuit board and the second circuit board.[0043]
• The first circuit board includes a power conditioner circuit, and a first side and a second side having a plurality of first circuit board contacts thereon. The first circuit board contacts include a first set of first circuit board contacts communicatively coupled to a first power conditioner circuit connector and a second set of first circuit board contacts communicatively coupled to a second power conditioning circuit connector.[0044]
• The second circuit board includes the power dissipating device mounted thereto and a plurality of second circuit board contacts disposed on a first side of the second circuit board facing the second side of the first circuit board. The second circuit board also includes a first set of second circuit board contacts communicatively coupled to a power dissipating device first connector and a second set of second circuit board contacts communicatively coupled to a second connector of the power dissipating device.[0045]
• The plurality of z-axis compliant conductors includes a first set of z-axis compliant conductors disposed between the first set of first circuit board contacts and the first set of second circuit board contacts and a second set of z-axis compliant conductors disposed between the second set of first circuit board contacts and the second set of second circuit board contacts.[0046]
• The first set of first circuit board contacts, the first set of z-axis compliant conductors, and the first set of second circuit board contacts define a plurality of first paths from the first circuit board to the second circuit board and wherein the second set of circuit board contacts, the second set of z-axis compliant conductors, and the second set of second circuit board contacts define a plurality of second paths from the first circuit board to the second circuit board.[0047]
• The present invention provides a spring-like structure which disconnectably connects between two or more substrates (such as a printed circuit board or IC package) whereby the connection is disconnectable at least on one of the two sides. The interconnection system provides for an extremely low impedance through a broad range of frequencies and allows for large amounts of current to pass from one substrate to the next either statically or dynamically. The interconnection system may be located close to the die or may be further away depending upon the system requirements. The interconnection may also be used to take up mechanical tolerances between the two substrates while providing a low impedance interconnect. Due to the low impedance connection, the design permits the displacement of bypass capacitors on the circuit board having the power dissipating device, and placement of these capacitors on the circuit board having the power conditioning circuitry, resulting in ease of manufacturing and improved reliability of the power dissipating device assembly.[0048]
• The present invention reduces or eliminates the need for supporting electronic components for the power dissipating device on the substrate, since the interconnect impedance between the power source and the electronic device is sufficiently low so that all or most of the supporting electronics can be located on the substrate containing the power source. Since the present invention does not use any socket connectors to supply power to the device, such socket connectors are freed to provide additional signals.[0049]
BRIEF DESCRIPTION OF THE DRAWINGS
• Referring now to the drawings in which like reference numbers represent corresponding parts throughout:[0050]
• FIGS. 1A and 1B are diagrams showing exploded views of the interconnection system as placed between two substrates, e.g., a voltage regulator module (VRM) mounted over a power dissipating device;[0051]
• FIGS.[0052]1C-1E are diagrams showing different electrical arrangements of the contacts;
• FIGS.[0053]2A-2C are diagrams showing exploded views of the interconnection system as placed between a processor substrate and a motherboard, the interconnection system occurring on the sides of the processor substrate;
• FIG. 2D are diagrams depicting a view of section A-A of FIG. 2C;[0054]
• FIGS.[0055]3A-3C are diagrams showing a simple stackup cross-section of the interconnection system as placed between two substrates;
• FIGS. 4A and 4B are diagrams showing an embodiment of a cantilever beam that may be used to implement the z-axis compliant contacts;[0056]
• FIGS.[0057]5A-5D are diagrams showing further embodiments of a cantilevered beam in which the different features of the beam construction are utilized to reduce the connection inductance of the compliant contacts;
• FIG. 6A is an isometric view of an assembly showing multiple pairs of z-axis compliant conductors arranged in two rows within an insulating frame structure;[0058]
• FIG. 6B is an isometric view of a pair of spring contacts in a scissor configuration;[0059]
• FIG. 6C is a section view showing how spring contacts arranged in a scissor configuration can be used to interconnect the first and second circuit boards;[0060]
• FIG. 6D is a plan view of the substrate in the embodiments illustrated in FIGS.[0061]6A-6C;
• FIG. 6E is a diagram illustrating an another embodiment of the z-axis compliant conductors and contact pads on the first circuit board;[0062]
• FIG. 6F is a diagram illustrating another embodiment of the invention in which a continuous linear contact pads on the second circuit board are used without opposing scissor configuration z-compliant conductors;[0063]
• FIG. 6G illustrates an embodiment of the present invention wherein the z-axis compliant conductors are not permanently affixed to any contacts on either the first circuit board or the second circuit board, thus permitting easy disassembly;[0064]
• FIG. 6H is a diagram presenting another embodiment of the present invention in which an x-axis compliant conductor interfaces with edge contacts on the second circuit board;[0065]
• FIG. 6I is a diagram presenting another embodiment of the z-axis compliant conductors having reduced impedance;[0066]
• FIG. 6J is a diagram presenting a cross section of the embodiment illustrated in FIG. 6I;[0067]
• FIG. 7 is a plan view illustrating another embodiment of the present invention utilizing multiple rows of z-axis compliant conductors;[0068]
• FIG. 8 is a diagram presenting a prior art stack up arrangement of a microprocessor substrate;[0069]
• FIG. 9 is a diagram presenting an improved power distribution system made possible by the present invention; and[0070]
• FIG. 10 is a diagram illustrating an embodiment of the present invention wherein the power conditioning unit is partitioned to provide multiple power signals, each differing in phase, and each being distributed to different sides of the power dissipating device.[0071]
• FIG. 11A is a diagram of a section view of direct power attachment to a substrate.[0072]
• FIG. 11B is a top view of FIG. 11A.[0073]
• FIG. 11C is a diagram of a blow-up of a section of view A-A in FIG. 1A.[0074]
• FIG. 12 is a diagram of a split-wedge washer.[0075]
• FIG. 13 is a diagram that shows the attachment of a section of FIGS. 11C and 12 combined.[0076]
• FIG. 14 is a diagram of a high level assembly view.[0077]
• FIG. 15 is a diagram of a low inductance frame standoff.[0078]
• FIG. 16 is a diagram of an assembly view with low inductance standoff and interface board.[0079]
• FIG. 17 is a diagram of a cross section view with low inductance standoff and interface board.[0080]
• FIG. 18 is a diagram of an exploded view of FIG. 16.[0081]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
• In the following description, reference is made to the accompanying drawings which form a part hereof, and which is shown, by way of illustration, several embodiments of the present invention. It is understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.[0082]
• The present invention describes a low impedance interconnection system operably placed between the two substrates whereby the interconnect is either placed to one side of the device or devices or the interconnect system circumferentially surrounds these elements.[0083]
• When a load change occurs in operation on one of these devices, a voltage will occur across the interconnect that can be described as shown below:[0084]$\Delta V=L\frac{\partial I_{\mathrm{Step}}}{\partial t}+{\mathrm{RI}}_{\mathrm{Step}}$

  
• wherein ΔV is the voltage across the interconnection system, L is the series loop inductance of the interconnect, R is the interconnect resistance, and I[0085]_stepis the step-change in load current.
• As shown above, the output voltage change ΔV increases linearly with the loop inductance L. Further, where rapidly changing currents are involved (as is the case with step changes in current, it is critically important that the interconnect system provides for a low inductance between the two substrates. During such a current step, reducing the loop inductance L reduces the ΔV that results from current changes, thus allowing power to be efficiently delivered from the current source to the load.[0086]
• FIGS. 1A and 1B are diagrams illustrating a[0087]structure10 which provides a power path from a power conditioning circuit to a high performance electronic power dissipating device via a plurality of paths, thus yielding very low impedance. Thestructure10 comprises amain board assembly14, anelectronic assembly13 having a high performance electronic power dissipating device, apower conversion assembly12 and aheat dissipating assembly11.
• The[0088]electronic assembly13 comprises a power dissipating device such as amicroprocessor134 assembled onto printed circuit board (PCB) or substrate130 (hereinafter, the terms “printed circuit board”, “circuit board” and “substrate” are used interchangeably). Thecircuit board130 includes one or more circuit traces which deliver power to the die of themicroprocessor134. Thecircuit board130 also includes circuit traces which route signals to a matrix ofpins131 communicatively coupled to microprocessor134 I/O connectors. Themicroprocessor134 is typically provided with a thermallyconductive lid133 in which the inside surface of the lid is in close thermal contact with the top of the die of the electronic device and the perimeter of the lid is sealed and attached to the surface of thesubstrate130. Although the package described herein is provided with a lid the present invention does not preclude the use of unlidded package construction methods.
• The signal pins[0089]131 engage with asocket141 which is mounted to amain board140 both of which are a part ofmain board assembly14. Signals from themain board assembly14 are dispersed to other electronic devices to form a complete operating unit such as a computer. Other methods may be employed to route the signals from thesubstrate130 to themain board140 which may not utilize either pins or sockets.
• The[0090]circuit board130 includes a plurality ofcontacts132. Thecontacts132 can include power contacts and/or ground contacts. The power and ground contacts are communicatively coupled to power connectors or pads135-137 of thepower dissipating device134, respectively.
• FIGS.[0091]1C-1E disclose several embodiments of the present invention showing different electrical arrangements of thecontacts132. In one embodiment, the power contacts include positivepolarity power contacts132A that are communicatively coupled to a positive polarity power connector or pad135 on thepower dissipating device134 and negativepolarity power contacts132B that are communicatively coupled to a negative polarity power connector or pad136 on thepower dissipating device134. Theground contacts132C are communicatively coupled to a ground connector or pad137 of thepower dissipating device134.
• In one embodiment of the present invention (illustrated in FIGS. 1D and 1E), the[0092]power contacts132A and/or132B are interleaved with theground contacts132C. In FIG. 1D, eachpower contact132A and/or132B is adjacent aground contact132C, and eachground contact132C is adjacent apower contact132A and/or132C. In another embodiment of the present invention, the positivepolarity power contacts132A are interleaved with negativepolarity power contacts132B in the same way. The foregoing interleaved or alternating design substantially reduces undesirable electrical impedance of the power path.
• In the embodiments shown in FIGS. 1A and B, the[0093]contacts132 are disposed around the perimeter of the electronic device and are a part of thesubstrate structure130.
• The[0094]substrate130 generally comprises a number of conductive layers that are used to route both signals and power and ground. When routing power, layer pairs adjacent to each other form a very low electrical interconnect impedance between thepower pads132 and the die power and/or ground connectors (e.g. pads) of theelectronic device134. These layer pairs are connected to thepower pads132 in a closely coupled arrangement to the planes. A further description of the conductive layers and their arrangement with respect to the z-axiscompliant conductors124 is presented in conjunction with FIGS.3A-3C below.
• A[0095]power conversion assembly12 is disposed directly above (along the z-axis) theelectronic assembly13. Thisassembly12 comprises an interconnect substrate commonly referred to as a printed circuit board (PCB)120, a power conversioncircuit having components121 such as switching transistors, transformers, inductors, capacitors, and control electronics;output capacitors123 and acompliant conductor assembly122 having a plurality of z-axiscompliant conductors124. These power conversion components can be segmented according to the VRM circuit topology to optimize the impedance and power flow through the power conditioning circuitry. For example, in the case of a multiphase VRM, the topology of the VRM can be designed to provide one or more of the phases, each at the appropriate connector, thus minimizing the interconnect impedance and the required circuit board real estate. The plurality of z-axiscompliant conductors124 circumscribe and interface with thecontacts132 on theelectronic assembly13 to provide a conductive path between thepower conversion assembly12 and theelectronic assembly13 having very low inductance. Further, theconductor assembly122 permits thepower conversion assembly12 and theelectronic assembly13 to be disassembled and separated without desoldering.
• A significant advantage to injecting power to the power dissipating device in a circumferential manner is that the current in any portion of the power planes of the substrate used to deliver power to the power dissipating device can be reduced significantly. As an example, if four compliant contact assemblies are located on each of the four sides adjacent to the power dissipating device, then, the maximum plane current is one-quarter the total current of the device assuming that the current in the device has a uniform current density at its interface to the substrate. Furthermore, the path length is significantly lower than other methods to deliver power to the substrate further reducing the voltage drop in the power delivery planes of the substrate (see, for example, U.S. Pat. No. 5,980,267, which is hereby incorporated by reference herein). Generally, the power delivery regulation budget is fixed and the power planes of the power dissipating device substrate are adjusted to maintain the desired budget either by increasing the number of planes or increasing the thickness of the planes as the current is increased or the budget is decreased. Circumscribed power delivery provides for significant reductions in both plane thickness and/or total number of planes.[0096]
• In the illustrated embodiment, the[0097]conductors124 of theconductor assembly122 are attached (e.g. soldered or bonded) to thesubstrate120. Further, theconductors124 of theconductor assembly122 are electrically coupled to thecontacts132 ofsubstrate130 through mechanical pressure applied to urge thesubstrate120 towards thesubstrate130.
• Other variations of this structure are possible. As an example, the[0098]compliant conductor assembly122 could be permanently attached tosubstrate130 with contact pads onsubstrate120 or, contact pads could be place on bothsubstrates120 and130 and the compliant contact could provide pressure contacts to both substrates. Note that some of the interconnect compliant contacts may be used for control and sense interfaces between the power circuitry inassembly12 and theelectronic assembly13. Finally, note thatsubstrate120 has an aperture to allow for thelid133 to pass through and thermally couple to theheatsink assembly11.
• In the past, it has been necessary to position bypass capacitors on[0099]substrate130 to provide for the transient current demands of the electronic device on the substrate. This has reduced the reliability of theelectronic assembly12 which is relatively much more expensive than the other assemblies. Thus, it is desirable to increase the reliability of this assembly to the highest degree possible. Because the interconnect inductance of thecompliant contacts122 is extremely low it is possible to position thenecessary bypass capacitors123 on thepower conversion substrate120. Further, note that thesecapacitors123 are located directly above theconductor assembly122 reducing the interconnect path length between the connector and the capacitors123 (thus decreasing the impedance) to approximately the thickness of thesubstrate120.
• [0100]Heatsink assembly11 is used to remove heat from both theelectronic assembly13 and thepower conversion assembly12.Heatsink assembly11 comprises a finned structure100, which is attached or is a part ofbase111. Heat slug ormesa112 is attached to or is a part ofbase111 and is used to both disperse heat from thelid122 and to mechanically conform to the proper vertical displacement between the lid of themicroprocessor134 and theheat sink base111. Thermal interface materials may be used to thermally couple thelid133 and themesa112 to theheatsink base111 and thesubstrate120/power components121. Theheatsink base111 may also comprise cavities to accommodate any components on the top side ofsubstrate120 such ascapacitors123.
• FIGS. 2A and 2B illustrate a[0101]structure15 which is similar to structure10 except the power conversion circuit components are located directly on themain board assembly18. The structure comprises themain board assembly18, a high performanceelectronic assembly17 and aheat dissipating assembly16.
• [0102]Electronic assembly17 is similar toelectronic assembly13 withsubstrate170,lid171 andpin matrix172. However,contacts173, which can be used as power pads, are located on the bottom side ofsubstrate170. In the illustrated embodiment, the contacts are disposed around the perimeter of theelectronic device172.
• [0103]Main board assembly18 comprises amain board180 withpower conversion components181 making up a power conditioner circuit andcompliant conductor assembly182 having a plurality of z-axiscompliant conductors185 circumscribing asocket183. As was the case withassembly13,bypass capacitors184 are placed onmain board180 directly under and in electrical communication with the z-axiscompliant conductors185.Heat sink assembly16 is disposed above and is thermally coupled to theelectronic assembly17. Theheat sink assembly16, which removes heat from theelectronic assembly17, comprises afinned structure160 andbase161.
• Thermal interface material can be used between the base[0104]161 and thelid171 to thermally couple the base161 and thelid171. Thermal energy may also be removed from thepower conversion components181. This can be accomplished by providing a thermal conduction path from the bottom of the main board to an adjacent chassis surface. This can also be accomplished by simply providing sufficient airflow around these components so as to directly cool them. It is also noted that as was the case with the embodiments illustrated in FIGS. 1A and 1B, where ultimate electrical performance is not needed,compliant conductor assembly182 andpower components181 may not need to circumscribesocket183 and may be located on less than all four sides ofsocket183.
• FIG. 2C is a diagram of a[0105]structure15 that is similar to that shown in FIG. 2A except thatcompliant conductor assembly182 are at least partially enclosed and contained within thesocket186 which mounts to themain board180. This facilitates the assembly ofmain board assembly18.
• FIG. 2D is a diagram presenting a section view (A-A) along one side of[0106]socket186 showing thesocket186 and thecompliant conductor182. Thesocket186 includes asection186A that secures individual z-compliant conductors182 in place by overmolding abase extension187 of theconductors182.Socket186 includes a pluralityfemale connectors193 which accept pins that are communicatively coupled to the power dissipating device. Each female connector is also communicatively coupled to solder balls, which are reflow soldered tocircuit pads190 onmain board180. The power dissipating device is thus electrically connected to themain board180, which, as shown in FIG. 2C, includespower components181 for power conditioning.
• The[0107]base192 ofcompliant contact182 is soldered topower contact pad189. This is preferably accomplished during the same reflow solder step used to couple thesolder balls191 to thecircuit pads190 on themain board180. Not shown are power connection paths to internal layers ofmain board193 fromsurface contact189.
• FIGS.[0108]3A-3C illustrate an embodiment of astackup30 configured to deliver power from apower conversion PCB301 to aprocessor substrate300. It will be recalled that a preferred embodiment of power delivery is to deliver power through alternating or interleaved contacts so as to reduce the interconnect impedance.
• FIG. 3A is a diagram showing a plan view of the[0109]stackup30 with theupper PCB300 removed, showing the arrangement of adjacent z-axiscompliant conductors305 and321 in the x-y plane. In one embodiment illustrated, the conductors are spaced approximately50 mils apart, to decrease impedance. Further, the illustrated z-axis compliant (or, equivalently, compliant)conductors305 and321 are cantilevered beams having bases that are soldered or other wise affixed to contacts (or circuit pads)303 and320, respectively. The other end of the compliant contact is pressed against the contact (or circuit pad) of theupper circuit board300.
• FIG. 3B is a diagram illustrating a cross section (A-A) of one polarity of power delivery, e.g., the positive polarity, while FIG. 3C illustrates a cross section (B-B) of the negative polarity, the two sections adjacent to one another forming the preferred interleave pattern.[0110]
• Referring to FIG. 3B,[0111]power conversion PCB301 containspower layers312 and313 whereinlayer312 represents the negative power layer, andlayer313 represents the positive power layer the two of which are in close proximity to one another to effect a low impedance power interconnect. A plated through hole (PTH)314 or similar conductor connects thepositive power layer313 to asurface pad303. Z-axiscompliant contact305 is shown as a cantilever beam having a base that is soldered304 tosurface pad303. The other end of thecompliant contact305 is pressed againstcircuit pad302 on the surface of thesubstrate300. Abypass capacitor322 is located below thecompliant contact305 and on the side of thefirst circuit board301opposite contact303. Thebypass capacitor322 includes first and second connectors such as conductive end metalization features306 and317, which are surface mounted and electrically coupled topads307 and316, respectively onPCB301.Circuit pad307 is connected to layer313 through an extension ofPTH314.Circuit pad316 is connected to layer312 through an inter-connector such as the illustrated blind via315. Preferably, thebypass capacitor322 is disposed directly below the compliant contact and associated structure (e.g. displaced from the structure in substantially only the z-axis), as this offers lower inductance than embodiments where thebypass capacitor322 is displaced laterally (in the x and/or y axes as well).
• In the illustrated embodiment,[0112]layer308 ofsubstrate300 is assigned a negative power polarity whilelayer309 ofsubstrate300 is assigned a positive power polarity. Likelayers312 and313, in thePCB301,layers308 and309 are in close proximity to one another to achieve a low impedance power interconnect. A power dissipating device located onsubstrate300 can therefore receive power throughlayers308 and309 of thesubstrate300.Circuit pad302 is electrically connected to layer309 through one or moreblind vias310 thus forming a low impedance interconnect fromlayer313 throughPTH314 to pad303 then throughcompliant contact305 to pad310 and then throughblind vias310 tolayer309. Note that layers308 and309 are located on or near the surface ofsubstrate300. This frees thesubstrate300 to use the other layers (represented as layers311) for signal interconnect for the power dissipating device without topological complications that arise from designs in which the power and ground layers are disposed away from the bottom surface of the substrate.
• Referring again to FIG. 3C, (which illustrates a cross section (B-B) of the negative polarity, thus forming the preferred interleave pattern with the cross section A-A in FIG. 3B) the negative polarity power interconnect is achieved by[0113]PTH319 connectinglayer312 to surface contact (e.g. pad)320 adjacent the positive polarity surface contact or pad303 on the inner side ofPCB301.Compliant contact321 is soldered304 or otherwise coupled tosurface pad320 while the other end of thecompliant contact321 is pressed against (surface)layer308 ofsubstrate300. Note that contact point forcompliant contact321 is shown as a point (or more specifically, a line segment along the y-axis) onlayer308 however, this contact area may be a unique area oflayer308 in which the surface is locally processed to provide special characteristics for this contact point such as gold plating over a nickel undercoat to improve the contact characteristics of the contact.Surface pad310 may be processed in a similar manner.
• Finally,[0114]capacitor322 may be the same bypass capacitor as shown in FIG. 3B or an additional bypass capacitor connected toplanes312 and313 through an extension ofPTH319 tosurface pad316 and blind via318 tosurface pad307. The result of the above is to provide a very low compact and low inductance compliant connection betweenPCB301 andsubstrate300 with the two substrates being separable. Furthermore, because the interconnection method provides for a very low inductance connection it is possible to either eliminate or considerably reduce bypass capacitors on thesubstrate300 containing the power dissipating device.
• Because such substrates are constructed such that the interconnects between[0115]layers308 and309 areblind vias310 which pass only between layer to layer and not through the entire substrate, signal layers311 and additional power/ground layers (if any) will not be permeated with large numbers of via interconnects (such as310) as would be if power entered from the top side ofsubstrate300. This has the benefit of freeing up signal routing space in these layers (such as311) where the number of via interconnects are substantially reduced due to the entrance of power to the bottom side ofsubstrate300.
• The embodiment shown in FIGS.[0116]3A-3C is superior to other interconnect designs wherein the capacitor is not placed below the z-axis compliant conductors and on the opposing side of the circuit board with the power conditioning circuitry. For example, if the capacitive element were placed on the second side of the first circuit board (the same side as the z-axis compliant conductor) and adjacent to the spring members, the length of the conductive path and hence the impedance of the interconnect would include not only the vias or PTHs traversing in the z-axis, but also traces or planes in the x-y plane. By placing thecapacitive element322 on the side of the circuit board opposing the z-axis compliant conductor and directly over (or under) the z-axis compliant conductor, the length of the conductive path (and hence the impedance) is substantially reduced. The conductive path length (and hence, the impedance) is further reduced by selecting the span of thecapacitive element322 and related structures (e.g. pads307 and316) to be substantially the same as the span (the length in the longitudinal, or x-axis, direction) of the z-axis compliant conductor. With the length of the conductive path minimized capacitive elements on the second circuit board (or substrate) can be removed, which improves manufacturability and reliability as well.
• FIGS. 4A and 4B illustrate an isometric view of one embodiment of a U-shaped z-axis[0117]compliant conductor40. Theconductor40 comprises a base401 which can be soldered or otherwise bonded to a substrate whilecontact surface400 is pressed against a pad on an opposite substrate. FIG. 4A shows theconductor40 in the uncompressed state while FIG. 4B shows the conductor in the compressed state. In the illustrated embodiment, thecontact surface400 is formed by an S-shaped portion having a curved surface. The curved surface assures that theconductor40 presents a surface parallel to the circuit board above thecontact40.
• FIGS. 5A and 5B illustrate an isometric view of another embodiment of the z-axis[0118]compliant conductor50. The conductor has a base orfirst shaft portion502 having afirst end504 and asecond end506 distal from thefirst end504. Thebase502 is generally soldered to a substrate contact. AU-shaped bend portion508 is coupled to thefirst shaft portion502. TheU-shaped bend portion508 includes a first end510 adjacent and coupled to the first shaft portionsecond end506 and asecond end512. Asecond shaft portion514 is coupled to theU-shaped bend portion508. The second shaft portion includes afirst end516 adjacent and coupled to the U-shaped portionsecond end512. Second shaft portion is adjacent and coupled to a secondU-shaped bend portion520. The second U-shaped bend portion comprises afirst end522 adjacent and coupled to thesecond end518 of thesecond shaft portion514 and asecond end524. The second U-shaped bend portion is adjacent and coupled to athird shaft portion526 disposed between thefirst shaft portion502 and thesecond shaft portion514. Thethird shaft portion526 includes afirst end528 adjacent and coupled to the second end of the secondU-shaped bend portion520 and asecond end530 distal from thefirst end528.Bend portion532 is disposed at thesecond end530.
• The[0119]conductor contact surface534 is pressed against a pad on an opposite substrate. The contact beam is then wrapped around and returns to the upper surface ofbase502 forming asecondary contact536 to thebase502. This embodiment has improved (reduced) connection inductance compared to the embodiment illustrated in FIGS. 4A and 4B because the mutual coupling betweenpath538 andpath540 is relatively low which establishes semi-independent and parallel connection paths betweencontact surface534 and thebase502.
• FIGS. 5C and 5D illustrate an isometric view of still another embodiment which is similar to that described in FIGS. 5A and 5B. FIG. 5C illustrates this embodiment in the uncompressed state whereas FIG. 5D illustrates the embodiment in the compressed state. This embodiment further comprises a third[0120]u-shaped bend portion557 coupled to thedistal end530 of thethird shaft portion526, afourth shaft portion555 coupled to the thirdu-shaped bend portion557. Thefourth shaft portion555 includes acontact portion556 distal from the thirdu-shaped bend portion557. When compressed, thecontact portion556 establishes an additional third path between thecontact point552 and the base502 that passes through thefourth shaft portion555, the thirdu-shaped bend portion557 and to thebase502. This embodiment has still further reduced inductance over the embodiment in FIGS. 5A and 5B because there are now threesemi-independent paths551,553 and555 between thecontact surface552 and the base550.
• Individual conductors can be grouped so as to ease assembly of the conductor onto a PCB or substrate using soldering or other joining processes. One method is to extend a surface feature (such as[0121]401) of the conductor to an area outside of the active portion of the conductor which is joined to a common bar during the stamping and forming fabrication process and then to overmold this extended feature with an insulating plastic resin up to the common bar but not including the bar. The bar is then cut off leaving a set of individual isolated contacts that are mechanically joined and can be handled during assembly as one unit.
• FIGS.[0122]6A-6C illustrate another embodiment of the invention in which z-axis compliant conductors similar to those shown in FIGS. 5A and 5B are arranged in a scissor configuration.
• FIGS. 6A and 6C illustrate an isometric view of the[0123]assembly60 showing pairs of z-axiscompliant conductors600A,600B,600C,600D (hereinafter alternatively referred to as first set or row of z-axis compliant conductors600) and601A,601B,601C,601D (hereinafter alternatively referred to as second set or row of z-axis compliant conductors601). Each of the conductors in eachrow600,601 of theassembly60 comprises aninterface portion668 and669 disposed away from the base of the conductor that is urged against the contact on the second circuit board. Further, eachrow600,601 ofassembly60 is preferably assigned a separate power polarity, e.g.,row601 might be assigned negative power polarity androw600 might be assigned a positive power polarity. The conductors of thefirst row600 and thesecond row601 are thereby interleaved to form conductor pairs resulting in a low inductance power path.
• Each of the[0124]conductors600,601 are held in place by an assembly such asovermold frame assembly602 having anouter portion602A and aninner portion602B. In the illustrated embodiment, the assembly holds the z-axis compliant conductors in place about at least a portion of the periphery of the power dissipating device.Hole667 is an alignment feature that may be desirably placed in the moldedassembly60 to align theassembly60 to the PCB (e.g. PCB120) during soldering.
• FIG. 6B illustrates an isometric view of a pair of[0125]spring contacts600A,601A in the scissor configuration. Thebase612 of each contact in the row of contacts is extended to overmold602 as described in the preceding paragraph to simplify assembly. In this arrangement, overmoldouter portion602A and overmoldinner portion602B are desirably joined at their respective ends to form the overmold assembly. An advantage of this configuration is that there is no resulting net torsional force about the y or z axes.
• FIG. 6C is a section view (section A-A illustrated in FIG. 6A) presenting an example where the scissor contacts described above are arranged in a[0126]stackup61 to deliver power from apower conversion PCB608 to aprocessor substrate609. Thecircuit pads610 onPCB608 require isolation between adjacent pads in the y-direction, because they will have alternating positive and negative power polarities. However, of significant importance is that contactingpads605 and606 on theprocessor substrate609 can be arranged to be a continuous linear pad in the y-direction. This provides for relaxed tolerances in the alignment of theprocessor substrate609 to thepower conversion substrate608 or PCB, and reduces the net torsional force on the two substrates. Note thatbypass capacitor607 may be installed beneath thecontact arrangement61 in a manner similar to that as described in FIG. 3.
• One technique of reducing the effective inductance of a multi-conductor connector is to assign adjacent conductors opposing current polarities. The magnetic fields of the opposing currents partially cancel each other, thus reducing the effective inductance of the overall connection. However, the effectiveness of this configuration is strongly dependent upon the configuration of the multiple conductors. In a simple configuration wherein the opposing faces of adjacent conductors are relatively narrow compared to their separation, the magnetic coupling between the conductors does not provide a substantial amount of magnetic field cancellation. However, if the separation distance between the substrates in a parallel plane connection scheme such as illustrated in FIG. 6C is small relative to the width of the conductors, then the magnetic field coupling between the planes becomes more significant, thus resulting in a lower inductance. This effect can be enhanced by arranging the conductors in each[0127]row600,601 of the connector in an opposing configuration as shown in FIG. 6B. Then, the current from one pair of conductors (e.g.600A and601A) now flows across each end of the connector bases and in internal planes of thesubstrates608 and609. This current magnetically couples with the current flowing in the non-base portions of the scissored conductors (600A and601A), reducing the overall inductance of the connection betweensubstrates609 and608. For the effective inductance of this scissored arrangement to be less than the effective inductance of a non-scissored arrangement, the angle that the conductors make with the PCB/substrate plane must be less than a particular value θ=f (t, w, s) wherein t is the conductor thickness (here, assumed uniform), w is the width (also assumed uniform) and s is the separation between adjacent conductors.
• FIG. 6D is a plan view of[0128]substrate609 further illustrating the concept of thecontinuous pads605 and606 that surroundpower dissipating device613. In the illustrated embodiment, thepads605 and606 are formed into a continuous rings, one inside the other.
• FIG. 6E illustrates a variation on the scissor contact design described in FIGS.[0129]6A-6C. Abase portion670 of an elongated z-axis compliant conductor630 (of a scissor pair) is soldered to pad632 onPCB608. The uppercantilevered beam portion634 ofcompliant conductor630 is pressed againstcontact pad631 ofsubstrate609 as previously described. However, in this configuration, rather than the secondary contact wrapping around and returning to the top surface of thebase502, thecontact630 wraps aroundportion635 ofcompliant conductor630 returning to aseparate contact pad633 onPCB608. Although bothcontact pads632 and633 are in electrical communication with the same power conditioning circuit, (e.g. through vias and conductive layers in the substrate609) the advantage of this configuration is that the mating surfaces636 ofcontact pad633 andcontact portion635 are not involved in the soldering process and as a consequence there is no risk that solder used to couple thebase670 of theconductor630 to thepad632 may flow into the contact region of thesecondary contact633. Additionally, because the secondary contact is further removed from the initial contact path there is less mutual coupling between the two contact paths which results in a lower overall connection inductance.
• FIG. 6F illustrates another embodiment of the present invention. In this embodiment, the[0130]stackup configuration64 includes a first and second set of U-shaped z-axis compliant conductors (640 and641, respectively) that are displaced from one another along the x-axis. The x-axis displacement allowscontact pads644 and645 to be constructed in a continuous linear fashion onsubstrate609 similar to the embodiment shown in FIGS. 6A, 6B and6C, without requiring that the first and second set ofconductors640,641 be oriented180 degrees from each other. Z-axiscompliant conductor640 is soldered or otherwise connected to contactpad642 onPCB608 which is connected to one polarity of a power circuit (e.g., as shown in FIGS.3A-3C) while z-axiscompliant conductor641 forward ofconductor640 and displaced fromconductor640 in the x-axis is also soldered or otherwise electrically coupled tocontact pad643 of a second polarity of a power circuit (also as shown in FIGS.3A-3C).
• The embodiments illustrated in FIGS.[0131]6A-6F have numerous advantages. First, as described above, they permit substantial misalignment between the z-axis compliant conductors and the contacts on the opposing circuit boards in the direction of the adjacent conductors (e.g. in the y-axis direction in FIGS.6B-F). Second, a nearly contiguous line of vias disposed through the pad region can be used for connecting the contacts to conductive planes within the circuit board, thus allowing a lower interconnect impedance in thesubstrate609. Third, as described further below with respect to FIGS. 6I and 6J, the arrangement shown in FIGS.6A-6C allows for improved electromagnetic coupling between each spring over arrangements where each of the z-axis compliant conductors are arranged in a single row.
• FIG. 6G illustrates a[0132]stackup configuration65 in which the z-axis compliant conductor is removably attached (e.g. not soldered, bonded, or otherwise permanently attached) to eithersubstrate609 orPCB608. In this configuration insulating (plastic, for example)overmold element652 retainscompliant conductor651. Additional conductors (disposed in the y direction) are also retained byplastic element652, forming a contact assembly that can be installed at the time of assembly ofsubstrate609 andPCB608. As before,section653 ofcompliant conductor651 is pressed againstcontact pad605 onsubstrate609 andsection654 is pressed againstcontact pad655 ofPCB608 completing one half of a power circuit betweenPCB608 andsubstrate609. The other half of the power circuit is completed by the adjacent conductor (displaced fromconductor651 in the y-axis). It is also recognized that an arrangement such as that which is shown in FIGS. 6F and 6G may also be applied in a similar manner as to the arrangement in FIG. 6C, with opposing or staggered conductors, using a multiple-part or shaped overmold.
• FIG. 6H illustrates still another arrangement wherein a compliant conductor may be used to provide power to a power dissipating device. In this arrangement, the plurality of first[0133]circuit board contacts664 are disposed on the edge of the first circuit board. While only asingle contact664 is shown, a plurality of contacts, electrically isolated from one another and distributed in the y-axis, are disposed on the edge of thefirst circuit board609.Section661 of each of the x-axiscompliant conductors660 is urged against anadjacent side contact664 which is electrically connected to internalconductive plane662 ofsubstrate664. The internalconductive plane662 is electrically coupled to the power dissipating device (via conductive planes, vias, and the like) to feed power to a power dissipating device disposed on thesubstrate664. The other end ofconductor660 is soldered or otherwise electrically connected to contactpad665 ofPCB608. Electrical connection between thecontact pad665 and to power layers of thePCB608 can be made by a combination of plated through holes, vias and interconnecting conductive layers in thePCB608.
• Only one contact is shown in the section view of FIG. 6H. However, it will be understood that a multiplicity of[0134]compliant contacts660 can be arranged along the y-axis and the multiplecompliant contacts660 can interface with a corresponding multiple ofedge contacts664, each electrically isolated from the others, to form multiple power connections betweenPCB608 andsubstrate664, wherein alternatingcontacts664 connect to alternatepolarity power plane663. In a preferred embodiment, thecontacts660 and related structures circumscribe all sides ofsubstrate664 to form a very low impedance power interconnect path betweenPCB608 andsubstrate664. Theconductor660 can also be designed with a bend to restrain thefirst circuit board609 in place, if desired.
• FIG. 6I illustrates one embodiment of the z-axis compliant conductor design. The illustrated z-axis compliant conductor pair which form a part of a larger array of conductors.[0135]Conductor671 carries current in of one polarity whileadjacent conductor672 carries current in an opposite polarity. As before, a practical method of assembling such an array is to join the individual conductors with an overmoldedplastic resin673 that supports theconductors671 and672. Of note is that each of theconductors671 and672 are provided with aslit677 and680 which creates two separate current paths inconductors671 and672 over a substantial portion of the length of the conductors. These separate current paths are identified as675,676 forconductor671 and678 and679 forconductor672. The result of this arrangement is to reduce the overall connection inductance between a PCB and a substrate.
• The reduced connection inductance of FIG. 6I can be explained by referring to FIG. 6J which illustrates a section view through the conductor sections as indicated by A-A. The top portion of FIG. 6J illustrates the arrangement where there is no slit, forming[0136]conductors681 and682, whereas the bottom portion illustrates the arrangement where theslits677 and680form conductors685,686,687 and688. The inductance of each conductor,681 or682, in the configuration without the slit is:${\mathrm{<figure-callout\; label="L"\; filenames="US20030214800A1-20031120-D00023.png"\; state="\{\{state\}\}"><figure-callout\; label="L"\; filenames="US20030214800A1-20031120-D00023.png"\; state="\{\{state\}\}">L</figure-callout></figure-callout>}}_{681,682}=2·\ln \frac{\mathrm{S1}}{0.2235·\left(t+\mathrm{W1}\right)}$

  
• For the configuration with the[0137]slit677,680, the inductance of the pair ofconductors685 and686 or687 and688 can be determined by calculating the inductance of each conductor and then noting that the conductor pair are in parallel with one another. The general equation for the inductance of a multi-conductor configuration where the current in all conductors is equal (this is the case since, by symmetry, a continuous set of paired contacts as shown in FIG. 6I must have the same current in each path) is:$l=2·\ln \frac{\mathrm{GMD}}{\mathrm{GMR}}{10}^{-7}$

  
• where GMD is the geometric mean distance from the first group of conductors to the second group of conductors and GMR designates the geometric mean of the individual geometric mean radii of the group together with the wire-to-wire distances among the conductors of that group. Applying the forgoing relationships yields an expression for the inductance of the[0138]conductors685,688,686,687 is as follows:$\begin{array}{c}{\mathrm{<figure-callout\; label="L"\; filenames="US20030214800A1-20031120-D00023.png"\; state="\{\{state\}\}"><figure-callout\; label="L"\; filenames="US20030214800A1-20031120-D00023.png"\; state="\{\{state\}\}">L</figure-callout></figure-callout>}}_{685,688}=2·\ln \frac{\sqrt{\left(\mathrm{S2}+\mathrm{S3}\right)\left(\mathrm{S2}+2·\mathrm{S3}\right)}}{\sqrt{\mathrm{.2235}·\left(t+\mathrm{W2}\right)·\mathrm{S3}}}{10}^{-7}\\ {\mathrm{<figure-callout\; label="L"\; filenames="US20030214800A1-20031120-D00023.png"\; state="\{\{state\}\}"><figure-callout\; label="L"\; filenames="US20030214800A1-20031120-D00023.png"\; state="\{\{state\}\}">L</figure-callout></figure-callout>}}_{686,687}=2·\ln \frac{\sqrt{\mathrm{S2}·\left(\mathrm{S2}+\mathrm{S3}\right)}}{\sqrt{\mathrm{.2235}·\left(t+\mathrm{W2}\right)·\mathrm{S3}}}{10}^{-7}\end{array}$

  
• The pair inductance then is simply L[0139]_685,688in parallel with L_686,687:$L_{\mathrm{pair}}=\frac{{\mathrm{<figure-callout\; label="L"\; filenames="US20030214800A1-20031120-D00023.png"\; state="\{\{state\}\}"><figure-callout\; label="L"\; filenames="US20030214800A1-20031120-D00023.png"\; state="\{\{state\}\}">L</figure-callout></figure-callout>}}_{685,688}·{\mathrm{<figure-callout\; label="L"\; filenames="US20030214800A1-20031120-D00023.png"\; state="\{\{state\}\}">L</figure-callout>}}_{686,687}}{{\mathrm{<figure-callout\; label="L"\; filenames="US20030214800A1-20031120-D00023.png"\; state="\{\{state\}\}"><figure-callout\; label="L"\; filenames="US20030214800A1-20031120-D00023.png"\; state="\{\{state\}\}">L</figure-callout></figure-callout>}}_{685,688}+{\mathrm{<figure-callout\; label="L"\; filenames="US20030214800A1-20031120-D00023.png"\; state="\{\{state\}\}"><figure-callout\; label="L"\; filenames="US20030214800A1-20031120-D00023.png"\; state="\{\{state\}\}">L</figure-callout></figure-callout>}}_{686,687}}$

  
• When the above equations are applied to practical conductor geometries, substantial reductions in inductance can be achieved by providing a slot in the contact arrangement as shown in FIG. 6I.[0140]
• It is understood that in all of the previously described conductor embodiments, it is important to design the contact arrangement such as to avoid rotational forces that may be imparted to the base of the contact wherein the base is soldered to one of the substrates. The reason for this is to eliminate normal forces that are not in compression (along the z-axis) which apply a torsional force to the base portion of the conductor, and which may result in solder creepage, and ultimately the failure of the solder joint between the base of the conductor and the substrate pad. This can be accomplished by designing the conductor so that the interface portion that contacts the second circuit board contact and the base portion that contacts the first circuit board contacts are disposed substantially only along the z-axis from one another (e.g. either above or below each other, but not displaced in the x-y plane). This can be achieved, for example as demonstrated in the foregoing description where the compliant conductor beam is folded over the base of the conductor.[0141]
• It is also desirable to design the conductor and contacts to cooperatively interact with each other to minimize contact resistance and insure good electrical connection. This can be accomplished, for example, with the S-shaped conductor portions (such as that which is illustrated in FIGS. 4A and 4B, or other electrical contact-enhancing designs).[0142]
• FIG. 7 is a diagram illustrating a plan view (looking up into PCB[0143]120) of another embodiment of the present invention. As in previous embodiments, the z-axis compliant conductors, as well as the contacts on the PCB and substrate that interface with the z-axis compliant conductors are disposed about the periphery of the power dissipating device. Further, the power and ground (or positive and negative power) conductive paths formed by the conductors and contacts were interleaved to reduce inductance. In the embodiment illustrated in FIG. 7, the set contacts on the first circuit board and the set of contacts on the second circuit board are separated into two subsets of contacts, and the z-axis compliant conductors are separated into two subsets of conductors as well. As was the case in the embodiments discussed previously, the first subsets of the contacts on the first and second circuit boards and the z-axis compliant conductors are disposed circumferentially around the power dissipating device. However, in this embodiment, the second set of contacts on the first and second circuit boards and the z-axis compliant conductors are disposed circumferentially around the first subset of contacts on the first and second circuit boards and the z-axis compliant conductors. The result is two “rings” of circuit paths from the first circuit board, through thefirst subset122A and thesecond subset122B of z-axis compliant conductors, to the second circuit board, wherein each ring includes a plurality of interleaved ground and power paths. The multiple “rings” ofcontacts122A and122B, one behind and disposed circumferentially about the other, are used to achieve even lower interconnect impedance between thePCB120 and thesubstrate130. This is accomplished at least in part because each of the multiple rows ofcontacts122A and122B effectively couple in parallel.
• One of the advantages of the present invention is that it permits simplification of the power/ground/signal interconnect between related printed circuit boards. FIG. 8 is a diagram illustrating a typical stackup arrangement[0144]5 having power/ground/signal interconnect contention problems. Thesubstrate847 of the stackup5 includes conductive circuit layers831,834,836,839, and841, and insulating layers (832,835,837,840, and842) reside between the circuit layers831,834,836,839, and841. Asurface layer826 typically is used for making contact through bumps to power dissipatingdevice827. The number of insulating and conducting layers may be increased or decreased depending upon the signal and power demands of the power dissipating device.
• In most integrated circuit packages, power enters from[0145]pins845 disposed on the opposite side of thepower dissipating device827 and is distributed throughpower vias833,838 in thesubstrate847. Thepower dissipating device827 has connectors for power and ground (828,829 shown) which connect to asurface layer826 ofsubstrate847. To ensure a low impedance DC power distribution path,multiple power vias838 and ground vias833 must pass throughsubstrate847 to connect with multiple power and ground pins (e.g.844 and843 respectively). Power and ground is distributed fromcontacts845 includinglower contacts844 and843 (which may be a large numbers of pin connections in a socket).
• [0146]Power contacts844 are coupled to one ormore power planes841 and836 by one ormore power vias838,848, and thence to power bumps829. Similarly,ground contacts843 are coupled to one or more ground planes839,834 by one or more ground vias849 and thence to ground bumps828. Signal contacts, e.g.,830, connect to conductive signal layers831 and then typically distribute signals to the periphery of the device through signal vias, e.g.,825, and then down into a signal contact, e.g.,846, for distribution to other components communicatively coupled to the contact846 (for example, a motherboard).
• FIG. 9 is a diagram of an improved power[0147]distribution system configuration90 in which power taps901 are provided through the top side ofsubstrate923 instead of through the bottom. Power taps901 represent where the compliant conductors make contact to the pads on the top surface of the substrate to distribute power from a power source to thepower dissipating device906 onsubstrate923.Power dissipating device906 onsubstrate923 is connected as described in FIG. 8, except that thatpower layer908 does not require substantial via distributions to lower layers such aslayers912 and914. Power enters power taps901 whereby thepower layer902 connects to theright power tap901B and theground plane910 connects to leftpower tap901A through via903.Ground plane910 then connects tovias924, which in turn connect to groundbumps905 onpower dissipating device906. Additionally, power is routed frompower plane902 to power bumps904 onpower dissipating device906. This completes the power distribution path for thesubstrate stackup923 from the source to the load, e.g., thepower dissipating device906. Note that for illustrative purposes, thebumps904,905 onpower dissipating device906 are raised slightly off of thepower plane902.
• Signal connections from[0148]power dissipating device906 may now be routed to one ormore bumps907, which connect to one ormore vias915 which route to one or more signal planes917. Other signals may now be distributed to pin connections (or alternatively other bump interconnects such as in an interposer to substrate connection) for connection to pins (such as921 through vias similar to922) which connect to a socket-like interconnect or PCB.Ground connections920 throughvias919 andground plane914 may now be used for signal reference only rather than for power distribution as well. As in FIG. 8, insulation layers909,911,913,916, and918 make up the rest of thesubstrate923 construction.
• This embodiment allows for a reduction in the number of layers because that power distribution is facilitated predominately through the top two[0149]layers908,910 ofsubstrate923. Additionally, since the power and ground conductive layers are disposed on a power dissipating device side of substantially all of the conductive signal layers, the passage of power through the planes of the conductive signal layers is minimized. The distribution of signals the x-y planes is also improved. This is due to elimination or reduction of the number of vias for power and ground distribution insubstrate923 that would normally have been used to connect topins845 as described in FIG. 8. Through elimination of the power and ground vias in these lower layers (utilizing the top two layers), x-y plane real estate is henceforth available for additional signal routing in the lower layer(s), e.g.,917.
• FIG. 10 illustrates an embodiment of the present invention wherein the power conditioning circuit or[0150]module1000 includes a plurality ofpower conditioning submodules1001A-1001D, which together provide a power signal having a plurality of phases. In this embodiment, the topology of thepower conditioning circuit1000 delivers power to a plurality ofcompliant conductors1003 advantageously arranged to apply different phases of the power signal to different sides of thepower dissipation device1006. Thepower dissipation device1006 is shown connected to power andground planes1005 and1004 located onsubstrate1002. It is understood that the power dissipation device/substrate1006/1002 resides at a level either above or below thevoltage regulation module1000. Power andground planes1005 and1004 then connect toVRM1000 throughcompliant conductors1003 which circumscribepower dissipating device1006 wherein the ground of each phase connects to groundplane1004 and the voltage out of each phase connects to thepower plane1005.
• Topologically, each phase is represented by an input voltage (VIN) to two FET switches and an L-C output circuit. In the illustrated embodiment, each phase operates 90 degrees out of phase with the other adjacent to it. Because of the organization of the phases and due to the placement of the[0151]compliant conductors1003 one may lay out the PCB ofVRM1000 in this topological fashion which improves routing and interconnect impedance due to the partitioning of each phase about the periphery of the power dissipating device. This allows the inductors, capacitors, and electronic drive circuitry (FETs, etc.) of each phase to be logically placed adjacent to a linearcompliant conductor1003 resulting in a superior layout and interconnect scheme which is synergistic with the topology of the VRM itself.
• FIGS.[0152]11A-11B illustrate the concept for mounting power directly to a board with the use of power pin attachments to the substrate of the package. Power pins [1102,1103] (e.g. power and ground) are attached electrically and mechanically tosubstrate1104.Ground return1103 is a coaxial integrated pad which is part of1101 and also acts as thermal heat-spreader for die1105 which is attached thermally to1103 throughthermal interface1106.
• FIG. 11C is a blow-up section of view A-A in FIG. 1A, which expands on the construction of the pin attachments.[0153]Power pin1102 is mounted tosubstrate1104 through solder orpress pin1110 which connects electrically to inter-plane1107 in substrate. Solder orpress pin1110 is connected to plated thru-hole1109 electrically and mechanically. Adielectric insulator1112 isolates1102 from1103. The center section of1102 is threaded for attachment to the board. Additionally,taper1111 is constructed to allow an electrical joint attachment to the board. This will be explained below.
• FIG. 12 illustrates a split-wedge washer and screw fastener construction designed to electrically and mechanically attach sub-assembly [A] to sub-assembly [B]. Split-[0154]wedge washer1217 is designed with alip section1219 for forcing mechanically sub-assembly [A] to [B].Wedge section1216 is shown along withsplit section1218.
• FIG. 13 shows the attachment of a section (FIG. 11C and FIG. 12 combined) integrated with[0155]board1320. The split-wedge washer engages electrically and mechanically to the side of plated thru-hole1322 in the board by havingtaper section1111 of1102spread1217 outward to force against [Z]. Simultaneously,screw fastener1215 forces sub-assembly [A] against [B] by pulling1217 against1320 and bringing assembly [B] against1320.Inter-power plane1321 is attached electrically to plated thru-hole1322 which connects to power distribution on1320. Additionally,ground pad1103 is attached electrically to bottom pad of1320 (not shown) to complete electrical circuit through vias which attach to ground plane on1320 (also not shown).
• FIG. 14 shows the high level assembly of [B] attaching to [A].[0156]VRM1424 andheatsink1423 are attached to1320 electrically, thermally, and mechanically as described in previous literature.Thermal interface1425 attaches to1320 thermally as also described in previous literature.EMI frame1426 is shown for completeness.
• FIG. 15 illustrates a low inductance ‘frame’ standoff sub-assembly [C]. A sheet metal frame is bent and joined at one corner to form an[0157]outer ground frame1525 with solder tabs for mounting permanently to one unit (either VRM board or main board). Adielectric tape1527 is attached to this structure as an insulator.Inner frame1526 is made in similar fashion to1525 but carries positive going current (e.g. connected to positive terminal of power supply) to supply power to IC. Mountingholes1528 are supplied to mount to one side of assembly to make mechanical and electrical connection. Due to the dimensions of the construction, and the current paths for the electrical interconnect, a very low inductance can be achieved resulting in a low voltage drop between the power supply and load for low frequency switching applications.
• FIG. 16 is an assembled view showing the construction together in an assembly with the structure mounted to an[0158]interface board1730.
• FIG. 17 illustrates the mounting to an interface board. The purpose of this board is to remove any need to mount power directly to the main board, which can improve rout ability and cost on the main board.[0159]
• FIG. 18 shows an exploded view of FIG. 16.[0160]
• While the foregoing embodiment is described with respect to a four phase power signal applied to each of a four-sided power dissipating device, the principles described above can be applied to embodiments with fewer or more than four sides and power signal phases, or to embodiments with non-polygonal configurations (e.g. circular, for example).[0161]
• In summary, the forgoing discussion discloses a low impedance power interconnect between the power dissipating device and the power source. The impedance of the power interconnect is low in inductance and resistance throughout a wide frequency band in order to ensure that the voltage drops across the interconnect are mitigated across it during dynamic switching of power. It can also be seen that the interconnect should provide large ‘z’ axis compliance. The arrangement also reduces or eliminates the need for supporting electronic components on the device substrate because the interconnect impedance between the power conditioning circuit and the device can be reduced to the point where all or most of the support electronics can be located on the substrate having the power conditioning circuit itself.[0162]
• The present invention also significantly reduces contentious routing of power to the power dissipating device because the power interconnect impedance is significantly lowered and can be routed to one or more sides of the power dissipating device.[0163]
• Further, since the upper layers of the power dissipating device substrate are used primarily for power distribution, the area on additional layers beneath the upper layers are free for use with for signal and other conductive interconnects. These other conductive interconnects can connect other interconnects or substrates beneath or above the stackup.[0164]
CONCLUSION
• The foregoing description of the preferred embodiment of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. For example, the substrate contacts and compliant conductors can be disposed proximate the outer periphery of the substrates rather than proximate the power dissipating device as described herein. Further, the compliant conductors may be rigid instead of compliant, while still permitting the detachable design described herein. Also, the compliant conductors can be integrated with other assemblies such as a socket, which might be used to interconnect signals to the microprocessor. Further, more than one linear set of contacts can be arranged to circumscribe the power dissipating device in a manner to increase the total number of contacts providing power and/or ground to the device, thus reducing the overall connection inductance and increasing total current carrying capability. The z-axis compliant contacts can also be configured so as to permit acceptance of stackup height variations.[0165]
• It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto. The above specification, examples and data provide a complete description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.[0166]

Claims (1)

What is claimed is:

1. An apparatus for providing power to a power dissipating device, comprising:

a first circuit board having a power conditioner circuit, the first circuit board having a first side and a second side having a plurality of first circuit board contacts thereon, the first circuit board contacts including a first set of first circuit board contacts communicatively coupled to a first power conditioner circuit connector and a second set of first circuit board contacts communicatively coupled to a second power conditioning circuit connector;

a second circuit board having:

the power dissipating device mounted thereto;

a plurality of second circuit board contacts disposed on a first side of the second circuit board, the second circuit board contacts including a first set of second circuit board contacts communicatively coupled to a power dissipating device first connector and a second set of second circuit board contacts communicatively coupled to a second connector of the power dissipating device;

a plurality of z-axis compliant conductors disposed at least partially between the first circuit board contacts and the second circuit board contacts; and

wherein the plurality of z-axis compliant conductors includes a first set of z-axis compliant conductors in contact with and disposed between the first set of first circuit board contacts and the first set of second circuit board contacts, and a second set of z-axis compliant conductors disposed in contact with and between the second set of first circuit board contacts and the second set of second circuit board contacts, and

wherein the first set of first circuit board contacts, the first set of z-axis compliant conductors, and the first set of second circuit board contacts define a plurality of first paths from the first circuit board to the second circuit board and wherein the second set of circuit board contacts, the second set of z-axis compliant conductors, and the second set of second circuit board contacts define a plurality of second paths from the first circuit board to the second circuit board.

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