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US20030176061A1 - Apparatuses For Treating Pluralities of Discrete Semiconductor Substrates - Google Patents

Apparatuses For Treating Pluralities of Discrete Semiconductor Substrates
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Publication number
US20030176061A1
US20030176061A1US10/349,697US34969703AUS2003176061A1US 20030176061 A1US20030176061 A1US 20030176061A1US 34969703 AUS34969703 AUS 34969703AUS 2003176061 A1US2003176061 A1US 2003176061A1
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mass
semiconductor substrates
reactive material
discrete semiconductor
exposing
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US10/349,697
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Trung Doan
Lyle Breiner
Er-Xuan Ping
Lingyi Zheng
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Abstract

The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

Description

Claims (81)

1. An atomic layer deposition method for treating a plurality of discrete semiconductor substrates, comprising:
placing the plurality of discrete semiconductor substrates in a reaction chamber;
simultaneously exposing the plurality of discrete semiconductor substrates to one or more of H, F and Cl within the chamber to remove exposed native oxide from the semiconductor substrates;
after removing the native oxide, simultaneously exposing the plurality of discrete semiconductor substrates to a first reactive material within the chamber to form a first mass across at least some exposed surfaces of the plurality of discrete semiconductor substrates;
removing the first reactive material from within the reaction chamber; and
after removing the first reactive material, simultaneously exposing the plurality of discrete semiconductor substrates within the chamber to a second reactive material to convert the first mass to a second mass.
17. A method for treating a plurality of discrete semiconductor substrates, comprising:
placing the plurality of discrete semiconductor substrates in a reaction chamber;
simultaneously exposing the plurality of discrete semiconductor substrates to oxygen within the chamber to form a uniform layer of oxide across exposed oxidizable surfaces of the semiconductor substrates;
after forming the oxide, simultaneously exposing the plurality of discrete semiconductor substrates to a first reactive material within the chamber to form a first mass across at least some portions of the plurality of discrete semiconductor substrates;
removing the first reactive material from within the reaction chamber; and
after removing the first reactive material, simultaneously exposing the plurality of discrete semiconductor substrates within the chamber to a second reactive material to convert the first mass to a second mass.
25. A method for treating a plurality of discrete semiconductor substrates, comprising:
placing the plurality of discrete semiconductor substrates in reaction chamber;
simultaneously exposing the plurality of discrete semiconductor substrates to a first reactive material within the chamber to form a first mass across at least some exposed surfaces of the plurality of discrete semiconductor substrates;
removing the first reactive material from the reaction chamber; and
after the removing, simultaneously exposing the plurality of discrete semiconductor substrates to a second reactive material within the chamber to convert the first mass to a second mass, the second mass comprising one or more of Ta, Ti, W, Al, Hf, SiO and Zr; wherein the listed composition of SiO is shown in terms of the elements contained therein rather than in terms of a stoichiometric relationship of the elements.
35. An atomic layer deposition method for treating a plurality of discrete semiconductor substrates, comprising:
placing the plurality of discrete semiconductor substrates in reaction chamber;
simultaneously exposing the plurality of discrete semiconductor substrates to a first reactive material within the chamber to form a first mass across at least some exposed surfaces of the plurality of discrete semiconductor substrates, the discrete semiconductor substrates being at a first temperature during the exposing to the first reactive material;
removing the first reactive material from the reaction chamber; and
after the removing, simultaneously exposing the plurality of discrete semiconductor substrates to a second reactive material within the chamber to convert the first mass to a second mass, the discrete semiconductor substrates being within 100° C. of the first temperature during the exposing to the second reactive material.
63. A method for treating a plurality of discrete semiconductor substrates, comprising:
placing the plurality of discrete semiconductor substrates in reaction chamber;
simultaneously exposing the plurality of discrete semiconductor substrates to a silicon-containing precursor within the chamber to form a silicon-containing mass across at least some exposed surfaces of the plurality of discrete semiconductor substrates, the discrete semiconductor substrates being at a first temperature during the exposing to the silicon-containing precursor, the first temperature being from 300° C. to 700° C.;
removing the silicon-containing precursor from the reaction chamber; and
after the removing, simultaneously exposing the plurality of discrete semiconductor substrates to a nitrogen-containing precursor within the chamber to convert the silicon-containing mass to silicon nitride, the discrete semiconductor substrates being within 100° C. of the first temperature during the exposing to the nitrogen-containing precursor.
74. A construction for treating a plurality of discrete semiconductor substrates, comprising:
a chamber configured to retain the plurality of discrete semiconductor substrates, the chamber having sidewalls, two of the sidewalls being on opposing sides of the chamber relative to one another, the two of sidewalls being a first sidewall and a second sidewall;
an inlet port opening into the chamber through the first sidewall, the first sidewall having a surface area which is reduced by at least about 30% due to the inlet port;
an outlet port opening into the chamber through the second sidewall, the second sidewall having a surface area which is reduced by at least about 30% due to the outlet port;
a gas source in fluid communication with the inlet port; and
a valve proximate the outlet port and configured to control gas flow through the outlet port.
US10/349,6972002-03-132003-01-22Apparatuses For Treating Pluralities of Discrete Semiconductor SubstratesAbandonedUS20030176061A1 (en)

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US10/099,216US7220312B2 (en)2002-03-132002-03-13Methods for treating semiconductor substrates
US10/349,697US20030176061A1 (en)2002-03-132003-01-22Apparatuses For Treating Pluralities of Discrete Semiconductor Substrates

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US10/099,216Expired - Fee RelatedUS7220312B2 (en)2002-03-132002-03-13Methods for treating semiconductor substrates
US10/349,697AbandonedUS20030176061A1 (en)2002-03-132003-01-22Apparatuses For Treating Pluralities of Discrete Semiconductor Substrates
US10/349,699AbandonedUS20030176057A1 (en)2002-03-132003-01-22Methods for treating pluralities of discrete semiconductor substrates
US10/349,565AbandonedUS20030176047A1 (en)2002-03-132003-01-22Methods for treating pluralities of discrete semiconductor substrates
US10/349,808Expired - Fee RelatedUS7183208B2 (en)2002-03-132003-01-22Methods for treating pluralities of discrete semiconductor substrates
US10/349,717AbandonedUS20030176062A1 (en)2002-03-132003-01-22Methods For Treating Pluralities of Discrete Semiconductor Substrates
US10/836,922Expired - Fee RelatedUS6835674B2 (en)2002-03-132004-04-30Methods for treating pluralities of discrete semiconductor substrates
US10/846,425Expired - LifetimeUS7112544B2 (en)2002-03-132004-05-13Method of atomic layer deposition on plural semiconductor substrates simultaneously
US10/914,828AbandonedUS20050009335A1 (en)2002-03-132004-08-09Apparatuses for treating pluralities of discrete semiconductor substrates; and methods for treating pluralities of discrete semiconductor substrates
US11/206,340Expired - LifetimeUS7247581B2 (en)2002-03-132005-08-17Methods for treating pluralities of discrete semiconductor substrates

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US10/349,699AbandonedUS20030176057A1 (en)2002-03-132003-01-22Methods for treating pluralities of discrete semiconductor substrates
US10/349,565AbandonedUS20030176047A1 (en)2002-03-132003-01-22Methods for treating pluralities of discrete semiconductor substrates
US10/349,808Expired - Fee RelatedUS7183208B2 (en)2002-03-132003-01-22Methods for treating pluralities of discrete semiconductor substrates
US10/349,717AbandonedUS20030176062A1 (en)2002-03-132003-01-22Methods For Treating Pluralities of Discrete Semiconductor Substrates
US10/836,922Expired - Fee RelatedUS6835674B2 (en)2002-03-132004-04-30Methods for treating pluralities of discrete semiconductor substrates
US10/846,425Expired - LifetimeUS7112544B2 (en)2002-03-132004-05-13Method of atomic layer deposition on plural semiconductor substrates simultaneously
US10/914,828AbandonedUS20050009335A1 (en)2002-03-132004-08-09Apparatuses for treating pluralities of discrete semiconductor substrates; and methods for treating pluralities of discrete semiconductor substrates
US11/206,340Expired - LifetimeUS7247581B2 (en)2002-03-132005-08-17Methods for treating pluralities of discrete semiconductor substrates

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US7220312B2 (en)2007-05-22
US20040203232A1 (en)2004-10-14
US20040235302A1 (en)2004-11-25
US7183208B2 (en)2007-02-27
US6835674B2 (en)2004-12-28
US20030176060A1 (en)2003-09-18
US20030176057A1 (en)2003-09-18
US20030176062A1 (en)2003-09-18
US7112544B2 (en)2006-09-26
US20030176047A1 (en)2003-09-18
US20060057800A1 (en)2006-03-16
US7247581B2 (en)2007-07-24
US20030186515A1 (en)2003-10-02
US20050009335A1 (en)2005-01-13

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