US20030173648A1 - Multi-die chip and method for making the same - Google Patents

Abstract

The present invention generally relates to a die perimeter region of a die having a microelectromechanical assembly fabricated thereon. This die perimeter region may be configured to facilitate electrically interconnecting adjacent die on a wafer. Moreover, this die perimeter region may be configured to facilitate separating the die from a wafer.

Description

FIELD OF THE INVENTION
• The present invention generally relates to a chip that is defined by a plurality of die, with each die including a microelectromechanical assembly, and, more particularly, to a configuration of a die perimeter region that facilitates having a multi-chip die.[0001]
BACKGROUND OF THE INVENTION
• There are a number of microfabrication technologies that have been utilized for making microstructures (e.g., micromechanical devices, microelectromechanical devices) by what may be characterized as micromachining, including LIGA (Lithography, Galvonoforming, Abforming), SLIGA (sacrificial LIGA), bulk micromachining, surface micromachining, micro electrodischarge machining (EDM), laser micromachining, 3-D stereolithography, and other techniques. Bulk micromachining has been utilized for making relatively simple micromechanical structures. Bulk micromachining generally entails cutting or machining a bulk substrate using an appropriate etchant (e.g., using liquid crystal-plane selective etchants; using deep reactive ion etching techniques). Another micromachining technique that allows for the formation of significantly more complex microstructures is surface micromachining. Surface micromachining generally entails depositing alternate layers of structural material and sacrificial material using an appropriate substrate (e.g., a silicon wafer) which functions as the foundation for the resulting microstructure. Various patterning operations (collectively including masking, etching, and mask removal operations) may be executed on one or more of these layers before the next layer is deposited so as to define the desired microstructure. After the microstructure has been defined in this general manner, the various sacrificial layers are removed by exposing the microstructure and the various sacrificial layers to one or more etchants. This is commonly called “releasing” the microstructure from the substrate, typically to allow at least some degree of relative movement between the microstructure and the substrate.[0002]
• It has been proposed to fabricate various types of optical switch configurations using various micromachining fabrication techniques. One of the issues regarding these types of optical switches is the number of mirrors that may be placed on a single die. A die is commonly referred to as that area defined by one field of a stepper (or contact aligner in some instances) that is utilized to lay out the die. In the case of a stepper, die size is generally limited to the maximum optical field size of the stepper, which is typically less than or on the order of 30 mm or so depending on the specific stepper being used. Reducing the size of the mirrors in order to realize the desired number of mirrors on a die may present various types of issues. For instance, there are of course practical limits as to how small the mirrors can be fabricated, or more limiting is the minimum acceptable size of the micromirrors for the optical application, which thereby limits the number of ports for the optical switch for a given die size. Therefore, it may not be possible to fabricate an optical switch with a certain number of ports using a single die. Moreover, as smaller and denser microstructures are incorporated on a die, impact on chip yield may become more and more of an issue. For instance, a microelectromechanical optical switch may be rendered defective during the handling of a chip on which the switch is fabricated as the size of the various microstructures is reduced, and the chip area is increased.[0003]
SUMMARY OF THE INVENTION
• A first aspect of the present invention generally relates to a desired configuration of what may be characterized as a die boundary region, namely that region on a die that borders the various microstructures of a microelectromechanical assembly that is fabricated on the die. For instance, this die boundary region may be in the form of an inter-die region between adjacent die, including without limitation between adjacent die on a wafer, chip, or the like. However, this die boundary region may be located on a perimeter of a chip or an individual die as well. Generally, the noted die boundary region is devoid of an oxide layer that is typically disposed between a dielectric layer and a substrate that is used in the fabrication of the microelectromechanical assembly on the die. However, those portions of the die that are disposed inwardly out of the die boundary region include an oxide layer between the dielectric layer and the substrate. Generally, a “dielectric layer” refers to a layer/film that is made up of one or more non-sacrificial and non-etchable materials. By contrast, an “oxide layer” generally refers to a layer/film that is made up of a material that is at least potentially etchable during a release etching step of a chip fabrication process. One advantage of this configuration is that a perimeter region of the chip/die will be suitable for engagement by handling equipment. Another advantage of this configuration is that die may be sawed or otherwise separated along a die boundary region, and subsequent exposure of the chip/die to a release etchant should not cause any portion of the oxide layer that is located between the dielectric layer and the substrate to be exposed to a release etchant. Any exposure of this oxide layer may produce an undesired undercut cantilevering the dielectric layer and resulting in an undesired structural instability or increased susceptibility to breakage for perimeter structures. Yet another advantage is that fabricating each inter-die region in this manner may allow a wafer to be fabricated in a manner such that a chip of any desired die size may be produced therefrom.[0004]
• The first aspect of the present invention is embodied by a chip that includes a substrate, an oxide layer, and a dielectric layer. The oxide layer overlies the substrate, while the dielectric layer overlies the oxide layer. The chip further includes a plurality of die. Each die includes a die perimeter region and a device region that is disposed inwardly of the corresponding die perimeter region. The device region of each die includes a first microelectromechanical assembly such that the chip may be properly characterized as having a plurality of first microelectromechanical assemblies. The oxide layer is disposed between the dielectric layer and the substrate in the device region of each of the die of the chip. This oxide layer may generally provide a function (among others) of supplying an additional electrical isolation layer (in addition to the dielectric layer) to the structure of the chip to further electrically isolate the substrate from the plurality of first microelectromechanical assemblies disposed on the device region of each die. However, the die perimeter region of each die is devoid of the oxide layer such that the dielectric layer is disposed directly on the substrate in each die perimeter region.[0005]
• Various refinements exist of the features noted in relation to the subject first aspect of the present invention. Further features may also be incorporated in the subject first aspect of the present invention as well. These refinements and additional features may exist individually or in any combination. Representative substrates that may be utilized by the first aspect include silicon, as well as any other appropriate chip substrate such as gallium arsenide (GaAs), gallium arsenide phosphide (GaAsP), ceramics, or other appropriate compound semiconductor substrates. Representative oxides that may be utilized by the first aspect include silicon dioxide, silicon oxynitrides, and any other appropriate oxides. Representative dielectric materials that may be utilized by the first aspect include silicon nitride, silicon carbide, and any other appropriate dielectric material.[0006]
• The lack of an oxide layer in the die perimeter region of each die of the chip of the first aspect provides a number of advantages in addition to preventing cantilevered dielectric layers subsequent to separation of the chip from the wafer and during and/or after a release etching step of a chip fabrication process. Initially, this lack of an oxide layer in the die perimeter region of each die provides flexibility at the wafer level of fabrication. For instance, this lack of an oxide layer in the die perimeter region of each die may reduce the complexity of the layout since each die may be of an identical configuration. For example, since the die may be substantially equal in size, making a chip of a first size may include cutting a chip from the wafer that has dimensions of 2 die wide by 3 die long. Continuing with the example, if a larger chip is desired, one may simply cut a bigger section (e.g., a chip having dimensions of 3 die wide by 3 die long) from the wafer. In other words, variations of this first aspect may generally enable chips of a wide variety of sizes to be fabricated simply by severing the wafer at desired locations along appropriate die boundaries. Moreover, the resulting layout of the various die on the wafer does not in and of itself limit the configuration of any chips to be formed therefrom in terms of the number of die per chip.[0007]
• The lack of an oxide layer in the die perimeter region also facilitates the separation of adjacent die from the wafer in a manner by providing a region which should be less susceptible to damage during the actual separation process (e.g., during sawing) or after an etch release. A number of features may be utilized by the first aspect to facilitate the realization of these types of advantages. In this regard, each adjacent pair of die in the case of the first aspect may be separated by what may be characterized as a die boundary. The oxide layer in each die associated with the first aspect may be spaced back at least about 25 microns, and more preferably from about 25 microns to about 100 microns from each of its die boundaries. In some variations, the oxide layer in each die may be spaced back from each of its corresponding die boundaries by a nominal distance comparable to at least half of the width of a saw kerf that may be utilized to separate the die. That is, the oxide layer in each die may be spaced inwardly of the perimeter of the given die by any one of the above-noted amounts. However, while some variations of the first aspect may exhibit the oxide layer being spaced back from one or more of its corresponding die boundaries by a distance greater than 100 microns, generally, the further the oxide layer is spaced back from the die boundary(ies), the smaller the size of the corresponding device region remaining on the die. In any event, each die perimeter region of the first aspect may be limited to the substrate, the dielectric layer, and a plurality of electrical traces that extend between adjacent pairs of die and that are disposed directly on the dielectric layer.[0008]
• Surface micromachining may be used to fabricate at least a portion of the microelectromechanical assembly that is fabricated on each die in the case of the first aspect. Surface micromachining allows for the formation of a plurality of vertically spaced and structurally interconnected microstructures and for a complexity that is not readily producible by other fabrication techniques. One or more etchants are typically used to release each of these microelectromechanical assemblies at the end of the fabrication process so as to allow for at least some type of movement of one or more microstructures relative to the substrate. Since the sacrificial layers used in the most common type of surface micromachining systems is typically a silicon oxide, exposing any of the oxide that is disposed between the dielectric layer and the substrate may result in an undesired etching of the same. Therefore, the first aspect may include totally encasing the oxide layer between the dielectric layer and the substrate. As previously mentioned, this oxide layer may generally provide a function (among others) of supplying an additional electrical isolation layer (in addition to the dielectric layer) to the structure of the chip to further electrically isolate the substrate from the plurality of first microelectromechanical assemblies disposed on the device region of each die.[0009]
• With further regard to using surface micromachining in relation to the first aspect, each first microelectromechanical assembly may include at least one and more typically a plurality of structural layers that are disposed in vertically spaced relation. “Vertically spaced” means that there is a gap between a given part of the first microelectromechanical system and an underlying structure, which may include the substrate. In one embodiment, no vertically spaced structure of any of the first microelectromechanical assemblies is disposed within about 100 microns of any adjacent die boundary. Consider the case where a first die is bordered by second, third, fourth, and fifth die. All vertically spaced portions of the first microelectromechanical assembly on the first die are disposed inwardly by the above-noted amount from the die boundary between the first and second die, from the die boundary between the first and third die, from the die boundary between the first and fourth die, and from the die boundary between the first and fifth die.[0010]
• Each of the plurality of die on the chip of the first aspect may be of an identical structure or configuration. That is, the same microelectromechanical assembly may be fabricated on each die, and these microelectromechanical assemblies may collectively define a desired microelectromechanical system. For instance, such a microelectromechanical system may be a mirror array. In one embodiment, each microelectromechanical assembly includes a plurality of mirrors and at least one actuator interconnected therewith so as to be able to move the corresponding mirror in a desired manner relative to the substrate. These mirrors may be used for providing any appropriate optical function, including such that the chip is configured as an optical switch, an adaptive optical array, an optical scanner array, a thermal imaging array, or any other array of devices that may be too large to be wholly encompassed by one die.[0011]
• The die perimeter region of each die associated with the chip of the first aspect may be configured such that there are no vertically-spaced layers or microstructures therewithin. That is, each die perimeter region may be configured such that all portions thereof are directly supported by an underlying layer or structure. This provides a desired configuration for handling of the chip such that handling tools would not contact sensitive device surfaces. One way to characterize each die perimeter region is as a die perimeter boundary channel or the like. Another way to characterize each such die perimeter region is that the dielectric layer disposed therein is vertically offset from those portions of the dielectric layer that are disposed in the device region of the corresponding die.[0012]
• One or more electrical lines, conductors, traces or the like may progress from one die to an adjacent die, and thereby cross a die boundary therebetween in the case of the first aspect. The first aspect may include features that enhance this “electrical interconnection” of adjacent die. Consider the case where there is a first die and a second die. A first electrical trace may be disposed in the device region of the first die, while a second electrical trace may be disposed in the device region of the second die. A third electrical trace may be disposed in the die perimeter region of at least one of the first and second die. Both the first and second electrical traces terminate in spaced relation to the third electrical trace. A first electrical jump connection may extend between the first and third electrical traces, while a second electrical jump connection may extend between the second and third electrical traces. Therefore, an electrical signal may pass between the first die and the second die using the noted structure.[0013]
• In one embodiment, the above-noted first jump connection that may be utilized by the first aspect includes a first post that extends at least generally upwardly from the first electrical trace, a second post that extends at least generally upwardly from the third electrical trace, and a first jumper that extends between the first and second posts. This configuration allows the first jumper to be disposed in vertically spaced relation to the entirety of the dielectric layer. Similarly, the above-noted second jump connection includes a third post that extends at least generally from the second electrical trace, a fourth post that extends at least generally upwardly from the third electrical trace, and a second jumper that extends between the third and fourth posts. This configuration also allows the second jumper to be disposed in vertically spaced relation to the entirety of the dielectric layer. In one embodiment, each corresponding pair of first and second jump connections are spaced back from the die boundary therebetween by a distance of at least about 25 microns, however, other distances may be appropriate.[0014]
• In one embodiment, the above-noted first, second, and third electrical traces that may be utilized by the first aspect are disposed directly on the dielectric layer. Since the dielectric layer in the die perimeter region may be disposed at a lower elevation than those portions of the dielectric layer that are disposed in the corresponding device region, the first and second electrical traces may be characterized as being vertically offset from the third electrical trace. This same type of electrical interconnection may be utilized for each adjacent pair of die and for any number of electrical traces.[0015]
• Shields may be disposed over electrical traces in the case of the first aspect. Each shield may be spaced back at least about 25 microns from an adjacentmost die boundary. Stated another way, each shield over each electrical trace that passes through a die perimeter region (directly or using the above-noted type of jump connections) is preferably spaced back from the die boundary by the above-noted amount. This provides a desired advantage when the chip of the first aspect is formed by sawing the same from a wafer. In any event, sawing through/along one or more of the types of die perimeter regions utilized by the first aspect, in an area where shields are not disposed over any electrical traces, desirably reduces the potential for the formation of debris/fragments that may adversely affect the operation of one or more of the microelectromechanical assemblies fabricated on the various die.[0016]
• The chip of the first aspect may include a chip perimeter and a chip perimeter region that is disposed inwardly of the chip perimeter. The dielectric layer may be disposed directly on the substrate in this chip perimeter region, and the chip perimeter region may also be devoid of the oxide layer. The chip perimeter region may be defined by the die perimeter region of one or more die. In this case the chip perimeter could be defined by sawing along/through one or more die perimeter regions in the above-noted manner. A plurality of electrical traces may extend through the chip perimeter region and terminate at the chip perimeter. A shield may be disposed over at least a portion of each of these electrical traces. An end of each of the shields that is adjacentmost to the chip perimeter is preferably spaced back at least about 25 microns from the chip perimeter, however, other distances may be appropriate.[0017]
• A second aspect of the present invention relates to a desirable way of establishing an electrical interconnection of sorts between adjacent die. Although this manner of establishing an electrical connection may be employed at the wafer stage, such electrical interconnections will then exist when the wafer is separated into chips as well. The second aspect will be described in the form of such a chip. A chip embodied by the second aspect includes a substrate and a plurality of die that are fabricated in an appropriate manner using this substrate. Each die includes a die perimeter region and a device region that is disposed inwardly of the corresponding die perimeter region. The device region of each die includes a first microelectromechanical assembly such that the chip may be properly characterized as having a plurality of first microelectromechanical assemblies. One or more electrical lines, conductors, traces or the like progress from between at least some adjacent pairs of die, and thereby cross a die boundary therebetween in the case of the second aspect.[0018]
• The second aspect includes features that at least generally enhance this “electrical interconnection” of adjacent pairs of die. Consider the case where there is a first die and a second die that are disposed in abutting relation. A first electrical trace may be disposed in the device region of the first die, while a second electrical trace may be disposed in the device region of the second die. A third electrical trace may be disposed in the die perimeter region of at least one of the first and second die. Both the first and second electrical traces terminate in spaced relation to the third electrical trace. A first electrical jump connection extends between the first and third electrical traces, while a second electrical jump connection extends between the second and third electrical traces. Therefore, an electrical signal may progress between the first die and the second die using the noted structure.[0019]
• Various refinements exist of the features noted in relation to the subject second aspect of the present invention. Further features may also be incorporated in the subject second aspect of the present invention as well. These refinements and additional features may exist individually or in any combination. Each of the plurality of die on the chip of the second aspect may be of an identical structure or configuration. That is, the same microelectromechanical assembly may be fabricated on each die, and these microelectromechanical assemblies may collectively define a desired microelectromechanical system. For instance, such a microelectromechanical system may be a mirror array. In one embodiment, each microelectromechanical assembly includes a plurality of mirrors and at least one actuator interconnected therewith so as to be able to move the corresponding mirror in a desired manner relative to the substrate. These mirrors may be used for providing any appropriate optical function, including, but not limited to, the chip being configured as an optical switch, an adaptive optical array, or an optical scanner array.[0020]
• The first jump connection that may be utilized by the second aspect may include a first post that extends at least generally upwardly from the first electrical trace, a second post that extends at least generally upwardly from the third electrical trace, and a first jumper that extends between the first and second posts. Similarly, the second jump connection may include a third post that extends at least generally upwardly from the second electrical trace, a fourth post that extends at least generally upwardly from the third electrical trace, and a second jumper that extends between the third and fourth posts. In one embodiment, each corresponding pair of first and second jump connections is spaced back from the die boundary therebetween by a distance of at least about 25 microns. However, other distances may be appropriate.[0021]
• The first and second electrical traces utilized by the second aspect may be disposed at one elevation, and the third electrical trace utilized by the second aspect may be disposed at a different elevation. That is, the first and second electrical traces may be vertically offset from the third electrical trace. One way in which these vertical offsets may be realized is by using surface micromachining techniques. The vertical offset of the noted electrical traces may exist by the die perimeter region of each die being configured such that there is no oxide layer between a dielectric layer and the substrate in these die perimeter regions. Therefore, the various features discussed above in relation to the first aspect may be utilized by the second aspect as well.[0022]
• The jump connections associated with the second aspect reduce the potential for the development of shorts between adjacent electrical traces that cross die perimeter regions that are in the form of a channel or the like. Consider the case where the die perimeter region of each die includes a dielectric layer that directly interfaces with the substrate, while the device region of each die includes an oxide layer between this dielectric layer and the substrate to realize the benefits discussed above in relation to the first aspect. Therefore, the various features of the first aspect may be utilized by the second aspect as well. In the event that electrical traces were simply patterned directly on the dielectric layer to progress from one die to the next across a pair of abuttingly disposed die perimeter regions that collectively define a channel or the like along the perimeter of the device region, it is likely that electrical shorts would develop on one or both of the “vertical” walls of this channel. The second aspect addresses this potential condition by utilizing a plurality of discrete electrical traces that are disposed at least principally in the lateral dimension, along with a plurality of jump connections. Each such jump connection again may include typically a pair of at least generally vertically disposed electrical contacts or posts. The lower extremes of these electrical contacts or posts interface with the discrete electrical traces to be electrically interconnected, while the upper extremes of these electrical contacts or posts are electrically interconnected by a conductive strip or the like. Each jump connection electrically interconnects corresponding pairs of vertically offset electrical traces in a manner such that the above-noted vertical walls are bypassed by the electrical path. It should be appreciated that surface micromachining may be readily employed to fabricate a jump connection of this type.[0023]
• A third aspect of the present invention relates to a method for fabricating a chip. The method includes forming a first oxide layer over an appropriate substrate. A first die boundary channel is formed in the first oxide layer. This first die boundary channel extends down through the first oxide layer and preferably to the substrate. A dielectric layer is formed over the first oxide layer and within at least a lower portion of the die boundary channel. A pair of die are defined on opposite sides of the first die boundary channel. Each of these die includes a microelectromechanical assembly. The first and second die are thereafter separated from each other along the first die boundary channel.[0024]
• Various refinements exist of the features noted in relation to the subject third aspect of the present invention. Further features may also be incorporated in the subject third aspect of the present invention as well. These refinements and additional features may exist individually or in any combination. The first die boundary channel may be formed by patterning the oxide layer. A first die boundary channel may be formed around the perimeter of each die that is being fabricated on a wafer. This then does not provide a limiting factor in relation to the number of die utilized per chip.[0025]
• The sidewalls of the first die boundary channel are defined by exposed edge surfaces of the oxide layer, while the floor or base of the first die boundary channel is preferably defined by the substrate. In one embodiment, the sidewalls of the first die boundary channel are disposed in at least substantially parallel relation. In another embodiment, the sidewalls of the first die boundary channel are separated by a distance that is generally within a range about 50 microns up to about 300 microns, however, other distances of separation may be appropriate. Forming the dielectric layer after defining the first die boundary channel allows a dielectric material to coat the exposed edge surfaces of the oxide layer that define the sidewalls of the first die boundary channel. As such, the oxide layer is in effect encased by a dielectric material. When the first and second die are separated along the first die boundary channel, such as by sawing, the cut does not result in the exposure of any of the oxide layer. This then protects the oxide layer when the resulting chip is exposed to a release etchant.[0026]
• The formation of a dielectric layer over an oxide layer of the type presented by the third aspect will leave a depression in the dielectric layer that corresponds with the location of the first die boundary channel. This depression in the dielectric layer may be characterized as a second die boundary channel. There may be a need for an electrical signal to progress from one die to another die, and to thereby cross through the second die boundary channel, and to have a corresponding electrical trace formed on the dielectric layer. One way to provide this electrical path would be to utilize the configuration discussed above in relation to the second aspect. Those various features discussed above in relation to any of the aspects of the present invention may be incorporated in any other aspects of the present invention, and in any appropriate manner noted herein.[0027]
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1A is a plan view of one embodiment of a wafer having a plurality of die.[0028]
• FIG. 1B is an enlarged plan view of a pair of die from the wafer of FIG. 1A.[0029]
• FIG. 1C is a plan view of one embodiment of a chip that may be separated from the wafer of FIG. 1A.[0030]
• FIG. 1D is a plan view of one embodiment of at least a portion of a mirror array that may be formed on each die of the chip of FIG. 1C.[0031]
• FIG. 1E is an enlarged plan view of one of the mirror assemblies from the mirror array of FIG. 1D.[0032]
• FIG. 2 is a top view of three die configurations that may be utilized by the wafer of FIG. 1A.[0033]
• FIG. 3A is a magnified top view of an inter-die region between first and second die.[0034]
• FIG. 3B is a cross-sectional view of the first die of FIG. 3A taken along cut-[0035]line3B-3B.
• FIG. 3C is a magnified top view of circle[0036]3C of FIG. 3A.
• FIG. 3D is alternative embodiment of the configuration illustrated in FIG. 3C.[0037]
• FIGS.[0038]4A-4K are sequential views of a method for making a chip having at least one conductive line and corresponding line shield(s).
• FIG. 5A is a cross-sectional view of the die of FIG. 5B taken along cut-[0039]line5A-5A.
• FIG. 5B is a top view of the die of FIG. 5A.[0040]
• FIG. 6A is a cross-sectional view of the die of FIG. 6B taken along cut-[0041]line6A-6A.
• FIG. 6B is a top view of the die of FIG. 6A illustrating a bridge structure electrically interconnecting first and second segments of respective conductive lines.[0042]
• FIGS.[0043]7A-Q are sequential views of a method for making a die of the type presented in FIGS.6A-B.
DETAILED DESCRIPTION
• The present invention will now be described in relation to the accompanying drawings which at least assist in illustrating its various pertinent features. Surface micromachining may be utilized to fabricate the various microstructures to be described herein. Various surface micromachined microstructures and the basic principles of surface micromachining are disclosed in U.S. Pat. Nos. 5,867,302, issued Feb. 2, 1999, and entitled “BISTABLE MICROELECTROMECHANICAL ACTUATOR”; and 6,082,208, issued Jul. 4, 2000, and entitled “METHOD FOR FABRICATING FIVE-LEVEL MICROELECTROMECHANICAL STRUCTURES AND MICROELECTROMECHANICAL TRANSMISSION FORMED”, the entire disclosures of which are incorporated by reference in their entirety herein.[0044]
• Surface micromachining generally entails depositing alternate layers of structural material and sacrificial material using an appropriate substrate which functions as the foundation for the resulting microstructure, which may include one or more individual microstructures. The term “substrate” as used herein means those types of structures that can be handled by the types of equipment and processes that are used to fabricate micro-devices on, within, and/or from the substrate using one or more micro photolithographic patterns. An exemplary material for the substrate is silicon. Various patterning operations (collectively encompassing the steps of masking, etching, and mask removal operations) may be executed on one or more of these layers before the next layer is deposited so as to define the desired microstructure. After the microstructure has been defined in this general manner, at least some of the various sacrificial layers are removed by exposing the microstructure and the various sacrificial layers to one or more etchants. This is commonly called “releasing” the microstructure from the substrate, typically to allow at least some degree of relative movement between the microstructure and the substrate. The term “sacrificial layer”, therefore, means any layer or portion thereof of any surface micromachined microstructure that is used to fabricate the microstructure, but which does not exist in the final configuration. Exemplary materials for the sacrificial layers described herein include undoped silicon dioxide or silicon oxide, and doped silicon dioxide or silicon oxide (“doped” indicating that additional elemental materials are added to the film during or after deposition). Exemplary materials for the structural layers of the microstructure include doped or undoped polysilicon and doped or undoped silicon. The various layers described herein may be formed/deposited by techniques such as chemical vapor deposition (CVD) and including low-pressure CVD (LPCVD), atmospheric-pressure CVD (APCVD), and plasma-enhanced CVD (PECVD), thermal oxidation processes, and physical vapor deposition (PVD) and including evaporative PVD and sputtering PVD, as examples.[0045]
• Only those portions of a microelectromechanical system that are relevant to the present invention will be described herein. There may, and typically will, be other microstructures that are included in a given microelectromechanical system.[0046]
• FIG. 1A illustrates a[0047]wafer12 having a plurality ofdie16. Typically each die16 will be of the same configuration. Each adjacent pair ofdie16 is separated by adie boundary20. Each die16 is defined by one field of a photolithographic stepper. An exemplary stepper capable of defining the die16 may be the Ultratech 1600DSA stepper manufactured by Ultratech Stepper, Inc., of San Jose, Calif. Any appropriate stepper may be utilized to define thedie16. It should be noted that thewafer12 may also have a plurality of edge die24 that define partial die patterns. The partial die24 generally are not utilized in a product, but instead are usually discarded, or are not patterned at all.
• FIG. 1B provides further details regarding the layout of the die[0048]16 on thewafer12. A microelectromechanical assembly is typically formed on only a certain portion of each die16. In one embodiment, the same microelectromechanical assembly is formed on each die16, and a chip having a plurality of these identical microelectromechanical assemblies may be defined by removing an appropriate collection of die16 from the wafer12 (e.g., by sawing). That area of a givendie16 that is occupied by a microelectromechanical assembly may be characterized as adevice region18. Eachdevice region18 of a givendie16 is surrounded by aperimeter region19. An inter-die region22 is disposed between each adjacent pair ofdie16, and is thereby defined by a portion of theperimeter region19 of each die16. The inter-die region22 between each adjacent pair ofdie16 is also commonly referred to in the art as a street or avenue. Alignment targets (not shown) for the stepper may be formed on thewafer12 in areas that will become the inter-die regions22 to assist in aligning the various die16 on thewafer12. Adjacent die16 on thewafer12 are typically separated by sawing along the appropriate inter-die regions22 surrounding a givendie16. As will be discussed in more detail below, one aspect of the present invention deals with a multi-die chip having a plurality of electrical traces extending between adjacent pairs ofdie16. Therefore, at least certain areas of the inter-die regions22 in this case will be occupied by these electrical traces.
• One embodiment of a chip[0049]26 that may be formed from thewafer12 is illustrated in FIG. 1C. The chip26 includes four die16 that were sawed from thewafer12 at least generally along therelevant die boundaries20. Any appropriate number ofdie16 may be used to define the chip26. Once again, in one embodiment an identical microelectromechanical assembly is formed on each die16. The chip26 includes achip perimeter27 and achip perimeter region28 that is spaced inwardly from thechip perimeter27. Thechip perimeter region27 is defined by that portion of aperimeter region19 of a die16 that does not abut aperimeter region19 of another die16.
• An appropriate microelectromechanical assembly is formed within the[0050]device region18 of each die16 of the chip26. One embodiment of such a microelectromechanical assembly is illustrated in FIG. 1D in the form of amirror array400. Themirror array400 is defined by a plurality ofrows402 ofmirror assemblies408. Power to eachrow402 ofmirror assemblies408 is provided by an off-chipelectrical contact assembly404 that is disposed on each end of eachrow402, and by abus406 that extends between eachrow402. Representative functions that may be performed by themirror array400 include, but are not limited to optical switching, adaptive optical arrays, and optical scanner arrays. Any number ofrows402 may be defined on thedevice region18 of a givendie16. Eachrow402 of themirror array400 may be defined by any number ofmirror assemblies408. In one embodiment, sixrows402 ofmirror assemblies408 are utilized by thearray400, and there are 6mirror assemblies408 in eachrow402. However, since there is a limited amount of space on each die16, the number ofmirror assemblies408 perdie16 is limited. Therefore, providing a chip26 having a plurality ofidentical die16, each with amirror array400 fabricated thereon, allows for realizing an increased number ofmirror assemblies408.
• Details regarding the configuration of each[0051]mirror assembly408 of themirror array400 are presented in FIG. 1E. Themirror assembly408 generally includes amirror410 and a pair ofpositioning assemblies416 that are fabricated using anappropriate substrate436. Themirror410 is interconnected with thesubstrate436 by a substrate interconnect412 of any appropriate type (e.g., an appropriately configured compliant member/spring). Themirror410 may be interconnected with the substrate412 in any appropriate manner in order to realize a desired movement of themirror410 relative to thesubstrate436 depending upon the position of each of thepositioning assemblies416. Themirror410 in fact need not be interconnected with thesubstrate436 at all.
• Each[0052]positioning assembly416 generally includes adisplacement assembly438. Thedisplacement assembly438 includes pair ofactuators426 that are collectively interconnected with adisplacement multiplier430. Power for each of theactuators426 is provided by an actuatorelectrical interconnect assembly440 from the bus406 (FIG. 1D). Eachpositioning assembly416 further includes a tether or coupling424 anelevator418. In this regard, thedisplacement multiplier430 is interconnected with one end of thetether424. The opposite end of thetether424 in turn is interconnected with a portion of theelevator418 that is able to move at least generally away from or toward thesubstrate436, depending upon the direction of motion of theactuators426 relative to thesubstrate436. This movable portion of theelevator418 in turn is interconnected with themirror410 by anelevator interconnect414 of any appropriate type and at any appropriate location.
• The[0053]actuators426 may be of any appropriate type for microelectromechanical applications. Bothactuators426 are interconnected with thesubstrate436 in any appropriate manner for movement at least generally in a lateral dimension (at least generally parallel to the lateral extent of the substrate436). One or more electrical traces (not shown in FIG. 1E, but defining the actuatorelectrical interconnect assembly440 illustrated in FIG. 1D) extend from thebus406 of themirror array400 to each of theactuators426. Movement of theactuators426 relative to thesubstrate436 is transferred to acommon output yoke428 or the like. Although a pair ofactuators426 are disclosed for eachpositioning assembly416, the number ofactuators426 perpositioning assembly416 is not of particular importance in relation to the present invention.
• The[0054]output yoke428 is appropriately interconnected with aninput structure432 of thedisplacement multiplier430. Anoutput structure434 of thedisplacement multiplier430 is interconnected with thetether424. Thedisplacement multiplier430 may be of any appropriate configuration to achieve a desired relative motion at least generally in the lateral dimension between theinput structure432 and theoutput structure434. Generally, theinput structure432 and theoutput structure434 each move relative to thesubstrate436 by a flexing of those beams of thedisplacement multiplier430 that are anchored to thesubstrate436. Displacement multipliers are described in U.S. Pat. No. 6,174,179 to Kota et al. and issued on Jan. 16, 2001, the entire disclosure of which is incorporated by reference herein.
• Movement of the[0055]output structure434 of thedisplacement multiplier430 is transferred to theelevator418 by thetether424. Theelevator418 may be of any appropriate configuration. Generally, theelevator418 includes afree end420 that is able to move at least generally away from or toward thesubstrate436 along an appropriate path, depending upon the direction of the motion of theactuators426. This motion may be characterized as being at least generally of a pivotal-like nature in that thefree end420 of theelevator418 moves at least generally about an axis that extends through a pair ofanchors422 where theelevator418 is fixed to thesubstrate436. Flexures or the like may be used to interconnect theelevator418 with theanchors422. This motion is then transferred to themirror410 by thecorresponding elevator interconnect414. It should be appreciated that themirror410 may be disposed in a variety of positions relative to thesubstrate436 depending upon the position of thefree end420 of each of theelevators418, where theelevators418 interconnect with themirror410, and where, if at all, themirror410 is interconnected with thesubstrate436.
• FIG. 2 illustrates a series of adjacent die of the type that may be formed on the[0056]wafer12 of FIG. 1A. Afirst die34, asecond die38, and athird die42 are generally formed on an appropriate substrate (such as thewafer12 of FIG. 1A). Thefirst die34 and second die38 are separated by a first die boundary46. Similarly, thesecond die38 and third die42 are separated by asecond die boundary50. The first die34 generally has a microelectromechanical assembly (not shown, but for instance, themirror array400 of FIG. 1D) disposed in afirst device region54. Likewise, thesecond die38 generally has a microelectromechanical assembly (not shown, but for instance, themirror array400 of FIG. 1D) disposed at asecond device region58, and thethird die42 generally has a microelectromechanical assembly (not shown, but for instance, themirror array400 of FIG. 1D) disposed at athird device region62. An inter-die region30ais disposed between thefirst device region54 and thesecond device region58, while an inter-die region30bis disposed between thesecond device region58 and thethird device region62. A plurality of first conductive lines or traces66 extend across the first die boundary46 and electrically interconnect the first andsecond device regions54,58 of the respective first andsecond die34,38. Similarly, a plurality of second conductive lines or traces70 extend across thesecond die boundary50 and interconnect the second andthird device regions58,62 of the respective second andthird die38,42. The first die34 also has a plurality of third conductive lines or traces68 that extend from thefirst device region54 to adie boundary36 of thefirst die34. Thisdie boundary36 may abut a similarly configured die (not shown) or may define the edge of a chip that includes the die34,38,42. Likewise, thethird die42 has a plurality of fourth conductive lines or traces72 that extend from thethird device region62 to adie boundary44 of thethird die42. Thisdie boundary44 similarly may abut a similarly configured die (not shown) or may define the edge of a chip that includes the die34,38,42. “Conductive lines or traces,” as referred to herein, generally are fabricated from an appropriate structural material(s) that is capable of providing an electrical path. An off-chip electrical contact74 (e.g., a bond pad or the like) is disposed in each of the various conductive lines between the corresponding device region and the corresponding die boundary.
• FIG. 3A illustrates a magnified view of an[0057]inter-die region80 between first andsecond die84,86, respectively. In one embodiment, a wafer may be fabricated to have each of its die exhibit the same characteristics to be discussed in relation to thedie84,86. Moreover, any chip may include any number of die having the type of characteristics to be discussed in relation to thedie84,86. Thefirst die84 and second die86 are separated by adie boundary82. Thefirst die84 includes a firstelectrical contact pad88 and afirst line shield90. Similarly, thesecond die86 has a secondelectrical contact pad92 and asecond line shield94. A conductive line or trace96aextends from thedie boundary82 to thefirst contact pad88. Similarly, a conductive line or trace96bextends from thedie boundary82 to thesecond contact pad92. Theconductive lines96a,96balso extend from thecontact pads88,92, respectively, to a device region (not shown) associated with the correspondingdie84,86.
• The[0058]first line shield90 houses only a portion of theconductive line96a. Thisfirst line shield90 includes a firstdistal end93 disposed toward but spaced back from thedie boundary82. Similarly, thesecond line shield94 houses only a portion of the conductive line96b.Thissecond line shield94 includes a seconddistal end97 disposed toward but spaced back from thedie boundary82. The first and second distal ends93,97 of the respective first and second line shields90,94 are each separated from thedie boundary82 by afirst distance85 of at least about 25 microns in one embodiment, and within a range of about 25 microns to about 100 microns in another embodiment. The first andsecond contact pads88,92 are also spaced back from thedie boundary82 by asecond distance82 of at least about 50 microns in one embodiment, and within a range of about 50 microns to about 200 microns in another embodiment. Spacing each of theshields90,94 back from thedie boundary82 alleviates the need to saw through theshields90,94 if thefirst die84 is to be separated from thesecond die86. Furthermore, spacing each of theshields90,94 back from thedie boundary82 also reduces the potential that theshields90,94 will become damaged during handling of the resultant chip(s). That is, theshields90,94 are sufficiently spaced from thedie boundary82 so that the potential for contacting the same during handling of the resultant chip(s) should be desirably reduced.
• FIG. 3B illustrates further details regarding the relationship between the[0059]shield90 and theconductive line96a, and the same is equally applicable to theshield94 and conductive line96b. Theconductive line96aand thefirst line shield90 are in direct contact with adielectric layer89 of thefirst die84. Thefirst line shield90 includes first and second laterally spacedshield walls76,77. Thefirst line shield90 has ashield top78 that is disposed in spaced relation to the conductive line96 by the first andsecond shield walls76,77. With this configuration, it should be appreciated that it would be desirable to avoid having to saw through theshields90,94 if separating the die84 from thedie86.
• FIGS. 3A and 3C illustrated that the end portions of the[0060]conductive lines96a,96bare bulged at thedie boundary82. This is done to ensure adequate “overlap” of theconductive line96aof thefirst die84 and the conductive line96bof thesecond die86. That is, the end portions of thelines96a,96bare bulged at thedie boundary82 to increase the potential for establishing electrical contact between thelines96a,96bwhen fabricating thedie84,86 on a wafer. FIG. 3D illustrates a situation where at least one of the die84′,86′ was misaligned on the wafer. Since the resulting configuration of FIG. 3D is different from that of FIGS. 3A and 3C, a “single prime” designation is used in FIG. 3D. Even though this misalignment exists in the case of the FIG. 3D embodiment, the bulged end portions of theconductive lines96a,96bstill sufficiently overlap at thedie boundary82 to establish an electric connection across thedie boundary82. The size of the bulge is dependant and determined by the die-to-die alignment tolerancing of the specific photolithographic stepper tool being used.
• FIGS.[0061]4A-4K illustrate a method for forming a conductive line or trace and corresponding line shield of the type discussed above in relation to FIGS.3A-D. In FIG. 4A, anoxide layer102 is formed over afirst substrate100 so that a lateral dimension of a top surface of theoxide layer102 is at least generally parallel with a firstupper surface101 of thefirst substrate100. FIG. 4B shows anon-conductive dielectric layer104 formed over theoxide layer102. While FIG. 4B illustrates that the firstsacrificial layer102 remains across the entirety of theupper surface101 of thefirst substrate100, other embodiments to be described herein have thisoxide layer102 patterned so that only part of theoxide layer102 remains prior to forming thedielectric layer104. In this case, thedielectric layer104 is in direct contact with theupper surface101 of thefirst substrate100.
• A first[0062]structural layer106 is formed over thedielectric layer104 in FIG. 4C, and in FIG. 4D the firststructural layer106 is patterned to form a first conductive line ortrace103. In FIG. 4E, a firstsacrificial layer108 is formed over the firstconductive line103. The portion of the secondsacrificial layer108 that is formed over the firstconductive line103 will likely be bulged to a certain degree. It may then be desirable to planarize the firstsacrificial layer108 into the form presented in FIG. 4F. FIG. 4G illustrates that first andsecond shield channels107A,107B can then be patterned into the firstsacrificial layer108 in spaced relation to and on opposite sides of the firstconductive line103. This patterning step of FIG. 4G generally includes etching entirely through the firstsacrificial layer108 and down to thedielectric layer104. Accordingly, these first andsecond shield channels107A,107B are generally at least partially defined by the secondsacrificial layer108.
• As shown in FIG. 4H, a second[0063]structural layer110 is then generally formed over the firstsacrificial layer108. The material that defines the secondstructural layer110 will also then occupy the space within thechannels107A,107B that were formed in the firstsacrificial layer107A,107B. The secondstructural layer108 may be patterned to define the upper portion of aline shield109 as illustrated in FIG. 41. Since there will be depressions in the secondstructural layer108 over thechannels107A,107B, it may be desirable to planarize the upper surface of the secondstructural layer108 before patterning the same. The resulting configuration from such a planarization is presented in FIG. 4J. Finally, and as shown in FIG. 4K (from the planarized configuration of FIG. 4J), the firstsacrificial layer108 is removed by contacting the same with an appropriate release etchant. The result of the method illustrated in FIGS.4A-4K is aconductive line103 that is substantially isolated from electrical “cross-talk” with any adjacent conductive lines by aline shield109. Both theconductive line103 and theshield109 are in direct contact with thenon-conductive dielectric layer104. In addition, theconductive line103 is appropriately separated from theline shield109 by anopen space105.
• Another embodiment of a[0064]die112 is presented in FIGS.5A-B. Thedie112 includes adie boundary134. Thisdie boundary134 may define an edge of a chip (where each die of the chip may be configured in the manner of the die112) or may join with a similarly configured die to define an inter-die region generally of the above-noted type (not shown). Any such adjoining die would of course be a mirror image of the configuration presented in FIG. 5A. The die112 of FIGS.5A-B generally includes adie perimeter region122 that is disposed inwardly of thedie boundary112, and adevice region124 that is disposed inwardly of thedie perimeter region122. Any appropriate microelectromechanical assembly may be fabricated in thedevice region124, including themirror array400 discussed above in relation to FIGS.1D-E.
• The[0065]die112 is configured in a manner so as to enhance the separation of the die112 from the wafer and to facilitate handling of the die112 once removed from a wafer. In this regard, thedie112 is formed on anappropriate substrate130. Anoxide layer132 is disposed on thesubstrate130 in thedevice region124, but not in thedie perimeter region122. One way in which this may be fabricated is by depositing theoxide layer132 over the entire surface of thesubstrate130, and thereafter patterning theoxide layer132 so as to remove theoxide layer132 from what is to be thedie perimeter region122. In one embodiment, theoxide layer132 is spaced from thedie boundary134 by a distance of at least about 25 microns, and in another embodiment by a distance within a range of about 25 microns to about 100 microns.
• A[0066]dielectric layer116 is formed over theoxide layer132 in thedevice region124 and directly on thesubstrate130 in thedie perimeter region122. As such, that portion of thedielectric layer116 in thedie perimeter region122 is vertically offset from that portion of thedielectric layer116 in thedevice region124. Because of theintermediate oxide layer132 in thedevice region124, thedielectric layer116 is disposed further from thesubstrate130 in thedevice region124 in relation to the die perimeter region122 (whichdielectric layer116 interfaces with the substrate130). An at least generally vertically disposedwall126 of dielectric material interconnects these vertically offset portions of thedielectric layer116.
• A plurality of[0067]conductive lines120A-D are formed on thedielectric layer116 including within thedevice region124, within thedie perimeter region122, and along thewall126. Theseconductive lines120A-D each extend to thedie boundary134 and also extend within thedevice region124.Shields136A-D at least generally of the type discussed above in relation to the embodiment of FIGS.3A-C are disposed over their correspondingconductive line120A-D. Preferably, eachsuch shield136A-D is spaced inwardly from thedie boundary134 in the same manner discussed above in relation to the embodiment of FIGS.3A-C.
• The configuration of the[0068]die112 provides a number of advantages. Initially, thedie112 realizes the above-noted advantages regarding having theshields136 being sufficiently spaced from thedie boundary134. Moreover, the configuration of thedie112 provides for an encasement of theoxide layer132. Consider the case were the die112 is formed on a wafer and is separated from the remainder of the wafer by sawing at least generally along its correspondingdie boundary134 or at least within thedie perimeter region122. Since the outer perimeter of theoxide layer132 is spaced inwardly from thedie boundary134, this sawing will not pass through theoxide layer132 and thereby will not expose theoxide layer132. As such, when thedie112 is exposed to an etchant to release the microelectromechanical assembly fabricated in itsdevice region124, the release etchant will not have access to theoxide layer132 and thereby will not remove any portion of theoxide layer132. This would not be the case if theoxide layer132 was retained both in thedevice region124 and in thedie perimeter region122, where the sawing would pass through theoxide layer132. Subsequent exposure of the die112 to a release etchant would likely remove at least a perimeter portion of theoxide layer132 and leave an overlying portion of thedielectric layer116 unsupported. This would not be desirable on a number of bases.
• Notwithstanding the benefits of the configuration of the[0069]die112, there is one potential drawback. There may be an issue of shorts developing between adjacentconductive lines120 on the at least generally vertically disposedwall126 of thedielectric layer116. When an appropriate layer is formed on thedielectric layer116 and patterned to define the conductive lines or traces120A-D, it may not be possible to remove all of the material between what are supposed to be thediscrete lines120A-D on thewall126 due to the etchant tendencies. The failure to define separate and discreteconductive lines120A-D on thewall126 may lead at least some of theconductive lines120A-D to short, which of course would not be desirable.
• Another embodiment of a[0070]die140 is illustrated in FIGS.6A-B. Generally, thedie140 realizes the same benefits as thedie112 of FIGS.5A-B. In addition, thedie140 desirably addresses the above-noted potential shorting problem of thedie112 of FIGS.5A-B. The die140 of FIGS.6A-B includes adie boundary162. Thisdie boundary162 may define an edge of a chip or may join with a similarly configured die to define an inter-die region generally of the above-noted type (not shown). Any such adjoining die would of course be a mirror image of the configuration presented in FIGS.6A-B. The die140 generally includes adie perimeter region154 that is disposed inwardly of thedie boundary162, and adevice region156 that is disposed inwardly of thedie perimeter region154. Any appropriate microelectromechanical assembly may be fabricated in thedevice region156, including themirror array400 discussed above in relation to FIGS.1D-E.
• The[0071]die140 is formed on asubstrate152. Anoxide layer160 is disposed on thesubstrate152 in thedevice region156, but not in thedie perimeter region154. That is, aperimeter161 of theoxide layer160 is laterally spaced from thedie boundary162. One way in which this may be fabricated is by depositing theoxide layer160 over the entire surface of thesubstrate152, and thereafter patterning theoxide layer160 so as to remove theoxide layer160 from what is to be thedie perimeter region154. In any case, adielectric layer150 is formed over theoxide layer116 in thedevice region156 and on thesubstrate152 in thedie perimeter region154. As such, that portion of thedielectric layer150 in thedie perimeter region154 is vertically offset from that portion of thedielectric layer150 in thedevice region156. An at least generally vertically disposedwall148 of dielectric material interconnects these vertically spaced portions of thedielectric layer150.
• The[0072]die140 further includes a plurality of conductive lines or traces166A-D and corresponding conductive lines or traces168A-D that are arranged/electrically interconnected in a manner which alleviates the shorting issue discussed above in relation to thedie112. In this regard, theconductive lines166A-D progress from thedie boundary162 toward, but not to, thewall148 of thedielectric layer150 such that they terminate in spaced relation thereto. The conductive lines168A-D are disposed in thedevice region156 and thereby in overlying relation to theoxide layer160. These conductive lines168A-D progress toward, but not to, thewall148 from an opposite side/direction in relation to theconductive lines166A-D. Since the conductive lines168A-D are separated from thesubstrate152 by only thedielectric layer150, while the conductive lines168A-D are separated from thesubstrate152 by both thedielectric layer150 and theoxide layer160, theconductive lines166A-D are vertically offset from their corresponding conductive line168A-D. Shields170A-D generally of the type discussed above in relation to the embodiment of FIGS.3A-C are disposed over their corresponding conductive lines168A-D. Preferably, eachsuch shield170A-D is spaced inwardly from thedie boundary162 in the same manner discussed above in relation to the embodiment of FIGS.3A-C.
• The[0073]conductive lines166A-D are electrically interconnected with their corresponding conductive lines168A-D by a corresponding jump connector orbridge178A-D. Details regarding the configuration of thesebridges178A-D are illustrated in FIG. 6A. Thebridge178A includes first and second electricallyconductive posts182,184 that contact and extend at least generally upwardly from the respectiveconductive lines166A and168A. Each of theseposts182,184 may be formed from one or more structural layers in a surface micromachined system (two of such layers in the illustrated embodiment). Since thepost182 interfaces with theconductive line166A, it is taller than thepost184 that interfaces with the conductive line168A and that is disposed at a higher elevation. Both the first andsecond posts182 and184 are also laterally spaced from thewall148 of thedielectric layer150. In order to reduce the potential for damage to thebridge178A during handling, thepost182 is spaced back from thedie boundary162 by a distance of at least about 25 microns in one embodiment, and within a range of about 25 microns to about 100 microns in another embodiment.
• An electrically[0074]conductive jumper180A extends between and electrically interconnects theposts182,184 of thebridge178A. Thejumper180A is disposed in vertically spaced relation to the uppermost portion of thewall148 of thedielectric layer150. Therefore, a current flowing through the conductive line168A from thedevice region156 flows up thepost184 through thejumper180A, down thepost182, and through the conductive line168A. As a result of this bypass, the possible existence of any material that is used to form theconductive lines166A and168A and that is not removed from thewall148 of thedielectric layer150 when patterning theconductive lines166A,168A will be electrically isolated from theconductive lines166A,168A.
• FIGS.[0075]7A-7Q illustrate a method for forming multiple, electrically interconnected die of the type presented in FIGS.6A-B. Referring to FIG. 7A, afirst substrate212 is utilized as a base material. Multiple layers are sequentially deposited/formed over thisfirst substrate212. As illustrated in FIG. 7B, afirst oxide layer216 is formed over thefirst substrate212 so that a lateral dimension of atop surface218 of thefirst oxide layer216 is at least generally parallel with a firstupper surface214 of thefirst substrate212. FIG. 7C then shows that a laterally extendingdie boundary channel222 is patterned to encompass adie boundary226 that separates first andsecond die230,232. Afirst wall234 of thedie boundary channel222 is generally defined by afirst portion236 of thefirst oxide layer216 disposed on thefirst die230. Similarly, asecond wall240 of thedie boundary channel222 is defined by a second portion242 of thefirst oxide layer216 disposed on thesecond die232. Afloor246 of thedie boundary channel222 is defined by thefirst substrate212. The first andsecond walls234,240 of thedie boundary channel222 are at least generally vertically disposed. In one embodiment, the first andsecond walls234,240 of thedie boundary channel222 are each separated from thedie boundary226 by a first distance250 of at least about 50 microns.
• Referring to FIG. 7D, a[0076]dielectric layer220 is formed over thefirst oxide layer216 and thedie boundary channel222. Thus, the first andsecond walls234,240 and thefloor246 of theboundary channel222 are covered with thedielectric layer220. Accordingly, a direct interface is provided between thedielectric layer220 and thefirst substrate212 at thefloor246 of theboundary channel222. That is, thedielectric layer220 and the portion of thefirst substrate212 that defines thefloor246 of theboundary channel222 are in a surface-to-surface contact relationship.
• With regard to the remaining portion of the method for making the[0077]chip140 of FIGS.6A-B, the description will be directed only to thefirst die230. However, homologous structural components will be shown (but not described) for thesecond die232. It will be understood that any of the structural and/or functional descriptions pertaining to thefirst die230 may also pertain to thesecond die232.
• As shown in FIG. 7E, a first[0078]structural layer224 is formed over thefirst dielectric layer220. Referring to FIG. 7F, this firststructural layer224 is generally patterned to at least formconductive lines266,268 that are separate and discrete from each other. Theconductive line266 is positioned over thefloor246 of theboundary channel222 and theconductive line268 is positioned over thefirst oxide layer216 such that thelines266,268 are vertically offset. Additionally, this patterning step exposes aknee area254 defined by afirst portion256 of thedielectric layer220 which generally covers thefirst wall234 of thedie boundary channel222, asecond portion258 of thedielectric layer220 which covers afirst segment262 of thefloor246 of thedie boundary channel222 juxtaposed to thefirst wall234, and athird portion260 of thedielectric layer220 which covers asecond segment264 of thetop surface218 of thefirst oxide layer216 juxtaposed to thefirst wall234.
• Referring to FIG. 7G, a first[0079]sacrificial layer228 is formed over the firststructural layer224 including theconductive lines266,268. This firstsacrificial layer228 is then patterned to form first andsecond post receptacles270,272, as illustrated in FIG. 7H. Afirst bottom surface274 of thefirst post receptacle270 is defined by a portion of theconductive line266. Similarly, a secondbottom surface276 of thesecond post receptacle272 is defined by a portion of theconductive line268. In addition,walls280 of these first andsecond post receptacles270,272 are at least partially defined by the firstsacrificial layer228. As illustrated, the patterning of these first andsecond post receptacles270,272 includes etching through the entirety of the firstsacrificial layer228. Thus, at a minimum, these first andsecond post receptacles270,272 allow for establishing a structural connection with the respectiveconductive lines266,268 of the firststructural layer224.
• Referring now to FIG. 7I, a second[0080]structural layer238 is formed over the firstsacrificial layer228. More specifically, the structural material that makes up the secondstructural layer238 is also deposited within and at least substantially fills the first andsecond post receptacles270,272. In other words, this structural material substantially occupies an entirety of the first andsecond post receptacles270,272. In addition, first andsecond depressions280,282 are formed on a superior surface278 of the secondstructural layer238 generally in vertical alignment with where the structural material occupies the respective first andsecond post receptacles270,272. Referring to FIG. 7J, this secondstructural layer238 is then patterned to have respective first andsecond posts284,286 having lower portions that are generally complimentary in shape, design, and configuration with the first andsecond post receptacles270,272. As shown, the resultant first andsecond posts284,286 are in direct contact with the respectiveconductive lines266,268 of the firststructural layer224.
• Referring now to FIG. 7K, a second[0081]sacrificial layer244 is formed over the secondstructural layer238. More specifically, the secondsacrificial layer244 is formed over the first andsecond posts284,286 of the secondstructural layer238 as well as the firstsacrificial layer228. Although FIG. 7K shows a definitive border between the first and secondsacrificial layers228,244, typically this will not be the case as the secondsacrificial layer244 and the firstsacrificial layer228 will generally appear to be continuous. In any case, anupper surface292 of the secondsacrificial layer244 may retain a wavy or uneven contour after being deposited (not shown). Referring to FIG. 7L, theupper surface292 of the thirdsacrificial layer244 may then be planarized in an appropriate manner, such as by chemical polishing, to yield a sufficiently flatupper surface292 of the secondsacrificial layer244, but one which still has a sufficient thickness over theposts84,86.
• The second[0082]sacrificial layer244 is then patterned to define third andfourth post receptacles271,273, as illustrated in FIG. 7M. A third bottom surface275 of the third post receptacle271 is defined by thefirst post284. Similarly, a fourth bottom surface277 of thefourth post receptacle273 is defined by thesecond post286. In addition,walls294 of the third andfourth post receptacles271,273 are defined by the secondsacrificial layer244. Thus, at a minimum, these third andfourth post receptacles271,273 allow for establishing a structural interconnection with the respective first andsecond posts284,286. Accordingly, this patterning of the third andfourth post receptacles271,273 generally includes etching entirely through the secondsacrificial layer244 to the first andsecond posts284,286. In any case, the third andfourth post receptacles271,273 are preferably positioned directly above (i.e., vertically aligned with) the corresponding first andsecond posts284,286, although the portions of the first andsecond posts284,286, which are exposed by respective third andfourth post receptacles271,273, will typically have a slightly larger diameter than theircorresponding post receptacles271,273.
• Referring now to FIG. 7N, a third[0083]structural layer248 is formed over the secondsacrificial layer244. Structural material of this thirdstructural layer248 is deposited within the third andfourth post receptacles271,273 to form respective third andfourth posts285,287. In other words, the structural material that defines the thirdstructural layer248 is also deposited within and at least substantially fills the third andfourth post receptacles271,273 that were previously formed in the secondsacrificial layer244, and such may be characterized as being part of the thirdstructural layer248. Although FIG. 7N shows a definitive intersection line between the first andthird posts284,285, as well as between the second andfourth posts286,287, typically such an intersection will not exist and instead will at least appear to be continuous structures.
• As a result of depositing/forming the third[0084]structural layer248, third and fourth depressions281,283 may appear on a superior surface279 of the thirdstructural layer248 generally in vertical alignment with where the structural material occupies the respective third andfourth post receptacles271,273. Turning to FIG. 7O, this thirdstructural layer248 is then patterned to have the third andfourth posts285,287 generally coinciding with the shape, design, and configuration of the third andfourth post receptacles271,273, respectively. In addition, the thirdstructural layer248 is at the same time patterned to have a bridge beam orjumper296 extending between and interconnecting the third andfourth posts285,287. Since thedepressions298 exist on the upper surface of the thirdstructural layer248 over what was once thepost receptacles271,273, it may be desirable to planarize the upper surface of the thirdstructural layer248 before patterning the same to define theposts285,287 and thejumper296. The resulting configuration of such a planarization is presented in FIG. 7P. In any case, a jump connector or bridge of thefirst die230 is thus defined by the combined structure of the first, second, third, andfourth posts284,286,285,287, and thejumper296. This completes the definition of the jump connector orbridge structure300. It should be appreciated that a system that includes thebridge structure300 will likely include other microstructural components than those illustrated in the fabrication method of FIGS.7A-7Q. It should also be appreciated that the method illustrated in FIG.7A-7Q may include some variational embodiments. For example, one variational embodiment may include the firstsacrificial layer228 being deposited to exhibit an appropriate thickness and then planarized and patterned. Subsequently, an entire bridge structure may then be made from a deposition and patterning of the secondstructural layer238, thus making a bridge structure without using the secondsacrificial layer244 and thirdstructural layer248 in this variation of the fabrication process.
• FIG. 7P also shows, as a first option, that the[0085]first die230 may be separated from thesecond die232 to define a chip, such as by sawing at least at thedie boundary226. This separation of thefirst die230 from thesecond die232 generally includes cutting through an entirety of whatever layers/materials are positioned at thedie boundary226, in this case, the firststructural layer224, thedielectric layer220, thefirst substrate212, the firstsacrificial layer228, and the secondsacrificial layer244. This separation step generally exposes adie edge231. Thisdie edge231 is generally devoid of exposed oxide material from thefirst oxide layer216 between thedielectric layer220 and thefirst substrate212. Thereafter, the chip may be exposed to a release etchant to remove sacrificial layers in the system. Specifically, and referring to FIG. 7Q, thefirst die230 is exposed to a release etchant which removes the exposed sacrificial material of any of the sacrificial layers, including thesacrificial layers228,244. However, none of thefirst oxide layer216 is etched away at theedge231 of thefirst die230 due to the firstsacrificial layer216 not being exposed at theedge231.
• Another option would be to include both the[0086]first die230 and thesecond die232 in a chip. In this case, it should be appreciated that the above-described structure would allow an appropriate electrical signal to be transferred between thefirst die230 and thesecond die232 using the pair ofjump connectors300 between thefirst die230 and thesecond die232.
• Those skilled in the art will now see that certain modifications can be made to the apparatus and methods herein disclosed with respect to the illustrated embodiments, without departing from the spirit of the instant invention. And while the invention has been described above with respect to the preferred embodiments, it will be understood that the invention is adapted to numerous rearrangements, modifications, and alterations, and all such arrangements, modifications, and alterations are intended to be within the scope of the appended claims.[0087]

Claims (65)

What is claimed:

1. A chip, comprising:

a substrate;

an oxide layer;

a dielectric layer; and

a plurality of die, wherein each of said plurality of die comprises a die perimeter region and a device region disposed inwardly of said die perimeter region, wherein said device region of each of said plurality of die comprises a first microelectromechanical assembly such that said chip comprises a plurality of said first microelectromechanical assemblies, wherein said oxide layer is disposed between said dielectric layer and said substrate in said device region of each of said plurality of die, and wherein said die perimeter region of each of said plurality of die is devoid of said oxide layer such that said dielectric layer is disposed directly on said substrate in each said die perimeter region.

2. A chip, as claimed inclaim 1, wherein:

said substrate is formed from a material selected from the group consisting of silicon, gallium arsenide, gallium arsenide phosphide, and ceramics, said oxide layer is formed from a material selected from the group consisting of silicon dioxide and silicon oxynitrides, and said dielectric layer is formed from a material selected from the group consisting of silicon nitride and silicon carbide.

3. A chip, as claimed inclaim 1, wherein:

said oxide layer is totally encased by said dielectric layer.

4. A chip, as claimed inclaim 1, wherein:

each adjacent pair of die of said plurality of die are separated by a die boundary, wherein said oxide layer in each said die is spaced back at least about 25 microns back from each surrounding said die boundary.

5. A chip, as claimed inclaim 1, wherein:

each of said plurality of die are of an identical structure.

6. A chip, as claimed inclaim 1, wherein:

each said first microelectromechanical assembly comprises a mirror array.

7. A chip, as claimed inclaim 1, wherein:

each said first microelectromechanical assembly comprises a plurality of mirrors and a plurality of actuators, wherein at least one said actuator is interconnected with each said mirror to control a position of said mirror relative to said substrate.

8. A chip, as claimed inclaim 1, wherein:

said chip is configured as a device selected from the group consisting of an optical switch, an adaptive optical array, an optical scanner array, and a thermal imaging array.

9. A chip, as claimed inclaim 1, wherein:

said chip is configured as a device comprising an array of microstructures that encompasses an area greater in size than a single said device region.

10. A chip, as claimed inclaim 1, wherein:

at least a portion of each said first microelectromechanical assembly is fabricated by surface micromachining.

11. A chip, as claimed inclaim 1, wherein:

each adjacent pair of die of said plurality of die are separated by a die boundary, wherein each said first microelectromechanical assembly comprises at least one vertically spaced layer, wherein there are no said vertically spaced layers within about 100 microns of any of said die boundaries.

12. A chip, as claimed inclaim 1, wherein:

said dielectric layer in said die perimeter region of each of said plurality of die is vertically offset from said dielectric layer in said device region of each of said plurality of die.

13. A chip, as claimed inclaim 1, wherein:

said die perimeter region of each of said plurality of die consists essentially of said substrate, said dielectric layer, and a plurality of electrical traces.

14. A chip, as claimed inclaim 1, wherein:

said plurality of die comprises first and second die disposed in abutting relation, wherein said chip further comprises:

a first electrical trace disposed in said device region of said first die;

a second electrical trace disposed in said device region of second die;

a third electrical trace extending across adjacent die perimeter regions of said first and second die, wherein said first electrical trace terminates prior to reaching said third electrical trace, and wherein said second electrical trace terminates prior to reaching said third electrical trace.

15. A chip, as claimed inclaim 14, wherein:

said first and second electrical traces are disposed at a first elevation and said third electrical trace is disposed at a second elevation that is different from said first elevation.

16. A chip, as claimed inclaim 14, wherein:

said third electrical trace is vertically offset in relation to each of said first and second electrical traces.

17. A chip, as claimed inclaim 14, further comprising:

a first electrical jump connection between said first and third electrical traces; and

a second electrical jump connection between said second and third electrical traces.

18. A chip, as claimed inclaim 17, wherein:

said first electrical jump connection comprises a first post interconnected with said first electrical trace, a second post interconnected with said third electrical trace, and a first jumper disposed in vertically spaced relation to an entirety of said dielectric layer and extending between and interconnecting said first and second posts; and

said second electrical jump connection comprises a third post interconnected with said second electrical trace, a fourth post interconnected with said third electrical trace, and a second jumper disposed in vertically spaced relation to an entirety of said dielectric layer and extending between and interconnecting said third and fourth posts.

19. A chip, as claimed inclaim 17, wherein:

said first and second die are separated by a die boundary, wherein each of said first and second jump connections are spaced from said die boundary by a distance of at least about 25 microns.

20. A chip, as claimed inclaim 1, further comprising:

a plurality of electrical traces extending between said device regions of each adjacent pair of said plurality of die.

21. A chip, as claimed inclaim 20, further comprising:

a shield disposed over each of said plurality of electrical traces, wherein each said shield is spaced back at least about 25 microns from a die boundary between each said in adjacent pair of said plurality of die.

22. A chip, as claimed inclaim 1, further comprising:

a chip perimeter and a chip perimeter region disposed inwardly of said chip perimeter, wherein said dielectric layer is disposed directly on said substrate in said chip perimeter region such that said chip perimeter region is devoid of said oxide layer.

23. A chip, as claimed inclaim 21, further comprising:

a plurality of electrical traces extending through said chip perimeter region and terminating at said chip perimeter.

24. A chip, as claimed inclaim 23, further comprising:

a shield disposed over at least a portion of each of said plurality of electrical traces, wherein each said shield is spaced back at least about 25 microns from said chip perimeter.

25. A chip, comprising:

a substrate;

a plurality of die comprising first and second die, wherein each of said plurality of die comprises a die perimeter region and a device region disposed inwardly of said die perimeter region, wherein said device region of each of said plurality of die comprises a first microelectromechanical assembly such that said chip comprises a plurality of said first microelectromehanical assemblies;

a first electrical trace disposed in said device region of said first die;

a second electrical trace disposed in said device region of said second die;

a third electrical trace extending across adjacent die perimeter regions of said first and second die, wherein said first electrical trace terminates prior to reaching said third electrical trace, and wherein said second electrical trace terminates prior to reaching said third electrical trace;

a first electrical jump connection between said first and third electrical traces; and

a second electrical jump connection between said second and third electrical traces.

26. A chip, as claimed inclaim 25, wherein:

said first and second die are separated by a die boundary, wherein each of said first and second jump connections are spaced from said die boundary by a distance of at least about 25 microns.

27. A chip, as claimed inclaim 25, wherein:

said first electrical jump connection comprises a first post interconnected with said first electrical trace, a second post interconnected with said third electrical trace, and a first jumper disposed in vertically spaced relation to said first and third electrical traces and extending between and interconnecting said first and second posts; and

said second electrical jump connection comprises a third post interconnected with said second electrical trace, a fourth post interconneced with said third electrical trace, and a second jumper disposed in vertically spaced relation said second and third electrical traces and extending between and interconnecting said third and fourth posts.

28. A chip, as claimed inclaim 25, wherein:

each of said plurality of die are of an identical structure.

29. A chip, as claimed inclaim 25, wherein:

each said first microelectromechanical assembly comprises a mirror array.

30. A chip, as claimed inclaim 25, wherein:

each said first microelectromechanical assembly comprises a plurality of mirrors and a plurality of actuators, wherein at least one said actuator is interconnected with each said mirror to control a position of said mirror relative to said substrate.

31. A chip, as claimed inclaim 25, wherein:

said chip is configured as a device selected from the group consisting of an optical switch, an adaptive optical array, an optical scanner aray, and a thermal imaging array.

32. A chip, as claimed inclaim 25, wherein:

at least a portion of each said first microelectromechanical assembly is fabricated by surface micromachining.

33. A chip, as claimed inclaim 25, wherein:

each adjacent pair of die of said plurality of die are separated by a die boundary, wherein each said first microelectromechanical assembly comprises at least one vertically spaced layer, wherein there are no said vertically spaced layers within about 100 microns of any of said die boundaries.

34. A chip, as claimed inclaim 25, wherein:

said first and second electrical traces are disposed at a first elevation and said third electrical trace is disposed at a second elevation that is different from said first elevation.

35. A chip, as claimed inclaim 25, wherein:

said third electrical trace is vertically offset in relation to each of said first and second electrical traces.

36. A chip, as claimed inclaim 25, further comprising:

an oxide layer;

a dielectric layer, wherein said oxide layer is disposed between said dielectric layer and said substrate in said device region of each of said plurality of die, and wherein said die perimeter region of each of said plurality of die is devoid of said oxide layer such that said dielectric layer is disposed directly on said substrate in each said die perimeter region.

37. A chip, as claimed inclaim 36, wherein:

said die perimeter region of each of said plurality of die consists essentially of said substrate, said dielectric layer, and a plurality of electrical traces.

38. A chip, as claimed inclaim 36, wherein:

said substrate is formed from a material selected from the group consisting of silicon, gallium arsenide, gallium arsenide phosphide, and ceramics, said oxide layer is formed from a material selected from the group consisting of silicon dioxide and silicon oxynitrides, and said dielectric layer is formed from a material selected from the group consisting of silicon nitride and silicon carbide.

39. A chip, as claimed inclaim 36, wherein:

said oxide layer is totally encased by said dielectric layer.

40. A chip, as claimed inclaim 36, wherein:

each adjacent pair of die of said plurality of die are separated by a die boundary, wherein said oxide layer in each said die is spaced back at least about 25 microns from each surrounding said die boundary.

41. A chip, as claimed inclaim 36, wherein:

said dielectric layer in said die perimeter region of each of said plurality of die is vertically offset from said dielectric layer in said device region of each of said plurality of die.

42. A chip, as claimed inclaim 36, further comprising:

a chip perimeter and a chip perimeter region disposed inwardly of said chip perimeter, wherein said dielectric layer is disposed directly on said substrate in said chip perimeter region such that said chip perimeter region is devoid of said oxide layer.

43. A chip, as claimed inclaim 42, further comprising:

a plurality of electrical traces extending through said chip perimeter region and terminating at said chip perimeter.

44. A chip, as claimed inclaim 43, further comprising:

a shield disposed over at least a portion of each of said plurality of electrical traces, wherein each said shield is spaced back at least about 25 microns from said chip perimeter.

45. A method for fabricating a chip, comprising the steps of:

forming a first oxide layer over a substrate;

forming a first die boundary channel in said first oxide layer that extends down through said first oxide layer and to said substrate;

forming a dielectric layer over said first oxide layer and within at least a lower portion of said first die boundary channel;

defining first and second die on opposite sides of at least a portion of said first die boundary channel, wherein each said die comprises a microelectromechanical assembly; and

separating said first die from said second die at least along a portion of said first die boundary channel.

46. A method, as claimed inclaim 45, wherein said forming a first die boundary channel step comprises patterning said first oxide layer.

47. A method, as claimed inclaim 45, wherein said forming a first die boundary channel step comprises defining first and second sidewalls of said first die boundary channel with first and second edge surfaces, respectively, of said first oxide layer.

48. A method, as claimed inclaim 47, wherein said first and second edge surfaces of said first oxide layer are separated by a distance within a range of about 50 microns to about 300 microns.

49. A method, as claimed inclaim 47, wherein said first and second edge surfaces of said first oxide layer are disposed in at least generally parallel relation.

50. A method, as claimed inclaim 47, wherein said forming a dielectric layer step comprises coating said first and second edge surfaces of said first oxide layer with a dielectric material.

51. A method, as claimed inclaim 45, wherein said forming a first die boundary channel step comprises defining a closed perimeter for said first die boundary channel, wherein said first die is surrounded by said first die boundary channel.

52. A method, as claimed inclaim 45, wherein said forming a dielectric layer step comprises filling only a lower portion of said first die boundary channel with a dielectric material.

53. A method, as claimed inclaim 45, wherein said forming a dielectric layer step comprises protecting said first oxide layer from exposure to a release etchant to which said chip is exposed after said separating step.

54. A method, as claimed inclaim 45, wherein said defining first and second die step comprises using a field stepper.

55. A method, as claimed inclaim 45, wherein:

said defining first and second die step comprises forming an identical said microelectromechanical assembly on each of said first and second die.

56. A method, as claimed inclaim 55, wherein said defining first and second die step comprises forming all microstructures of said microelectromechanical assembly for each of said first and second die outside of said first die boundary channel.

57. A method, as claimed inclaim 45, wherein said separating step comprises sawing at least generally along said at least a portion of said first die boundary channel.

58. A method, as claimed inclaim 45, wherein said defining first and second die step comprises forming at least one electrical trace that extends across said at least a portion of said first die boundary channel directly on said dielectric layer.

59. A method, as claimed inclaim 58, further comprising the step of forming a shield over only a portion of each said electrical trace such that said separating step fails to pass through any portion of any said shield.

60. A method, as claimed inclaim 59, wherein said separating step defines a first edge of said chip, wherein each said shield is separated from said first edge by a distance of at least about 25 microns.

61. A method, as claimed inclaim 45, wherein said defining first and second die step comprises forming a first electrical trace for said first die that is located out of said first die boundary channel, forming a second electrical trace for said second die that is located out of said first die boundary channel, forming a third electrical trace on said dielectric layer within said first die boundary channel, forming a first jump connection between said first and third electrical traces, and forming a second jump connection between said second and third electrical traces.

62. A method, as claimed inclaim 61, wherein a first portion of said third electrical trace is associated with said first die and a second portion of said third electrical trace is associated with said second die, and wherein ends of said first and second portions of said third electrical trace are merged together.

63. A method, as claimed inclaim 61, wherein said forming a dielectric layer step comprises forming a second die boundary channel within said first die boundary channel, wherein said second die boundary channel comprises a base and first and second sidewalls that are defined by a dielectric material, wherein said third electrical trace terminates prior to reaching said first sidewall of said second die boundary channel and prior to reaching said second sidewall of said second die boundary channel.

64. A method for fabricating a chip, comprising the steps of:

forming a plurality of rows and columns of die on a wafer, wherein each of said die is identical and comprises a first microelectromechanical assembly; and

electrically interconnecting at least one of each adjacent pair of said die in each of said columns and each said adjacent pair of said die in each of said rows such that a first chip of a first number of said die may be formed from said wafer and that a second chip of a second number of said die may be formed from said wafer, wherein said first number is different from said second number.

65. A chip, comprising:

a substrate;

a plurality of die comprising first and second die, wherein each said die comprises a first microelectromechanical assembly such that said chip comprises a plurality of said first microelectromechanical assemblies;

a die boundary between each adjacent pair of said die and comprising a first die boundary between said first and second die;

a first electrical trace extending from said first die boundary at least toward said first microelectromechanical assembly of said first die;

a first shield that is spaced from said first die boundary by a distance of at least about 25 microns and that is then disposed over a corresponding portion of said first electrical trace;

a second electrical trace extending from said first die boundary at least toward said first microelectromechanical assembly of said second die; and

a second shield that is spaced from said first die boundary by a distance of at least about 25 microns and that is then disposed over a corresponding portion of said second electrical trace.

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