US20030173641A1 - Semiconductor device with STI and its manufacture - Google Patents

Abstract

A semiconductor device includes: a silicon substrate with semiconductor elements; an isolation trench formed in the silicon substrate for isolating active regions in the silicon substrate, the isolation trench having a trapezoidal cross sectional shape having a width gradually narrowing with a depth from the surface of the silicon substrate; a first liner insulating film formed on the surface of the trench and made of a silicon oxide film or a silicon oxynitride film having a thickness of 1 to 5 nm; a second liner insulating film formed on the first liner insulating film and made of a silicon nitride film having a thickness of 2 to 8 nm; and an isolation region burying the trench defined by the second liner insulating film.

Description

CROSS REFERENCE TO RELATED APPLICATION
• This application is based on Japanese Patent Application No. 2002-074871, filed on Mar. 18, 2002, the entire contents of which are incorporated herein by reference.[0001]
BACKGROUND OF THE INVENTION
• A) Field of the Invention[0002]
• The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having shallow trench isolation (STI) and its manufacture method.[0003]
• B) Description of the Related Art[0004]
• Local oxidation of silicon (LOCOS) is known as one method for the element isolation of a semiconductor device.[0005]
• According to LOCOS technique, a silicon oxide film is formed on a silicon substrate as a buffer layer, thereafter a silicon nitride film as an oxidation prevention film is formed, the silicon nitride film is patterned and then the surface of the silicon substrate is thermally oxidized.[0006]
• While the silicon substrate is thermally oxidized, oxidizing species such as oxygen and moisture invade the buffer silicon oxide film. As a result, the silicon substrate surface under the silicon nitride film is oxidized and silicon oxide regions having a shape called a bird's beak are formed. These bird's beak regions cannot be used substantially as an element forming region (active region) so that the area of the active region is reduced.[0007]
• If the surface of a silicon substrate is thermally oxidized by using a silicon nitride film pattern having openings of various sizes, the thickness of a silicon oxide film formed on the silicon substrate surface in an area corresponding to an opening of a smaller size is thinner than that of a silicon oxide film formed in an area corresponding to an opening of a lager size. This phenomenon is called thinning.[0008]
• The area not used as the active region in the whole area of a semiconductor substrate increases because of bird's beaks and thinning which occur more often as semiconductor devices are made finer. Namely, since a ratio of the active region to the whole substrate area is substantially lowered, high integration of semiconductor devices is hindered.[0009]
• Trench isolation (TI) technique is know as the technique of forming active regions by which a trench is formed in the surface layer of a semiconductor substrate and insulating material or polysilicon is filled in the trench. This method has been used bipolar transistor LSIs which require a deep isolation region.[0010]
• Application of trench isolation technique to MOS transistor LSIs is prevailing because of no bird's beak and thinning. Isolation for a MOS transistor LSI does not require as deep isolation as that of a bipolar transistor LSI and can be realized by a relatively shallow trench of about 0.1 to 1.0 μm. This is called a shallow trench isolation (STI) structure.[0011]
• With reference to FIGS. 9A to[0012]9H, an STI process will be described.
• As shown in FIG. 9A, on the surface of a[0013]silicon substrate1, asilicon oxide film2 having a thickness of, e.g., 10 nm is formed by thermal oxidation. On thissilicon oxide film2, asilicon nitride film3 having a thickness of e.g., 100 to 150 nm is formed by chemical vapor deposition (CVD). Thesilicon oxide layer2 functions as a buffer layer for relaxing a stress between thesilicon substrate1 andsilicon nitride film3. Thesilicon nitride film3 is functions also as a stopper layer during a later polishing process.
• A[0014]resist pattern4 is formed on thesilicon nitride film3. An opening defined by theresist pattern4 defines an area in which the active region is formed. The region of the silicon substrate under the resist pattern becomes an active region where device elements are formed.
• By using the[0015]resist pattern4 as an etching mask, thesilicon nitride film3 exposed in the opening and the underlyingsilicon oxide film2 andsilicon substrate1 are etched to a depth of, e.g., about 0.5 μm by reactive ion etching (RIE) to form atrench6. Thereafter, theresist pattern4 is removed.
• As shown in FIG. 9B, the silicon substrate surface exposed in the[0016]trench6 is thermally oxidized to form asilicon oxide film7 having a thickness of, e.g., 10 nm.
• As shown in FIG. 9C, burying the trench, a[0017]silicon oxide layer9 is deposited over the silicon substrate, for example, by high density plasma (HDP) CVD. In order to make dense thesilicon oxide film9 as the isolation region, the silicon substrate is annealed, for example, in a nitrogen atmosphere at 900 to 1100° C.
• As shown in FIG. 9D, by using the[0018]silicon nitride film3 as a stopper, thesilicon oxide layer9 is etched downward by chemical mechanical polishing (CMP) or reactive ion etching (RIE). Thesilicon oxide film9 is left only in the trench defined by thesilicon nitride film3. At this stage, annealing may be performed for making silicon oxide dense.
• As shown in FIG. 9E, the[0019]silicon nitride film3 is removed by using hot phosphoric acid. Next, the buffersilicon oxide film2 on the surface of thesilicon substrate1 is removed by using dilute hydrofluoric acid. At this time, thesilicon oxide film9 buried in the trench is also etched.
• As shown in FIG. 9F, the surface of the[0020]silicon substrate1 is thermally oxidized to form a sacrificialsilicon oxide film22 on thesilicon substrate1 surface. Impurity ions of a predetermined conductivity type are implanted into the surface layer of thesilicon substrate1 via the sacrificial silicon oxide film, and activated to formwells10 of the predetermined conductivity type in thesilicon substrate1.
• The sacrificial[0021]silicon oxide film22 is thereafter removed by using dilute hydrofluoric acid. While the sacrificial silicon oxide film is removed, thesilicon oxide layer9 is also etched by the dilute hydrofluoric acid. By a plurality of hydrofluoric acid processes, thesilicon oxide layer9 buried in the trench is etched so that a dug divot or indent is formed along the side of the active region.
• As shown in FIG. 9G, the surface of the exposed silicon substrate is thermally oxidized to form a[0022]silicon oxide film11 having a desired thickness which film is used as the gate insulating film. Apolysilicon layer12 is deposited over thesilicon substrate1, and patterned to form a gate electrode. Impurity ions of the conductivity type opposite to that of thewells10 are implanted and activated to form source/drain regions. If necessary, side wall spacers are formed on the side walls of the gate electrode, and impurity ions are again implanted and activated to form high impurity concentration source/drain regions.
• FIG. 9H shows the characteristics of drain current relative to gate voltage of a transistor manufactured as above. The abscissa represents gate voltage and the ordinate represents drain current. A curve r shows the characteristic of a normal transistor. A curve h shows the characteristics of a transistor formed by the above-described processes. As seen from the curve h, the drain current starts flowing at a lower gate voltage. This analysis results in that a parasitic transistor turning on at a low threshold voltage is added.[0023]
• If the shoulder S of the[0024]isolation region9 is etched and divots or recesses are formed as shown in FIG. 9G, the shoulder of the active region of the silicon substrate is surrounded by the gate electrode not only from the upper surface of the active region but also from the side thereof. As voltage is applied to the gate electrode having such a shape, the shoulder of the active region undergoes an electric field concentration so that a transistor having a lower threshold voltage is formed. This parasitic transistor forms the hump characteristics indicated by the curve h shown in FIG. 9H.
• As seen from the curve h, the drain current at a higher gate voltage is lower than that of the curve r. As heat treatment is performed in order to make dense the silicon oxide buried in the trench, the[0025]silicon oxide layer9 contracts so that the active region surrounded by thesilicon oxide film9 receives a compression stress.
• As the compression stress is applied, the mobility of electron/hole in the active region of the[0026]silicon substrate1 may lower, which reduces the saturated drain current. As the element is made finer and the area of the active region is made small, the influence of the compression stress increases.
• In IEDM 1988, pp. 92-95, B. Davari et al. have proposed to implant ions into the shoulder of an active region in order to suppress the hump characteristics.[0027]
• Another method has been proposed to round the shoulder of an active region through thermal oxidation in order to suppress the hump characteristics. Since the shoulder is rounded and the electric field concentration is relaxed, the influence of a parasitic transistor can be mitigated.[0028]
• In IEDM 1992, pp. 57-60, Pierre C. Fazan et al. have proposed to form insulating side wall spacers on the side walls of an isolation silicon oxide film protruding from an upper surface of a silicon substrate to thereby bury divots.[0029]
• Although STI is suitable for the microfine structure of semiconductor devices, there occur problems specific to STI. New techniques capable of solving the problems specific to STI have been desired to date.[0030]
SUMMARY OF THE INVENTION
• It is an object of this invention to provide a semiconductor device with STI capable of presenting good transistor characteristics. It is another object of the invention to provide a method of manufacturing a semiconductor device having good transistor characteristics.[0031]
• According to one aspect of the present invention, there is provided a semiconductor device comprising: a silicon substrate with semiconductor elements; an isolation trench formed in the silicon substrate for separating active regions in the silicon substrate, the isolation trench having a trapezoidal cross sectional shape having a width gradually narrowing with a depth from a surface of the silicon substrate; a first liner insulating film formed on a surface of the trench and made of a silicon oxide film or a silicon oxynitride film having a thickness of 1 to 5 nm; a second liner insulating film formed on the first liner insulating film and made of a silicon nitride film having a thickness of 2 to 8 nm; and an isolation region burying the trench defined by the second liner insulating film.[0032]
• According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising steps of: (a) forming a polishing stopper layer on a surface of a silicon substrate, the stopper layer including a silicon oxide film and a silicon nitride film; (b) etching the stopper layer and the silicon substrate by using a mask to form a trench; (c) forming a first liner insulating film on a surface of the silicon substrate exposed in the trench, the first liner insulating film being a silicon oxide film or a silicon oxynitride film having a thickness of 1 to 5 nm; (d) forming a second liner insulating film on the first liner insulating film, the second liner insulating film being made of a silicon nitride film having a thickness of 2 to 8 nm; (e)-depositing an isolation layer on the silicon substrate, the isolation layer burying the trench defined by the second liner insulating film; (f) polishing and removing an unnecessary portion of the isolation layer by using the stopper layer as a polishing stopper; and (g) etching the stopper layer.[0033]
• As above, it is possible to provide a transistor device with STI and relaxed electric field concentration on the shoulders of an active region, and its manufacture method.[0034]
• Since a silicon nitride film is left at least on the side walls of a trench, a tensile stress is applied to the channel region of the active region so that a reduction in the mobility can be relaxed.[0035]
• The formation of a hump and the reverse narrow channel effects can be suppressed.[0036]
BRIEF DESCRIPTION OF THE DRAWINGS
• FIGS. 1A to[0037]1H are cross sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the invention.
• FIGS. 2A and 2B are a plan view and a cross sectional view showing a semiconductor device manufactured by the embodiment method illustrated in FIGS. 1A to[0038]1H.
• FIGS. 3A and 3B are graphs showing the characteristics of a semiconductor device manufactured by the embodiment method illustrated in FIGS. 1A to[0039]1H, as compared to the characteristics of a semiconductor device of prior art.
• FIGS. 4A and 4B are a graph showing the effects of a silicon nitride film left on the side walls of a trench and a graph showing the dependency of a saturated drain current upon a source/drain width.[0040]
• FIGS. 5A to[0041]5D are cross sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the invention.
• FIGS. 6A to[0042]6D are cross sectional views illustrating a method of manufacturing a semiconductor device according to a further embodiment of the invention.
• FIGS. 7A to[0043]7H are cross sectional views illustrating a method of manufacturing a semiconductor device according to still another embodiment of the invention.
• FIGS. 8A to[0044]8K are cross sectional views illustrating a method of manufacturing a semiconductor device according to still another embodiment of the invention.
• FIGS. 9A to[0045]9H are cross sectional views illustrating a method of manufacturing a semiconductor device according to prior art and a graph showing the characteristics of a transistor manufactured by this method.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
• Embodiments of the invention will be described with reference to the accompanying drawings.[0046]
• FIGS. 1A to[0047]1H are schematic cross sectional views illustrating main processes of a method of manufacturing a semiconductor device according to an embodiment of the invention.
• As shown in FIG. 1A, the surface of a[0048]silicon substrate1 is thermally oxidized to form asilicon oxide film2 having a thickness of 9 to 21 nm, e.g., 10 nm. On thesilicon oxide film2, asilicon nitride film3 having a thickness of 100 to 150 nm is formed by low pressure (LP) chemical vapor deposition (CVD). For example, LPCVD is performed at a temperature of 700° C. by using SiCl₂H₂and NH₃as source gas.
• A resist film is coated on the[0049]silicon nitride film3, exposed and developed to form a resistpattern4. The resistpattern4 has an opening or openings for defining an isolation region or regions and active regions (element regions) each surrounded by the isolation region. The width of an opening5ais, for example, 0.2 to 1 μm.
• By using the resist[0050]pattern4 as an etching mask, thesilicon nitride film3,silicon oxide film2 andsilicon substrate1 are etched. Thesilicon substrate1 is etched by a depth of 0.5 μm to form atrench6. For example, the silicon nitride film and silicon oxide film are etched by using mixture gas of CF₄+CHF₃+Ar as etchant, and thesilicon substrate1 is etched by using mixture gas of HBr+O₂or Cl₂+O₂as etchant.
• With these etching conditions, the side walls of the[0051]trench6 have slanted surfaces. With these slanted surfaces, electric field concentration upon the shoulder of the active region can be relaxed. The resistpattern4 is thereafter removed.
• As shown in FIG. 1B, the silicon substrate surface exposed in the[0052]trench6 is thermally oxidized to form asilicon oxide film7 having a thickness of 1 to 5 nm. The whole silicon surface exposed in thetrench6 is covered with thesilicon oxide film7.
• As shown in FIG. 1C, a[0053]silicon nitride film8 is formed by LPCVD, covering the surfaces of thesilicon oxide film7 andsilicon nitride film3. The thickness of thesilicon nitride film8 is 2 to 8 nm. This thickness of 2 to 8 nm of thesilicon nitride film8 makes it difficult for hot phosphoric acid to be used for etching silicon nitride to penetrate into thisthin film8.
• LPCVD is performed at a temperature of about 650° C. by using mixture gas of SiCl[0054]₂H₂+NH₃as source gas. The silicon nitride film formed by such thermal CVD has a tensile stress of 1 GPa or larger. The direction of this stress is opposite to that of the stress in a buried silicon layer after heat treatment for making it dense to be described later. The thickness of 1 to 5 nm of thesilicon oxide film7 makes it difficult for dilute hydrofluoric acid to be used for etching silicon oxide to penetrate into thisthin film7.
• As shown in FIG. 1D, a[0055]silicon oxide layer9 is deposited over the substrate with thesilicon nitride film8, for example, by high density plasma (HDP) CVD, thesilicon oxide layer9 burying the trench. If the trench has a depth of 0.5 μm, the thickness of thesilicon layer9 is set to about 0.6 to 1 μm in the flat area.
• The silicon oxide layer is formed by using mixture gas of SiH[0056]₄and oxygen or TEOS and ozone as source gas. After thesilicon oxide layer9 is grown, annealing at about 1000° C. is performed to make thesilicon oxide layer9 dense. The film quality of thesilicon oxide layer9 in the trench after the annealing is approximately similar to that of the thermally oxidized film. Although the dense silicon oxide layer has a compression stress, the directions of this compression stress and the tensile stress of the silicon nitride film are opposite so that both the stresses are cancelled out. The mobility can therefore be prevented from being lowered by the compression stress.
• As shown in FIG. 1E, an unnecessary region of the[0057]silicon oxide layer9 at a position higher than thesilicon nitride films3 and8 is removed by performing chemical mechanical polishing (CMP). CMP is performed by holding the silicon substrate between upper and lower rotating surface plates which are controlled to have, for example, a revolution speed of 20 rpm, a pressure of 5 psi therebetween and a back pressure of 5 psi. As polishing agent, slurry mainly containing colloidal silica or cerium oxide slurry is used.
• Under such polishing conditions, an etching rate of the[0058]silicon nitride film3 is small so that thesilicon nitride film3 functions as a polishing stopper. In the state after the polishing, thesilicon oxide layer9 is approximately flush with thesilicon nitride film3, and thesilicon oxide layer9 is left only in the opening defined by thesilicon nitride film3. In this example, although thesilicon oxide layer9 at a position higher than thesilicon nitride film3 is removed by CMP, it may be removed by RIE using mixture gas of CF₄+CHF₃.
• As shown in FIG. 1F, the[0059]silicon nitride film3 is etched by hot phosphoric acid. At this time, thesilicon nitride film8 on the side wall of thesilicon nitride film3 is also etched. As thesilicon nitride film3 is removed, the upper surface of thesilicon nitride film8 between thesilicon oxide film7 on thesilicon substrate1 and the buriedsilicon oxide layer9 is exposed.
• Since the thickness of the[0060]silicon nitride film8 is set as thin as 2 to 8 nm, hot phosphoric acid having a relatively high viscosity is hard to penetrate into this thin film so that thesilicon nitride film8 between thesilicon oxide film7 andsilicon oxide layer9 is hardly etched.
• As the[0061]silicon nitride film3 and thesilicon nitride film8 on the side wall of thesilicon nitride film3 are removed by hot phosphoric acid, the upper portion of thesilicon oxide layer9 protrudes from the surface of thesilicon substrate1 as shown in FIG. 1F.
• Thereafter, the[0062]silicon oxide film2 on the surface of thesilicon substrate1 is removed by dilute hydrofluoric acid. At this time, the protrudedsilicon oxide layer9 is also etched slightly.
• The upper surface of the[0063]silicon oxide film7 formed on the trench surface is also exposed. Since the thickness of thesilicon oxide film7 is set as thin as 1 to 5 nm, dilute hydrofluoric acid is hard to enter this thin film so that thesilicon oxide film7 is hardly etched.
• As shown in FIG. 1G, the surface of the[0064]silicon substrate1 is thermally oxidized to grow asacrificial oxide film22.
• By using the[0065]sacrificial oxide film22 as a through oxide film, ions are implanted into the surface layer of thesilicon substrate1. Implanted impurity ions are activated to formwells10 having a predetermined conductivity type. For example, n- and p-type wells are formed independently by ion implantation using resist masks. After the well10 is formed, the sacrificial oxide film is removed by dilute hydrofluoric acid.
• A plurality of hydrofluoric acid etching processes etch the projected portion of the[0066]silicon oxide layer9 and divots are formed along the side of the shoulder of the active region. However, thesilicon nitride film8 andsilicon oxide film7 are hardly etched and they cover the side of the active region.
• If buffered hydrofluoric acid mixed with NH[0067]₄H having a viscosity higher than dilute hydrofluoric acid is used, it is possible to suppress etching thesilicon oxide film7 more reliably.
• As shown in FIG. 1H, the sacrificial oxide film is removed and the exposed surface of the[0068]silicon substrate1 is thermally oxidized to form a gate insulatingoxide film11 having a thickness of, e.g., 2 nm. Prior to forming the gate insulatingoxide film11, dilute hydrofluoric acid etching is performed to such an extent that a thermally oxidized film would be etched by 20 nm. Apolysilicon layer12 is formed over the substrate surface and patterned to form a gate electrode. Thereafter, impurity ions of a conductivity type opposite to that of the well10 are implanted to form source/drain regions on both sides of the gate electrode. If necessary, side wall spacers are formed on the side walls of the gate electrode, and impurity ions are implanted and activated to form high impurity concentration source/drain regions.
• FIG. 2A is a plan view showing the layout of active regions AR defined by an[0069]isolation region9 and agate electrode12 formed on the surface of a silicon substrate. FIGS. 1A to1H are the cross sectional views taken along line B-B′ in FIG. 2A. Each active region AR is surrounded by theisolation region9. A MOS inverter is constituted of two active regions.
• The plan view of FIG. 2A shows the state before side wall spacers are formed. After the side wall spacers are formed, impurity ions having a conductivity type opposite to that of the wells are implanted to form high impurity concentration source/drain regions.[0070]
• FIG. 2B is a cross sectional view taken along a line A-A′ shown in FIG. 2A. As shown in FIG. 2B, the side wall spacers SW are formed on the side walls of the gate electrode, and the source/drain regions S/D are formed on both sides of the gate electrode. A[0071]silicide film13 is formed on the upper surfaces of thegate electrode12 and source/drain regions S/D. Asilicon oxide film7 and asilicon nitride film8 are made very thin so that etchant cannot enter these films and upper surfaces thereof are left scarcely etched.
• Since the upper surface of the[0072]silicon nitride film8 is positioned not lower than the surface of the silicon substrate, the tensile stress of thesilicon nitride film8 is applied effectively to the channel region.
• FIG. 3A shows the characteristics of a n-type MOS transistor formed by the processes described previously. The characteristics of the MOS transistor having a gate length of 0.1 μm and a gate width of 1 μm were measured. A curve p shows the characteristics of a transistor of conventional techniques, and a curve s shows the characteristics of a transistor of an embodiment. It was confirmed that a saturated drain current increased and the mobility to be otherwise lowered by a compression stress was maintained by the tensile stress of the nitride film. The saturated drain current was improved by 5%. The existence of a parasitic MOS transistor was not confirmed and the absence of a hump was confirmed. The reverse narrow channel effect was also studied.[0073]
• FIG. 3B is a graph showing the measurement results. A curve p shows the characteristics of a transistor of conventional techniques, and a curve s shows the characteristics of a transistor of an embodiment. According to the conventional techniques, as the gate width is made narrow, the threshold voltage gradually lowers, which indicates the existence of the reverse short channel effect. In contrast, it can be seen from the curve s of the embodiment that even if the gate width is made narrow, the threshold voltage scarcely lowers and that the reverse narrow channel effect can be suppressed. This may be ascribed to that there is less contribution of a parasitic MOS transistor.[0074]
• A tensile stress in a channel region relative to an indent-or depression amount of an upper surface of a liner silicon nitride film formed on the inner surface of a trench was simulated by changing the indent position of the upper surface of the silicon nitride film from the surface of the semiconductor substrate.[0075]
• FIG. 4A is a graph showing how the tensile stress in the channel region of an active region changes with the depression amount of a side wall silicon nitride film from a silicon substrate surface. The depression amount is 0 when the surface of the silicon nitride film is flush with the surface of the semiconductor substrate, and it increases as the silicon nitride film is depressed from the semiconductor substrate surface. The tensile stress in the channel region reduces as the depression amount of the silicon nitride film increases. If the silicon nitride film is depressed by about 30 nm or more, it can be considered that the effects of the silicon nitride film disappear nearly.[0076]
• In other words, the tensile stress can be effectively applied to the channel region in the active region by limiting the depression amount of the silicon nitride film from the surface of the semiconductor substrate. The tensile stress can be applied effectively to the channel region by setting the depression amount to about 10 nm or smaller.[0077]
• A change in the saturated drain current relative to the width (SD width) of a source/drain region along the source/drain direction was also measured.[0078]
• FIG. 4B is a graph showing a change in the saturated drain current relative to the SD width. According to conventional techniques, as the SD width becomes narrow, the saturated drain current Ids lowers. According to the embodiment, even if the SD width becomes narrow, the saturated drain current Ids is maintained almost constant.[0079]
• In this embodiment, the liner silicon nitride film is formed from the bottom surface to side wall of the trench. The liner[0080]silicon nitride film5 may be formed extending to the upper surface of the active region.
• FIGS. 5A to[0081]5D are cross sectional views illustrating main processes of a method of manufacturing a semiconductor device according to another embodiment of the invention.
• After processes similar to those described with reference to FIG. 1A are performed, a[0082]silicon nitride film3, asilicon oxide film2 and asemiconductor substrate1 are etched by using a resist pattern as an etching mask to form atrench6 in the semiconductor substrate.
• As shown in FIG. 5A, the[0083]silicon oxide film2 is side-etched by dilute hydrofluoric acid solution to retract thesilicon oxide film2 by about 10 nm from the side walls of thesilicon nitride film3. The resist pattern is removed either before or after this side etching.
• As shown in FIG. 5B, similar to the above-described embodiment, the substrate surface exposed in the trench and in the retracted space of the[0084]silicon oxide film2 is thermally oxidized to form asilicon oxide film7 having a thickness of 1 to 5 nm. Thereafter, similar to the process in FIG. 1C, asilicon nitride film8 having a thickness of 2 to 8 nm is formed over the whole surface of the substrate by CVD.
• The thickness of the[0085]silicon oxide film2 is set to such a value that the retracted space of thesilicon oxide film2 is not completely filled with thesilicon nitride film8. For example, assuming that the thickness of thesilicon oxide film2 is 15 nm, a twofold of a total thickness of thesilicon oxide film7 andsilicon nitride film8 is set thinner than 15 nm.
• As shown in FIG. 5B, a[0086]silicon oxide layer9 is deposited, for example, by HDP-CVD, the trench being buried with thesilicon oxide layer9. Thereafter, similar to the process in FIG. 1F, an unnecessary portion of thesilicon oxide layer9 at the position higher than thesilicon nitride films3 and8 is removed by CMP. Annealing is performed in order to make thesilicon oxide layer9 dense.
• As shown in FIG. 5C, the[0087]silicon nitride film3 and thesilicon nitride film8 in contact with theformer film8 are etched by hot phosphoric acid. In this case, a portion of thesilicon nitride film8 between thesilicon oxide film2 andsilicon oxide layer9 is hardly etched because the thickness of thesilicon nitride film8 is as thin as 2 to 8 nm. As a result, a lamination of thesilicon oxide film7 andsilicon nitride film8 is left on the shoulder of the active region of thesilicon substrate1. Thereafter, similar to the previously described embodiment, thesilicon oxide film2 is removed and a sacrificial oxide film is grown to thereafter perform ion implantation and activation.
• As shown in FIG. 5D, after the sacrificial film is removed and a[0088]gate oxide film11 is formed, apolysilicon layer12 is deposited and patterned to form a gate electrode.
• In this embodiment, the lamination layer of the[0089]silicon oxide film7 andsilicon nitride film8 is left on the shoulder of the active region. Therefore, the tensile stress applied to the channel region becomes large as shown in FIG. 4A. Thepolysilicon gate electrode12 formed on the lamination layer faces the shoulder of the active region via the insulating lamination layer thicker than the gate insulating film. Therefore, the electric field concentration can be relaxed.
• A method of leaving the lamination layer of the silicon oxide film and silicon nitride film on the shoulder of the active region is not limited to the above embodiment.[0090]
• FIGS. 6A to[0091]6D are cross sectional views illustrating main processes of a method of manufacturing a semiconductor device according to a further embodiment of the invention.
• As shown in FIG. 6A, after a trench is etched, the trench surface in the[0092]semiconductor substrate1 is thermally oxidized to form asilicon oxide film7 having a thickness of 1 to 5 nm. Next, thesilicon nitride film3 is etched, for example, by about 10 nm by hot phosphoric acid. Since thesilicon oxide films2 and7 are not etched, only thesilicon nitride film3 is etched so that thesilicon nitride film3 is retracted, for example, by about 10 nm from the side walls of thesilicon oxide layer7. After the side walls of thesilicon nitride film3 are retracted, asilicon nitride film8 having a thickness of 2 to 8 nm is formed.
• As shown in FIG. 6B, a[0093]silicon oxide layer9 is deposited on the surface of the semiconductor substrate, for example, by HDP-CVD, the trench being buried with thesilicon oxide layer9. The shoulder of the active region of thesubstrate1 is covered with portions of thesilicon oxide films2 and7 andsilicon nitride film8 on which thesilicon oxide layer9 is deposited.
• CMP is then performed to remove an unnecessary portion of the[0094]silicon oxide layer9 at the position higher than the surface of thesilicon nitride film3.
• As shown in FIG. 6C, the[0095]silicon nitride film3 and thesilicon nitride film8 in contact with theformer film3 are etched by hot phosphoric acid. In this case, a portion of thesilicon nitride film8 between thesilicon oxide films2 and7 andsilicon oxide layer9 is hardly etched because the hot phosphoric acid does not penetrate into the portion of the silicon nitride film.
• Thereafter, similar to the previously described embodiment, the[0096]silicon oxide film2 is removed and a sacrificial oxide film is grown to thereafter perform ion implantation and activation and then remove the sacrificial oxide film.
• As shown in FIG. 6D, a[0097]gate oxide film11 is formed on the exposed surface of the active region. Although thesilicon oxide layer9 has divots etched along the side of the shoulder of the active region, the shoulder is maintained covered with thesilicon oxide films2 and7 andsilicon nitride film8. A polysilicon layer is deposited and patterned to form a gate electrode. Similar to the embodiment shown in FIGS. 5A to5D, since the shoulder of the active region is covered with the lamination layer of the silicon oxide films and silicon nitride film, a large tensile stress is applied to the channel region so that an electric field concentration is relaxed when a voltage is applied to the gate electrode.
• In the embodiments described above, the surface of a trench is covered with a liner insulating film made of a lamination layer of a silicon oxide film and a silicon nitride film. The liner insulating film may be made of a single film.[0098]
• FIGS. 7A to[0099]7H are cross sectional views illustrating main processes of a method of manufacturing a semiconductor device according to still another embodiment of the invention.
• As shown in FIG. 7A, after a trench is etched, a[0100]silicon oxide film2 is side-etched to retract the side walls of thesilicon oxide film2 by about 10 nm from the side walls of asilicon nitride film3. This process is similar to the process in FIG. 5A. The condition of limiting the thickness of thesilicon oxide film2 is, however, different.
• As shown in FIG. 7B, the shoulder of the active region and the bottom corners of the trench are rounded, for example, by chemical dry etching. This dry etching removes the surface layer of the trench, and the layer damaged by trench etching, if any, is removed. The shoulder of the active region is rounded to a circular cross sectional shape having a radius of curvature approximately equal to the retraction amount of the[0101]silicon oxide film2. The silicon surface after dry etching is a clean surface with fewer defects.
• As shown in FIG. 7C, a[0102]silicon nitride film8 having a thickness of 2 to 8 nm is formed on the surface of the semiconductor substrate by CVD. If the thickness of thesilicon oxide film2 is set greater than a twofold of the thickness of thesilicon nitride film8, it is possible to prevent the retracted space from being buried with thesilicon nitride film8. For example, assuming that the thickness of thesilicon oxide film2 is 15 nm, the thickness of thesilicon nitride film8 is set to 5 nm.
• As shown in FIG. 7D, after the[0103]silicon nitride film8 is formed, asilicon oxide layer9 is deposited to bury the trench.
• As shown in FIG. 7E, the[0104]silicon oxide layer9 is polished by CMP using thesilicon nitride film9 as a polishing stopper. After the surface of thesilicon oxide film9 is planarized, annealing is performed, for example, for 30 minutes at 1000° C. in an N₂atmosphere in order to make the buried silicon oxide film dense.
• As shown in FIG. 7F, the[0105]silicon nitride film3 is etched by hot phosphoric acid. Portions of thesilicon nitride film8 between thesilicon substrate1 andsilicon oxide layer9 and between thesilicon oxide film2 andsilicon oxide layer9 are left unetched because the hot phosphoric acid cannot penetrate into the portions of thesilicon nitride film8.
• As shown in FIG. 7G, the[0106]silicon oxide film2 is removed, a sacrificial film is grown, and ion implantation and activation is performed. After the sacrificial film is removed, agate oxide film11 is formed by thermal oxidation. Although the upper portion of thesilicon oxide layer9 is etched by the dilute hydrofluoric acid process of removing the silicon oxide film, thesilicon nitride film8 covering the shoulder of the active region is left unetched.
• As shown in FIG. 7H, a[0107]polysilicon layer12 is deposited covering thegate oxide film11, and patterned to form a gate electrode. Since the shoulder of the active region is rounded, the degree of an electric field concentration can be mitigated when a voltage is applied to the gate electrode.
• In the embodiments described above, a silicon oxide film and a silicon nitride film are formed on the surface of a silicon substrate, and the silicon nitride film is used as the CMP stopper. A lamination layer having a different structure may be formed on a semiconductor substrate.[0108]
• FIGS. 8A to[0109]8K are cross sectional views illustrating main processes of a method of manufacturing a semiconductor device according to still another embodiment of the invention.
• As shown in FIG. 8A, a[0110]silicon oxide film2 similar to those of the above-described embodiments is formed on the surface of asemiconductor substrate1. On thissilicon oxide film2, an amorphous silicon film2ais formed. On this amorphous silicon film2a, asilicon nitride film3 similar to those of the above-described embodiments is formed. A photoresist layer is coated on the surface of thesilicon nitride film3, and exposed and developed to form a resistpattern4.
• As shown in FIG. 8B, by using the resist[0111]pattern4 as an etching mask, thesilicon nitride film3, amorphous silicon film2aandsilicon oxide film2 are etched and then the silicon substrate is etched to form atrench6.
• As shown in FIG. 8C, the amorphous silicon film[0112]2ais selectively etched. For example, isotropic etching in a liquid phase is performed by using HF+HNO₃+H₂O or HF+NH₄OH+H₂O₂+H₂O to retract the side walls of the amorphous silicon film2a. During this etching, thesilicon substrate1 is scarcely etched because of a difference of an etching selection ratio between the amorphous silicon film and crystal silicon.
• As shown in FIG. 8D, the exposed silicon surface is oxidized. A silicon oxide film[0113]7ais formed on theamorphous silicon film7 and asilicon oxide film7 is formed on the silicon substrate. Instead of oxidizing the silicon surface, it may by oxynitridized. The thickness of the silicon oxide film or silicon oxynitride film is set to such a value that etchant for etching silicon oxide in a later process is hard to penetrate into the film. The silicon oxynitride film has a smaller etching rate than the silicon oxide film so that the detraction amount by etching can be reduced.
• As shown in FIG. 8E, a[0114]silicon nitride film8 is formed on the whole surface of the substrate to a thickness of, e.g., 5 nm by CVD. The thickness of thesilicon nitride film8 is set to such as value that hot phosphoric acid etchant does not penetrate into thesilicon nitride film8.
• As shown in FIG. 8F, a[0115]silicon oxide layer9 is deposited burying the trench. As shown, the shoulder of the active region is covered with a lamination layer of thesilicon oxide film7 andsilicon nitride film8, and thesilicon oxide layer9 covers the lamination layer.
• As shown in FIG. 8G, CMP is performed to remove an unnecessary portion of the[0116]silicon oxide layer9 at the position higher than thesilicon nitride film3. The state shown in FIG. 8G shows thesilicon nitride film3 partially removed. CMP is performed to the extent that thesilicon nitride film3 appears and is not removed completely.
• As shown in FIG. 8H, the silicon nitride film is removed by hot phosphoric acid. With this etching, the exposed[0117]silicon nitride film3 and thesilicon nitride film8 in contact with the former film are etched. However, since the thickness of thesilicon nitride film8 is selected to such an extent that the hot phosphoric acid does not penetrate into thesilicon nitride film8, the retraction amount of thesilicon nitride film8 from the upper surface thereof is limited.
• As shown in FIG. 8I, the amorphous silicon film[0118]2ais removed by NH₃+H₂O+isopropyl alcohol (IPA).
• As shown in FIG. 8J, the[0119]silicon oxide films2 and7aare removed. This etching slightly etches the surface of thesilicon oxide layer9. Thenitride film8, when projected, may be removed since it is very thin. Thereafter, a sacrificial film is formed and ion implantation and activation is performed to formwells10. After the sacrificial film is removed, a gate oxide film is formed on the exposed surface of the active region.
• As shown in FIG. 8K, a polysilicon film is formed covering the[0120]gate insulating film11, and patterned to form agate electrode12. The shoulder of the active region is maintained covered with thesilicon oxide film7 andsilicon nitride film8. Depending upon the process conditions, a portion of thesilicon oxide layer9 is left on thesilicon nitride film8. Since thegate electrode12 is formed on this structure, an electric field concentration upon the shoulder of the active region can be relaxed when a voltage is applied to the gate electrode. A large tensile stress is applied to the channel region.
• The present invention has been described in connection with the preferred embodiments. The invention is not limited only to the above embodiments. It is apparent that various modifications, improvements, combinations, and the like can be made by those skilled in the art.[0121]

Claims (21)

What we claim are:

1. A semiconductor device comprising:

a silicon substrate with semiconductor elements;

an isolation trench formed in said silicon substrate for isolating active regions in said silicon substrate, said isolation trench having a trapezoidal cross sectional shape having a width gradually narrowing with a depth from a surface of said silicon substrate;

a first liner insulating film formed on a surface of said trench and made of a silicon oxide film or a silicon oxynitride film having a thickness of 1 to 5 nm;

a second liner insulating film formed on said first liner insulating film and made of a silicon nitride film having a thickness of 2 to 8 nm; and

an isolation region burying said trench defined by said second liner insulating film.

2. A semiconductor device according toclaim 1, wherein an upper end of said second liner insulating film is retracted by less than about 10 nm from the surface of said silicon substrate.

3. A semiconductor device according toclaim 1, wherein said first and second liner insulating films extend from side walls of said trench to an upper surface of the silicon substrate.

4. A semiconductor device according toclaim 3, wherein said isolation region includes a portion extending on said second liner insulating layer above the upper surface of said silicon substrate.

5. A semiconductor device according toclaim 4, wherein said second liner insulating film includes a portion extending on side walls of said extending portion of said isolation region.

6. A semiconductor device according toclaim 1, wherein said second liner insulating film has a tensile stress of 1 GPa or larger.

7. A semiconductor device comprising:

a silicon substrate with semiconductor elements;

an isolation trench formed in said silicon substrate for isolating active regions in said silicon substrate, said isolation trench having generally a trapezoidal cross sectional shape having a width gradually narrowing with a depth from a surface of said silicon substrate and having a gradually broadening upper portion, said isolation trench defining the active regions with rounded shoulders;

a liner insulating film formed on a surface of said trench and made of a silicon nitride film having a thickness of 2 to 8 nm; and

an isolation region burying said trench defined by said liner insulating film.

8. A semiconductor device according toclaim 7, wherein a cross sectional shape of the shoulder of the active region is approximately a segment of a circle.

9. A semiconductor device according toclaim 7, wherein said liner insulating film applies a tensile stress of 1 GPa or larger to the active region.

10. A semiconductor device accordingclaim 7, further comprising an underlying liner layer of silicon oxide between the surface of said trench and said line insulating film.

11. A method of manufacturing a semiconductor device, comprising steps of:

(a) forming a polishing stopper layer on a surface of a silicon substrate, said stopper layer including a lower silicon oxide film and an upper silicon nitride film;

(b) etching said stopper layer and the silicon substrate by using a mask to form a trench;

(c) forming a first liner insulating film on a surface of the silicon substrate exposed in said trench, said first liner insulating film being a silicon oxide film or a silicon oxynitride film having a thickness of 1 to 5 nm;

(d) forming a second liner insulating film on said first liner insulating film, said second liner insulating film being made of a silicon nitride film having a thickness of 2 to 8 nm;

(e) depositing an isolation layer on said silicon substrate, said isolation layer burying said trench defined by said second liner insulating film;

(f) polishing and removing an unnecessary portion of said isolation layer by using said stopper layer as a polishing stopper; and

(g) etching said stopper layer.

12. A method according toclaim 11, further comprising between said steps (b) and (c) a step of:

(h) side-etching the silicon oxide film of said stopper layer to form retracted portions of the silicon oxide film.

13. A method according toclaim 12, wherein thicknesses of the silicon oxide film of said stopper layer and said first and second liner insulating films are set to such values that said retracted portions are not buried by the first and second liner insulating films.

14. A method according toclaim 11, further comprising between said steps (b) and (c) a step of:

(i) etching the silicon nitride film of said stopper layer to form retracted portions of the silicon nitride film and partially expose partial upper surfaces of the underlying silicon oxide film.

15. A method according toclaim 11, wherein said stopper layer includes, from lower position, a silicon oxide film, an amorphous silicon film and a silicon nitride film and the method further comprises between said steps (b) and (c) a step of:

(j) side-etching the amorphous silicon film to form retracted portions of the amorphous silicon film.

16. A method according toclaim 11, wherein said step (d) forms a silicon nitride film having a tensile stress of 1 GPa or larger.

17. A method according toclaim 11, wherein said step (g) includes a step of etching the silicon nitride film of said stopper layer by hot phosphoric acid.

18. A method according toclaim 11, wherein said step (g) includes a step of etching the silicon oxide film of said stopper layer by dilute hydrofluoric acid or buffered hydrofluoric acid.

19. A method of manufacturing a semiconductor device, comprising steps of:

(a) forming a polishing stopper layer on a surface of a silicon substrate, said stopper layer including a lower silicon oxide film and an upper silicon nitride film;

(b) etching said stopper layer and the silicon substrate by using a mask to form a trench in an isolation region defining active regions;

(c) side-etching the silicon oxide film of said stopper layer to retract side walls of the silicon oxide film;

(d) etching silicon to round a shoulder of the active region exposed by the retracted side wall;

(e) forming a liner insulating film on the surface of the silicon substrate, said liner insulating film being made of a silicon nitride film having a thickness of 2 to 8 nm;

(f) depositing an isolation layer on said silicon substrate, said isolation layer burying said trench defined by said liner insulating film;

(g) polishing and removing an unnecessary portion of said isolation layer by using said stopper layer as a polishing stopper; and

(h) etching said stopper layer.

20. A method according toclaim 19, wherein said step (e) forms a silicon nitride film having a tensile stress of 1 GPa or larger.

21. A method according toclaim 19, wherein said step (h) includes a step of etching the silicon nitride film by hot phosphoric acid.

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