US20030143782A1 - Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures - Google Patents
Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structuresDownload PDFInfo
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- US20030143782A1 US20030143782A1US10/061,825US6182502AUS2003143782A1US 20030143782 A1US20030143782 A1US 20030143782A1US 6182502 AUS6182502 AUS 6182502AUS 2003143782 A1US2003143782 A1US 2003143782A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/041—Modification of switching materials after formation, e.g. doping
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
- H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8825—Selenides, e.g. GeSe
Definitions
- This inventionrelates to methods of forming non-volatile resistance variable devices, and to methods of forming silver selenide comprising structures.
- One type of integrated circuitrycomprises memory circuitry where information is stored in the form of binary data.
- the circuitrycan be fabricated such that the data is volatile or non-volatile. Volatile storing memory devices result in loss of data when power is interrupted. Non-volatile memory circuitry retains the stored data even when power is interrupted.
- a voltage potentialis applied to a certain one of the electrodes, with the other of the electrode being held at zero voltage or ground.
- the electrode having the voltage applied theretofunctions as an anode, while the electrode held at zero or ground functions as a cathode.
- the nature of the resistance variable materialis such that it undergoes a change at a certain applied voltage. With such voltage applied, a low resistance state is induced into the material such that electrical conduction can occur between the top and bottom electrodes.
- the preferred resistance variable material received between the electrodestypically and preferably comprises a chalcogenide material having metal ions diffused therein.
- a chalcogenide material having metal ions diffused thereintypically and preferably comprises a chalcogenide material having metal ions diffused therein.
- One specific exampleincludes one or more layers of germanium selenide having silver ions diffused therein and one or more layers of silver selenide having excess silver ions diffused therein. It is, however, difficult to form silver rich silver selenide.
- a method of forming a non-volatile resistance variable deviceincludes forming a patterned mass comprising elemental silver over a substrate.
- a layer comprising elemental seleniumis formed over the substrate and including the patterned mass comprising elemental silver.
- the substrateis exposed to conditions effective to react only some of the elemental selenium with the elemental silver to form the patterned mass to comprise silver selenide. Unreacted elemental selenium is removed from the substrate.
- a first conductive electrodeis provided in electrical connection with one portion of the patterned mass comprising silver selenide.
- a germanium selenide comprising materialis provided in electrical connection with another portion of the patterned mass comprising silver selenide.
- a second conductive electrodeis provided in electrical connection with the germanium selenide comprising material.
- a method of forming a silver selenide comprising structureincludes forming a substrate comprising a first outer portion and a second outer portion.
- the first outer portioncomprises a patterned mass comprising elemental silver.
- the second outer portiondoes not comprise elemental silver.
- a layer comprising elemental seleniumis formed over the first and second outer portions.
- the substrateis exposed to oxidizing conditions effective to both, a) react elemental selenium received over the first portion with elemental silver to form the patterned mass to comprise silver selenide, and b) remove elemental selenium of the layer over the second outer portion from the substrate.
- FIG. 1is a diagrammatic perspective view of a semiconductor wafer fragment/section in process in accordance with an aspect of the invention.
- FIG. 2is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 1.
- FIG. 3is a view of the FIG. 2 wafer fragment at a processing step subsequent to that shown by FIG. 2.
- FIG. 4is a view of the FIG. 3 wafer fragment at a processing step subsequent to that shown by FIG. 3.
- FIG. 5is an alternate view of the FIG. 3 wafer fragment at an alternate processing step subsequent to that shown by FIG. 3.
- FIG. 6is a view of the FIG. 4 wafer fragment at a processing step subsequent to that shown by FIG. 4.
- FIG. 7is a view of the FIG. 6 wafer fragment at a processing step subsequent to that shown by FIG. 6.
- FIG. 8is an alternate view of the FIG. 3 wafer fragment at an alternate processing step subsequent to that shown by FIG. 3.
- FIG. 9is a diagrammatic perspective view of an alternate embodiment semiconductor wafer fragment/section in process in accordance with an aspect of the invention.
- FIG. 10is a view of the FIG. 9 wafer fragment at a processing step subsequent to that shown by FIG. 9.
- FIG. 11is a view of the FIG. 10 wafer fragment at a processing step subsequent to that shown by FIG. 10.
- FIG. 12is a diagrammatic perspective view of another alternate embodiment semiconductor wafer fragment/section in process in accordance with an aspect of the invention.
- FIG. 13is a view of the FIG. 12 wafer fragment at a processing step subsequent to that shown by FIG. 12.
- FIG. 14is a view of the FIG. 13 wafer fragment at a processing step subsequent to that shown by FIG. 13.
- FIG. 15is a view of the FIG. 14 wafer fragment at a processing step subsequent to that shown by FIG. 14.
- FIG. 1depicts a substrate fragment 10 comprising a base substrate 12 and a first conductive electrode material 14 formed thereover.
- Base substrate 12might comprise any suitable supporting substrate, for example a semiconductor substrate which includes bulk monocrystalline silicon.
- semiconductor substrateor “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials).
- substraterefers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Also in the context of this document, the term “layer” encompasses both the singular and the plural unless otherwise indicated. Exemplary preferred material for layer 14 is elemental tungsten.
- An insulative material 16is formed over first conductive electrode material 14 .
- Suchhas been patterned by any suitable patterning method (i.e., lithography, such as photolithography) to form an opening 18 therethrough to first conductive electrode material 14 .
- Opening 18comprises some desired shape of at least a portion of a final resistance setable structure of the device being fabricated, as will be apparent from the continuing discussion.
- opening 18has been filled with an elemental silver comprising material 20 in electrical connection with first conductive electrode material 14 .
- An exemplary preferred material for material 20includes at least 50 molar percent elemental silver, even more preferably at least 95 molar percent elemental silver, and even more preferably greater than 99 molar percent elemental silver.
- insulative material 16has a substantially planar outermost surface proximate opening 18
- patterned mass/elemental silver comprising material 20 within opening 18has an outermost surface which is co-planar with the insulative material outer surface.
- patterned mass 20can be considered as having some maximum first thickness, with an example thickness range being from about 50 Angstroms to about 2000 Angstroms.
- One example method of producing the construction illustrated by FIG. 2would be to deposit a layer of silver comprising material blanketly over the substrate, and then planarizing such layer back at least to the top of outer insulative layer 16 .
- depositionmight occur by chemical or physical means.
- polishing or planarizingcould occur by resist etch back, chemical polishing, mechanical polishing or any combination thereof, or by any other existing or yet-to-be-developed method.
- FIG. 2depicts but one example of forming a patterned mass comprising elemental silver over a substrate.
- a layer 22 comprising elemental seleniumis formed over substrate 10 and including patterned mass 20 comprising elemental silver.
- layer 22comprises elemental selenium of at least 90 molar percent, more preferably at least 95 molar percent elemental selenium, and even more preferably greater than 99 molar percent elemental selenium.
- substrate 10has been exposed to conditions effective to react elemental selenium 22 received over the elemental silver of mass 20 to form at least a portion of the filled opening/patterned mass to comprise silver selenide 25 .
- such exposing to the conditionsare effective to react only some of elemental selenium comprising layer 22 , with those portions formed over insulative material 16 being essentially unreacted.
- the exposingis illustrated as forming the patterned mass to entirely comprise silver selenide material 25 .
- the exposingpreferably forms that portion of the patterned mass which is transformed to comprise at least 50 molar percent silver selenide, and more preferably at least 80 molar percent silver selenide. Further preferably, that portion which is formed is ideally substantially homogenous.
- FIG. 5depicts an alternate embodiment 10 a. Like numerals from the first embodiment are utilized where appropriate, with differences being indicated by the suffix “a”.
- FIG. 5depicts forming an outermost portion 25 a of the patterned mass to comprise silver selenide, while an innermost portion 20 a of the patterned mass remains as the deposited silver comprising material initially formed.
- the remaining thickness of innermost portion 20 ais preferably from 0 to 10 percent of the total thickness of the illustrated patterned mass.
- FIGS. 4 and 5depicts but one embodiment wherein the exposing forms more than one-half of the filled opening to comprise silver selenide. Alternately, by way of example only, one-half or less than one-half might be filled. Further in the preferred embodiment as shown, the exposing forms the patterned mass to have a maximum second thickness which is greater than the maximum first thickness.
- One example preferred process for the subject exposingincludes annealing the substrate at a temperature of from about 40° C. to about 100° C. at a pressure of from about 30 mTorr to 760 Torr for from about one to three hours. Higher temperatures typically result in a higher annealing rate. Conditions and time can be controlled to achieve a desired amount of the mass to be transformed to silver selenide comprising material. Further, by way of example only, annealing in a suitable oxidizing atmosphere is also a possibility, as is more fully described below.
- unreacted elemental selenium 22has been removed from the substrate.
- the preferred removingremoves all remaining unreacted elemental selenium from the substrate.
- One example of removingcomprises chemical etching, and preferably in a manner which is selective to remove elemental selenium comprising material 16 selectively relative to silver selenide comprising material 25 .
- An example wet etch for doing sowould include utilizing hydrogen peroxide, for example at from room temperature to 50° C. and ambient pressure.
- An example dry processwould include plasma etching using CF 4 .
- an alternate process for removing unreacted elemental seleniumcomprises increasing the temperature of the substrate to closer to the melting temperature of selenium, say from 200° C. to 250° C., and at atmospheric pressure for from 10 minutes to one hour, effective to cause evaporation of the unreacted selenium from the substrate.
- a germanium selenide material layer 26(i.e., preferably 40 molar percent germanium and 60 molar percent selenium) is formed over and in electrical connection with silver selenide comprising material 25 .
- a second conductive electrode material 28is formed thereover, and thereby in electrical connection with silver selenide 25 through material 26 .
- Second conductive electrode material 28might be the same as first conductive electrode material 14 , or be different.
- An exemplary preferred material for electrode 28 in the depicted and described embodimentis elemental silver.
- suchprovides exemplary processing of providing a first conductive electrode in electrical connection with one portion of patterned mass 25 comprising silver selenide, providing a germanium selenide comprising material in electrical connection with another portion of the patterned mass comprising silver selenide, and providing a second conductive electrode in electrical connection with the germanium selenide comprising material.
- FIG. 8depicts an alternate embodiment 10 c which depicts an alternate processing of the FIG. 3 wafer which produces a slightly modified construction to that depicted by FIG. 4.
- the exposing and the removinghave occurred in a common processing step comprising at least 100° C. and an atmosphere which removes unreacted elemental selenium by oxidation thereof.
- the oxidizing atmosphereutilizes a weak oxidizer or a dilute oxidizer, for example at less than or equal to five percent by volume oxidizer, with less than or equal to one percent being more preferred.
- An example preferred oxidizing atmospherecomprises at least one of N 2 O, NO x , O 3 , F 2 and Cl 2 .
- preferred conditionsinclude an elevated temperature of from 40° C. to 250°C., a pressure at from 30 mTorr to 760 Torr and from 30 minutes to two hours.
- the oxidizing conditions and atmosphereare preferably selected to be sufficiently dilute or weak, as identified above, to prevent the complete oxidation of selenium comprising material 22 over patterned mass 20 prior to driving (either physically or by reacting) elemental selenium into patterned mass 20 such that an effective silver selenide mass 25 c is formed.
- oxidizingwill typically result in some removal of elemental selenium by oxidation at the outermost portion of elemental selenium comprising layer 22 over the patterned mass during the oxidizing.
- the exposingdrives at least a majority of that portion of the elemental selenium received over the patterned mass into the patterned mass.
- the inventionfurther contemplates a method of forming any silver selenide comprising structure regardless of whether such is utilized in the fabrication of a non-volatile resistance variable device.
- Such methodcontemplates forming a substrate comprising a first outer portion and a second outer portion, with the first outer portion constituting a patterned mass comprising elemental silver and the second portion not comprising elemental silver.
- an outermost portion of patterned mass 20 comprising elemental silvercomprises an exemplary first outer portion, with the outermost portion of insulative 16 constituting an exemplary second outer portion.
- a layer comprising elemental seleniumis formed over the first and second outer portions.
- the substrateis exposed to oxidizing conditions, by way of example only such as those described above, effective to both a) react elemental selenium received over the first portion with elemental silver to form the patterned mass to comprise silver selenide, and b) remove elemental selenium of a layer over the second outer portion from the substrate.
- the exposingremoves all unreacted elemental selenium from the substrate.
- such exposingwill tend to remove some of the elemental selenium of the layer over the first portion from the substrate, but still preferably drive at least a majority of that portion of the elemental selenium received over the first portion into the patterned mass, and more preferably at least 80 molar percent.
- such exposingpreferably forms the patterned mass to have a maximum second thickness which is greater than its maximum first thickness immediately prior to the exposing.
- FIGS. 9 - 11illustrate an alternate embodiment 10 d. Like numerals from the first described embodiment are utilized where appropriate, with differences being indicated by the suffix “d” or with different numerals.
- FIG. 9depicts an alternate elemental silver comprising material 20 d received within opening 18 . Such comprises a lower exemplary germanium selenide portion 21 (i.e., preferably 40 percent germanium and 60 percent selenium), and an overlying preferred 99 percent-plus pure elemental silver region 23 . By way of example only, such could be formed by suitable deposition and planarization relative to insulative layer 16 . A selenium comprising layer 22 d is formed thereover.
- substrate 10 dhas been subjected to the preferred exposing and removing processing (either together or in different steps) effective to form a silver selenide mass 25 d and to remove at least some, and preferably all, unreacted elemental selenium from the substrate.
- Another germanium selenide layer 26 d and a second electrode 28 dare formed thereover.
- FIGS. 12 - 15The above-described embodiments describe and depict exemplary methods of forming a patterned mass comprising elemental silver. Such embodiments depict forming a patterned opening within insulative material over a substrate, and at least partially filling the opening with an elemental silver comprising material. However, the invention contemplates any method of forming a patterned mass comprising elemental silver. By way of example only, one such alternate process is described with reference to FIGS. 12 - 15 .
- FIG. 12depicts another alternate embodiment 10 e, with like numerals from the first embodiment being utilized and differences being indicated with the suffix “e” or with different numerals.
- FIG. 12depicts the depositing of a silver comprising material 20 e.
- Material 20 ehas been patterned, for example by photopatterning and then subtractively etching after the patterning.
- Other patterningsuch as laser patterning or any other method of patterning, is contemplated, whether existing or yet-to-be-developed.
- an elemental selenium comprising layer 22 eis formed over patterned mass 20 e.
- the substratehas been exposed to conditions effective to react only some of elemental selenium 22 e with the elemental silver to form a patterned mass 25 e to comprise silver selenide.
- a preferred germanium selenide layer 26 e and a preferred second electrode 28 eare formed thereover.
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Abstract
Description
- This invention relates to methods of forming non-volatile resistance variable devices, and to methods of forming silver selenide comprising structures.[0001]
- Semiconductor fabrication continues to strive to make individual electronic components smaller and smaller, resulting in ever denser integrated circuitry. One type of integrated circuitry comprises memory circuitry where information is stored in the form of binary data. The circuitry can be fabricated such that the data is volatile or non-volatile. Volatile storing memory devices result in loss of data when power is interrupted. Non-volatile memory circuitry retains the stored data even when power is interrupted.[0002]
- This invention was principally motivated in making improvements to the design and operation of memory circuitry disclosed in U.S. Pat. Nos. 5,761,115; 5,896,312; 5,914,893; and 6,084,796 to Kozicki et al., which ultimately resulted from U.S. patent application Ser. No. 08/652,706, filed on May 30, 1996, disclosing what is referred to as a programmable metallization cell. Such a cell includes opposing electrodes having an insulating dielectric material received therebetween. Received within the dielectric material is a variable resistance material. The resistance of such material can be changed between low resistance and high resistance states. In its normal high resistance state, to perform a write operation, a voltage potential is applied to a certain one of the electrodes, with the other of the electrode being held at zero voltage or ground. The electrode having the voltage applied thereto functions as an anode, while the electrode held at zero or ground functions as a cathode. The nature of the resistance variable material is such that it undergoes a change at a certain applied voltage. With such voltage applied, a low resistance state is induced into the material such that electrical conduction can occur between the top and bottom electrodes.[0003]
- Once this occurs, the low resistance state is retained when the voltage potentials are removed. Such can effectively result in the resistance of the mass of resistance variable material between the electrodes dropping by a factor of 1,000. Such material can be returned to its highly resistive state by reversing the voltage potential between the anode and cathode. Again, the highly resistive state is maintained once the reverse voltage potentials are removed. Accordingly, such a device can, for example, function as a programmable memory cell of memory circuitry.[0004]
- The preferred resistance variable material received between the electrodes typically and preferably comprises a chalcogenide material having metal ions diffused therein. One specific example includes one or more layers of germanium selenide having silver ions diffused therein and one or more layers of silver selenide having excess silver ions diffused therein. It is, however, difficult to form silver rich silver selenide.[0005]
- While the invention was principally motivated in addressing the above issues, it is in no way so limited. The artisan will appreciate applicability of the invention in other aspects unrelated to the above issues, with the invention only being limited by the accompanying claims as literally worded without limiting reference to the specification, and as appropriately interpreted in accordance with the doctrine of equivalents.[0006]
- The invention includes methods of forming non-volatile resistance variable devices, and methods of forming silver selenide comprising structures. In one implementation, a method of forming a non-volatile resistance variable device includes forming a patterned mass comprising elemental silver over a substrate. A layer comprising elemental selenium is formed over the substrate and including the patterned mass comprising elemental silver. The substrate is exposed to conditions effective to react only some of the elemental selenium with the elemental silver to form the patterned mass to comprise silver selenide. Unreacted elemental selenium is removed from the substrate. A first conductive electrode is provided in electrical connection with one portion of the patterned mass comprising silver selenide. A germanium selenide comprising material is provided in electrical connection with another portion of the patterned mass comprising silver selenide. A second conductive electrode is provided in electrical connection with the germanium selenide comprising material.[0007]
- In one implementation, a method of forming a silver selenide comprising structure includes forming a substrate comprising a first outer portion and a second outer portion. The first outer portion comprises a patterned mass comprising elemental silver. The second outer portion does not comprise elemental silver. A layer comprising elemental selenium is formed over the first and second outer portions. The substrate is exposed to oxidizing conditions effective to both, a) react elemental selenium received over the first portion with elemental silver to form the patterned mass to comprise silver selenide, and b) remove elemental selenium of the layer over the second outer portion from the substrate.[0008]
- Preferred embodiments of the invention are described below with reference to the following accompanying drawings.[0009]
- FIG. 1 is a diagrammatic perspective view of a semiconductor wafer fragment/section in process in accordance with an aspect of the invention.[0010]
- FIG. 2 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 1.[0011]
- FIG. 3 is a view of the FIG. 2 wafer fragment at a processing step subsequent to that shown by FIG. 2.[0012]
- FIG. 4 is a view of the FIG. 3 wafer fragment at a processing step subsequent to that shown by FIG. 3.[0013]
- FIG. 5 is an alternate view of the FIG. 3 wafer fragment at an alternate processing step subsequent to that shown by FIG. 3.[0014]
- FIG. 6 is a view of the FIG. 4 wafer fragment at a processing step subsequent to that shown by FIG. 4.[0015]
- FIG. 7 is a view of the FIG. 6 wafer fragment at a processing step subsequent to that shown by FIG. 6.[0016]
- FIG. 8 is an alternate view of the FIG. 3 wafer fragment at an alternate processing step subsequent to that shown by FIG. 3.[0017]
- FIG. 9 is a diagrammatic perspective view of an alternate embodiment semiconductor wafer fragment/section in process in accordance with an aspect of the invention.[0018]
- FIG. 10 is a view of the FIG. 9 wafer fragment at a processing step subsequent to that shown by FIG. 9.[0019]
- FIG. 11 is a view of the FIG. 10 wafer fragment at a processing step subsequent to that shown by FIG. 10.[0020]
- FIG. 12 is a diagrammatic perspective view of another alternate embodiment semiconductor wafer fragment/section in process in accordance with an aspect of the invention.[0021]
- FIG. 13 is a view of the FIG. 12 wafer fragment at a processing step subsequent to that shown by FIG. 12.[0022]
- FIG. 14 is a view of the FIG. 13 wafer fragment at a processing step subsequent to that shown by FIG. 13.[0023]
- FIG. 15 is a view of the FIG. 14 wafer fragment at a processing step subsequent to that shown by FIG. 14.[0024]
- This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).[0025]
- Exemplary embodiment methods of forming a non-volatile resistance variable device are initially described with reference to FIGS.[0026]1-8. FIG. 1 depicts a
substrate fragment 10 comprising abase substrate 12 and a firstconductive electrode material 14 formed thereover.Base substrate 12 might comprise any suitable supporting substrate, for example a semiconductor substrate which includes bulk monocrystalline silicon. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Also in the context of this document, the term “layer” encompasses both the singular and the plural unless otherwise indicated. Exemplary preferred material forlayer 14 is elemental tungsten. - An[0027]
insulative material 16 is formed over firstconductive electrode material 14. Such has been patterned by any suitable patterning method (i.e., lithography, such as photolithography) to form anopening 18 therethrough to firstconductive electrode material 14.Opening 18 comprises some desired shape of at least a portion of a final resistance setable structure of the device being fabricated, as will be apparent from the continuing discussion. - Referring to FIG. 2, opening[0028]18 has been filled with an elemental
silver comprising material 20 in electrical connection with firstconductive electrode material 14. An exemplary preferred material formaterial 20 includes at least 50 molar percent elemental silver, even more preferably at least 95 molar percent elemental silver, and even more preferably greater than 99 molar percent elemental silver. In the illustrated preferred example,insulative material 16 has a substantially planar outermost surfaceproximate opening 18, and patterned mass/elementalsilver comprising material 20 withinopening 18 has an outermost surface which is co-planar with the insulative material outer surface. Further, patternedmass 20 can be considered as having some maximum first thickness, with an example thickness range being from about 50 Angstroms to about 2000 Angstroms. - One example method of producing the construction illustrated by FIG. 2 would be to deposit a layer of silver comprising material blanketly over the substrate, and then planarizing such layer back at least to the top of[0029]
outer insulative layer 16. By way of example only, such deposition might occur by chemical or physical means. Further, the polishing or planarizing could occur by resist etch back, chemical polishing, mechanical polishing or any combination thereof, or by any other existing or yet-to-be-developed method. Further, alternately and by way of example only, the illustrated FIG. 2 construction might be fabricated by an electroless or other deposition ofsilver comprising material 20 within the illustrated opening such thatmaterial 20 effectively only deposits therein and grows upwardly, with the growth preferably being stopped wherematerial 20 approximately reaches the upper surface ofinsulative material 16. Regardless, FIG. 2 depicts but one example of forming a patterned mass comprising elemental silver over a substrate. - Referring to FIG. 3, a[0030]
layer 22 comprising elemental selenium is formed oversubstrate 10 and including patternedmass 20 comprising elemental silver. Preferably,layer 22 comprises elemental selenium of at least 90 molar percent, more preferably at least 95 molar percent elemental selenium, and even more preferably greater than 99 molar percent elemental selenium. - Referring to FIG. 4,[0031]
substrate 10 has been exposed to conditions effective to reactelemental selenium 22 received over the elemental silver ofmass 20 to form at least a portion of the filled opening/patterned mass to comprisesilver selenide 25. In the depicted and preferred embodiment, such exposing to the conditions are effective to react only some of elementalselenium comprising layer 22, with those portions formed overinsulative material 16 being essentially unreacted. In the FIG. 4 depicted and preferred embodiment, the exposing is illustrated as forming the patterned mass to entirely comprisesilver selenide material 25. Regardless, the exposing preferably forms that portion of the patterned mass which is transformed to comprise at least 50 molar percent silver selenide, and more preferably at least 80 molar percent silver selenide. Further preferably, that portion which is formed is ideally substantially homogenous. - FIG. 5 depicts an[0032]
alternate embodiment 10a.Like numerals from the first embodiment are utilized where appropriate, with differences being indicated by the suffix “a”. FIG. 5 depicts forming an outermost portion25aof the patterned mass to comprise silver selenide, while aninnermost portion 20aof the patterned mass remains as the deposited silver comprising material initially formed. By way of example only, the remaining thickness ofinnermost portion 20ais preferably from 0 to 10 percent of the total thickness of the illustrated patterned mass. Each of FIGS. 4 and 5 depicts but one embodiment wherein the exposing forms more than one-half of the filled opening to comprise silver selenide. Alternately, by way of example only, one-half or less than one-half might be filled. Further in the preferred embodiment as shown, the exposing forms the patterned mass to have a maximum second thickness which is greater than the maximum first thickness. - One example preferred process for the subject exposing includes annealing the substrate at a temperature of from about 40° C. to about 100° C. at a pressure of from about 30 mTorr to 760 Torr for from about one to three hours. Higher temperatures typically result in a higher annealing rate. Conditions and time can be controlled to achieve a desired amount of the mass to be transformed to silver selenide comprising material. Further, by way of example only, annealing in a suitable oxidizing atmosphere is also a possibility, as is more fully described below.[0033]
- Referring to FIG. 6, unreacted[0034]
elemental selenium 22 has been removed from the substrate. The preferred removing, as shown, removes all remaining unreacted elemental selenium from the substrate. One example of removing comprises chemical etching, and preferably in a manner which is selective to remove elementalselenium comprising material 16 selectively relative to silverselenide comprising material 25. An example wet etch for doing so would include utilizing hydrogen peroxide, for example at from room temperature to 50° C. and ambient pressure. An example dry process would include plasma etching using CF4. Further by way of example only, an alternate process for removing unreacted elemental selenium comprises increasing the temperature of the substrate to closer to the melting temperature of selenium, say from 200° C. to 250° C., and at atmospheric pressure for from 10 minutes to one hour, effective to cause evaporation of the unreacted selenium from the substrate. - Referring to FIG. 7, a germanium selenide material layer[0035]26 (i.e., preferably 40 molar percent germanium and 60 molar percent selenium) is formed over and in electrical connection with silver
selenide comprising material 25. A secondconductive electrode material 28 is formed thereover, and thereby in electrical connection withsilver selenide 25 throughmaterial 26. Secondconductive electrode material 28 might be the same as firstconductive electrode material 14, or be different. An exemplary preferred material forelectrode 28 in the depicted and described embodiment is elemental silver. Regardless, in the preferred embodiment such provides exemplary processing of providing a first conductive electrode in electrical connection with one portion of patternedmass 25 comprising silver selenide, providing a germanium selenide comprising material in electrical connection with another portion of the patterned mass comprising silver selenide, and providing a second conductive electrode in electrical connection with the germanium selenide comprising material. - The above-described exemplary preferred embodiment processes conducted the exposing and the removing in different or separate processing steps. The invention also contemplates conducting the exposing and the removing in the same or single common processing step. FIG. 8 depicts an[0036]
alternate embodiment 10cwhich depicts an alternate processing of the FIG. 3 wafer which produces a slightly modified construction to that depicted by FIG. 4. In FIG. 8, the exposing and the removing have occurred in a common processing step comprising at least 100° C. and an atmosphere which removes unreacted elemental selenium by oxidation thereof. Preferably, the oxidizing atmosphere utilizes a weak oxidizer or a dilute oxidizer, for example at less than or equal to five percent by volume oxidizer, with less than or equal to one percent being more preferred. An example preferred oxidizing atmosphere comprises at least one of N2O, NOx, O3, F2and Cl2. By way of example only, preferred conditions include an elevated temperature of from 40° C. to 250°C., a pressure at from 30 mTorr to 760 Torr and from 30 minutes to two hours. - The oxidizing conditions and atmosphere are preferably selected to be sufficiently dilute or weak, as identified above, to prevent the complete oxidation of[0037]
selenium comprising material 22 over patternedmass 20 prior to driving (either physically or by reacting) elemental selenium into patternedmass 20 such that an effectivesilver selenide mass 25cis formed. However, such oxidizing will typically result in some removal of elemental selenium by oxidation at the outermost portion of elementalselenium comprising layer 22 over the patterned mass during the oxidizing. Most preferably in this and any embodiment, the exposing drives at least a majority of that portion of the elemental selenium received over the patterned mass into the patterned mass. - The invention further contemplates a method of forming any silver selenide comprising structure regardless of whether such is utilized in the fabrication of a non-volatile resistance variable device. Such method contemplates forming a substrate comprising a first outer portion and a second outer portion, with the first outer portion constituting a patterned mass comprising elemental silver and the second portion not comprising elemental silver. By way of example only and with respect to FIGS. 2 and 3, an outermost portion of patterned[0038]
mass 20 comprising elemental silver comprises an exemplary first outer portion, with the outermost portion ofinsulative 16 constituting an exemplary second outer portion. A layer comprising elemental selenium is formed over the first and second outer portions. The substrate is exposed to oxidizing conditions, by way of example only such as those described above, effective to both a) react elemental selenium received over the first portion with elemental silver to form the patterned mass to comprise silver selenide, and b) remove elemental selenium of a layer over the second outer portion from the substrate. Preferably, the exposing removes all unreacted elemental selenium from the substrate. Further, and in accordance with the above-described preferred embodiment, such exposing will tend to remove some of the elemental selenium of the layer over the first portion from the substrate, but still preferably drive at least a majority of that portion of the elemental selenium received over the first portion into the patterned mass, and more preferably at least 80 molar percent. Further, such exposing preferably forms the patterned mass to have a maximum second thickness which is greater than its maximum first thickness immediately prior to the exposing. - The depicted and above-described embodiments show processes wherein at least a majority and in one case essentially all of the material within opening[0039]18 is formed to comprise elemental silver. FIGS.9-11 illustrate an
alternate embodiment 10d.Like numerals from the first described embodiment are utilized where appropriate, with differences being indicated by the suffix “d” or with different numerals. FIG. 9 depicts an alternate elementalsilver comprising material 20dreceived withinopening 18. Such comprises a lower exemplary germanium selenide portion21 (i.e., preferably 40 percent germanium and 60 percent selenium), and an overlying preferred 99 percent-plus pureelemental silver region 23. By way of example only, such could be formed by suitable deposition and planarization relative to insulativelayer 16. Aselenium comprising layer 22dis formed thereover. - Referring to FIG. 10,[0040]
substrate 10dhas been subjected to the preferred exposing and removing processing (either together or in different steps) effective to form asilver selenide mass 25dand to remove at least some, and preferably all, unreacted elemental selenium from the substrate. - Referring to FIG. 11, another[0041]
germanium selenide layer 26dand asecond electrode 28dare formed thereover. - The above-described embodiments describe and depict exemplary methods of forming a patterned mass comprising elemental silver. Such embodiments depict forming a patterned opening within insulative material over a substrate, and at least partially filling the opening with an elemental silver comprising material. However, the invention contemplates any method of forming a patterned mass comprising elemental silver. By way of example only, one such alternate process is described with reference to FIGS.[0042]12-15.
- FIG. 12 depicts another[0043]
alternate embodiment 10e,with like numerals from the first embodiment being utilized and differences being indicated with the suffix “e” or with different numerals. FIG. 12 depicts the depositing of asilver comprising material 20e.Material 20ehas been patterned, for example by photopatterning and then subtractively etching after the patterning. Other patterning, such as laser patterning or any other method of patterning, is contemplated, whether existing or yet-to-be-developed. - Referring to FIG. 13, an elemental[0044]
selenium comprising layer 22eis formed over patternedmass 20e. - Referring to FIG. 14, the substrate has been exposed to conditions effective to react only some of[0045]
elemental selenium 22ewith the elemental silver to form a patternedmass 25eto comprise silver selenide. Any of the above-described processing, including an oxidation process which removes22efrom the process during the exposing, is contemplated, of course, and are only preferred examples. - Referring to FIG. 15, a preferred[0046]
germanium selenide layer 26eand a preferredsecond electrode 28eare formed thereover. - The above constructions can be effectively preferably fabricated to form programmable metallization cells over memory and other integrated circuitry.[0047]
- In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.[0048]
Claims (51)
1. A method of forming a non-volatile resistance variable device, comprising:
forming a patterned mass comprising elemental silver over a substrate;
forming a layer comprising elemental selenium over the substrate and including the patterned mass comprising elemental silver;
exposing the substrate to conditions effective to react only some of the elemental selenium with the elemental silver to form the patterned mass to comprise silver selenide;
removing unreacted elemental selenium from the substrate;
providing a first conductive electrode in electrical connection with one portion of the patterned mass comprising silver selenide;
providing a germanium selenide comprising material in electrical connection with another portion of the patterned mass comprising silver selenide; and
providing a second conductive electrode in electrical connection with the germanium selenide comprising material.
2. The method ofclaim 1 wherein the patterned mass comprises at least 50 molar percent elemental silver prior to the exposing.
3. The method ofclaim 1 wherein the patterned mass comprises at least 95 molar percent elemental silver prior to the exposing.
4. The method ofclaim 1 wherein the layer comprising elemental selenium comprises at least 90 molar percent elemental selenium prior to the exposing.
5. The method ofclaim 1 wherein the layer comprising elemental selenium comprises at least 95 molar percent elemental selenium prior to the exposing.
6. The method ofclaim 1 wherein the exposing and the removing occur in a common processing step.
7. The method ofclaim 1 wherein the exposing and the removing occur in different processing steps.
8. The method ofclaim 1 wherein the exposing and the removing occur in a common processing step comprising at least 40° C. and an atmosphere which removes unreacted elemental selenium by oxidation thereof.
9. The method ofclaim 1 wherein the removing of the unreacted elemental selenium comprises chemical etching after the exposing.
10. The method ofclaim 1 wherein the removing of the unreacted elemental selenium comprises evaporation after the exposing.
11. The method ofclaim 1 wherein the exposing forms the patterned mass to comprise at least 50 molar percent silver selenide.
12. The method ofclaim 1 wherein the exposing forms the patterned mass to comprise at least 80 molar percent silver selenide.
13. The method ofclaim 1 wherein the exposing drives at least a majority of that portion of the elemental selenium received over the patterned mass into the patterned mass.
14. The method ofclaim 1 wherein the patterned mass comprises greater than 50 molar percent elemental silver prior to the exposing, the exposing forming an outermost portion of the patterned mass to comprise greater than 50 molar percent silver selenide, with an innermost portion of the patterned mass remaining at greater than 50 molar percent elemental silver.
15. The method ofclaim 1 wherein the patterned mass comprises greater than 90 molar percent elemental silver prior to the exposing, the exposing forming an outermost portion of the patterned mass to comprise greater than 90 molar percent silver selenide, with an innermost portion of the patterned mass remaining at greater than 90 molar percent elemental silver.
16. The method ofclaim 1 wherein the patterned mass as formed prior to the exposing has a maximum first thickness, the exposing forming the patterned mass to have a maximum second thickness which is greater than the maximum first thickness.
17. The method ofclaim 1 wherein the removing removes all unreacted elemental selenium from the substrate.
18. The method ofclaim 1 wherein forming the patterned mass comprising elemental silver comprises depositing an elemental silver comprising material, photopatterning it, and subtractively etching it after the photopatterning.
19. The method ofclaim 1 wherein forming the patterned mass comprising elemental silver comprises forming a patterned opening within insulative material over the substrate, and at least partially filling the opening with an elemental silver comprising material.
20. A method of forming a non-volatile resistance variable device, comprising:
forming a patterned mass comprising at lest 90 molar percent elemental silver over a substrate and to a first maximum thickness;
forming a layer comprising at least 90 molar percent elemental selenium over the substrate and including the patterned mass comprising elemental silver;
exposing the substrate to conditions effective to react only some of the elemental selenium with the elemental silver to form the patterned mass to comprise silver selenide, the exposing forming the silver selenide to be rich in silver, and forming the patterned mass to have a maximum second thickness which is greater than the maximum first thickness, the exposing forming the patterned mass to comprise at least 80 molar percent silver selenide, the exposing driving at least a majority of that portion of the elemental selenium received over the patterned mass into the patterned mass;
removing all unreacted elemental selenium from the substrate;
providing a first conductive electrode in electrical connection with one portion of the patterned mass comprising silver selenide;
providing a germanium selenide comprising material in electrical connection with another portion of the patterned mass comprising silver selenide; and
providing a second conductive electrode in electrical connection with the germanium selenide comprising material.
21. A method of forming a non-volatile resistance variable device, comprising:
forming a first conductive electrode material over a substrate;
forming an insulative material over the first conductive electrode material and an opening therethrough to the first conductive electrode material, the opening comprising a desired shape of at least a portion of a final resistance setable structure of the device;
filling the opening with an elemental silver comprising material in electrical connection with the first conductive electrode material;
forming a layer comprising elemental selenium over the insulative material and over the elemental silver comprising material within the opening;
exposing the substrate to conditions effective to react elemental selenium received over the elemental silver to form at least a portion of the filled opening to comprise silver selenide;
removing unreacted elemental selenium received over the insulative material from the substrate; and
providing a germanium selenide comprising material in electrical connection with the silver selenide; and
providing a second conductive electrode in electrical connection with the germanium selenide comprising material.
22. The method ofclaim 21 wherein the exposing forms at least a majority portion of the filled opening to comprise silver selenide.
23. The method ofclaim 21 wherein the exposing forms less than one half of the filled opening to comprise silver selenide.
24. The method ofclaim 21 wherein the elemental silver comprising material comprises at least 50 molar percent elemental silver prior to the exposing.
25. The method ofclaim 21 wherein the elemental silver comprising material comprises at least 95 molar percent elemental silver prior to the exposing.
26. The method ofclaim 21 wherein the layer comprising elemental selenium comprises at least 90 molar percent elemental selenium prior to the exposing.
27. The method ofclaim 21 wherein the layer comprising elemental selenium comprises at least 95 molar percent elemental selenium prior to the exposing.
28. The method ofclaim 21 wherein the exposing and the removing occur in a common processing step.
29. The method ofclaim 21 wherein the exposing and the removing occur in different processing steps.
30. The method ofclaim 21 wherein the exposing and the removing occur in a common processing step comprising at least 40° C. and an atmosphere which removes unreacted elemental selenium by oxidation thereof.
31. The method ofclaim 21 wherein the removing of the unreacted elemental selenium comprises chemical etching after the exposing.
32. The method ofclaim 21 wherein the removing of the unreacted elemental selenium comprises evaporation after the exposing.
33. The method ofclaim 21 wherein the exposing forms at least 80% of the filled opening to comprise silver selenide.
34. The method ofclaim 21 wherein the exposing drives at least a majority of that portion of the elemental selenium received over the elemental silver comprising material into the elemental silver comprising material.
35. The method ofclaim 21 wherein the filled opening comprises greater than 50 molar percent elemental silver prior to the exposing, the exposing forming an outermost portion of the filled opening to comprise greater than 50 molar percent silver selenide, with an innermost portion of the filled opening remaining at greater than 50 molar percent elemental silver.
36. The method ofclaim 21 wherein the filled opening comprises greater than 90 molar percent elemental silver prior to the exposing, the exposing forming an outermost portion of the filled opening to comprise greater than 90 molar percent silver selenide, with an innermost portion of the filled opening remaining at greater than 90 molar percent elemental silver.
37. The method ofclaim 21 wherein the insulative material has a substantially planar outermost surface proximate the opening and the elemental silver comprising material within the filled opening has an outermost surface which is coplanar with the insulative material outer surface prior to the exposing, the elemental silver comprising material within the opening prior to the exposing having a maximum first thickness, the exposing forming the patterned mass to have a maximum second thickness which is greater than the maximum first thickness.
38. The method ofclaim 21 wherein the removing removes all unreacted elemental selenium from the substrate.
39. A method of forming a silver selenide comprising structure, comprising:
forming a substrate comprising a first outer portion and a second outer portion, the first outer portion comprising a patterned mass comprising elemental silver, the second outer portion not comprising elemental silver;
forming a layer comprising elemental selenium over the first and second outer portions; and
exposing the substrate to oxidizing conditions effective to both, a) react elemental selenium received over the first portion with elemental silver to form the patterned mass to comprise silver selenide, and b) remove elemental selenium of the layer over the second outer portion from the substrate.
40. The method ofclaim 39 wherein the exposing removes some of the elemental selenium of the layer over the first portion from the substrate.
41. The method ofclaim 39 wherein the exposing drives at least a majority of that portion of the elemental selenium received over the first portion into the patterned mass.
42. The method ofclaim 39 wherein the exposing drives at least a 80 molar percent of that portion of the elemental selenium received over the first portion into the patterned mass.
43. The method ofclaim 39 wherein the exposing comprises a temperature of from about 40° C. to about 250° C.
44. The method ofclaim 39 wherein the oxidizing conditions comprise an atmosphere comprising at least one of N2O, NOX, O3, F2, and Cl2.
45. The method ofclaim 39 wherein the exposing removes all elemental selenium of the layer over the second outer portion from the substrate.
46. The method ofclaim 39 wherein the exposing removes all unreacted elemental selenium from the substrate.
47. The method ofclaim 39 wherein the patterned mass comprises at least 95 molar percent elemental silver prior to the exposing.
48. The method ofclaim 39 wherein the layer comprising elemental selenium comprises at least 95 molar percent elemental selenium prior to the exposing.
49. The method ofclaim 39 wherein the patterned mass as formed prior to the exposing has a maximum first thickness, the exposing forming the patterned mass to have a maximum second thickness which is greater than the maximum first thickness.
50. The method ofclaim 39 wherein forming the patterned mass comprising elemental silver comprises depositing an elemental silver comprising material, photopatterning it, and subtractively etching it after the photopatterning.
51. The method ofclaim 39 wherein forming the patterned mass comprising elemental silver comprises forming a patterned opening within insulative material over the substrate, and at least partially filling the opening with an elemental silver comprising material.
Priority Applications (11)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/061,825US20030143782A1 (en) | 2002-01-31 | 2002-01-31 | Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures |
| AU2003212814AAU2003212814A1 (en) | 2002-01-31 | 2003-01-21 | Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures |
| DE60320373TDE60320373T2 (en) | 2002-01-31 | 2003-01-21 | METHOD OF MANUFACTURING NON-VOLATILE RESISTANT COMPONENTS AND METHOD OF MANUFACTURING SILVER-SELENO-FIXED STRUCTURES |
| EP03708848AEP1470589B1 (en) | 2002-01-31 | 2003-01-21 | Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures |
| AT03708848TATE392714T1 (en) | 2002-01-31 | 2003-01-21 | PRODUCTION PROCESS FOR NON-VOLATILE RESISTOR-CHANGING COMPONENTS AND PRODUCTION PROCESS FOR STRUCTURES CONTAINING SILVER SELENIDES |
| PCT/US2003/001498WO2003065456A2 (en) | 2002-01-31 | 2003-01-21 | Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures |
| CNB038076551ACN100375284C (en) | 2002-01-31 | 2003-01-21 | Methods of forming nonvolatile variable resistance devices and methods of forming silver selenide comprising structures |
| JP2003564939AJP2005516418A (en) | 2002-01-31 | 2003-01-21 | Method for forming nonvolatile variable resistance device and method for forming silver selenide-containing structure |
| KR1020047011805AKR100660245B1 (en) | 2002-01-31 | 2003-01-21 | A method of forming a nonvolatile resistive variable element and a method of forming a structure including silver selenide |
| TW092102209ATWI251263B (en) | 2002-01-31 | 2003-01-30 | Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures |
| US10/634,897US6812087B2 (en) | 2002-01-31 | 2003-08-06 | Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/061,825US20030143782A1 (en) | 2002-01-31 | 2002-01-31 | Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/634,897ContinuationUS6812087B2 (en) | 2002-01-31 | 2003-08-06 | Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US20030143782A1true US20030143782A1 (en) | 2003-07-31 |
Family
ID=27610193
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/061,825AbandonedUS20030143782A1 (en) | 2002-01-31 | 2002-01-31 | Methods of forming germanium selenide comprising devices and methods of forming silver selenide comprising structures |
| US10/634,897Expired - LifetimeUS6812087B2 (en) | 2002-01-31 | 2003-08-06 | Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/634,897Expired - LifetimeUS6812087B2 (en) | 2002-01-31 | 2003-08-06 | Methods of forming non-volatile resistance variable devices and methods of forming silver selenide comprising structures |
Country Status (10)
| Country | Link |
|---|---|
| US (2) | US20030143782A1 (en) |
| EP (1) | EP1470589B1 (en) |
| JP (1) | JP2005516418A (en) |
| KR (1) | KR100660245B1 (en) |
| CN (1) | CN100375284C (en) |
| AT (1) | ATE392714T1 (en) |
| AU (1) | AU2003212814A1 (en) |
| DE (1) | DE60320373T2 (en) |
| TW (1) | TWI251263B (en) |
| WO (1) | WO2003065456A2 (en) |
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Also Published As
| Publication number | Publication date |
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| US6812087B2 (en) | 2004-11-02 |
| KR100660245B1 (en) | 2006-12-20 |
| JP2005516418A (en) | 2005-06-02 |
| DE60320373D1 (en) | 2008-05-29 |
| KR20040083432A (en) | 2004-10-01 |
| EP1470589B1 (en) | 2008-04-16 |
| CN1647278A (en) | 2005-07-27 |
| CN100375284C (en) | 2008-03-12 |
| DE60320373T2 (en) | 2009-02-19 |
| WO2003065456A2 (en) | 2003-08-07 |
| AU2003212814A1 (en) | 2003-09-02 |
| US20040029351A1 (en) | 2004-02-12 |
| WO2003065456A3 (en) | 2003-12-04 |
| EP1470589A2 (en) | 2004-10-27 |
| TW200303040A (en) | 2003-08-16 |
| TWI251263B (en) | 2006-03-11 |
| ATE392714T1 (en) | 2008-05-15 |
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