US20030137048A1 - Stacking system and method - Google Patents

Abstract

The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.

Description

RELATED APPLICATIONS
• This application is a continuation of U.S. application Ser. No. 10/005,581, filed Oct. 26, 2001, pending, which is hereby incorporated by reference.[0001]
TECHNICAL FIELD
• The present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits in chip-scale packages.[0002]
BACKGROUND OF THE INVENTION
• A variety of techniques are used to stack packaged integrated circuits. Some methods require special packages, while other techniques stack conventional packages. In some stacks, the leads of the packaged integrated circuits are used to create a stack, while in other systems, added structures such as rails provide all or part of the interconnection between packages. In still other techniques, flexible conductors with certain characteristics are used to selectively interconnect packaged integrated circuits.[0003]
• The predominant package configuration employed during the past decade has encapsulated an integrated circuit (IC) in a plastic surround typically having a rectangular configuration. The enveloped integrated circuit is connected to the application environment through leads emergent from the edge periphery of the plastic encapsulation. Such “leaded packages” have been the constituent elements most commonly employed by techniques for stacking packaged integrated circuits.[0004]
• Leaded packages play an important role in electronics, but efforts to miniaturize electronic components and assemblies have driven development of technologies that preserve circuit board surface area. Because leaded packages have leads emergent from peripheral sides of the package, leaded packages occupy more than a minimal amount of circuit board surface area. Consequently, alternatives to leaded packages have recently gained market share.[0005]
• One family of alternative packages is identified generally by the term “chip scale packaging” or CSP. CSP refers generally to packages that provide connection to an integrated circuit through a set of contacts (often embodied as “bumps” or “balls”) arrayed across a major surface of the package. Instead of leads emergent from a peripheral side of the package, contacts are placed on a major surface and typically emerge from the planar bottom surface of the package.[0006]
• The goal of CSP is to occupy as little area as possible and, preferably, approximately the area of the encapsulated IC. Therefore, CSP leads or contacts do not typically extend beyond the outline perimeter of the package. The absence of “leads” on package sides renders most stacking techniques devised for leaded packages inapplicable for CSP stacking.[0007]
• CSP has enabled reductions in size and weight parameters for many applications. For example, micro ball grid array (μBGA) for flash and SRAM and wirebond on tape or rigid laminate CSPs for SRAM or EEPROM have been employed in a variety of applications. CSP is a broad category including a variety of packages from near chip scale to die-sized packages such as the die sized ball grid array (DSBGA) recently described in proposed JEDEC standard 95-1 for DSBGA. To meet the continuing demands for cost and form factor reduction with increasing memory capacities, CSP technologies that aggregate integrated circuits in CSP technology have recently been developed. For example, Sharp, Hitachi, Mitsubishi and Intel recently undertook support of what are called the S-CSP specifications for flash and SRAM applications. Those S-CSP specifications describe, however, stacking multiple die within a single chip scale package and do not provide a technology for stacking chip scale packages. Stacking integrated circuits within a single package requires specialized technology that includes reformulation of package internals and significant expense with possible supply chain vulnerabilities.[0008]
• There are several known techniques for stacking packages articulated in chip scale technology. The assignee of the present invention has developed previous systems for aggregating μBGA packages in space saving topologies. The assignee of the present invention has systems for stacking BGA packages on a DIMM in a RAMBUS environment.[0009]
• In U.S. Pat. No. 6,205,654 B1 owned by the assignee of the present invention, a system for stacking ball grid array packages that employs lead carriers to extend connectable points out from the packages is described. Other known techniques add structures to a stack of BGA-packaged ICs. Still others aggregate CSPs on a DIMM with angular placement of the packages. Such techniques provide alternatives, but require topologies of added cost and complexity.[0010]
• U.S. Pat. No. 6,262,895 B1 to Forthun (the “Forthun patent”) purports to disclose a technique for stacking chip scale packaged ICs. The Forthun patent discloses a “package” that exhibits a flex circuit wrapped partially about a CSP. The flex circuit is said to have pad arrays on upper and lower surfaces of the flex.[0011]
• The flex circuit of the Forthun “package” has a pad array on its upper surface and a pad array centrally located upon its lower surface. On the lower surface of the flex there are third and fourth arrays on opposite sides from the central lower surface pad array. To create the package of Forthun, a CSP contacts the pad array located on the upper surface of the flex circuit. As described in the Forthun patent, the contacts on the lower surface of the CSP are pushed through “slits” in the upper surface pads and advanced through the flex to protrude from the pads of the lower surface array and, therefore, the bottom surface of the package. Thus, the contacts of the CSP serve as the contacts for the package. The sides of the flex are partially wrapped about the CSP to adjacently place the third and fourth pad arrays above the upper major surface of the CSP to create from the combination of the third and fourth pad arrays, a fifth pad array for connection to another such package. Thus, as described in the Forthun disclosure, a stacked module of CSPs created with the described packages will exhibit a flex circuit wrapped about each CSP in the module.[0012]
• The previous known methods for stacking CSPs apparently have various deficiencies including complex structural arrangements and thermal or high frequency performance issues. Typically, the reliability of chip scale packaging is closely scrutinized. During such reliability evaluations, CSP devices often exhibit temperature cycle performance issues. CSPs are generally directly mounted on a PWB or other platform offset from the PWB by only the height of the ball or bump array emergent from the lower surface of the CSP. Consequently, stresses arising from temperature gradients over time are concentrated in the short lever arm of a low-height ball array. The issues associated with temp cycle performance in single CSPs will likely arise in those prior art CSP stacking solutions where the stack is offset from the PWB or application platform by only the height of the lower CSP ball grid array.[0013]
• Thermal performance is also a characteristic of importance in CSP stacks. To increase dissipation of heat generated by constituent CSPs, the thermal gradient between the lower CSP and upper CSP in a CSP stack or module should be minimized. Prior art solutions to CSP stacking do not, however, address thermal gradient minimization in disclosed constructions.[0014]
• What is needed, therefore, is a technique and system for stacking integrated circuits packaged in chip scale technology packaging that provides a thermally efficient, reliable structure that performs well at higher frequencies but does not add excessive height to the stack yet allows production at reasonable cost with readily understood and managed materials and methods.[0015]
SUMMARY OF THE INVENTION
• The present invention stacks chip scale-packaged integrated circuits (CSPs) into modules that conserve PWB or other board surface area. The present invention can be used to advantage with CSP packages of a variety of sizes and configurations ranging from typical BGAs with footprints somewhat larger than the contained die to smaller packages such as, for example, die-sized packages such as DSBGA. Although the present invention is applied most frequently to chip scale packages that contain one die, it may be employed with chip scale packages that include more than one integrated circuit die.[0016]
• In a two-high CSP stack or module devised in accordance with a preferred embodiment of the present invention, two CSPs are stacked, with one CSP disposed above the other. The two CSPs are connected with a pair of flex circuits. Each of the pair of flex circuits is partially wrapped about a respective opposite lateral edge of the lower CSP of the module. The flex circuit pair connects the upper and lower CSPs and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB).[0017]
• The present invention may be employed to advantage in numerous configurations and combinations of CSPs in modules provided for high-density memories or high capacity computing.[0018]
SUMMARY OF THE DRAWINGS
• FIG. 1 is an elevation view of[0019]module10 devised in accordance with a preferred embodiment of the present invention.
• FIG. 2 is an elevation view of[0020]module10 devised in accordance with a preferred embodiment of the present invention.
• FIG. 3 depicts, in enlarged view, the area marked “A” in FIG. 2.[0021]
• FIG. 4 is an enlarged detail of an exemplar connection in a preferred embodiment of the present invention.[0022]
• FIG. 5 is an enlarged depiction of an exemplar area around a lower flex contact in a preferred embodiment of the present invention.[0023]
• FIG. 6 depicts a first outer surface layer of a flex circuit employed in a preferred embodiment of the present invention.[0024]
• FIG. 7 depicts a first outer surface layer of a flex circuit employed in a preferred embodiment of the present invention.[0025]
• FIG. 8 depicts a first conductive layer of a flex circuit employed in a preferred embodiment of the present invention.[0026]
• FIG. 9 illustrates a first conductive layer of a flex circuit employed in a preferred embodiment of the present invention.[0027]
• FIG. 10 depicts an intermediate layer of a flex circuit employed in a preferred embodiment of the present invention.[0028]
• FIG. 11 depicts an intermediate layer of a right side flex circuit employed in a preferred embodiment of the present invention.[0029]
• FIG. 12 depicts a second conductive layer of a flex circuit of a preferred embodiment of the present invention.[0030]
• FIG. 13 depicts a second conductive layer of a flex circuit of a preferred embodiment of the present invention.[0031]
• FIG. 14 depicts a second outer layer of a flex circuit employed in a preferred embodiment of the present invention.[0032]
• FIG. 15 reflects a second outer layer of a flex circuit employed in a preferred embodiment of the present invention.[0033]
• FIG. 16 depicts an alternative preferred embodiment of the present invention.[0034]
• FIG. 17 illustrates a JEDEC pinout for DDR-II FBGA packages.[0035]
• FIG. 18 illustrates the pinout of a[0036]module10 in an alternative preferred embodiment of the invention.
• FIG. 19 illustrates the pinout of a[0037]module10 in an alternative embodiment of the invention.
• FIG. 20 depicts the pinout of an exemplar CSP employed in a preferred embodiment of the invention.[0038]
• FIG. 21 depicts a second conductive layer of a flex circuit employed in an alternative preferred embodiment of the present invention.[0039]
• FIG. 22 depicts a second conductive layer of a flex circuit employed in an alternative preferred embodiment of the present invention.[0040]
DESCRIPTION OF PREFERRED EMBODIMENTS
• FIG. 1 is an elevation view of[0041]module10 devised in accordance with a preferred embodiment of the present invention.Module10 is comprised ofupper CSP12 andlower CSP14. Each ofCSPs12 and14 have anupper surface16 and alower surface18 and oppositelateral sides20 and22.
• The invention is used with CSP packages of a variety of types and configurations such as, for example, those that are die-sized, as well those that are near chip-scale as well as the variety of ball grid array packages known in the art. Collectively, these will be known herein as chip scale packaged integrated circuits (CSPs) and preferred embodiments will be described in terms of CSPs, but the particular configurations used in the explanatory figures are not, however, to be construed as limiting. For example, the elevation views of FIGS. 1 and 2 are depicted with CSPs of a particular profile known to those in the art, but it should be understood that the figures are exemplary only. Later figures show embodiments of the invention that employ CSPs of other configurations as an example of one other of the many alternative CSP configurations with which the invention may be employed. The invention may be employed to advantage in the wide range of CSP configurations available in the art where an array of connective elements is emergent from at least one major surface. The invention is advantageously employed with CSPs that contain memory circuits but may be employed to advantage with logic and computing circuits where added capacity without commensurate PWB or other board surface area consumption is desired.[0042]
• Typical CSPs, such as, for example, ball-grid-array (“BGA”), micro-ball-grid array (“μBGA”), and fine-pitch ball grid array (“FBGA”) packages have an array of connective contacts embodied, for example, as leads, bumps, solder balls, or balls that extend from[0043]lower surface18 of a plastic casing in any of several patterns and pitches. An external portion of the connective contacts is often finished with a ball of solder. Shown in FIG. 1 areCSP contacts24 alonglower surfaces18 ofCSPs12 and14.CSP contacts24 provide connection to the integrated circuit within the respective packages. Collectively,CSP contacts24 compriseCSP array26 shown as to lowerCSP14 in the depicted particular package configuration asCSP arrays26₁and26₂which collectively compriseCSP array26.
• In FIG. 1, flex circuits (“flex”, “flex circuits” or “flexible circuit structures”)[0044]30 and32 are shown partially wrapped aboutlower CSP14 withflex30 partially wrapped overlateral side20 oflower CSP14 and flex32 partially wrapped aboutlateral side22 oflower CSP14.Lateral sides20 and22 may be in the character of sides or may, if the CSP is especially thin, be in the character of an edge. Any flexible or conformable substrate with a multiple internal layer connectivity capability may be used as a flex circuit in the invention. The entire flex circuit may be flexible or, as those of skill in the art will recognize, a PCB structure made flexible in certain areas to allow conformability aroundlower CSP14 and rigid in other areas for planarity along CSP surfaces may be employed as an alternative flex circuit in the present invention. For example, structures known as rigid-flex may be employed.
• Portions of[0045]flex circuits30 and32 are fixed toupper surface16 oflower CSP14 by adhesive34 which is shown as a tape adhesive, but may be a liquid adhesive or may be placed in discrete locations across the package. Preferably, adhesive34 is thermally conductive. Adhesives that include a flux are used to advantage in assembly ofmodule10.Layer34 may also be a thermally conductive medium to encourage heat flow between the CSPs ofmodule10.
• [0046]Flex circuits30 and32 are multi-layer flexible circuit structures that have at least two conductive layers. Preferably, the conductive layers are metal such as alloy 110. The use of plural conductive layers provides advantages as will be seen and the creation of a distributed capacitance acrossmodule10 intended to reduce noise or bounce effects that can, particularly at higher frequencies, degrade signal integrity, as those of skill in the art will recognize.Module10 of FIG. 1 hasmodule contacts36 collectively identified as module array38.
• FIG. 2 shows a[0047]module10 devised in accordance with a preferred embodiment of the invention. FIG. 2 illustrates use of aconformal media40 provided in a preferred embodiment to assist in creating conformality of structural areas ofmodule10. Planarity of the module is improved byconformal media40. Preferably,conformal media40 is thermally conductive. In alternative embodiments, thermal spreaders or a thermal medium may be placed as shown byreference41. Identified in FIG. 2 areupper flex contacts42 andlower flex contacts44 that are at one of the conductive layers offlex circuits30 and32.Upper flex contacts42 andlower flex contacts44 are conductive material and, preferably, are solid metal.Lower flex contacts44 are collectively lowerflex contact array46.Upper flex contacts42 are collectively upperflex contact array48. Only some ofupper flex contacts42 andlower flex contacts44 are identified in FIG. 2 to preserve clarity of the view. It should be understood that each offlex circuits30 and32 have bothupper flex contacts42 andlower flex contacts44.Lower flex contacts44 are employed withlower CSP14 andupper flex contacts42 are employed withupper CSP12. FIG. 2 has an area marked “A” that is subsequently shown in enlarged depiction in FIG. 3.
• FIG. 3 depicts in enlarged view, the area marked “A” in FIG. 2. FIG. 3 illustrates the connection between[0048]example CSP contact24 andmodule contact36 throughlower flex contact44 to illustrate the solid metal path fromlower CSP14 tomodule contact36 and, therefore, to an application PWB to which module is connectable. As those of skill in the art will understand, heat transference frommodule10 is thereby encouraged.
• With continuing reference to FIG. 3,[0049]CSP contact24 andmodule contact36 together offsetmodule10 from an application platform such as a PWB. The combined heights ofCSP contact24 andmodule contact36 provide a moment arm longer than the height of asingle CSP contact24 alone. This provides a longer moment arm through which temperature-gradient-over-time stresses (such as typified by temp cycle), can be distributed.
• [0050]Flex30 is shown in FIG. 3 to be comprised of multiple layers.Flex30 has a firstouter surface50 and a secondouter surface52.Flex circuit30 has at least two conductive layers interior to first and secondouter surfaces50 and52. There may be more than two conductive layers inflex30 andflex32. In the depicted preferred embodiment, firstconductive layer54 and secondconductive layer58 are interior to first and secondouter surfaces50 and52.Intermediate layer56 lies between firstconductive layer54 and secondconductive layer58. There may be more than one intermediate layer, but one intermediate layer of polyimide is preferred.
• As depicted in FIG. 3 and seen in more detail in later figures,[0051]lower flex contact44 is preferably comprised from metal at the level of secondconductive layer58 interior to secondouter surface52.Lower flex contact44 is solid metal in a preferred embodiment and is comprised of metal alloy such as alloy 110. This results in a solid metal pathway fromlower CSP14 to an application board thereby providing a significant thermal pathway for dissipation of heat generated inmodule10.
• FIG. 4 is an enlarged detail of an exemplar connection between[0052]example CSP contact24 andexample module contact36 throughlower flex contact44 to illustrate the solid metal path fromlower CSP14 tomodule contact36 and, therefore, to an application PWB to whichmodule10 is connectable. As shown in FIG. 4,lower flex contact44 is at secondconductive layer58 that is interior to first and second outer surface layers50 and52 respectively, offlex circuit30.
• FIG. 5 is an enlarged depiction of an exemplar area around a[0053]lower flex contact44 in a preferred embodiment.Windows60 and62 are opened in first and second outer surface layers50 and52 respectively, to provide access to particularlower flex contacts44 residing at the level of secondconductive layer58 in the flex. Theupper flex contacts42 are contacted byCSP contacts24 ofupper CSP12.Lower flex contacts44 andupper flex contacts42 are particular areas of conductive material (preferably metal such as alloy 110) at the level of secondconductive layer58 in the flex.Upper flex contacts42 andlower flex contacts44 are demarked in secondconductive layer58 and, as will be shown in subsequent Figs., may be connected to or isolated from the conductive plane of secondconductive layer58. Demarking alower flex contact44 from secondconductive layer58 is represented in FIG. 5 bydemarcation gap63 shown at secondconductive layer58. Where an upper orlower flex contact42 or44 is not completely isolated from secondconductive layer58, demarcation gaps do not extend completely around the flex contact as shown, for example, bylower flex contacts44C in later FIG. 12.CSP contacts24 oflower CSP14 pass through awindow60 opened through firstouter surface layer50, firstconductive layer54, andintermediate layer56, to contact an appropriatelower flex contact44.Window62 is opened through secondouter surface layer52 through whichmodule contacts36 pass to contact the appropriatelower flex contact44.
• Respective ones of[0054]CSP contacts24 ofupper CSP12 andlower CSP14 are connected at the secondconductive layer58 level inflex circuits30 and32 to interconnect appropriate signal and voltage contacts of the two CSPs.Respective CSP contacts24 ofupper CSP12 andlower CSP14 that convey ground (VSS) signals are connected at the firstconductive layer54 level inflex circuits30 and32 by vias that pass throughintermediate layer56 to connect the levels as will subsequently be described in further detail. Thereby,CSPs12 and14 are connected. Consequently, whenflex circuits30 and32 are in place aboutlower CSP14,respective CSP contacts24 of each of upper andlower CSPs12 and14 are in contact with upper andlower flex contacts42 and44, respectively. Selected ones ofupper flex contacts42 andlower flex contacts44 are connected. Consequently, by being in contact withlower flex contacts44,module contacts36 are in contact with both upper andlower CSPs12 and14.
• In a preferred embodiment,[0055]module contacts36 pass throughwindows62 opened in secondouter layer52 to contactlower CSP contacts44. In some embodiments, as will be later shown,module10 will exhibit a module contact array38 that has a greater number of contacts than do the constituent CSPs ofmodule10. In such embodiments, some ofmodule contacts36 may contactlower flex contacts44 that do not contact one of theCSP contacts24 oflower CSP14 but are connected toCSP contacts24 ofupper CSP12. This allowsmodule10 to express a wider datapath than that expressed by theconstituent CSPs12 or14. Amodule contact36 may also be in contact with alower flex contact44 to provide a location through which different levels of CSPs in the module may be enabled when no unused CSP contacts are available or convenient for that purpose.
• In a preferred embodiment, first[0056]conductive layer54 is employed as a ground plane, while secondconductive layer58 provides the functions of being a signal conduction layer and a voltage conduction layer. Those of skill will note that roles of the first and second conductive layers may be reversed with attendant changes in windowing and use of commensurate interconnections.
• As those of skill will recognize, interconnection of respective[0057]voltage CSP contacts24 of upper andlower CSPs12 and14 will provide a thermal path between upper and lower CSPs to assist in moderation of thermal gradients throughmodule10. Such flattening of the thermal gradient curve acrossmodule10 is further encouraged by connection of commonground CSP contacts24 of upper andlower CSPs12 and14 through firstconductive layer54. Those of skill will notice that between first and secondconductive layers54 and58 there is at least oneintermediate layer56 that, in a preferred embodiment, is a polyimide. Placement of such an intermediate layer between ground-conductive firstconductive layer54 and signal/voltage conductive secondconductive layer58 provides, in the combination, a distributed capacitance that assists in mitigation of ground bounce phenomena to improve high frequency performance ofmodule10.
• In a preferred embodiment, FIG. 6 depicts first[0058]outer surface layer50 of flex30 (i.e., left side of FIG. 1). The view is from above the flex looking down intoflex30 from the perspective of firstconductive layer54. Throughout the Figs., the location reference “B” is to orient views of layers offlex30 to those offlex32 as well as across layers.Windows60 are opened through firstouter surface layer50, firstconductive layer54, andintermediate layer56.CSP contacts24 oflower CSP14 pass throughwindows60 of firstouter surface layer50, firstconductive layer54, andintermediate layer56 to reach the level of secondconductive layer58 offlex30. At secondconductive layer58, selectedCSP contacts24 oflower CSP14 make contact with selectedlower flex contacts44.Lower flex contacts44 provide several types of connection in a preferred embodiment as will be explained with reference to later FIG. 12. Whenmodule10 is assembled, a portion offlex30 will be wrapped aboutlateral side20 oflower CSP14 to placeedge62 aboveupper surface16 oflower CSP14.
• In a preferred embodiment, FIG. 7 depicts first[0059]outer surface layer50 of flex32 (i.e., right side of FIG. 1). The view is from above the flex looking down intoflex32 from the perspective of firstconductive layer54. The location reference “B” relatively orients the views of FIGS. 6 and 7. The views of FIGS. 6 and 7 may be understood together with the reference marks “B” of each view being placed nearer each other than to any other corner of the other view of the pair of views of the same layer. As shown in FIG. 7,windows60 are opened through firstouter surface layer50, firstconductive layer54 andintermediate layer56.CSP contacts24 oflower CSP14 pass throughwindows60 of firstouter surface layer50, firstconductive layer54, andintermediate layer56 to reach the level of secondconductive layer58 offlex30. At secondconductive layer58, selectedCSP contacts24 oflower CSP14 make contact withlower flex contacts44.Lower flex contacts44 provide several types of connection in a preferred embodiment as will be explained with reference to later FIG. 12. Whenmodule10 is assembled, a portion offlex32 will be wrapped aboutlateral side22 oflower CSP14 to placeedge64 aboveupper surface16 oflower CSP14.
• FIG. 8 depicts first[0060]conductive layer54 offlex30.Windows60 continue the opened orifice inflex30 through whichCSP contacts24 oflower CSP14 pass to reach secondconductive layer58 and, therefore, selectedlower flex contacts44 at the level of secondconductive layer58.
• Those of skill will recognize that as[0061]flex30 is partially wrapped aboutlateral side20 oflower CSP14, firstconductive layer54 becomes, on the part offlex30 disposed aboveupper surface16 oflower CSP14, the lower-most conductive layer offlex30 from the perspective ofupper CSP12. In the depicted embodiment, thoseCSP contacts24 ofupper CSP12 that provide ground (VSS) connections are connected to the firstconductive layer54. Firstconductive layer54 lies beneath, however, secondconductive layer58 in that part offlex30 that is wrapped abovelower CSP14. Consequently, some means must be provided for connection of theupper flex contact42 to which ground-conveyingCSP contacts24 ofupper CSP12 are connected and firstconductive layer54. Consequently, in the depicted preferred embodiment, thoseupper flex contacts42 that are in contact with ground-conveyingCSP contacts24 ofupper CSP12 have vias that route throughintermediate layer56 to reach firstconductive layer54. The sites where those vias meet firstconductive layer54 are identified in FIG. 8 asvias66. These vias may be “on-pad” or coincident with theflex contact42 to which they are connected. Those of skill will note a match between the vias66 identified in FIG. 8 and vias66 identified in the later view of secondconductive layer58 of the depicted preferred embodiment. In a preferred embodiment, vias66 in coincident locations from Fig. to Fig. are one via. For clarity of the view, depicted vias in the figures are shown larger in diameter than in manufactured embodiments. As those of skill will recognize, the connection between conductive layers provided by vias (on or off pad) may be provided any of several well-known techniques such as plated holes or solid lines or wires and need not literally be vias.
• Also shown in FIG. 8 are off-[0062]pad vias74. Off-pad vias74 are disposed on firstconductive layer54 at locations near, but not coincident with selected ones ofwindows60. Unlikevias66 that connect selected ones ofupper flex contacts42 to firstconductive layer54, off-pad vias74 connect selected ones oflower flex contacts44 to firstconductive layer54. In the vicinity ofupper flex contacts42, secondconductive layer58 is between the CSP connected tomodule10 by the upper flex contacts42 (i.e., upper CSP12) and firstconductive layer54. Consequently, vias between ground-conveyingupper flex contacts42 and firstconductive layer54 may be directly attached to the selectedupper flex contacts42 through which ground signals are conveyed. In contrast, in the vicinity oflower flex contacts44, firstconductive layer54 is between the CSP connected tomodule10 by the lower flex contacts44 (i.e., lower CSP14) and secondconductive layer58. Consequently, vias between ground-conveyinglower flex contacts44 and firstconductive layer54 are offset from the selectedlower flex contacts44 by off-pad vias74 shown in offset locations.
• FIG. 9 illustrates first[0063]conductive layer54 offlex32. The location reference marks “B” are employed to relatively orient FIGS. 8 and 9.Windows60, vias66 and off-pad vias74 are identified in FIG. 9. Also shown in FIG. 9, are enablevias68 and70 and enabletrace72. Enable via70 is connected off-pad to a selectedlower flex contact44 that corresponds, in this preferred embodiment, to anunused CSP contact24 of lower CSP14 (i.e., a N/C). Amodule contact36 at that site conveys an enable signal (C/S) forupper CSP12 through the selected lower flex contact44 (which is at the level of second conductive layer58) to off-pad enable via70 that conveys the enable signal to firstconductive layer54 and thereby to enabletrace72. Enabletrace72 further conveys the enable signal to enable via68 which extends throughintermediate layer56 to selectedupper flex contact42 at the level of secondconductive layer58 where contact is made with the C/S pin ofupper CSP12. Thus, upper andlower CSPs12 and14 may be independently enabled.
• FIG. 10 depicts[0064]intermediate layer56 offlex30.Windows60 are shown opened inintermediate surface56.CSP contacts24 oflower CSP14 pass throughwindows60 inintermediate layer58 to reachlower flex contacts44 at the level of secondconductive layer58. Those of skill will notice that, in the depicted preferred embodiment,windows60 narrow in diameter from their manifestation in firstouter layer50.Vias66, off-pad vias74, and enablevias68 and70 pass throughintermediate layer56 connecting selected conductive areas at the level of first and secondconductive layers54 and58, respectively. FIG. 11 depictsintermediate layer56 offlex32 showingwindows60, vias66, off-pad vias74, and enablevias68 and70 passing throughintermediate layer56.
• FIG. 12 depicts second[0065]conductive layer58 offlex30 of a preferred embodiment of the present invention. Depicted are various types ofupper flex contacts42, various types oflower flex contacts44, signal traces76, andVDD plane78 as well as previously describedvias66 and off-pad vias74. Throughout FIGS. 12 and 13, only exemplars of particular features are identified to preserve clarity of the view.Flex contacts44A are connected to corresponding selectedupper flex contacts42A with signal traces76. To enhance the clarity of the view, only exemplarindividual flex contacts44A and42A are literally identified in FIG. 12. As shown, in this preferred embodiment, signal traces76 exhibit path routes determined to provide substantially equal signal lengths betweencorresponding flex contacts42A and44A. As shown, traces76 are separated from the larger surface area of secondconductive layer58 that is identified asVDD plane78.VDD plane78 may be in one or more delineated sections but, preferably is one section.Lower flex contacts44C provide connection toVDD plane78. In a preferred embodiment,upper flex contacts42C andlower flex contacts44C connectupper CSP12 andlower CSP14, respectively, toVDD plane78.Lower flex contacts44 that are connected to firstconductive layer54 by off-pad vias74 are identified aslower flex contacts44B. To enhance the clarity of the view, only exemplar individuallower flex contacts44B are literally identified in FIG. 12.Upper flex contacts42 that are connected to firstconductive layer54 byvias66 are identified asupper flex contacts42B.
• FIG. 13 depicts second[0066]conductive layer58 ofright side flex32 of a preferred embodiment of the present invention. Depicted are various types ofupper flex contacts42, various types oflower flex contacts44, signal traces76, andVDD plane78 as well as previously describedvias66, off-pad vias74, and enablevias70 and68. FIG. 13 illustratesupper flex contacts42A connected bytraces76 tolower flex contacts44A.VDD plane78 provides a voltage plane at the level of secondconductive layer58.Lower flex contacts44C andupper flex contacts42C connectlower CSP14 andupper CSP12, respectively, toVDD plane78.Lower flex contact44D is shown with enable via70 described earlier. Correspondingupper flex contact42D is connected tolower flex contact44D through enablevias70 and68 that are connected to each other through earlier described enabletrace72 at the firstconductive layer54 level offlex32.
• FIG. 14 depicts second[0067]outer layer52 offlex30.Windows62 are identified. Those of skill will recognize thatmodule contacts36 pass throughwindows62 to contact appropriatelower flex contacts44. Whenflex30 is partially wrapped aboutlateral side20 oflower CSP14, a portion of secondouter layer52 becomes the upper-most layer offlex30 from the perspective ofupper CSP12.CSP contacts24 ofupper CSP12 pass throughwindows64 to reach secondconductive layer58 and make contact with appropriate ones ofupper flex contacts42 located at that level. FIG. 15 reflects secondouter layer52 offlex32 andexhibits windows64 and62.Module contacts36 pass throughwindows62 to contact appropriatelower flex contacts44.CSP contacts24 ofupper CSP12 pass throughwindows64 to reach secondconductive layer58 and make contact with appropriate ones ofupper flex contacts42 located at that level.
• FIG. 16 depicts an alternative preferred embodiment of the present invention showing module.[0068]10. Those of skill will recognize that the embodiment depicted in FIG. 16 differs from that in FIG. 2 by the presence ofmodule contacts36E.Module contacts36E supply a part of the datapath ofmodule10 and may provide a facility for differential enablement of the constituent CSPs. Amodule contact36E not employed in wide datapath provision may provide a contact point to supply an enable signal to differentially enableupper CSP12 orlower CSP14.
• In a[0069]wide datapath module10, the data paths of the constituentupper CSP12 andlower CSP14 are combined to provide amodule10 that expresses a module datapath that is twice the width of the datapaths of the constituent CSPs in a two-high module10. The preferred method of combination is concatenation, but other combinations may be employed to combine the datapaths ofCSPs12 and14 on the array ofmodule contacts36 and36E.
• As an example, FIGS. 17, 18, and[0070]19 are provided to illustrate using addedmodule contacts36E in alternative embodiments of the present invention to provide wider datapaths formodule10 than are present inconstituent CSPs12 and14. FIG. 17 illustrates a JEDEC pinout for DDR-II FBGA packages. FIG. 18 illustrates the pinout provided bymodule contacts36 and36E of amodule10 expressing an 8-bit wide datapath.Module10 is devised in accordance with the present invention and is, in the exemplar embodiment, comprised of anupper CSP12 andlower CSP14 that are DDR-II-compliant in timing, but each of which are only 4 bits wide in datapath. As will be recognized, themodule10 mapped in FIG. 18 expresses an 8-bit wide datapath. For example, FIG. 18 depicts DQ pins differentiated in source between upper CSP12 (“top”) and lower CSP14 (“bot”) to aggregate to 8-bits. FIG. 19 illustrates the pinout provided bymodule contacts36 and36E ofmodule10 expressing a 16-bit wide datapath.Module10 is devised in accordance with the present invention and is, in this exemplar embodiment, comprised of anupper CSP12 andlower CSP14 that are DDR-II-compliant in timing, but each of which are only 8-bits wide in datapath. Those of skill in the art will recognize that the wide datapath embodiment may be employed with any of a variety of CSPs available in the field and such CSPs need not be DDR compliant.
• FIG. 20 illustrates a typical pinout of a memory circuit provided as a CSP and useable in the present invention. Individual array positions are identified by the JEDEC convention of numbered columns and alphabetic rows. The central area (e.g., A[0071]3-A6; B3-B6; etc.) is unpopulated.CSP contacts24 are present at the locations that are identified by alpha-numeric identifiers such as, for example, A3, shown as anexample CSP contact24. FIG. 21 depictssecond metal layer58 offlex30 in an alternative embodiment of the invention in whichmodule10 expresses a datapath wider than that expressed by either of the theconstituent CSPs12 and14.Lower flex contacts44E are not contacted byCSP contacts24 oflower CSP14, but are contacted bymodule contacts36E to provide, with selectedmodule contacts36, a datapath formodule10 that is 2 n-bits in width where the datapaths ofCSPs12 and14 have a width of n-bits. As shown in FIG. 21,lower flex contacts44E are connected toupper flex contacts42E. As shown in earlier FIG. 14,windows62 pass through secondouter layer52. In the alternative preferred embodiment for which secondconductive layer58 is shown in FIG. 21,module contacts36 and36E pass throughwindows62 in secondouter layer52 offlex circuit30, to contact appropriatelower flex contacts44.
• FIG. 22 illustrates[0072]second metal layer58 offlex32 in an alternative embodiment of the invention in whichmodule10 expresses a datapath wider than that expressed by either of the theconstituent CSPs12 and14.Lower flex contacts44E are not contacted byCSP contacts24 oflower CSP14, but are contacted bymodule contacts36E to provide, with selectedmodule contacts36, a datapath formodule10 that is 2 n-bits in width where the datapaths ofCSPs12 and14 have a width of n-bits. As shown in FIG. 22,lower flex contacts44E are connected toupper flex contacts42E. As shown in earlier FIG. 14,windows62 pass through secondouter layer52. In the alternative preferred embodiment for which secondconductive layer58 is shown in FIG. 22,module contacts36 pass throughwindows62 in secondouter layer52 offlex circuit32, to contact appropriatelower flex contacts44.
• In particular, in the embodiment depicted in FIGS. 21 and 22,[0073]module contacts36Econtact flex contacts44E and44EE. Those of skill will recognize thatlower flex contacts44E are, in the depicted embodiment, eight (8) in number and that there is another lower flex contacts identified by reference44EE shown on FIG. 21. Lower flex contact44EE is contacted by one of themodule contacts36E to provide differential enablement between upper and lower CSPs. Those of skill will recognize thatlower flex contacts44E are connected to correspondingupper flex contacts42E.CSP contacts24 ofupper CSP12 that convey data are in contact withupper flex contacts42E. Consequently, the datapaths of bothupper CSP12 andlower CSP14 are combined to provide a wide datapath onmodule10. With the depicted connections of FIGS. 21 and 22,lower flex contacts44E offlex circuits30 and32 convey tomodule contacts36E, the datapath ofupper CSP12, while otherlower flex contacts44 convey the datapath oflower CSP14 tomodule contacts36 to providemodule10 with a module datapath that is the combination of the datapath ofupper CSP12 andlower CSP14. In the depicted particular embodiment of FIGS. 21 and 22,module10 expresses a 16-bit datapath andCSP12 andCSP14 each express an 8-bit datapath.
• Although the present invention has been described in detail, it will be apparent to those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.[0074]

Claims (40)

1. A high-density circuit module comprising:

a first flex circuit having first and second conductive layers between which conductive layers is an intermediate layer, the first and second conductive layers being interior to first and second outer layers of the first flex circuit, the second conductive layer having upper and lower flex contacts, the upper flex contacts being accessible through second windows through the second outer layer and the lower flex contacts being accessible through first windows through the first outer layer, the first conductive layer and the intermediate layer, the lower flex contacts being further accessible through module contact windows through the second outer layer;

a second flex circuit having first and second conductive layers between which conductive layers is an intermediate layer, the first and second conductive layers being interior to first and second outer layers of the second flex circuit, the second conductive layer having upper and lower flex contacts, the upper flex contacts being accessible through second windows through the second outer layer and the lower flex contacts being accessible through first windows through the first outer layer and the first conductive layer and the intermediate layer, the lower flex contacts being further accessible through module contact windows through the second outer layer;

a first integrated circuit having first and second lateral sides and upper and lower major surfaces with contacts along the lower major surface, the contacts of the first integrated circuit connected to the lower flex contacts of the first and second flex circuits;

a second integrated circuit having first and second lateral sides and upper and lower major surfaces with contacts along the lower major surface, the contacts of the second integrated circuit connected to the upper flex contacts of the first and second flex circuits, the first and second flex circuits being disposed about the first and second lateral sides, respectively, of the first integrated circuit to place the upper flex contacts of the first and second flex circuits between the first and second integrated circuits; and

a set of module contacts passing through the module contact windows to contact the lower flex contacts of the first and second flex circuits.

2. The high-density circuit module ofclaim 1 in which a ground set of the upper flex contacts and a ground set of the lower flex contacts connect ground-conductive contacts of the first and second integrated circuits to the first conductive layer.

3. The high-density circuit module ofclaim 2 in which:

a data set of the contacts of the first integrated circuit express an n-bit datapath;

a data set of the contacts of the second integrated circuit express an n-bit datapath; and

a data set of module contacts comprised of selected ones of the set of module contacts and a set of supplemental module contacts, and the data set of module contacts expresses a 2 n-bit datapath that combines the n-bit datapath of the data set of the contacts of the first integrated circuit and the n-bit datapath of the data set of the contacts of the second integrated circuit.

4. The high-density circuit module ofclaim 2 in which the ground set of the upper flex contacts and the ground set of the lower flex contacts are connected to the first conductive layer with vias.

5. The high-density circuit module ofclaim 4 in which the ground set of lower flex contacts are connected to the first conductive layer with vias that are off-pad.

6. The high-density circuit module of claims1 or2 in which the second conductive layer comprises at least one demarked voltage plane and a voltage set of the upper flex contacts and a voltage set of the lower flex contacts connect voltage conductive contacts of the first and second integrated circuits to one of the at least one voltage planes.

7. A flex circuit connecting two integrated circuits in a high-density circuit module, the flex circuit comprising;

first and second outer layers; and

first and second conductive layers, between which there is an intermediate layer, the first and second conductive layers and the intermediate layer being interior to the first and second outer layers, the second conductive layer having demarked first and second flex contacts, the first flex contacts being accessible through first windows through the second outer layer and the second flex contacts being accessible through second windows through the first outer layer, the first conductive layer, and the intermediate layer, the first flex contacts in electrical connection with one of the two integrated circuits and the second flex contacts in electrical connection with the other of the two integrated circuits.

8. The flex circuit ofclaim 7 in which the second flex contacts are accessible through module windows through the second outer layer.

9. The flex circuit ofclaim 7 in which the first and second conductive layers are metal.

10. The flex circuit ofclaim 7 in which selected ones of the first flex contacts are connected to selected ones of the second flex contacts.

11. The flex circuit ofclaim 7 in which selected ones of the first flex contacts and selected ones of the second flex contacts are connected to the first conductive layer.

12. The flex circuit ofclaim 9 in which the metal of the first and second conductive layers is alloy 110.

13. The flex circuit ofclaim 10 in which the connected selected ones of the first and second flex contacts are connected with traces.

14. The flex circuit ofclaim 11 in which selected ones of the first flex contacts and selected ones of the second flex contacts are connected to the first conductive layer with vias.

15. The flex circuit ofclaim 14 in which selected ones of the first flex contacts are connected to the first conductive layer with on-pad vias.

16. The flex circuit ofclaim 14 in which selected ones of the second flex contacts are connected to the first conductive layer with off-pad vias.

17. A high-density circuit module that employs the flex circuit ofclaim 7 to connect selected contacts of a first integrated circuit to selected contacts of a second integrated circuit, the first and second integrated circuits being in stacked conjunction with each other.

18. A high-density circuit module comprising:

a first flex circuit devised in accordance withclaim 7;

a second flex circuit devised in accordance withclaim 7;

a first integrated circuit having contacts, the contacts of the first integrated circuit being connected to the first flex contacts of each of the first and second flex circuits;

a second integrated circuit having contacts, the first integrated circuit being disposed above the second integrated circuit and the contacts of the second integrated circuit being connected to the second flex contacts of each of the first and second flex circuits; and

a set of module contacts in contact with the second flex contacts.

19. A high-density circuit module comprising:

a first flex circuit devised in accordance withclaim 7;

a second flex circuit devised in accordance withclaim 7;

a first integrated circuit having contacts, the contacts of the first integrated circuit being connected to the second flex contacts of each of the first and second flex circuits;

a second integrated circuit having contacts, the first integrated circuit being disposed above the second integrated circuit and the contacts of the second integrated circuit being connected to the first flex contacts of each of the first and second flex circuits; and

a set of module contacts in contact with the first flex contacts.

20. The high-density module of claims18 or19 in which for the first and second flex circuits, the first conductive layer conveys ground, and a conductive plane of the second conductive layer conveys voltage and the intermediate layer is insulative to create a distributed capacitor in the first and second flex circuits.

21. A high-density circuit module comprising:

a first integrated circuit having an n-bit wide datapath;

a second integrated circuit having an n-bit wide datapath, the first integrated circuit being disposed above the first integrated circuit;

a pair of flex circuits that collectively combine the n-bit wide datapaths of the first and second integrated circuits to provide on a set of module contacts, a module datapath that is 2 n-bits wide.

22. The high-density circuit module ofclaim 21 in which the flex circuits that comprise the pair of flex circuits are each iterations of the flex circuit ofclaim 7.

23. A high-density circuit module comprising:

a first integrated circuit having first and second lateral sides and upper and lower major surfaces and a set of contacts along the lower major surface;

a second integrated circuit having first and second lateral sides and upper and lower major surfaces and a set of contacts along the lower major surface, the first integrated circuit being disposed above the second integrated circuit;

a pair of flex circuits, each of which pair having a first conductive layer and a second conductive layer, both said conductive layers being interior to first and second outer layers, and demarcated at the second conductive layer of each flex circuit there being upper and lower flex contacts, the upper flex contacts being connected to the contacts of the first integrated circuit and the lower flex contacts being connected to the contacts of the second integrated circuit and a set of module contacts.

24. The high-density circuit module ofclaim 23 in which:

a chip-enable module contact is connected to an enable lower flex contact that is connected to a chip select contact of the first integrated circuit.

25. The high-density circuit module ofclaim 24 in which the connection between the enable lower flex contact and the chip select contact of the first integrated circuit is through an enable connection at the first conductive layer.

26. The high-density circuit module ofclaim 23 in which a first one of the flex circuit pair is partially wrapped about the first lateral side of the second integrated circuit and a second one of the flex circuit pair is partially wrapped about the second lateral side of the second integrated circuit to dispose the upper flex contacts above the upper major surface of the second integrated circuit and beneath the lower major surface of the first integrated circuit.

27. The high-density circuit module ofclaim 26 in which there is thermally conductive material between the first and second integrated circuits.

28. The high-density circuit module ofclaim 26 in which the first integrated circuit expresses an n-bit datapath and the second integrated circuit expresses an n-bit datapath, each of the flex circuits of the flex circuit pair having supplemental lower flex contacts which, in combination with the lower flex contacts, provide connection for the set of module contacts and a set of supplemental module contacts to express a 2 n-bit module datapath that combines the n-bit datapath expressed by the first integrated circuit and the n-bit datapath expressed by the second integrated circuit.

29. A high-density circuit module comprising:

a first integrated circuit having first and second major surfaces with a plurality of contacts along the first major surface;

a second integrated circuit having first and second major surfaces with a plurality of contacts along the first major surface, the first integrated circuit being disposed above the second integrated circuit;

a pair of flex circuits, each of which has an outer layer and an inner layer and first and second conductive layers between which conductive layers there is an intermediate layer, the second conductive layer having demarked a plurality of upper and lower flex contacts and a voltage plane, a first set of said plurality of upper and lower flex contacts being connected to the voltage plane, a second set of said plurality of upper and lower flex contacts being connected to the first conductive layer, and a third set of said plurality of upper and lower flex contacts being comprised of selected ones of upper flex contacts that are connected to corresponding selected ones of lower flex contacts, the plurality of contacts of the first integrated circuit being connected to the upper flex contacts and the plurality of contacts of the second integrated circuit being connected to the lower flex contacts; and

a set of module contacts in contact with the lower flex contacts.

30. The high density circuit module ofclaim 29 in which the first and second integrated circuits are memory circuits.

31. The high-density circuit module ofclaim 29 in which:

a data set of the plurality of contacts of the first integrated circuit express an n-bit datapath;

a data set of the plurality of contacts of the second integrated circuit express an n-bit datapath:

each of the flex circuits of the pair of flex circuits has supplemental lower flex contacts which, in combination with the lower flex contacts, provide connection for the set of module contacts and a set of supplemental module contacts to express a 2 n-bit module datapath that combines the n-bit datapath expressed by the data set of the plurality of contacts of the first integrated circuit and the n-bit datapath expressed by the data set of the plurality of contacts of the second integrated circuit.

32. The high-density circuit module ofclaim 29 in which the second set of said plurality of upper and lower flex contacts is connected to the first conductive layer with vias that pass through the intermediate layer.

33. The high-density circuit module ofclaim 32 in which the second set of said plurality of upper and lower flex contacts is comprised of upper flex contacts connected to the first conductive layer with on-pad vias.

34. The high-density circuit module ofclaim 32 in which the second set of said plurality of upper and lower flex contacts is comprised of lower flex contacts connected to the first conductive layer with off-pad vias.

35. The high-density circuit module ofclaim 29 in which the contacts of the second integrated circuit are spherical in shape and have a contact diameter and the module contacts are spherical in shape and have a module contact diameter.

36. The high-density circuit module ofclaim 35 mounted on a board and the first major surface of the second integrated circuit is offset from the board by a distance which is at least as great as the sum of the contact diameter and the module contact diameter.

37. The high-density circuit module of claims29,30,31 or36 in which between the first and second integrated circuits there is a thermally conductive layer.

38. The high-density circuit module ofclaim 37 in which the thermally conductive layer is a thermally conductive adhesive that contacts, but does not cover the entirety of the second major surface of the second integrated circuit.

39. A high-density circuit module comprising:

a first integrated circuit having a set of first contacts;

a second integrated circuit having a set of second contacts, the first integrated circuit being disposed above the second integrated circuit;

a pair of flex circuits, each of which flex circuits of the pair has first and second outer layers and a first conductive layer and a second conductive layer between which conductive layers there is an intermediate layer, the first and second conductive layers and the intermediate layer each being interior to the first and second outer layers, each of the flex circuits having first and second sets of flex contacts demarked at the first conductive layer, the first set of flex contacts being accessible through first windows that pass through the second outer layer, the second conductive layer and the intermediate layer, the second set of flex contacts being accessible through second windows that pass through the first outer layer and accessible through module contact windows that pass through the second outer layer, the second conductive layer and the intermediate layer, the second contacts of the second integrated circuit being connected to the second set of flex contacts and the first contacts of the first integrated circuit being connected to the first set of flex contacts; and

a set of module contacts that are in contact with the second set of flex contacts.

40. A high-density circuit module comprising:

a first integrated circuit having a set of first contacts;

a second integrated circuit having a set of second contacts, the first integrated circuit being disposed above the second integrated circuit;

a pair of flex circuits, each of which flex circuits of the pair has first and second outer layers and a first conductive layer and a second conductive layer between which conductive layers there is an intermediate layer, the first and second conductive layers and the intermediate layer each being interior to the first and second outer layers, each of the flex circuits having first and second sets of flex contacts demarked at the first conductive layer, the first set of flex contacts being accessible through first windows that pass through the first outer layer, the second set of flex contacts being accessible through second windows that pass through the second outer layer, the second conductive layer and the intermediate layer and the second set of flex contacts being accessible through module contact windows that pass through the first outer layer, the second contacts of the second integrated circuit being connected to the second set of flex contacts and the first contacts of the first integrated circuit being connected to the first set of contacts; and

a set of module contacts that are in contact with the second set of flex contacts.

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