US20030116835A1 - Memory-module and a method of manufacturing the same - Google Patents
Memory-module and a method of manufacturing the sameDownload PDFInfo
- Publication number
- US20030116835A1 US20030116835A1US10/029,979US2997901AUS2003116835A1US 20030116835 A1US20030116835 A1US 20030116835A1US 2997901 AUS2997901 AUS 2997901AUS 2003116835 A1US2003116835 A1US 2003116835A1
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- semiconductor devices
- protruded
- module
- terminal semiconductor
- memory
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Definitions
- the present inventionrelates to technology for manufacturing a semiconductor and, particularly, to technology that can be effectively applied to highly densely mounting the semiconductor chips on a memory-module.
- a memory-moduleis one of the module products mounting a plurality of semiconductor devices.
- the memory-moduleincludes a plurality of semiconductor devices having memory chips that are mounted on one surface or on both the front and back surfaces of a module board.
- the memory-modulemounts the memory by being mounted on a mother board provided in the personal computer or the work station with each module as a unit.
- SMDsurface mount device
- TSOPthin small outline package
- TCPtape carrier package
- Japanese Patent Laid-Open No. 209368/1998discloses a CPU (central processing unit) module
- Japanese Patent Laid-Open No. 258466/1989discloses a memory-module mounting SMD parts having a DRAM (dynamic random access memory) chip
- Japanese Patent Laid-Open No. 86492/1995discloses technology for applying an underfiller resin in the MCM (multi-chip module).
- the SMD parts to be mounted on the above-mentioned conventional memory-modulehave a large package size compared with the chip size due to the package body (semiconductor device body) that is sealed and the outer leads.
- the object of the present inventionis to provide a memory-module that offers an increased module capacity as a result of enhancing the density for mounting the semiconductor chips and is capable of coping with a high-speed bus, and a method of manufacturing the same.
- the memory-module of the present inventioncomprises protruded terminal semiconductor devices having protruded terminals as external terminals, mounted via the protruded terminals, and are provided with wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes of semiconductor chips; lead terminal semiconductor devices having outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips; and a module board supporting the protruded terminal semiconductor devices and the lead terminal semiconductor devices; wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices are mounted in a mixed manner on the module board.
- the memory-module of the inventioncomprises protruded terminal semiconductor devices of a chip size having protruded terminals as external terminals, mounted via the protruded terminals, and are provided with rewirings which are wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes in the areas of semiconductor chips; lead terminal semiconductor devices having outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips; and a module board supporting the protruded terminal semiconductor devices and the lead terminal semiconductor devices; wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices are mounted in a mixed manner on the module board.
- the semiconductor chipscan be mounted requiring the least areas, making it possible to increase the density for mounting the semiconductor chips.
- the method of manufacturing a memory-modulecomprises a step for preparing protruded terminal semiconductor devices having protruded terminals as external terminals, and wiring portions for expanding the pitch of the protruded terminals to be wider than the pitch of the bonding electrodes of semiconductor chips; a step for preparing lead terminal semiconductor devices having outer leads which are the external terminals electrically connected to the bonding electrodes of the semiconductor chips; a step for arranging the protruded terminal semiconductor devices and the lead terminal semiconductor devices on a module board; and a step for simultaneously reflowing the protruded terminal semiconductor devices and the lead terminal semiconductor devices to mount them on the module board; wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices are mounted in a mixed manner on the module board.
- the method of manufacturing a memory-module of the present inventioncomprises a step for preparing protruded terminal semiconductor devices of a chip size having protruded terminals as external terminals, and rewirings which are wiring portions for expanding the pitch of the protruded terminals to be wider than the pitch of the bonding electrodes in the areas of semiconductor chips; a step for preparing lead terminal semiconductor devices having outer leads which are external terminals electrically connected to the bonding electrodes of the semiconductor chips; a step for arranging the protruded terminal semiconductor devices and the lead terminal semiconductor devices on a module board; and a step for simultaneously reflowing the protruded terminal semiconductor devices and the lead terminal semiconductor devices to mount them on the module board; wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices are mounted in a mixed manner on the module board.
- FIGS. 1A, 1B and 1 Care diagrams illustrating the structure of a memory-module according to an embodiment 1 of the present invention, wherein FIG. 1A is a plan view, FIG. 1B is a side view, and FIG. 1C is a sectional view along the A-A section of FIG. 1A;
- FIG. 2is an enlarged partial sectional view illustrating, on an enlarged scale, a portion B in the sectional view of FIG. 1C;
- FIG. 3is a view of block circuits of the memory-module shown in FIG. 1;
- FIG. 4is a perspective view illustrating the appearance of the structure of a wafer process package (protruded terminal semiconductor device) mounted on the memory-module shown in FIG. 1;
- FIGS. 5A and 5Bare diagrams illustrating an SMD (lead terminal semiconductor device) mounted on the memory-module shown in FIG. 1 and the structure of a wafer process package, wherein FIG. 5A is a plan view of the SMD and FIG. 5B is a plan view of the wafer process package;
- FIG. 6is a process flow illustrating the steps for manufacturing the wafer process package mounted on the memory-module shown in FIG. 1;
- FIGS. 7A, 7B, 7 C, 7 D, 7 E and 7 Fare enlarged partial sectional views illustrating the structure of the semiconductor wafer corresponding to the major steps in the process flow shown in FIG. 6;
- FIG. 8is a basic mounting flow illustrating the procedure for mounting the wafer process package and the SMD on the module board so as to be mounted on the memory-module shown in FIG. 1;
- FIG. 9is a mounting flow illustrating the procedure for mounting the wafer process package on the module board so as to be mounted on the memory-module shown in FIG. 1;
- FIG. 10is an enlarged partial perspective view illustrating a method of applying an underfiller resin onto the wafer process package mounted on the memory-module shown in FIG. 1;
- FIGS. 11A, 11B, 11 C, 11 D, 11 E, 11 F, 11 G and 11 Hare views illustrating the permeation of the underfiller resin that is applied as shown in FIG. 10, and wherein FIGS. 11A, 11C, 11 E and 11 G are perspective views and FIGS. 11B, 11D, 11 F and 11 H are plan views showing the semiconductor chip in a see-through manner;
- FIGS. 12is a plan view illustrating a modified structure of the memory-module of the embodiment 1 of the present invention.
- FIG. 13is a plan view illustrating a modified structure of the memory-module of the embodiment 1 of the present invention.
- FIGS. 14A, 14B, 14 C, 14 D, 14 E, 14 F, 14 G and 14 Hare views illustrating the permeation of the underfiller resin that is applied according to a modified example of the embodiment 1 of the invention, and wherein FIGS. 14A, 14C, 14 E and 14 G are perspective views and FIGS. 14B, 14D, 14 F and 14 H are plan views illustrating a semiconductor chip in a see-through manner;
- FIGS. 15A and 15Bare view illustrating a modified structure of the memory-module according to the embodiment 1 of the present invention, wherein FIG. 15A is a plan view and FIG. 15B is a side view;
- FIG. 16is a side view illustrating the memory-module of FIG. 15 in a warped state
- FIG. 17is a plan view illustrating a modified structure of the memory-module according to the embodiment 1 of the present invention.
- FIG. 18is a side view illustrating the memory-module of FIG. 17 in a warped state
- FIG. 19is a plan view illustrating the structure of the memory-module according to an embodiment 2 of the present invention.
- FIGS. 20A and 20Bare views illustrating the structure of a memory-module according to an embodiment 3 of the present invention, wherein FIG. 20A is a plan view and FIG. 20B is a side view;
- FIG. 21is a diagram of block circuits of the memory-module shown in FIG. 20;
- FIG. 22is a bottom view illustrating the structure of a wafer process package (protruded terminal semiconductor device) mounted on the memory-module shown in FIG. 20;
- FIG. 23is a diagram of wirings on the side of the board illustrating an example of wirings on the module board at a portion C in the memory-module shown in FIG. 20;
- FIG. 24is a diagram of wirings illustrating a modified example of the bump arrangement on the wafer process package in the memory-module according to the embodiment 3 of the invention and a modified example of the wirings on the side of the board corresponding thereto;
- FIG. 25is a diagram of wirings illustrating a modified example of the bump arrangement on the wafer process package in the memory-module according to the embodiment 3 of the invention and a modified example of the wirings on the side of the board corresponding thereto;
- FIG. 26is a diagram of wirings illustrating a modified example of the bump arrangement on the wafer process package in the memory-module according to the embodiment 3 of the invention and a modified example of the wirings on the side of the board corresponding thereto;
- FIG. 27is a diagram of bump arrangement and wirings illustrating a further modified example of the bump arrangement on the wafer process package and of the wirings on the side of the board shown in FIG. 25;
- FIGS. 28A, 28B and 28 Care views illustrating the structure of a CSP which is a modified example of the protruded terminal semiconductor device mounted on the memory-module of the present invention, wherein FIG. 28A is a plan view, FIG. 28B is a sectional view and FIG. 28C is a bottom view;
- FIGS. 29A and 29Bare views illustrating the structure of a BGA of the chip face-up mounting system which is a modified example of the protruded terminal semiconductor device mounted on the memory-module of the present invention, wherein FIG. 29A is a perspective view illustrating the appearance and FIG. 29 B is a sectional view; and
- FIGS. 30A, 30B and 30 Care views illustrating the structure of the BGA of the chip face-down mounting system which is a modified example of the protruded terminal semiconductor device mounted on the memory-module of the present invention, wherein FIG. 30A is a plan view, FIG. 30B is a sectional view and FIG. 30C is a bottom view.
- FIG. 1is a diagram illustrating the structure of a memory-module according to an embodiment 1 of the present invention, wherein FIG. 1A is a plan view, FIG. 1B is a side view and FIG. 1C is a sectional view along the A-A section of FIG. 1A, FIG. 2 is an enlarged partial sectional view illustrating, on an enlarged scale, a portion B in the sectional view of FIG. 1C, FIG. 3 is a view of block circuits of the memory-module shown in FIG. 1, FIG. 4 is a perspective view illustrating the appearance of the structure of a wafer process package (protruded terminal semiconductor device) mounted on the memory-module shown in FIG. 1, FIG.
- a wafer process packageprotruded terminal semiconductor device
- FIG. 5is a diagram illustrating an SMD (surface mount-type semiconductor device having lead terminals, which is hereinafter referred to as lead terminal semiconductor device) mounted on the memory-module shown in FIG. 1 and the structure of a wafer process package, wherein FIG. 5A is a plan view of the SMD and FIG. 5B is a plan view of the wafer process package, FIG. 6 is a process flow illustrating the steps for manufacturing the wafer process package mounted on the memory-module shown in FIG. 1, FIGS. 7A, 7B, 7 C, 7 D, 7 E and 7 F are enlarged partial sectional views illustrating the structure of the semiconductor wafer corresponding to the major steps in the process flow shown in FIG. 6, FIG.
- SMDsurface mount-type semiconductor device having lead terminals, which is hereinafter referred to as lead terminal semiconductor device
- FIG. 8is a basic mounting flow illustrating the procedure for mounting the wafer process package and the SMD on the module board so as to be mounted on the memory-module shown in FIG. 1
- FIG. 9is a mounting flow illustrating the procedure for mounting the wafer process package on the module board so as to be mounted on the memory-module shown in FIG. 1
- FIG. 10is an enlarged partial perspective view illustrating a method of applying an underfiller resin onto the wafer process package mounted on the memory-module shown in FIG. 1
- FIGS. 11A, 11C, 11 E and 11 Gare perspective views illustrating the permeation of the underfiller resin that is applied as shown in FIG. 10
- FIGS. 11B, 11D, 11 F and 11 Hare plan views showing the semiconductor chip in a see-through manner, FIGS.
- FIGS. 12 and 13are plan views illustrating the modified structures of the memory-module of the embodiment 1 of the present invention
- FIGS. 14A, 14C, 14 E and 14 Gare perspective views illustrating the permeation of the underfiller resin that is applied according to modified examples of the embodiment 1 of the invention
- FIGS. 14B, 14D, 14 F and 14 Hare plan views illustrating a semiconductor chip in a see-through manner
- FIG. 15is a view illustrating a modified structure of the memory-module according to the embodiment 1 of the present invention, wherein FIG. 15A is a plan view and FIG. 15B is a side view
- FIG. 16is a side view illustrating the memory-module of FIG. 15 in a warped state
- FIG. 17is a plan view illustrating a modified structure of the memory-module according to the embodiment 1 of the present invention
- FIG. 18is a side view illustrating the memory-module of FIG. 17 in a warped state.
- a memory-module 100 of the embodiment 1 shown in FIG. 1comprises protruded terminal semiconductor devices having protruded terminals as external terminals, mounted via the protruded terminals and having wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes la of the semiconductor chips 1 ; TSOPs (thin small outline packages) which are lead terminal semiconductor devices 20 having semiconductor chips 1 , outer leads 21 as the external terminals and are mounted via the outer leads 21 which are electrically connected to the bonding electrodes 1 a of the semiconductor chips 1 ; and a module board 2 for supporting the protruded terminal semiconductor devices and TSOPs 20 ; wherein the protruded terminal semiconductor devices and the TSOPs 20 are mounted in a mixed manner on the module board 2 by the simultaneous reflowing.
- TSOPsthin small outline packages
- the protruded terminal semiconductor devicehas a plurality of bump electrodes 11 (protruded terminals) that serve as the external terminals arranged in an area of a package body 13 (semiconductor device body), and wiring portions for expanding the pitch among the bump electrodes 11 to be wider than the pitch among the bonding electrodes 1 a of the semiconductor chip 1 .
- the lead terminal semiconductor devicehas a plurality of outer leads 21 serving as the external terminals that are arranged protruding from the package body 22 (semiconductor device body).
- the bonding electrodes 1 a of the semiconductor chip 1are formed by using, for example, aluminum or the like, and are electrically connected to the bonding wires when the wires are to be bonded.
- the external terminals of the protruded terminal semiconductor device and of the lead terminal semiconductor deviceare electrically connected to the connection electrodes on the side of the module board 2 when the semiconductor devices are mounted on the mounting board such as the module board 2 .
- the embodiment 1deals with the case where the protruded terminal semiconductor device is a wafer process package (hereinafter abbreviated as WPP) 10 which is a small semiconductor device of a chip size.
- WPPwafer process package
- the memory-module 100 of the embodiment 1includes WPPs 10 which are the protruded terminal semiconductor devices of a chip size, TSOPs 20 which are SMD (surface mount type package) parts and are lead terminal semiconductor devices, and an EEPROM (electrically erasable programmable read-only memory) 5 which is a nonvolatile read-only memory as an example of another lead terminal semiconductor device, that are mounted in a mixed manner on the module board 2 .
- WPPs 10which are the protruded terminal semiconductor devices of a chip size
- TSOPs 20which are SMD (surface mount type package) parts and are lead terminal semiconductor devices
- an EEPROM (electrically erasable programmable read-only memory) 5which is a nonvolatile read-only memory as an example of another lead terminal semiconductor device, that are mounted in a mixed manner on the module board 2 .
- the WPP 10is a protruded terminal semiconductor device having bump electrodes 11 which are the protruded terminals serving as the external terminals, and is mounted on the module board 2 via bump electrodes 11 , and is provided with rewirings 12 which are wiring portions for expanding the pitch among the bump electrodes 11 to be wider than the pitch among the bonding electrodes 1 a in an area of the semiconductor chip 1 .
- the bump electrodes 11 used for the WPP 10have little dispersion in the height, decreasing percent defective when it is mounted on the board and, hence, improve the mounting yield. Besides, the bump electrodes 11 have a mounting height of about 0.13 mm, which makes it possible to decrease the mounting height.
- capacitors 3on the memory-module 100 are further mounted capacitors 3 , small surface-attached resistors 4 and other electronic parts in addition to the WPPs 10 , TSOPS 20 and EEPROM 5 .
- the memory-module 100 of the embodiment 1includes 18 WPPs 10 , two TSOPs 20 , 18 capacitors 3 , 36 small surface-attached resistors 4 and one EEPROM 5 that are mounted on either the front surface or the back surface thereof, and 18 WPPs 10 that are mounted on the surface on the opposite side thereof.
- the WPPs 10in a total number of 18 in a sequence on both sides of the two TSOPs 20 (ten on one side and eight on the other side with the TSOPs 20 being sandwiched therebetween) on one surface of the module board 2 .
- the one (TSOP 20 arranged on the upper side in FIG. 1)is a PLL (phase-locked loop) 6 which is a frequency control means and the other one (TSOP 20 arranged on the lower side in FIG. 1) is a register 8 having a register function.
- PLLphase-locked loop
- both the PLL 6 and the register 8are the lead terminal semiconductor devices.
- Each capacitor 3is arranged to correspond to each WPP 10 close thereto.
- a total of 36 small surface-attached resistors 4are arranged in sequence; i.e., two for each WPP 10 .
- the small surface-attached resistors 4are provided to correspond to the I/Os of the memory-module 100 .
- the memory-module 100 of the embodiment 1there are provided 36 I/Os on one surface and, hence, the surface-attached resistors 4 are mounted in a number of 36.
- the small surface-attached resistors 4 of the number of 36are arranged in a sequence nearly along and near the connection terminals 2 a which are the external terminals of the module board 2 .
- the TSOPs 20 and the WPPs 10are mounted by the simultaneous reflowing. As shown in FIG. 2, however, the WPP 10 is sealed with the underfiller resin after the reflow, so that a sealing portion 14 is formed.
- the surrounding of the bump electrodes 11 between the package body 13 of WPP 10 and the module board 2is sealed with a resin thereby to form the sealed portion 14 .
- the memory-module 100 shown in FIG. 1uses the WPPs 10 as DRAMs and further uses the module board 2 of a bus of a width of 72 bits with error code correction.
- the memory-module 100mounts a total of 36 DRAMs (WPPs 10 ) on both the front and back surfaces of the module board 2 .
- the DRAMhas, for example, 64 megabits (16 M ⁇ 4)
- the DRAM modulehas a constitution of 16 words ⁇ 72 bits ⁇ 2 banks.
- FIG. 3is a diagram of block circuits of the memory-module 100 shown in FIG. 1, i.e., the diagram of block circuits of the DRAM module of the constitution of 16 words ⁇ 72 bits ⁇ 2 banks.
- the RS0 system and the RS2 system of the bank 1operate simultaneously, and the RS1 system and the RS3 system of the bank 2 operate simultaneously.
- the bank 1 or the bank 2is selected by a register 8 .
- the bank 1is read out, the bank 2 is not read out.
- the bank 2is read out, the bank 1 is not read out.
- a terminal A (S 0 to S 3 ) of the register 8is connected to a chip select (CS) terminal of the DRAM (WPP 10 ) of either the bank 1 or the bank 2 .
- the bank that is selected by the register 8forms an input to the CS terminal of the selected semiconductor chip 1 .
- D 0 to D 35 of each chiprepresent the WPPs 10 of the number of 36 , and the [I (input)/O (output) 0 to I/O 3 ] terminals of each chip are connected to the connection terminals 2 a of the module board 2 as independent terminals.
- the I/Os used as dataconsist of 64 bits of from DQ 0 to DQ 63
- the I/Os used as checkconsist of 8 bits of from CB 0 to CB 7 .
- the sum of the twoconstitutes a two-bank constitution of 72 bits.
- [A 0 to A 11 ]are address inputs
- [DQ 0 to DQ 63 ]are data inputs/outputs
- [CB 0 to CB 7 ]are check bits (data inputs/outputs)
- [S 0 to S 3 ]are chip select inputs
- [RE]is a row enable (RAS) input
- [CE]is a column enable (CAS) input
- [W]is a write enable input
- [DQMB 0 to DQMB 7 ]are bite data masks
- [CK 0 to CK 3 ]are clock inputs
- [CKE 0 ]is a clock enable input
- [WP]is a write protection for serial PD
- [REGE]is a register enable
- [SDA]is a data input/output for serial PD
- [SCL]is a clock input for serial PD
- the bonding electrodes 1 a of the semiconductor chip 1 in the WPP 10are electrically connected to the solder bump electrodes 11 which are the external terminals through rewirings 12 .
- the bonding electrodes 1 a arranged at a narrow pitchare expanded by the rewirings 12 to a pitch of the bump electrodes 11 that are electrically connected thereto.
- the deviceis efficiently produced at a low cost compared with the small packages assembled by a method of production similar to that of manufacturing packages of the SMD (surface mount type) parts.
- FIG. 5illustrates the TSOP 20 which is an SMD part and the WPP 10 which is the protruded terminal semiconductor device of the chip size, from which a difference in the size can be comprehended.
- FIG. 5Ais a plan view of the TSOP 20 mounted on the memory-module 100 shown in FIG. 1
- FIG. 5Bis a plan view of the WPP 10 mounted on the memory-module 100 shown in FIG. 1.
- the WPP 10can be realized in a small size since it has neither the inner leads nor the outer leads 21 .
- the mounting areacan be greatly reduced as compared to when the TSOPs 20 that are formed by being individually treated are mounted.
- the mounting areacan be minimized so far as the semiconductor chips 1 are mounted and, hence, the module capacity can be greatly increased.
- the WPPs 10are mounted without using any special mounting device such as the flip chip bonder, and makes it possible to decrease the number of the steps for mounting.
- the WPPs 10can be mounted permitting the pitch among the bump electrodes 11 that are the external terminals to be expanded to be broader than the pitch of when the flip chips are mounted, enabling the wiring rule to be broadened on the module board 2 . This does not drive up the cost of the module board 2 , and makes it possible to realize the memory-module 100 of a highly dense mounted form suppressing the cost.
- the wiring lengths from the bonding electrodes 1 a of the semiconductor chip 1 to the bump electrodes 11 which are the external terminalsbecome shorter than the wiring lengths from the bonding electrodes 1 a to the ends of the outer leads 21 of the SMD part such as TSOP 20 , making it possible to transfer signals at a high speed.
- the WPPs 10are formed by treating the wafers in the preceding steps. In the subsequent steps, therefore, they are all treated in a unit of the wafer even in a step of forming the devices one by one.
- a reticle for exposure to lightmust be prepared for every kind of products.
- a material having general applicabilityis used for the semiconductor devices (packages) that are incorporated in the lead frames. Therefore, the products that are not produced in large quantity are better not in the form of the WPPs 10 .
- the devices that are better formed as WPPs 10are those chips produced maintaining a high yield and obtained in a large number per a wafer and, particularly, are those small memory devices.
- the devices that are not better in the form of WPPs 10are those chips produced maintaining a low yield and obtained in a small number per a wafer and, particularly, are those large chips, end devices or devices produced in small quantity. Further, when an ASIC (application specific integrated circuit) having many external terminals compared to the chip area, is obtained in the form of the WPP 10 , a sufficiently large pitch is not often maintained among the bump electrodes 11 . In this case, too, the package should be in a conventional form for easy mounting.
- ASICapplication specific integrated circuit
- the waferis subjected to a pre-treatment at step S 1 shown in FIG. 6.
- the bonding electrode lais exposed on the main surface of the silicon board 7 shown in FIG. 7A thereby to form an inorganic insulating protection film 7 a.
- a WPP first insulating layeris formed at step S 2 . That is, as shown in FIG. 7B, the first insulating layer 7 b of polyimide or fluorine-contained resin is formed on the inorganic insulating protection film 7 a of the silicon board 7 .
- a WPP rewiring layeris formed. That is, as shown in FIG. 7C, a rewiring 12 is formed on the first insulating layer 7 b being electrically connected to the bonding electrode 1 a.
- a WPP second insulating layeris formed. That is, as shown in FIG. 7D, a second insulating layer 7 d comprising polyimide or epoxy is formed on the rewiring 12 .
- a WPP-UBMunderbump metal
- a diffusion-preventing adhesion layer 7 cwhich is a UBM is formed being electrically connected to the rewiring 12 .
- step S 6the wafer is inspected (W-test). This is to inspect whether the wafer has been treated as contemplated relying on the electric characteristics by bringing a probe needle into contact with the electrode pad formed on a scribe area of the semiconductor wafer (silicon board 7 ).
- step S 7the silicon board 7 is inspected by using the probe (P-test 1). This is to detect defective portions by inspecting whether the semiconductor chip 1 electrically works properly by bringing the probe needle into contact with the bonding electrode 1 a of the silicon board 7 .
- step S 8the defective portions are relieved; i.e., laser blown fuses is executed. This is to relieve defective portions by cutting the fuse in a redundancy circuit by laser beam.
- testis effected by using probe (P-test 2). This is to make sure whether the defective portion relieved by the P-test 1 has been corrected.
- step S 10marking is effected on the back surface of the wafer to attach a predetermined mark to the back surface of the silicon board 7 .
- a bumpis formed at step S 11 . That is, as shown in FIG. 7F, a bump electrode 11 (protruded terminal) which is an external terminal of the WPP 10 is formed on the diffusion-preventing adhesion layer 7 c which is the UBM provided at an end drawn out from the bonding electrode 1 a on the rewiring 12 .
- the bump electrode 11is formed by, for example, a printing method.
- a metal mask corresponding to the bump-forming positionis disposed on the wafer (silicon board 7 ), a solder paste is applied, the metal mask is removed, followed by reflowing at one time to form the bump electrodes 11 at one time on the wafer.
- step S 12the semiconductor wafer, i.e., the silicon board 7 is cut by dicing, thereby to form the WPP 10 as shown in FIG. 4.
- step S 13the WPP 10 is subjected to the aging, i.e., to the burn-in (BI) testing.
- step S 14the single products are sorted out to select non-defective WPPs 10 .
- the BG stepis to decrease the height of the WPP 10 by decreasing the thickness of the silicon board 7 by grinding the back surface of the silicon board 7 .
- thisis to decrease the thickness of the semiconductor chip 1 in order to decrease the thickness of the WPP 10 .
- the thickness of the silicon board 7can be decreased. Even when the scribing width on the silicon board 7 is decreased at the time of dicing to obtain an increased number of the chips, the dicing is effected without hindering the infiltration of the cooling water at the time of dicing into the scribe grooves.
- steps S 6 to S 9test of wafer (W-test), test using probe (P-test 1), relief by laser, test using probe (P-test 2)) in the procedure of production shown in FIG. 6 may be executed between step S 1 of putting the wafer to the pre-treatment and step S 2 of forming the WPP first insulating layer.
- steps S 6 to S 9are executed after the step S 1 of putting the wafer to the pre-treatment.
- the memory-module 100 shown in FIG. 1is obtained by mounting the WPPs 10 on both the front and back surfaces of the module board 2 and mounting the TSOPs 20 on one surface thereof.
- the WPPs 10are produced in compliance with the process flow shown in FIG. 6.
- the semiconductor chip 1 possessed by the WPP 10is a DRAM.
- step S 15first, the solder is printed on the module board 2 to form terminals (land pads) for electric connection to the ends of the outer leads 21 of the lead terminal semiconductor devices and to the bump electrodes 11 of the WPPs 10 .
- SMDsare mounted at step S 16 and WPPs 10 are mounted at step S 17 .
- step S 18reflowing is effected at one time in order to electrically connect the outer leads 21 of the lead terminal semiconductor devices to the land pads, and the bump electrodes 11 of the WPPs 10 to the land pads.
- washingis effected at step S 19 .
- the washingmay not be effected.
- step S 20a resin is underfilled to effect the sealing.
- step S 21 shown in FIG. 9first, the solder is printed on predetermined portions on the module board 2 .
- step S 22the parts are mounted on the surfaces of the module.
- step S 23all of the above-mentioned parts on the front surface of the module board 2 are mounted by the batchwise (simultaneous) solder reflowing.
- step S 24the parts are mounted on the back surface of the module.
- the partsare arranged on the back surface of the module board 2 by using the mounting machine in the same manner as on the front surface.
- step S 25all of the above-mentioned parts on the back surface of the module board 2 are mounted by the batchwise (simultaneous) solder reflowing.
- the memory-module 100is fabricated mounting (in a mixed manner) predetermined numbers of WPPs 10 (of a number of 18 ⁇ 2), TSOPs 20 (of a number of 2), small surface-attached resistors 4 and EEPROM 5 on both the front and back surfaces of the module board 2 .
- washingis effected at step S 26 .
- Washingmay not be effected.
- step S 27the module is tested. That is, the memory-module 100 is inspected in a predetermined manner to detect defective chips.
- step S 28the defective chips are repaired and are exchanged.
- the solderis melted by being heated again, the defective chip (defective semiconductor device) is removed and is replaced by a non-defective chip (non-defective semiconductor device).
- step S 29all parts are mounted by effecting the reflowing again.
- washingis effected at step S 30 .
- Washingmay not be effected.
- the WPPs 10are sealed by being underfilled with the resin.
- the underfillingis that when the WPP 10 has a relatively large chip size like DRAM and fails to exhibit a sufficient function for buffering stress to the bump electrodes 11 , the resin 9 is applied between the package body 13 of the WPP 10 and the module body 2 to decrease the stress exerted on the bump electrodes 11 .
- the underfillingis a sealing with resin between the package body 13 of the WPP 10 and the module board 2 , in order to solidify and protect the surrounding of the bump electrode 11 with the resin 9 .
- the liquid resin 9is applied onto the module board 2 one surface by one surface from a nozzle 60 a of a dispenser 60 shown in FIG. 10. That is, the resin 9 is applied onto the WPPs 10 on the front and back surfaces of the module board 2 one surface by one surface.
- the front and back surfaces of the module board 2are heated at one time to simultaneously cure the resin 9 on the front and back surfaces. That is, after the application of the resin 9 on both surfaces has been finished, the two surfaces are simultaneously cured (hardened) by baking by heating the atmosphere or by the like means.
- step S 32as shown in FIG. 9, casing is effected, and the module is finally tested at step S 33 .
- Predetermined dataare written into the EEPROM 5 by using a special writer.
- the bonding electrodes 1 aare mounted on the mounting board without being rearranged by rewirings 12 . Therefore, the pitch is narrow among the external terminals, the wiring rule becomes strict on the mounting board, and the cost of the mounting board is driven up.
- the WPPs 10 on the memory-module 100 of the embodiment 1exhibit much effect in their mounting (decreases the number of the mounting steps since no special mounting device such as flip-chip bonder is used) than mounting the bare chips.
- FIG. 10is a view illustrating a method of applying the resin for underfilling the WPPs 10 mounted on the memory-module 100 of FIG. 1, and FIG. 11 is a view illustrating the permeation of the resin 9 that is applied by the method of application shown in FIG. 10.
- arrowsindicate the direction in which the nozzle 60 a travels.
- the dispenser 60 and the nozzle 60 amove on the short sides of the WPPs 10 along the arrows.
- the dispenser 60is moved intermittently and nearly linearly along the direction of short sides of the WPPs 10 having a rectangular shape on a plane, and the resin 9 is successively dripped on the short sides of the WPPs 10 from the upper side of the WPPs 10 through the nozzle 60 a . That is, when the application on one WPP 10 has finished, the nozzle 60 a is moved to an end on the front side of the short side of a next WPP 10 , and the nozzle 60 a is once stopped at this position.
- the resin 9is dripped while moving the nozzle 60 a from the end of the front side of the short side of the WPP 10 toward the end of the rear side thereof and, at this position, motion of the nozzle 60 a and dripping of the resin 9 are once halted.
- the nozzle 60 ais moved to an end on the front side of the short side of the neighboring WPP 10 , and the resin 9 is similarly dripped and, thus, the WPPs 10 are successively underfilled.
- FIG. 11illustrates the spreading of wet resin 9 that is applied by the method shown in FIG. 10 to the WPPs 10 of DRAMs in which the bump electrodes 11 are arranged in 15 rows ⁇ 4 columns
- FIGS. 11A and 11Billustrate a state right after the resin is applied onto the short side
- FIGS. 11C and 11Dillustrate a state when a predetermined period of time (short time) has passed after the application
- FIGS. 11E and 11Fillustrate a state when a predetermined period of time (long time) has passed after the application
- FIGS. 11G and 11Hillustrate a state where the resin 9 is applied by moving the nozzle 60 a one turn to form a fillet 9 a along the periphery after the predetermined period of time (long time) has passed after the application.
- FIGS. 11E and 11Fit is also allowable to move again the dispenser 60 and the nozzle 60 a about the package body 13 of the WPP 10 after the wet resin 9 has spread throughout between the WPP 10 and the module board 2 to reliably form the fillet 9 a shown in FIG. 11G, so that the WPP 10 is secured to the module board 2 more strongly.
- FIG. 12illustrates the structure of a memory-module 200 which is modified from the memory-module 100 of the embodiment 1 of the invention.
- the memory-module 200includes 18 WPPs 10 (protruded terminal semiconductor devices) that are mounted being arranged in a sequence maintaining an equal pitch on one surface of the module board 2 , and one TSOP 20 (lead terminal semiconductor device) mounted near the WPPs 10 , the TSOP 20 (lead terminal semiconductor device) being arranged near the center of the WPPs 10 that are arranged in a sequence.
- WPPs 10protruded terminal semiconductor devices
- the resin 9 for underfilling the WPPs 10is applied nearly linearly onto the short sides of 18 WPPs 10 arranged in a sequence.
- FIG. 13illustrates the structure of a memory-module 300 which is modified from the memory-module 100 of the embodiment 1 of the invention.
- 18 WPPs 10are mounted on the module board 2 in the form of groups (masses) each consisting of two or four in a two rows ⁇ two columns matrix arrangement.
- the individual WPPs 10are mounted with their lengthwise direction in parallel with the direction of the short sides of the module board 2 of the memory-module 300 .
- Described hereis a method of efficiently applying the resin 9 for underfilling the WPPs 10 in a state where the WPPs 10 are mounted.
- the resin 9When the temperature for applying the resin 9 is low, the resin 9 is applied to the package body 13 of the WPP 10 on the side of the long side, since the resin 9 may be infiltrated into between the package body 13 and the module board 2 over a short distance. This makes it possible to shorten the time for application.
- the WPPs 10 having I/O of ( ⁇ 4) constitutionare collected in a number of four to obtain a 16-bit constitution, and are mounted as a group.
- FIG. 14is a diagram illustrating the permeation of the resin 9 when it is applied according to a modified embodiment.
- the underfiller resin 9is applied to the outer peripheries along the two opposing sides of the package bodies 13 as shown in FIG. 14.
- the resin 9is applied to both short sides of the WPPs 10 from the ends on one side to the ends on the opposite side.
- FIGS. 14A and 14Bindicate the loci of motion of the dispenser 60 .
- FIGS. 14C and 14Dillustrate a state right after the application on both short sides (two sides)
- FIGS. 14E and 14Fillustrate a state when a predetermined period of time (intermediate time) has passed after the application
- FIGS. 14G and 14Hillustrate a state of infiltration of the resin 9 of when a predetermined period of time (long time) has passed after the application.
- the resin 9 permeated starting from both short sidesis still in a separated state leaving an intermediate region where no resin 9 exists even in the final stage of infiltration of the resin 9 .
- the difference in the thermal expansion between the package body 13 and the module board 2 , and stress acting on the bump electrodes 11 due to the warping of the module board 2increase with an increase in the distance from the center of the package body 13 and become a maximum at the bump electrodes 11 at the corners. Therefore, if the resin 9 is permeating near both short sides of the package body 13 of a rectangular shape, the stress acting on the bump electrodes 11 can be decreased to some extent even if there exists an intermediate region where the resin 9 is not existing.
- the resin 9may simply be applied to the four corners of the package body 13 .
- a decreased stressacts on the bump electrodes 11 arranged along the outermost circumference and, hence, the bump electrodes 11 feature extended life for connection.
- FIGS. 15A and 15Billustrate the structure of a memory-module 400 modified from the memory-module 100 , and in which 16 WPPs 10 are mounted in a sequence maintaining an equal pitch on one surface of the module board 2 .
- the underfiller resin 9is linearly applied to 16 WPPs 10 arranged in a sequence.
- Arrows shown in FIG. 15Aindicate the locus of motion of the dispenser 60 (see FIG. 10).
- FIG. 16illustrates a state where the memory-module 400 shown in FIG. 15 is deflected. This happens when the ends of the module board 2 are held at the time of inserting the socket for inspecting the memory-module 400 .
- This structurewithstands the load from the outer side and, hence, improves the reliability of the memory-module 400 .
- the WPPs 10 of a number of 16are mounted being divided into four regions each including four of them along the direction in which the plurality of connection terminals 2 a are arranged on the module board 2 , the sealing portion 14 continuing over the four WPPs 10 in each region.
- the WPPs 10are mounted being divided into groups (masses), and are sealed by being underfilled as designated at the sealing portion 14 in a continuing manner with the group as a unit. Therefore, the portions of the groups (masses) of the memory-module 500 exhibit increased rigidity apparently including the WPPs 10 .
- the neighboring sealing portions 14may often become continuous due to some factors affecting the application of the underfiller resin 9 , such as gaps among the WPPs 10 .
- the memory-module 500that includes the non-mounting portions 2 b that are not partly continuous as shown in FIGS. 17 and 18, deflects at the non-mounting portions 2 b when an external force is exerted, preventing the stress from being applied to the connection portions of bump electrodes 11 of the WPPs 10 or to the semiconductor chips 1 .
- the WPPs 10 on the memory-module 500feature improved reliability in the connection.
- the WPPs 10are sealed by underfilling, and the whole surfaces of the chips or the major portions are secured more strongly. As a result, shock resistance is improved and moisture resistance is improved, too.
- a TCPtape carrier package
- the chipsare often cracked as their thickness is decreased.
- shock resistanceis improved by securing the chips relying on the underfilling, preventing the chips from being cracked.
- the WPPs 10are sealed by underfilling and are mounted on the module board 2 with the main surfaces of the semiconductor chips 1 and the surfaces (back surfaces) of the opposite side being exposed. Moreover, the whole main surfaces or the main portions of the semiconductor chips 1 are secured to the module board 2 by being underfill-sealed, making it possible to decrease the heat resistance.
- FIG. 19is a plan view illustrating the structure of the memory-module according to an embodiment 2 of the present invention.
- the memory-module 600 of the embodiment 2includes 72 WPPs 10 (protruded terminal semiconductor devices) which are DRAMs mounted in a matrix arrangement. Connection of input/output signals to the WPPs 10 is accomplished in a manner that a group (mass) includes a total of 9 WPPs 10 consisting of one for ECC and eight of two rows (in the memory-module 600 of FIG.
- the direction in parallel with the short sides of the module board 2is referred to as row and the direction at right angles therewith is referred to as column, which, however, may be reversed to the above), and nine FET (field-effect transistor)-bus switches 15 (lead terminal semiconductor devices) which are memory selection means are mounted for the WPPs 10 of each of the groups to switch each of the groups.
- FETfield-effect transistor
- connection of input/output signals to nine WPPs 10 of two rowsis switched within the group (8 WPPs) by a corresponding FET-bus switch 15 , making it possible to increase the number of the WPPs 10 without increasing the number of the connection terminals 2 a of the module board 2 .
- the memory-module 600mounts the WPPs 10 of a number four times as great as that of the memory-module 100 of the embodiment 1.
- the memory-module 600separately switches the I/Os using the FET-bus switches 15 , so that an increased number of DRAMs can be mounted.
- the FET-bus switches 15 of the memory-module 600are, for example, those of the SOP type, which are lead terminal semiconductor devices.
- FIG. 20is a view illustrating the structure of a memory-module according to an embodiment 3 of the present invention, wherein FIG. 20A is a plan view and FIG. 20B is a side view, FIG. 21 is a diagram of block circuits of the memory-module shown in FIG. 20, FIG. 22 is a bottom view illustrating the structure of a wafer process package (protruded terminal semiconductor device) mounted on the memory-module shown in FIG. 20, FIG. 23 is a diagram of wirings on the side of the board illustrating an example of wirings on the module board at a portion C in the memory-module shown in FIG. 20A, FIGS.
- FIG. 24, 25 and 26are diagrams of wirings illustrating modified examples of the bump arrangement on the wafer process package in the memory-module according to the embodiment 3 of the invention and modified examples of the wirings on the side of the board corresponding thereto
- FIG. 27is a diagram of bump arrangement and wirings illustrating a further modified example of the bump arrangement on the wafer process package and of the wirings on the side of the board shown in FIG. 25.
- the memory-module 700 of the embodiment 3 shown in FIGS. 20A and 20Bis an unbuffered SDRAM (static DRAM)-DIMM (dual in-line memory-module) of 8 bytes having 168 pins, and includes 8 WPPs 10 (protruded terminal semiconductor devices), small surface-attached resistors 4 , capacitors 3 and an EEPROM 5 that are mounted in a mixed manner on one surface thereof.
- SDRAMstatic DRAM
- DIMMdual in-line memory-module
- the memory-module 700does not mount the registers 8 that are mounted on the memory-module 100 of FIG. 1.
- FIG. 21is a diagram of block circuits of the memory-module 700 shown in FIG. 20, constituting two banks.
- the chips D 0 to D 15represent WPPs 10 of a number of 16 on both surfaces, and [I/O 0 to I/O 3 ] terminals of each chip are connected as independent terminals to the connection terminals 2 a of the module board 2 .
- the DRAMs as a wholehave I/Os of 64 bits from DQ 0 to DQ 63 that are used as data, constituting two banks.
- the memory-module 700 shown in FIG. 20is inexpensive compared to the memory-module 100 shown in FIG. 1.
- the memory-module 700includes 8 WPPs 10 (protruded terminal semiconductor devices) which are DRAMS arranged in a sequence on one surface thereof, as well as capacitors 3 at portions among the neighboring WPPs 10 or by the WPPs 10 nearly at the centers in the lengthwise direction.
- WPPs 10protruded terminal semiconductor devices
- FIG. 22illustrates the structure of the WPP 10 used for the memory-module 700 .
- a free space 1 b without bump electrode 11is formed near the center in the lengthwise direction thereof.
- FIG. 23illustrates the wirings on the side of the module board 2 at the portion C in FIG. 20A.
- the capacitor 3(lead terminal semiconductor device) is mounted neighboring the free space 1 b of the semiconductor chip 1 , and power source wirings 2 c of the capacitor 3 are formed as surface-layer wirings 2 h on the surface layer opposing the free space 1 b of the semiconductor chip 1 on the module board 2 (they, however, may be formed as inner-layer wirings 2 g in the inner layer).
- the free space 1 b without bump electrode 11is formed near the center of the semiconductor chip 1 in the lengthwise direction thereof. Therefore, the connection can be accomplished without drawing the signal lines of the WPP 10 to the portions corresponding to the center of the chip on the module board 2 and, hence, the capacitor 3 can be mounted at a portion closest to the WPP 10 .
- the wiringsbecome the shortest between the WPPs 10 and the capacitors 3 to improve the operation characteristics.
- the module board 2is formed by a total of six metal layers including two core layers Vcc, a GND layer, and two signal line layers on each surface.
- Common wirings 2 e of the address/functional systemconnect the lands 2 d on the surface layer to which the bump electrodes 11 of the WPP 10 are connected, to the layer which is just thereunder through via-holes 2 f , and are connected to the inner-layer wirings 2 g that extend in the lengthwise direction of the module board 2 .
- the I/O wiringsare connected to the connection terminals 2 a disposed nearby through the surface-layer wirings 2 h of the module board 2 . This suppresses an increase in the inductance that results when the via-holes 2 f are passed through.
- Vss (GND) and Vddare extending sideways from the capacitor 3 , which, however, may be readily connected to the core layers through via-holes 2 f.
- FIGS. 24, 25 and 26are diagrams illustrating modified examples of the bump arrangement of the WPP 10 in the memory-module 700 of the embodiment 3 and modified examples of the wirings on the side of the board corresponding thereto, and FIG. 27 illustrates a further modified example of the bump arrangement of the wafer process package shown in FIG. 25 and of the wirings on the side of the board.
- a group of common bump electrodes (group of common protruded terminals) 1 cwhich is a group of common electrodes such as of addresses, functions, power source and GND that can be connected in common among the WPPs 10
- a group of independent bump electrodes (group of independent protruded terminals) 1 dthat is a group of independent electrodes such as of I/Os independently connected for each of the WPPs 10 .
- the group of independent bump electrodes 1 dis arranged at an end on one side which is the short side of the package body 13 .
- eight WPPs 10are mounted with their groups of independent bump electrodes 1 d being directed to the side of the connection terminals 2 a of the module board 2 .
- the pitchis broadened among the group of common bump electrodes 1 c , i.e., among the bump electrodes 11 of the address system and functional system.
- the pitchis expanded in the lengthwise direction of the chip so that many wirings can be formed in the direction at right angles with the lengthwise direction of the package body 13 passing among the bump electrodes.
- the pitchis decreased among the group of independent bump electrodes 1 d , i.e., among the bump electrodes 11 of the I/O system, and the bump electrodes are arranged in the outer periphery on one side of the package body 13 .
- the groups of common bump electrodes 1 care regularly arranged by rewirings 12 being inclined with respect to the package bodies 13 .
- the wiring density of the module board 2can be maximized and the lengths of the common wirings 2 e can be minimized.
- the GND and Vcc layers of the surface layer and of the inner layerare partly used as signal layers to produce the module board 2 of four layers and, hence, to assemble the memory-module 700 by using this module board 2 .
- the independent wirings 2 i of the I/O systemare connected from the bump electrodes 11 provided on the side of the connection terminals 2 a , and the plurality of common wirings 2 e connecting the common electrodes such as of addresses, functions, power source and GND are so formed as to pass among the chips.
- the groups of common bump electrodes 1 care arranged like a grid using rewirings 12 (see FIG. 22).
- the rewirings 12are used for distributing the power source and GND wirings in the chip, and one bump electrode 11 is electrically connected to a plurality of bonding electrodes 1 a through the rewirings 12 to decrease the number of the bump electrodes 11 (to decrease the number of the external terminals).
- connectionis made using the surface layer only of the module board 2 , and the bump electrodes 11 are arranged without being inclined. Therefore, the wirings are accomplished by utilizing the bending and inclination of the wirings on the side of the board.
- the pitch among the bump electrodes 11is slightly expanded to be larger than that of the bump arrangement of the WPPs 10 shown in FIG. 25, and the bump electrodes are arranged on the module board 2 being inclined in the lengthwise direction or in the direction of the short side.
- the common wirings 2 e on the side of the module board 2are inclined relative to the lengthwise direction of the package bodies 13 .
- the common wirings 2 eare formed straight like the common wirings 2 e shown in FIG. 24.
- FIG. 27illustrates a further modified example in which the pitch among the bump electrodes 11 is slightly expanded to be larger than that of the bump arrangement of the WPPs 10 shown in FIG. 25.
- independent pins other than those of the I/O systemare drawn out from the lower side.
- the bitsare specially constituted to decrease the number of pins to thereby increase the gap among the common wirings 2 e , the I/O pins and other independent pins having a narrow pitch (d 1 >d 2 in FIG. 27).
- the modified example shown in FIG. 27exhibits such an effect that an increased number of wirings can be drawn among the pins since the gap is broadened among the common wirings. Therefore, the wirings on the module board 2 can be used in common using the surface-layer wirings 2 h only, without using the inner-layer wirings 2 g (see FIG. 23) of the module board 2 .
- the I/O pins and independent pins such as of the power sourcehave a narrow pitch. These pins may have a narrow pitch since the wirings are drawn downward, i.e., drawn to the connection terminals 2 a without passing among the pins.
- the mounting landsare not particularly indicated on the module board 2 and the slit-like openings in the resist at right angles with the common wirings 2 e are regarded to be false lands for connection by soldering, in order to increase the wiring density on the module board 2 up to its limit.
- the EEPROM 5was the lead terminal semiconductor device having outer leads 21 .
- the EEPROM 5 which is a nonvolatile read-only memorymay be formed in the same structure as the protruded terminal semiconductor device, i.e., as the WPP 10 , and may be mounted.
- the EEPROM 5 of the WPP structureis not sealed by underfilling but the WPPs 10 which are the DRAMs only are underfilled.
- the EEPROM 5 of the WPP structureis detachably mounted on the module board 2 .
- the EEPROM 5is produced maintaining a low yield and when it is detected to be defective upon electrically writing data therein, the EEPROM 5 is better replaced by a non-defective one.
- the EEPROM 5has a small chip size compared to the DRAM, causes small stress to exert on the bump electrodes 11 , and maintains reliability to a sufficient degree even without being underfilled.
- the mounting areacan be decreased compared to when the SOP type device is mounted and the cost can be decreased to be lower than that of the SOP type device.
- the above-mentioned embodiments 1, 2 and 3have dealt with the memory-modules of the type mounting the WPPs 10 on both the front and back surfaces of the module board 2 .
- the memory-modulemay be the one of the type mounting the WPPs 10 on one surface only.
- the lead terminal semiconductor device mounted together with the WPPs 10is not limited to TSOP 20 but may be such a semiconductor device as QFP (quad flat package) or TCP (tape carrier package) in addition to TSOP 20 .
- the protruded terminal semiconductor devicesare the WPPs 10 .
- the protruded terminal semiconductor devicesmay be any other semiconductor devices provided their external terminals are bump electrodes 11 and are equipped with wiring portions for expanding the pitch among the bonding electrodes 1 a of the semiconductor chips 1 to be wider than the pitch among the bump electrodes 11 .
- FIGS. 28, 29 and 30illustrate modified examples of the protruded terminal semiconductor device other than the WPP 10 .
- FIGS. 28A, 28B and 28 Cillustrate a CSP (chip scale package) 30 as a modified example of the protruded terminal semiconductor device.
- the CSP 30has a chip size nearly equal to, or slightly larger than, the semiconductor chip 1 , and is of the fan in structure that supports the semiconductor chip 1 by a tape board 32 by interposing an elastomer 31 .
- a plurality of bump electrodes 34protruded terminals of solder or the like are formed as external terminals within an area of the semiconductor chip 1 , the connection leads 32 a provided on the tape board 32 are electrically connected to the bonding electrodes 1 a of the semiconductor chip 1 , and terminal pitch-expanding wirings 32 b are formed on the tape board 32 to expand the pitch among the bump electrodes 34 to be wider than the pitch among the bonding electrodes 1 a of the semiconductor chip 1 .
- a sealing portion 33is formed on the bonding electrodes 1 a of the semiconductor chip 1 .
- FIGS. 29A and 29Billustrate a BGA (ball grid array) 40 of the chip face-up mounting system as a modified example of the protruded terminal semiconductor device.
- the BGA 40is the one in which the semiconductor chip 1 is secured to a BGA board 42 in a face-up manner through a die-bonding material 45 , and the bonding electrodes 1 a of the semiconductor chip 1 are electrically connected to the board electrodes 42 f of the BGA board 42 through bonding wires 41 of gold or the like material.
- a plurality of bump electrodes 44protruded terminals of solder or the like material are arranged as external terminals like a grid on the back surface of the BGA board 42 , and terminal pitch-expanding wirings 42 a are formed on the BGA board 42 to expand the pitch among the bump electrodes 44 to be wider than the pitch among the bonding electrodes 1 a of the semiconductor chip 1 .
- the terminal pitch-expanding wirings 42 ainclude signal wirings 42 b , GND plane 42 c , Vdd plane 42 d and through holes 42 e.
- a molded portion 43is formed for sealing the semiconductor chip 1 and the bonding wires 41 with a resin.
- FIGS. 30A, 30B and 30 Cillustrate a BGA (ball grid array) 50 of the chip face-down mounting system as a modified example of the protruded terminal semiconductor device.
- the BGA 50is of the flip-chip structure in which the semiconductor chip 1 is mounted on the BGA board 52 in a face-down manner via small bumps 51 , and the bonding electrodes 1 a of the semiconductor chip 1 are electrically connected to the electrodes of the BGA board 52 through the small bumps 51 .
- the bump electrodes 54protruded terminals of solder or the like material are arranged as external terminals like a grid on the back surface of the BGA board 52 , and terminal pitch-expanding wirings 52 a (see FIG. 30C) are formed on the BGA board 52 to expand the pitch among the bump electrodes 54 to be wider than the pitch among the bonding electrodes 1 a (see FIG. 29) of the semiconductor chip 1 .
- a gap between the semiconductor chip 1 and the BGA board 52i.e., the periphery of the small bumps 51 , is underfilled with a resin to form a sealed portion 53 .
- the terminal pitch-expanding wirings 32 b , 42 a and 52 aare provided, respectively, to expand the pitch among the bump electrodes 34 , 44 , 54 to be wider than the pitch among the bonding electrodes la of the semiconductor chip 1 , which, therefore, can be mounted by reflowing on the module board 2 or the like.
- the WPPsare mounted as the protruded terminal semiconductor devices while expanding the pitch among the bump electrodes which are the external terminals to be wider than the pitch among those of the flip chips, making it possible to expand the wiring rules on the module board and, hence, to realize a highly densely mounted memory-module suppressing the cost.
- the bonding electrodes of the semiconductor chipcan be connected to the bump electrodes which are the external terminals of the WPPs through wirings of lengths shorter than those of the SMD parts such as TSOPS. This enables the memory-module to cope with high-speed operations and, hence, to cope with high-speed buses.
- the WPPsare sealed by underfilling and are mounted on the module board in a state where the back surfaces of the semiconductor chips are exposed and, besides, the whole main surfaces of the semiconductor chips are secured to the module board by underfill-sealing, enabling the heat resistance of the memory-module to be decreased.
- the memory-moduleexhibits improved heat-radiating performance and extended life.
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Abstract
Description
- The present invention relates to technology for manufacturing a semiconductor and, particularly, to technology that can be effectively applied to highly densely mounting the semiconductor chips on a memory-module.[0001]
- The technology described below is the one discussed by the present inventors in studying and accomplishing the present invention, and is roughly as described below.[0002]
- A memory-module is one of the module products mounting a plurality of semiconductor devices.[0003]
- The memory-module includes a plurality of semiconductor devices having memory chips that are mounted on one surface or on both the front and back surfaces of a module board. In mounting the memory on a personal computer or a work station, the memory-module mounts the memory by being mounted on a mother board provided in the personal computer or the work station with each module as a unit.[0004]
- As the semiconductor device mounted on the memory-module, there has been used the one of the surface mount type called SMD (surface mount device) having a semiconductor chip sealed with a resin and having lead terminals (external terminals) for drawing the electrodes to the outside of the resin-sealed portion, as represented by TSOP (thin small outline package) and TCP (tape carrier package).[0005]
- Module products of various structures have been disclosed in, for example, Japanese Patent Laid-Open Nos. 209368/1998, 258466/1989 and 86492/1995.[0006]
- Japanese Patent Laid-Open No. 209368/1998 discloses a CPU (central processing unit) module, and Japanese Patent Laid-Open No. 258466/1989 discloses a memory-module mounting SMD parts having a DRAM (dynamic random access memory) chip. Japanese Patent Laid-Open No. 86492/1995 discloses technology for applying an underfiller resin in the MCM (multi-chip module).[0007]
- The SMD parts to be mounted on the above-mentioned conventional memory-module have a large package size compared with the chip size due to the package body (semiconductor device body) that is sealed and the outer leads.[0008]
- As a result, limitation is imposed on the number of the semiconductor chips that can be mounted on the module board.[0009]
- There further arouses a problem in that due to the inductance added as a result of the sealing, it becomes difficult to design a memory-module having a high-speed interface to meet a high-speed CPU.[0010]
- The object of the present invention is to provide a memory-module that offers an increased module capacity as a result of enhancing the density for mounting the semiconductor chips and is capable of coping with a high-speed bus, and a method of manufacturing the same.[0011]
- The above and other objects as well as novel features of the present invention will become obvious from the description of the specification and the attached drawings.[0012]
- Briefly described below are representative examples of the inventions disclosed in this application.[0013]
- That is, the memory-module of the present invention comprises protruded terminal semiconductor devices having protruded terminals as external terminals, mounted via the protruded terminals, and are provided with wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes of semiconductor chips; lead terminal semiconductor devices having outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips; and a module board supporting the protruded terminal semiconductor devices and the lead terminal semiconductor devices; wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices are mounted in a mixed manner on the module board.[0014]
- Further, the memory-module of the invention comprises protruded terminal semiconductor devices of a chip size having protruded terminals as external terminals, mounted via the protruded terminals, and are provided with rewirings which are wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes in the areas of semiconductor chips; lead terminal semiconductor devices having outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips; and a module board supporting the protruded terminal semiconductor devices and the lead terminal semiconductor devices; wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices are mounted in a mixed manner on the module board.[0015]
- In mounting the protruded terminal semiconductor devices together with the lead terminal semiconductor devices in a mixed manner, therefore, the mounting is accomplished requiring mounting areas nearly equal to those of the semiconductor chips.[0016]
- Therefore, the semiconductor chips can be mounted requiring the least areas, making it possible to increase the density for mounting the semiconductor chips.[0017]
- This makes it possible to increase the module capacity of the memory-module.[0018]
- The method of manufacturing a memory-module according to the present invention comprises a step for preparing protruded terminal semiconductor devices having protruded terminals as external terminals, and wiring portions for expanding the pitch of the protruded terminals to be wider than the pitch of the bonding electrodes of semiconductor chips; a step for preparing lead terminal semiconductor devices having outer leads which are the external terminals electrically connected to the bonding electrodes of the semiconductor chips; a step for arranging the protruded terminal semiconductor devices and the lead terminal semiconductor devices on a module board; and a step for simultaneously reflowing the protruded terminal semiconductor devices and the lead terminal semiconductor devices to mount them on the module board; wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices are mounted in a mixed manner on the module board.[0019]
- Further, the method of manufacturing a memory-module of the present invention comprises a step for preparing protruded terminal semiconductor devices of a chip size having protruded terminals as external terminals, and rewirings which are wiring portions for expanding the pitch of the protruded terminals to be wider than the pitch of the bonding electrodes in the areas of semiconductor chips; a step for preparing lead terminal semiconductor devices having outer leads which are external terminals electrically connected to the bonding electrodes of the semiconductor chips; a step for arranging the protruded terminal semiconductor devices and the lead terminal semiconductor devices on a module board; and a step for simultaneously reflowing the protruded terminal semiconductor devices and the lead terminal semiconductor devices to mount them on the module board; wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices are mounted in a mixed manner on the module board.[0020]
- FIGS. 1A, 1B and[0021]1C are diagrams illustrating the structure of a memory-module according to an
embodiment 1 of the present invention, wherein FIG. 1A is a plan view, FIG. 1B is a side view, and FIG. 1C is a sectional view along the A-A section of FIG. 1A; - FIG. 2 is an enlarged partial sectional view illustrating, on an enlarged scale, a portion B in the sectional view of FIG. 1C;[0022]
- FIG. 3 is a view of block circuits of the memory-module shown in FIG. 1;[0023]
- FIG. 4 is a perspective view illustrating the appearance of the structure of a wafer process package (protruded terminal semiconductor device) mounted on the memory-module shown in FIG. 1;[0024]
- FIGS. 5A and 5B are diagrams illustrating an SMD (lead terminal semiconductor device) mounted on the memory-module shown in FIG. 1 and the structure of a wafer process package, wherein FIG. 5A is a plan view of the SMD and FIG. 5B is a plan view of the wafer process package;[0025]
- FIG. 6 is a process flow illustrating the steps for manufacturing the wafer process package mounted on the memory-module shown in FIG. 1;[0026]
- FIGS. 7A, 7B,[0027]7C,7D,7E and7F are enlarged partial sectional views illustrating the structure of the semiconductor wafer corresponding to the major steps in the process flow shown in FIG. 6;
- FIG. 8 is a basic mounting flow illustrating the procedure for mounting the wafer process package and the SMD on the module board so as to be mounted on the memory-module shown in FIG. 1;[0028]
- FIG. 9 is a mounting flow illustrating the procedure for mounting the wafer process package on the module board so as to be mounted on the memory-module shown in FIG. 1;[0029]
- FIG. 10 is an enlarged partial perspective view illustrating a method of applying an underfiller resin onto the wafer process package mounted on the memory-module shown in FIG. 1;[0030]
- FIGS. 11A, 11B,[0031]11C,11D,11E,11F,11G and11H are views illustrating the permeation of the underfiller resin that is applied as shown in FIG. 10, and wherein FIGS. 11A, 11C,11E and11G are perspective views and FIGS. 11B, 11D,11F and11H are plan views showing the semiconductor chip in a see-through manner;
- FIGS.[0032]12 is a plan view illustrating a modified structure of the memory-module of the
embodiment 1 of the present invention; - FIG. 13 is a plan view illustrating a modified structure of the memory-module of the[0033]
embodiment 1 of the present invention; - FIGS. 14A, 14B,[0034]14C,14D,14E,14F,14G and14H are views illustrating the permeation of the underfiller resin that is applied according to a modified example of the
embodiment 1 of the invention, and wherein FIGS. 14A, 14C,14E and14G are perspective views and FIGS. 14B, 14D,14F and14H are plan views illustrating a semiconductor chip in a see-through manner; - FIGS. 15A and 15B are view illustrating a modified structure of the memory-module according to the[0035]
embodiment 1 of the present invention, wherein FIG. 15A is a plan view and FIG. 15B is a side view; - FIG. 16 is a side view illustrating the memory-module of FIG. 15 in a warped state;[0036]
- FIG. 17 is a plan view illustrating a modified structure of the memory-module according to the[0037]
embodiment 1 of the present invention; - FIG. 18 is a side view illustrating the memory-module of FIG. 17 in a warped state;[0038]
- FIG. 19 is a plan view illustrating the structure of the memory-module according to an[0039]
embodiment 2 of the present invention; - FIGS. 20A and 20B are views illustrating the structure of a memory-module according to an[0040]
embodiment 3 of the present invention, wherein FIG. 20A is a plan view and FIG. 20B is a side view; - FIG. 21 is a diagram of block circuits of the memory-module shown in FIG. 20;[0041]
- FIG. 22 is a bottom view illustrating the structure of a wafer process package (protruded terminal semiconductor device) mounted on the memory-module shown in FIG. 20;[0042]
- FIG. 23 is a diagram of wirings on the side of the board illustrating an example of wirings on the module board at a portion C in the memory-module shown in FIG. 20;[0043]
- FIG. 24 is a diagram of wirings illustrating a modified example of the bump arrangement on the wafer process package in the memory-module according to the[0044]
embodiment 3 of the invention and a modified example of the wirings on the side of the board corresponding thereto; - FIG. 25 is a diagram of wirings illustrating a modified example of the bump arrangement on the wafer process package in the memory-module according to the[0045]
embodiment 3 of the invention and a modified example of the wirings on the side of the board corresponding thereto; - FIG. 26 is a diagram of wirings illustrating a modified example of the bump arrangement on the wafer process package in the memory-module according to the[0046]
embodiment 3 of the invention and a modified example of the wirings on the side of the board corresponding thereto; - FIG. 27 is a diagram of bump arrangement and wirings illustrating a further modified example of the bump arrangement on the wafer process package and of the wirings on the side of the board shown in FIG. 25;[0047]
- FIGS. 28A, 28B and[0048]28C are views illustrating the structure of a CSP which is a modified example of the protruded terminal semiconductor device mounted on the memory-module of the present invention, wherein FIG. 28A is a plan view, FIG. 28B is a sectional view and FIG. 28C is a bottom view;
- FIGS. 29A and 29B are views illustrating the structure of a BGA of the chip face-up mounting system which is a modified example of the protruded terminal semiconductor device mounted on the memory-module of the present invention, wherein FIG. 29A is a perspective view illustrating the appearance and FIG.[0049]29B is a sectional view; and
- FIGS. 30A, 30B and[0050]30C are views illustrating the structure of the BGA of the chip face-down mounting system which is a modified example of the protruded terminal semiconductor device mounted on the memory-module of the present invention, wherein FIG. 30A is a plan view, FIG. 30B is a sectional view and FIG. 30C is a bottom view.
- Embodiments of the present invention will now be described in detail with reference to the drawings.[0051]
- (Embodiment 1)[0052]
- FIG. 1 is a diagram illustrating the structure of a memory-module according to an[0053]
embodiment 1 of the present invention, wherein FIG. 1A is a plan view, FIG. 1B is a side view and FIG. 1C is a sectional view along the A-A section of FIG. 1A, FIG. 2 is an enlarged partial sectional view illustrating, on an enlarged scale, a portion B in the sectional view of FIG. 1C, FIG. 3 is a view of block circuits of the memory-module shown in FIG. 1, FIG. 4 is a perspective view illustrating the appearance of the structure of a wafer process package (protruded terminal semiconductor device) mounted on the memory-module shown in FIG. 1, FIG. 5 is a diagram illustrating an SMD (surface mount-type semiconductor device having lead terminals, which is hereinafter referred to as lead terminal semiconductor device) mounted on the memory-module shown in FIG. 1 and the structure of a wafer process package, wherein FIG. 5A is a plan view of the SMD and FIG. 5B is a plan view of the wafer process package, FIG. 6 is a process flow illustrating the steps for manufacturing the wafer process package mounted on the memory-module shown in FIG. 1, FIGS. 7A, 7B,7C,7D,7E and7F are enlarged partial sectional views illustrating the structure of the semiconductor wafer corresponding to the major steps in the process flow shown in FIG. 6, FIG. 8 is a basic mounting flow illustrating the procedure for mounting the wafer process package and the SMD on the module board so as to be mounted on the memory-module shown in FIG. 1, FIG. 9 is a mounting flow illustrating the procedure for mounting the wafer process package on the module board so as to be mounted on the memory-module shown in FIG. 1, FIG. 10 is an enlarged partial perspective view illustrating a method of applying an underfiller resin onto the wafer process package mounted on the memory-module shown in FIG. 1, FIGS. 11A, 11C,11E and11G are perspective views illustrating the permeation of the underfiller resin that is applied as shown in FIG. 10 and FIGS. 11B, 11D,11F and11H are plan views showing the semiconductor chip in a see-through manner, FIGS. 12 and 13 are plan views illustrating the modified structures of the memory-module of theembodiment 1 of the present invention, FIGS. 14A, 14C,14E and14G are perspective views illustrating the permeation of the underfiller resin that is applied according to modified examples of theembodiment 1 of the invention and FIGS. 14B, 14D,14F and14H are plan views illustrating a semiconductor chip in a see-through manner, FIG. 15 is a view illustrating a modified structure of the memory-module according to theembodiment 1 of the present invention, wherein FIG. 15A is a plan view and FIG. 15B is a side view, FIG. 16 is a side view illustrating the memory-module of FIG. 15 in a warped state, FIG. 17 is a plan view illustrating a modified structure of the memory-module according to theembodiment 1 of the present invention, and FIG. 18 is a side view illustrating the memory-module of FIG. 17 in a warped state. - A memory-[0054]
module 100 of theembodiment 1 shown in FIG. 1 comprises protruded terminal semiconductor devices having protruded terminals as external terminals, mounted via the protruded terminals and having wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes la of thesemiconductor chips 1; TSOPs (thin small outline packages) which are leadterminal semiconductor devices 20 havingsemiconductor chips 1, outer leads21 as the external terminals and are mounted via the outer leads21 which are electrically connected to thebonding electrodes 1aof thesemiconductor chips 1; and amodule board 2 for supporting the protruded terminal semiconductor devices andTSOPs 20; wherein the protruded terminal semiconductor devices and theTSOPs 20 are mounted in a mixed manner on themodule board 2 by the simultaneous reflowing. - Here, the protruded terminal semiconductor device has a plurality of bump electrodes[0055]11 (protruded terminals) that serve as the external terminals arranged in an area of a package body13 (semiconductor device body), and wiring portions for expanding the pitch among the
bump electrodes 11 to be wider than the pitch among thebonding electrodes 1aof thesemiconductor chip 1. - The lead terminal semiconductor device has a plurality of[0056]
outer leads 21 serving as the external terminals that are arranged protruding from the package body22 (semiconductor device body). - In the protruded terminal semiconductor device and the lead terminal semiconductor device, the[0057]
bonding electrodes 1aof thesemiconductor chip 1 are formed by using, for example, aluminum or the like, and are electrically connected to the bonding wires when the wires are to be bonded. - The external terminals of the protruded terminal semiconductor device and of the lead terminal semiconductor device are electrically connected to the connection electrodes on the side of the[0058]
module board 2 when the semiconductor devices are mounted on the mounting board such as themodule board 2. - The[0059]
embodiment 1 deals with the case where the protruded terminal semiconductor device is a wafer process package (hereinafter abbreviated as WPP)10 which is a small semiconductor device of a chip size. - Therefore, the memory-[0060]
module 100 of theembodiment 1 includesWPPs 10 which are the protruded terminal semiconductor devices of a chip size,TSOPs 20 which are SMD (surface mount type package) parts and are lead terminal semiconductor devices, and an EEPROM (electrically erasable programmable read-only memory)5 which is a nonvolatile read-only memory as an example of another lead terminal semiconductor device, that are mounted in a mixed manner on themodule board 2. - Here, as shown in FIG. 4, the[0061]
WPP 10 is a protruded terminal semiconductor device havingbump electrodes 11 which are the protruded terminals serving as the external terminals, and is mounted on themodule board 2 viabump electrodes 11, and is provided withrewirings 12 which are wiring portions for expanding the pitch among thebump electrodes 11 to be wider than the pitch among thebonding electrodes 1ain an area of thesemiconductor chip 1. - The[0062]
bump electrodes 11 used for theWPP 10 have little dispersion in the height, decreasing percent defective when it is mounted on the board and, hence, improve the mounting yield. Besides, thebump electrodes 11 have a mounting height of about 0.13 mm, which makes it possible to decrease the mounting height. - Referring to FIG. 1, on the memory-[0063]
module 100 are further mountedcapacitors 3, small surface-attachedresistors 4 and other electronic parts in addition to theWPPs 10,TSOPS 20 andEEPROM 5. - That is, the memory-[0064]
module 100 of theembodiment 1 includes 18WPPs 10, twoTSOPs 20, 18capacitors 3, 36 small surface-attachedresistors 4 and oneEEPROM 5 that are mounted on either the front surface or the back surface thereof, and 18WPPs 10 that are mounted on the surface on the opposite side thereof. - In the memory-[0065]
module 100 of theembodiment 1, there are arranged the WPPs10 in a total number of 18 in a sequence on both sides of the two TSOPs20 (ten on one side and eight on the other side with theTSOPs 20 being sandwiched therebetween) on one surface of themodule board 2. - Between the two[0066]
TSOPs 20, the one (TSOP 20 arranged on the upper side in FIG. 1) is a PLL (phase-locked loop)6 which is a frequency control means and the other one (TSOP 20 arranged on the lower side in FIG. 1) is aregister 8 having a register function. - That is, in the memory-[0067]
module 100 of theembodiment 1, both thePLL 6 and theregister 8 are the lead terminal semiconductor devices. - Each[0068]
capacitor 3 is arranged to correspond to eachWPP 10 close thereto. - Further, a total of 36 small surface-attached[0069]
resistors 4 are arranged in sequence; i.e., two for eachWPP 10. The small surface-attachedresistors 4 are provided to correspond to the I/Os of the memory-module 100. In the memory-module 100 of theembodiment 1, there are provided 36 I/Os on one surface and, hence, the surface-attachedresistors 4 are mounted in a number of 36. The small surface-attachedresistors 4 of the number of 36 are arranged in a sequence nearly along and near theconnection terminals 2awhich are the external terminals of themodule board 2. - Referring to FIG. 1A, the[0070]
module board 2 of the memory-module 100 measures, for example, L=133.35 mm and M=38.1 mm, and the mounting height (max) is N=4 mm as shown in FIG. 1B. - In the memory-[0071]
module 100 of theembodiment 1, further, theTSOPs 20 and theWPPs 10 are mounted by the simultaneous reflowing. As shown in FIG. 2, however, theWPP 10 is sealed with the underfiller resin after the reflow, so that a sealingportion 14 is formed. - That is, the surrounding of the[0072]
bump electrodes 11 between thepackage body 13 ofWPP 10 and themodule board 2 is sealed with a resin thereby to form the sealedportion 14. - The memory-[0073]
module 100 shown in FIG. 1 uses theWPPs 10 as DRAMs and further uses themodule board 2 of a bus of a width of 72 bits with error code correction. - Therefore, the memory-[0074]
module 100 mounts a total of 36 DRAMs (WPPs10) on both the front and back surfaces of themodule board 2. When the DRAM has, for example, 64 megabits (16 M×4), the DRAM module has a constitution of 16 words×72 bits×2 banks. - FIG. 3 is a diagram of block circuits of the memory-[0075]
module 100 shown in FIG. 1, i.e., the diagram of block circuits of the DRAM module of the constitution of 16 words×72 bits×2 banks. - In the structure of FIG. 3, the RS0 system and the RS2 system of the[0076]
bank 1 operate simultaneously, and the RS1 system and the RS3 system of thebank 2 operate simultaneously. Thebank 1 or thebank 2 is selected by aregister 8. When thebank 1 is read out, thebank 2 is not read out. Similarly, when thebank 2 is read out, thebank 1 is not read out. - A terminal A (S[0077]0 to S3) of the
register 8 is connected to a chip select (CS) terminal of the DRAM (WPP10) of either thebank 1 or thebank 2. The bank that is selected by theregister 8 forms an input to the CS terminal of the selectedsemiconductor chip 1. - D[0078]0 to D35 of each chip represent the
WPPs 10 of the number of36, and the [I (input)/O (output)0 to I/O3] terminals of each chip are connected to theconnection terminals 2aof themodule board 2 as independent terminals. - In all DRAMs, the I/Os used as data consist of 64 bits of from DQ[0079]0 to DQ63, and the I/Os used as check consist of 8 bits of from CB0 to CB7. The sum of the two constitutes a two-bank constitution of 72 bits.
- Symbols attached to the terminals shown in FIG. 3 are described below. [A[0080]0 to A11] are address inputs, [DQ0 to DQ63] are data inputs/outputs, [CB0 to CB7] are check bits (data inputs/outputs), [S0 to S3] are chip select inputs, [RE] is a row enable (RAS) input, [CE] is a column enable (CAS) input, [W] is a write enable input, [DQMB0 to DQMB7] are bite data masks, [CK0 to CK3] are clock inputs, [CKE0] is a clock enable input, [WP] is a write protection for serial PD, [REGE] is a register enable, [SDA] is a data input/output for serial PD, [SCL] is a clock input for serial PD, [SA0 to SA2] are serial address inputs, [Vcc] is a power source of the high-potential side, [Vss] is a ground, and [NC] is a non-connection.
- Next, the structure of the[0081]
WPP 10 will be described in detail. Referring to FIG. 4, thebonding electrodes 1aof thesemiconductor chip 1 in theWPP 10 are electrically connected to thesolder bump electrodes 11 which are the external terminals throughrewirings 12. - That is, the[0082]
bonding electrodes 1aarranged at a narrow pitch are expanded by therewirings 12 to a pitch of thebump electrodes 11 that are electrically connected thereto. - This is to form a package of a chip size by forming functional portions of the elements in a unit of the wafer and, then, effecting the dicing to divide into[0083]
individual semiconductor chips 1. - Therefore, the device is efficiently produced at a low cost compared with the small packages assembled by a method of production similar to that of manufacturing packages of the SMD (surface mount type) parts.[0084]
- FIG. 5 illustrates the[0085]
TSOP 20 which is an SMD part and theWPP 10 which is the protruded terminal semiconductor device of the chip size, from which a difference in the size can be comprehended. - FIG. 5A is a plan view of the[0086]
TSOP 20 mounted on the memory-module 100 shown in FIG. 1, and FIG. 5B is a plan view of theWPP 10 mounted on the memory-module 100 shown in FIG. 1. - As shown in FIG. 5, compared to the DRAM of the SMD (surface mount) type package such as[0087]
TSOP 20, theWPP 10 can be realized in a small size since it has neither the inner leads nor the outer leads21. - By mounting the DRAMs in the form of WPPs[0088]10 on the
module board 2 as in the memory-module 100 of theembodiment 1, therefore, the mounting area can be greatly reduced as compared to when theTSOPs 20 that are formed by being individually treated are mounted. - That is, by mounting the[0089]
WPPs 10, the mounting area can be minimized so far as thesemiconductor chips 1 are mounted and, hence, the module capacity can be greatly increased. - The same capacity can be realized even by mounting the flip chips which is the mounting of bare chips. In mounting the flip chips, however, there is formed no[0090]
rewiring 12. Accordingly, the pitch is small among the external terminals, and it is not allowed to accomplish the mounting by reflow simultaneously with the SMD type parts. Therefore, the parts mounting the bare chips must be mounted one by one by using a flip chip bonder, which is inferior in efficiency to mounting theWPPs 10. - In other words, the[0091]
WPPs 10 are mounted without using any special mounting device such as the flip chip bonder, and makes it possible to decrease the number of the steps for mounting. - Further, the[0092]
WPPs 10 can be mounted permitting the pitch among thebump electrodes 11 that are the external terminals to be expanded to be broader than the pitch of when the flip chips are mounted, enabling the wiring rule to be broadened on themodule board 2. This does not drive up the cost of themodule board 2, and makes it possible to realize the memory-module 100 of a highly dense mounted form suppressing the cost. - In the[0093]
WPP 10, further, the wiring lengths from thebonding electrodes 1aof thesemiconductor chip 1 to thebump electrodes 11 which are the external terminals become shorter than the wiring lengths from thebonding electrodes 1ato the ends of the outer leads21 of the SMD part such asTSOP 20, making it possible to transfer signals at a high speed. - This enables the memory-[0094]
module 100 to operate at high speeds and, hence, to cope with a high-speed bus. - Described below is the reason why the semiconductor devices (packages) mounted on the memory-[0095]
module 100 of theembodiment 1 are not all in the form of WPPs10, i.e., why theWPPs 10 which are the protruded terminal semiconductor devices of the chip size and the SMD parts (TSOPs20 in the embodiment 1) are mounted in a mixed manner. - The[0096]
WPPs 10 are formed by treating the wafers in the preceding steps. In the subsequent steps, therefore, they are all treated in a unit of the wafer even in a step of forming the devices one by one. - When the number of non-defective products is small in a piece of wafer, the defective products must be worked, driving up the cost.[0097]
- As a result, for some kinds of products for which the yields of the semiconductor wafers are not so high, no cost merit is obtained.[0098]
- Further, a reticle for exposure to light must be prepared for every kind of products. For the products that are not produced in large quantity, therefore, a material having general applicability is used for the semiconductor devices (packages) that are incorporated in the lead frames. Therefore, the products that are not produced in large quantity are better not in the form of the[0099]
WPPs 10. - Besides, physical conditions play important roles. From a relationship between the number of the terminals to be drawn out and the chip size, the logical devices in the form of small chips but having many terminals to be drawn out, are better not in the form of the[0100]
WPP 10. This is because the electrode pads (diffusion-preventingadhesion layers 7cshown in FIG. 7) and thebump electrodes 11 cannot be formed after therewirings 12 are formed from thebonding electrodes 1a. - Therefore, the devices that are better formed as WPPs[0101]10 are those chips produced maintaining a high yield and obtained in a large number per a wafer and, particularly, are those small memory devices.
- On the other hand, the devices that are not better in the form of WPPs[0102]10 are those chips produced maintaining a low yield and obtained in a small number per a wafer and, particularly, are those large chips, end devices or devices produced in small quantity. Further, when an ASIC (application specific integrated circuit) having many external terminals compared to the chip area, is obtained in the form of the
WPP 10, a sufficiently large pitch is not often maintained among thebump electrodes 11. In this case, too, the package should be in a conventional form for easy mounting. - Next, described below is a method of manufacturing the[0103]
WPP 10 with reference to a process flow of WPP10 (see FIG. 1) shown in FIG. 6 and sectional views of the wafer shown in FIG. 7 corresponding to the principal steps in the process flow. - First, the wafer is subjected to a pre-treatment at step S[0104]1 shown in FIG. 6. The bonding electrode la is exposed on the main surface of the
silicon board 7 shown in FIG. 7A thereby to form an inorganic insulatingprotection film 7a. - Then, a WPP first insulating layer is formed at step S[0105]2. That is, as shown in FIG. 7B, the first insulating
layer 7bof polyimide or fluorine-contained resin is formed on the inorganic insulatingprotection film 7aof thesilicon board 7. - Then, at step S[0106]3, a WPP rewiring layer is formed. That is, as shown in FIG. 7C, a
rewiring 12 is formed on the first insulatinglayer 7bbeing electrically connected to thebonding electrode 1a. - Then, at step S[0107]4, a WPP second insulating layer is formed. That is, as shown in FIG. 7D, a second
insulating layer 7dcomprising polyimide or epoxy is formed on therewiring 12. - Then, at step S[0108]5, a WPP-UBM (underbump metal) is formed. That is, as shown in FIG. 7E, a diffusion-preventing
adhesion layer 7cwhich is a UBM is formed being electrically connected to therewiring 12. - Then, at step S[0109]6, the wafer is inspected (W-test). This is to inspect whether the wafer has been treated as contemplated relying on the electric characteristics by bringing a probe needle into contact with the electrode pad formed on a scribe area of the semiconductor wafer (silicon board7).
- Then, at step S[0110]7, the
silicon board 7 is inspected by using the probe (P-test 1). This is to detect defective portions by inspecting whether thesemiconductor chip 1 electrically works properly by bringing the probe needle into contact with thebonding electrode 1aof thesilicon board 7. - Then, at step S[0111]8, the defective portions are relieved; i.e., laser blown fuses is executed. This is to relieve defective portions by cutting the fuse in a redundancy circuit by laser beam.
- Then, at step S[0112]9, test is effected by using probe (P-test 2). This is to make sure whether the defective portion relieved by the P-
test 1 has been corrected. - Then, at step S[0113]10, marking is effected on the back surface of the wafer to attach a predetermined mark to the back surface of the
silicon board 7. - Then, a bump is formed at step S[0114]11. That is, as shown in FIG. 7F, a bump electrode11 (protruded terminal) which is an external terminal of the
WPP 10 is formed on the diffusion-preventingadhesion layer 7cwhich is the UBM provided at an end drawn out from thebonding electrode 1aon therewiring 12. - Here, the[0115]
bump electrode 11 is formed by, for example, a printing method. A metal mask corresponding to the bump-forming position is disposed on the wafer (silicon board7), a solder paste is applied, the metal mask is removed, followed by reflowing at one time to form thebump electrodes 11 at one time on the wafer. - Then, at step S[0116]12, the semiconductor wafer, i.e., the
silicon board 7 is cut by dicing, thereby to form theWPP 10 as shown in FIG. 4. - Then, at step S[0117]13, the
WPP 10 is subjected to the aging, i.e., to the burn-in (BI) testing. - At step S[0118]14, the single products are sorted out to select
non-defective WPPs 10. - Thus, the fabrication of the[0119]
WPP 10 is completed. - In the procedure of production shown in FIG. 6, no back grinding step (hereinafter abbreviated as BG) for grinding the back surface of the[0120]
silicon board 7 was executed after the test by using the probe (P-test 2) at step S9. However, the BG step may be executed after step S9 of test by using the probe (P-test 2) but before step S10O of marking the back surface of the wafer. - Here, the BG step is to decrease the height of the[0121]
WPP 10 by decreasing the thickness of thesilicon board 7 by grinding the back surface of thesilicon board 7. - In other words, this is to decrease the thickness of the[0122]
semiconductor chip 1 in order to decrease the thickness of theWPP 10. - Upon executing the BG step, it is allowed to decrease the height of mounting the WPP[0123]10 (e.g., to decrease to 1 mm or less).
- Through the BG step, further, the thickness of the[0124]
silicon board 7 can be decreased. Even when the scribing width on thesilicon board 7 is decreased at the time of dicing to obtain an increased number of the chips, the dicing is effected without hindering the infiltration of the cooling water at the time of dicing into the scribe grooves. - This prevents damage to the[0125]
silicon board 7 at the time of dicing, and enhances the yield of thesilicon boards 7. This is particularly effective at the time of dicing thesilicon board 7 having a diameter of 300 mm. - Further, steps S[0126]6 to S9 (test of wafer (W-test), test using probe (P-test 1), relief by laser, test using probe (P-test 2)) in the procedure of production shown in FIG. 6 may be executed between step S1 of putting the wafer to the pre-treatment and step S2 of forming the WPP first insulating layer.
- That is, steps S[0127]6 to S9 are executed after the step S1 of putting the wafer to the pre-treatment.
- This makes it possible to execute a series of tests using the probe prior to forming the insulating film on the[0128]
silicon board 7 and to assemble theWPP 10 without leaving damage even in case thebonding electrode 1ais damaged. - Next, described below with reference to FIGS. 8 and 9 is a method of manufacturing the memory-[0129]
module 100 shown in FIG. 1 of theembodiment 1. - The memory-[0130]
module 100 shown in FIG. 1 is obtained by mounting theWPPs 10 on both the front and back surfaces of themodule board 2 and mounting theTSOPs 20 on one surface thereof. - First, the[0131]
WPPs 10 are produced in compliance with the process flow shown in FIG. 6. - That is, the WPPs[0132]10 (protruded terminal semiconductor devices) of the chip size shown in FIG. 4 are prepared through the pre-treatment of the wafer (prepared in a number of 18×2=36), the
WPPs 10 having bump electrodes11 (protruded terminals) serving as external terminals, and rewirings12 (wiring portions) in the areas of thesemiconductor chips 1 for expanding the pitch among thebump electrodes 11 to be wider than the pitch among thebonding electrodes 1a. - In the[0133]
embodiment 1, thesemiconductor chip 1 possessed by theWPP 10 is a DRAM. - In addition to the[0134]
WPPs 10, there are assembled the lead terminal semiconductor devices which are SMD parts to be mounted on themodule board 2. - There are prepared two TSOPs[0135]20 (one being a
PLL 6 and the other being a register8) which are lead terminal semiconductor devices having outer leads21 that are external terminals electrically connected to the bonding electrodes la of thesemiconductor chips 1, an EEPROM5 (lead terminal semiconductor device), and small surface-attachedresistors 4 of a number of 36×2=72. - The mounting procedure will be roughly described in compliance with the basic flow for mounting the parts shown in FIG. 8.[0136]
- At step S[0137]15, first, the solder is printed on the
module board 2 to form terminals (land pads) for electric connection to the ends of the outer leads21 of the lead terminal semiconductor devices and to thebump electrodes 11 of theWPPs 10. - Thereafter, SMDs are mounted at step S[0138]16 and
WPPs 10 are mounted at step S17. - Then, at step S[0139]18, reflowing is effected at one time in order to electrically connect the outer leads21 of the lead terminal semiconductor devices to the land pads, and the
bump electrodes 11 of theWPPs 10 to the land pads. - Then, washing is effected at step S[0140]19. The washing, however, may not be effected.
- Further, at step S[0141]20, a resin is underfilled to effect the sealing.
- Next, the method of manufacturing the memory-[0142]
module 100 will be described in detail by using the mounting flow closely illustrated in FIG. 9. - At step S[0143]21 shown in FIG. 9, first, the solder is printed on predetermined portions on the
module board 2. - Then, at step S[0144]22, the parts are mounted on the surfaces of the module. Here, predetermined numbers of WPPs10 (of a number of 18), TSOPs20 (of a number of 2), small surface-attached resistors4 (of a number of 36) and EEPROM5 (of a number of 1) are arranged on the front surface of the
module board 2 using a mounting machine. - Then, at step S[0145]23, all of the above-mentioned parts on the front surface of the
module board 2 are mounted by the batchwise (simultaneous) solder reflowing. - Then, at step S[0146]24, the parts are mounted on the back surface of the module. Here, the parts are arranged on the back surface of the
module board 2 by using the mounting machine in the same manner as on the front surface. - Then, at step S[0147]25, all of the above-mentioned parts on the back surface of the
module board 2 are mounted by the batchwise (simultaneous) solder reflowing. - Thus, the memory-[0148]
module 100 is fabricated mounting (in a mixed manner) predetermined numbers of WPPs10 (of a number of 18×2), TSOPs20 (of a number of 2), small surface-attachedresistors 4 andEEPROM 5 on both the front and back surfaces of themodule board 2. - Then, washing is effected at step S[0149]26.
- Washing, however, may not be effected.[0150]
- Then, at step S[0151]27, the module is tested. That is, the memory-
module 100 is inspected in a predetermined manner to detect defective chips. - Then, at step S[0152]28, the defective chips are repaired and are exchanged. In this case, the solder is melted by being heated again, the defective chip (defective semiconductor device) is removed and is replaced by a non-defective chip (non-defective semiconductor device).
- Then, at step S[0153]29, all parts are mounted by effecting the reflowing again.
- Thereafter, washing is effected at step S[0154]30.
- Washing, however, may not be effected.[0155]
- Then, at step S[0156]31, the
WPPs 10 are sealed by being underfilled with the resin. The underfilling is that when theWPP 10 has a relatively large chip size like DRAM and fails to exhibit a sufficient function for buffering stress to thebump electrodes 11, theresin 9 is applied between thepackage body 13 of theWPP 10 and themodule body 2 to decrease the stress exerted on thebump electrodes 11. - That is, the underfilling is a sealing with resin between the[0157]
package body 13 of theWPP 10 and themodule board 2, in order to solidify and protect the surrounding of thebump electrode 11 with theresin 9. - To effect the underfilling, the[0158]
liquid resin 9 is applied onto themodule board 2 one surface by one surface from anozzle 60aof adispenser 60 shown in FIG. 10. That is, theresin 9 is applied onto theWPPs 10 on the front and back surfaces of themodule board 2 one surface by one surface. - After the application has been finished on both surfaces, the front and back surfaces of the[0159]
module board 2 are heated at one time to simultaneously cure theresin 9 on the front and back surfaces. That is, after the application of theresin 9 on both surfaces has been finished, the two surfaces are simultaneously cured (hardened) by baking by heating the atmosphere or by the like means. - Then, at step S[0160]32 as shown in FIG. 9, casing is effected, and the module is finally tested at step S33.
- Predetermined data are written into the[0161]
EEPROM 5 by using a special writer. - Thus, the assembling of the memory-[0162]
module 100 shown in FIG. 1 is completed. - Here, mounting the bare chip that requires the same area as when the[0163]
WPP 10 is mounted will be described for the purpose of comparing the two. - First, in mounting the bear chip, the[0164]
bonding electrodes 1aare mounted on the mounting board without being rearranged byrewirings 12. Therefore, the pitch is narrow among the external terminals, the wiring rule becomes strict on the mounting board, and the cost of the mounting board is driven up. In assembling the module, further, it becomes necessary to add a mounting step by using a flip chip bonder of a relatively slow processing speed in addition to the step of mounting the SMD parts by reflowing the solder. - Accordingly, the[0165]
WPPs 10 on the memory-module 100 of theembodiment 1 exhibit much effect in their mounting (decreases the number of the mounting steps since no special mounting device such as flip-chip bonder is used) than mounting the bare chips. - Next, described below is the underfilling method in the method of manufacturing the memory-[0166]
module 100 of theembodiment 1. - FIG. 10 is a view illustrating a method of applying the resin for underfilling the[0167]
WPPs 10 mounted on the memory-module 100 of FIG. 1, and FIG. 11 is a view illustrating the permeation of theresin 9 that is applied by the method of application shown in FIG. 10. - In FIG. 10, arrows indicate the direction in which the[0168]
nozzle 60atravels. Thedispenser 60 and thenozzle 60amove on the short sides of theWPPs 10 along the arrows. - According to the method of applying the resin of the[0169]
embodiment 1, thedispenser 60 is moved intermittently and nearly linearly along the direction of short sides of theWPPs 10 having a rectangular shape on a plane, and theresin 9 is successively dripped on the short sides of theWPPs 10 from the upper side of theWPPs 10 through thenozzle 60a. That is, when the application on oneWPP 10 has finished, thenozzle 60ais moved to an end on the front side of the short side of anext WPP 10, and thenozzle 60ais once stopped at this position. - Thereafter, the[0170]
resin 9 is dripped while moving thenozzle 60afrom the end of the front side of the short side of theWPP 10 toward the end of the rear side thereof and, at this position, motion of thenozzle 60aand dripping of theresin 9 are once halted. - Then, in a state where the[0171]
resin 9 is no longer dripped, thenozzle 60ais moved to an end on the front side of the short side of the neighboringWPP 10, and theresin 9 is similarly dripped and, thus, theWPPs 10 are successively underfilled. - FIG. 11 illustrates the spreading of[0172]
wet resin 9 that is applied by the method shown in FIG. 10 to theWPPs 10 of DRAMs in which thebump electrodes 11 are arranged in 15 rows×4 columns, wherein FIGS. 11A and 11B illustrate a state right after the resin is applied onto the short side, FIGS. 11C and 11D illustrate a state when a predetermined period of time (short time) has passed after the application, FIGS. 11E and 11F illustrate a state when a predetermined period of time (long time) has passed after the application, and FIGS. 11G and 11H illustrate a state where theresin 9 is applied by moving thenozzle 60aone turn to form afillet 9aalong the periphery after the predetermined period of time (long time) has passed after the application. - Referring to FIGS. 11E and 11F, it is also allowable to move again the[0173]
dispenser 60 and thenozzle 60aabout thepackage body 13 of theWPP 10 after thewet resin 9 has spread throughout between theWPP 10 and themodule board 2 to reliably form thefillet 9ashown in FIG. 11G, so that theWPP 10 is secured to themodule board 2 more strongly. - FIG. 12 illustrates the structure of a memory-[0174]
module 200 which is modified from the memory-module 100 of theembodiment 1 of the invention. - The memory-[0175]
module 200 includes 18 WPPs10 (protruded terminal semiconductor devices) that are mounted being arranged in a sequence maintaining an equal pitch on one surface of themodule board 2, and one TSOP20 (lead terminal semiconductor device) mounted near theWPPs 10, the TSOP20 (lead terminal semiconductor device) being arranged near the center of theWPPs 10 that are arranged in a sequence. - That is, a plurality of (10 and 8) WPPs[0176]10 are arranged in a sequence on both sides of one
TSOP 20. - Further, nine SOPs (small outline packages)[0177]61 (registers8) which are the lead terminal semiconductor devices are mounted on the
module board 2 on the side of theconnection terminals 2awhich are the external terminals, and 18WPPs 10 are mounted on the side opposite to theconnection terminals 2a(on the side remote from theconnection terminals 2a), theindividual WPPs 10 being underfilled. - In the memory-[0178]
module 200 of this type of mounting, theresin 9 for underfilling theWPPs 10 is applied nearly linearly onto the short sides of 18WPPs 10 arranged in a sequence. - This makes it possible to efficiently apply the[0179]
resin 9. - FIG. 13 illustrates the structure of a memory-[0180]
module 300 which is modified from the memory-module 100 of theembodiment 1 of the invention. - In the memory-[0181]
module 300 shown in FIG. 13, 18WPPs 10 are mounted on themodule board 2 in the form of groups (masses) each consisting of two or four in a two rows×two columns matrix arrangement. - Further, the[0182]
individual WPPs 10 are mounted with their lengthwise direction in parallel with the direction of the short sides of themodule board 2 of the memory-module 300. - Described here is a method of efficiently applying the[0183]
resin 9 for underfilling the WPPs10 in a state where theWPPs 10 are mounted. - When the temperature for applying the[0184]
resin 9 is low, theresin 9 is applied to thepackage body 13 of theWPP 10 on the side of the long side, since theresin 9 may be infiltrated into between thepackage body 13 and themodule board 2 over a short distance. This makes it possible to shorten the time for application. - It is therefore desired to maintain space for moving the[0185]
nozzle 60aalong the long sides of at least one side of thepackage bodies 13, and to arrange the long sides thereof of the side where nonozzle 60amoves as close to other parts as possible from the standpoint of highly densely mounting the parts. - When the[0186]
semiconductor chip 1 has many bits and many DRAMs are connected to the same I/Os of the memory-module 300, a great advantage is obtained by applying the resin onto the DRAMs which are arranged as close as possible to each other in a 2×2 arrangement on the same plane. - With the[0187]
WPPs 10 being arranged as shown in FIG. 13, therefore, it is desired to apply theresin 9 to the outer peripheries of the long sides of the outer side along the outer long sides of theWPPs 10. When theresin 9 is applied along the outer long sides of 2×2 DRAMs (WPPs10) according to this method of application, theresin 9 does not flow onto thepackage bodies 13 to which the resin is not to be applied on the side opposite to thepackage bodies 13 to which the resin is to be applied. Or, theresin 9 does not leak or spread, either. - In the memory-[0188]
module 300, it is desired that theWPPs 10 having I/O of (×4) constitution are collected in a number of four to obtain a 16-bit constitution, and are mounted as a group. In mounting theWPPs 10 as shown in FIG. 13, therefore, it is desired to apply theresin 9 along the locus as indicated by arrows. - FIG. 14 is a diagram illustrating the permeation of the[0189]
resin 9 when it is applied according to a modified embodiment. - That is, in mounting the[0190]
WPPs 10 on a memory-module 400 as shown in FIG. 15, theunderfiller resin 9 is applied to the outer peripheries along the two opposing sides of thepackage bodies 13 as shown in FIG. 14. Here, theresin 9 is applied to both short sides of theWPPs 10 from the ends on one side to the ends on the opposite side. - Arrows shown in FIGS. 14A and 14B indicate the loci of motion of the[0191]
dispenser 60. FIGS. 14C and 14D illustrate a state right after the application on both short sides (two sides), FIGS. 14E and 14F illustrate a state when a predetermined period of time (intermediate time) has passed after the application, and FIGS. 14G and 14H illustrate a state of infiltration of theresin 9 of when a predetermined period of time (long time) has passed after the application. - In the[0192]
embodiment 1, theresin 9 permeated starting from both short sides is still in a separated state leaving an intermediate region where noresin 9 exists even in the final stage of infiltration of theresin 9. The difference in the thermal expansion between thepackage body 13 and themodule board 2, and stress acting on thebump electrodes 11 due to the warping of themodule board 2, increase with an increase in the distance from the center of thepackage body 13 and become a maximum at thebump electrodes 11 at the corners. Therefore, if theresin 9 is permeating near both short sides of thepackage body 13 of a rectangular shape, the stress acting on thebump electrodes 11 can be decreased to some extent even if there exists an intermediate region where theresin 9 is not existing. - Thus, the effect close to that of when the resin is applied to the whole surface of the[0193]
package body 13 is obtained requiring a decreased amount of theresin 9 and a shortened operation time. - In other words, it is made possible to shorten the time for application and to decrease the amount of application.[0194]
- Further, the[0195]
resin 9 may simply be applied to the four corners of thepackage body 13. In this case, a decreased stress acts on thebump electrodes 11 arranged along the outermost circumference and, hence, thebump electrodes 11 feature extended life for connection. - FIGS. 15A and 15B illustrate the structure of a memory-[0196]
module 400 modified from the memory-module 100, and in which 16WPPs 10 are mounted in a sequence maintaining an equal pitch on one surface of themodule board 2. In this memory-module 400, theunderfiller resin 9 is linearly applied to 16WPPs 10 arranged in a sequence. Arrows shown in FIG. 15A indicate the locus of motion of the dispenser60 (see FIG. 10). - FIG. 16 illustrates a state where the memory-[0197]
module 400 shown in FIG. 15 is deflected. This happens when the ends of themodule board 2 are held at the time of inserting the socket for inspecting the memory-module 400. - That is, as shown in FIG. 16, when the memory-[0198]
module 400 shown in FIG. 15 is deflected in the lengthwise direction thereof, the stress is nearly uniformly dispersed over the whole memory-module 400 since the memory-module 400 as a whole is deflected unless the sealingportions 14 of the neighboringWPPs 10 are integrally fabricated without coming into contact with each other. - This structure withstands the load from the outer side and, hence, improves the reliability of the memory-[0199]
module 400. - In a memory-[0200]
module 500 shown in FIGS. 17 and 18, theWPPs 10 of a number of 16 are mounted being divided into four regions each including four of them along the direction in which the plurality ofconnection terminals 2aare arranged on themodule board 2, the sealingportion 14 continuing over the fourWPPs 10 in each region. - That is, the[0201]
WPPs 10 are mounted being divided into groups (masses), and are sealed by being underfilled as designated at the sealingportion 14 in a continuing manner with the group as a unit. Therefore, the portions of the groups (masses) of the memory-module 500 exhibit increased rigidity apparently including theWPPs 10. - Therefore, the bending stress of the[0202]
module board 2 concentrates at the gaps among the groups of WPPs10. - That is, the neighboring sealing[0203]
portions 14 may often become continuous due to some factors affecting the application of theunderfiller resin 9, such as gaps among the WPPs10. Even in such a case, the memory-module 500 that includes thenon-mounting portions 2bthat are not partly continuous as shown in FIGS. 17 and 18, deflects at thenon-mounting portions 2bwhen an external force is exerted, preventing the stress from being applied to the connection portions ofbump electrodes 11 of theWPPs 10 or to thesemiconductor chips 1. - Since the stress is dispersed, the[0204]
WPPs 10 on the memory-module 500 feature improved reliability in the connection. - In the memory-[0205]
modules embodiment 1, theWPPs 10 are sealed by underfilling, and the whole surfaces of the chips or the major portions are secured more strongly. As a result, shock resistance is improved and moisture resistance is improved, too. - In the module product, a TCP (tape carrier package) may be laminated as another means for highly densely mounting the parts. According to this technology, however, the chips are often cracked as their thickness is decreased. In the memory-[0206]
modules embodiment 1, on the other hand, shock resistance is improved by securing the chips relying on the underfilling, preventing the chips from being cracked. - Further, the[0207]
WPPs 10 are sealed by underfilling and are mounted on themodule board 2 with the main surfaces of thesemiconductor chips 1 and the surfaces (back surfaces) of the opposite side being exposed. Moreover, the whole main surfaces or the main portions of thesemiconductor chips 1 are secured to themodule board 2 by being underfill-sealed, making it possible to decrease the heat resistance. - This helps improve the heat-radiating performance of the memory-[0208]
modules - (Embodiment 2)[0209]
- FIG. 19 is a plan view illustrating the structure of the memory-module according to an[0210]
embodiment 2 of the present invention. - The memory-[0211]
module 600 of theembodiment 2 includes 72 WPPs10 (protruded terminal semiconductor devices) which are DRAMs mounted in a matrix arrangement. Connection of input/output signals to theWPPs 10 is accomplished in a manner that a group (mass) includes a total of 9WPPs 10 consisting of one for ECC and eight of two rows (in the memory-module 600 of FIG. 19, the direction in parallel with the short sides of themodule board 2 is referred to as row and the direction at right angles therewith is referred to as column, which, however, may be reversed to the above), and nine FET (field-effect transistor)-bus switches15 (lead terminal semiconductor devices) which are memory selection means are mounted for theWPPs 10 of each of the groups to switch each of the groups. - That is, in the memory-[0212]
module 600, the connection of input/output signals to nineWPPs 10 of two rows is switched within the group (8 WPPs) by a corresponding FET-bus switch 15, making it possible to increase the number of theWPPs 10 without increasing the number of theconnection terminals 2aof themodule board 2. - Therefore, the memory-[0213]
module 600 mounts theWPPs 10 of a number four times as great as that of the memory-module 100 of theembodiment 1. - That is, the memory-[0214]
module 600 separately switches the I/Os using the FET-bus switches 15, so that an increased number of DRAMs can be mounted. - In appearance, the FET-[0215]
bus switches 15 of the memory-module 600 are, for example, those of the SOP type, which are lead terminal semiconductor devices. - The structure of the memory-[0216]
module 600 of theembodiment 2 in other respects and the method of manufacturing the memory-module 600 are the same as those of the memory-module 100 of theembodiment 1, and are not described here again. - (Embodiment 3)[0217]
- FIG. 20 is a view illustrating the structure of a memory-module according to an[0218]
embodiment 3 of the present invention, wherein FIG. 20A is a plan view and FIG. 20B is a side view, FIG. 21 is a diagram of block circuits of the memory-module shown in FIG. 20, FIG. 22 is a bottom view illustrating the structure of a wafer process package (protruded terminal semiconductor device) mounted on the memory-module shown in FIG. 20, FIG. 23 is a diagram of wirings on the side of the board illustrating an example of wirings on the module board at a portion C in the memory-module shown in FIG. 20A, FIGS. 24, 25 and26 are diagrams of wirings illustrating modified examples of the bump arrangement on the wafer process package in the memory-module according to theembodiment 3 of the invention and modified examples of the wirings on the side of the board corresponding thereto, and FIG. 27 is a diagram of bump arrangement and wirings illustrating a further modified example of the bump arrangement on the wafer process package and of the wirings on the side of the board shown in FIG. 25. - The memory-[0219]
module 700 of theembodiment 3 shown in FIGS. 20A and 20B is an unbuffered SDRAM (static DRAM)-DIMM (dual in-line memory-module) of 8 bytes having 168 pins, and includes 8 WPPs10 (protruded terminal semiconductor devices), small surface-attachedresistors 4,capacitors 3 and anEEPROM 5 that are mounted in a mixed manner on one surface thereof. - The memory-[0220]
module 700, however, does not mount theregisters 8 that are mounted on the memory-module 100 of FIG. 1. - FIG. 21 is a diagram of block circuits of the memory-[0221]
module 700 shown in FIG. 20, constituting two banks. - Symbols attached to the terminals shown in FIG. 21 are the same as those described with reference to the block circuit diagram of the memory-[0222]
module 100 of theembodiment 1, and are not described here again. - In the memory-[0223]
module 700 shown in FIG. 21, whether the S0 system of thebank 1 or the S1 system of thebank 2 be read out, is directly determined by a signal since noregister 8 has been mounted. That is, since the memory-module is of the unbuffered type, a signal directly enters either bank to select asemiconductor chip 1 of either bank. - The chips D[0224]0 to D15 represent
WPPs 10 of a number of 16 on both surfaces, and [I/O 0 to I/O3] terminals of each chip are connected as independent terminals to theconnection terminals 2aof themodule board 2. - The DRAMs as a whole have I/Os of 64 bits from DQ[0225]0 to DQ63 that are used as data, constituting two banks.
- The memory-[0226]
module 700 shown in FIG. 20 is inexpensive compared to the memory-module 100 shown in FIG. 1. - The[0227]
module board 2 of the memory-module 700 has a size of, for example, P=133.35 mm and Q=33.02 mm, and the mounting height (max) is R=4 mm as shown in FIG. 20B. - Referring to FIG. 20A, the memory-[0228]
module 700 includes 8 WPPs10 (protruded terminal semiconductor devices) which are DRAMS arranged in a sequence on one surface thereof, as well ascapacitors 3 at portions among the neighboringWPPs 10 or by theWPPs 10 nearly at the centers in the lengthwise direction. - This is to minimize the wiring length between the WPPs[0229]10 and the
capacitors 3. - Here, FIG. 22 illustrates the structure of the[0230]
WPP 10 used for the memory-module 700. - In the[0231]
semiconductor chip 1 ofWPP 10 shown in FIG. 22, afree space 1bwithoutbump electrode 11 is formed near the center in the lengthwise direction thereof. - This is done by partly changing the pitch among the[0232]
bump electrodes 11 byrewirings 12 so as to form thefree space 1b, i.e., to form thefree space 1bwithoutbump electrode 11 near the center of theWPP 10 in the lengthwise direction thereof. - FIG. 23 illustrates the wirings on the side of the[0233]
module board 2 at the portion C in FIG. 20A. - Referring to FIGS. 22 and 23, the capacitor[0234]3 (lead terminal semiconductor device) is mounted neighboring the
free space 1bof thesemiconductor chip 1, and power source wirings2cof thecapacitor 3 are formed as surface-layer wirings 2hon the surface layer opposing thefree space 1bof thesemiconductor chip 1 on the module board2 (they, however, may be formed as inner-layer wirings 2gin the inner layer). - That is, as shown in FIG. 22, the[0235]
free space 1bwithoutbump electrode 11 is formed near the center of thesemiconductor chip 1 in the lengthwise direction thereof. Therefore, the connection can be accomplished without drawing the signal lines of theWPP 10 to the portions corresponding to the center of the chip on themodule board 2 and, hence, thecapacitor 3 can be mounted at a portion closest to theWPP 10. - Accordingly, the wirings become the shortest between the WPPs[0236]10 and the
capacitors 3 to improve the operation characteristics. - Referring to FIG. 23, the[0237]
module board 2 is formed by a total of six metal layers including two core layers Vcc, a GND layer, and two signal line layers on each surface.Common wirings 2eof the address/functional system connect thelands 2don the surface layer to which thebump electrodes 11 of theWPP 10 are connected, to the layer which is just thereunder through via-holes 2f, and are connected to the inner-layer wirings 2gthat extend in the lengthwise direction of themodule board 2. - The I/O wirings are connected to the[0238]
connection terminals 2adisposed nearby through the surface-layer wirings 2hof themodule board 2. This suppresses an increase in the inductance that results when the via-holes 2fare passed through. - In the wirings shown in FIG. 23, the Vss (GND) and Vdd are extending sideways from the[0239]
capacitor 3, which, however, may be readily connected to the core layers through via-holes 2f. - FIGS. 24, 25 and[0240]26 are diagrams illustrating modified examples of the bump arrangement of the
WPP 10 in the memory-module 700 of theembodiment 3 and modified examples of the wirings on the side of the board corresponding thereto, and FIG. 27 illustrates a further modified example of the bump arrangement of the wafer process package shown in FIG. 25 and of the wirings on the side of the board. - In the WPPs[0241]10 in FIGS. 24, 25,26 and27, there are separately provided a group of common bump electrodes (group of common protruded terminals)1cwhich is a group of common electrodes such as of addresses, functions, power source and GND that can be connected in common among the
WPPs 10, and a group of independent bump electrodes (group of independent protruded terminals)1dthat is a group of independent electrodes such as of I/Os independently connected for each of theWPPs 10. - In the[0242]
WPP 10, further, the group ofindependent bump electrodes 1dis arranged at an end on one side which is the short side of thepackage body 13. On one surface of the memory-module 700, eightWPPs 10 are mounted with their groups ofindependent bump electrodes 1dbeing directed to the side of theconnection terminals 2aof themodule board 2. - On the[0243]
module board 2 are therefore formed surface-layer wirings 2hwhich arecommon wirings 2efor connecting the groups ofcommon bump electrodes 1cof eight WPPs10. - Here, the pitch is broadened among the group of[0244]
common bump electrodes 1c, i.e., among thebump electrodes 11 of the address system and functional system. In particular, the pitch is expanded in the lengthwise direction of the chip so that many wirings can be formed in the direction at right angles with the lengthwise direction of thepackage body 13 passing among the bump electrodes. - Further, the pitch is decreased among the group of[0245]
independent bump electrodes 1d, i.e., among thebump electrodes 11 of the I/O system, and the bump electrodes are arranged in the outer periphery on one side of thepackage body 13. - This makes it possible to form[0246]
common wirings 2erelying on the surface-layer wirings 2honly and, hence, to decrease the number of the wiring layers in themodule board 2. - In the WPPs[0247]10 shown in FIG. 24, the groups of
common bump electrodes 1care regularly arranged byrewirings 12 being inclined with respect to thepackage bodies 13. - This makes it possible to form the plurality of[0248]
common wirings 2ein parallel in the lengthwise direction of thepackage bodies 13 to connect common electrodes such as of addresses, functions, power source and GND. - As a result, the wiring density of the[0249]
module board 2 can be maximized and the lengths of thecommon wirings 2ecan be minimized. - When the number of the[0250]
bump electrodes 11 of theWPP 10 is relatively small compared to its chip size or when themodule board 2 involves fine wiring rules like an additive board, the GND and Vcc layers of the surface layer and of the inner layer are partly used as signal layers to produce themodule board 2 of four layers and, hence, to assemble the memory-module 700 by using thismodule board 2. - In this case, the[0251]
independent wirings 2iof the I/O system are connected from thebump electrodes 11 provided on the side of theconnection terminals 2a, and the plurality ofcommon wirings 2econnecting the common electrodes such as of addresses, functions, power source and GND are so formed as to pass among the chips. - In the WPPs[0252]10 as shown in FIG. 25, further, the groups of
common bump electrodes 1care arranged like a grid using rewirings12 (see FIG. 22). In this case, as shown in FIG. 22, therewirings 12 are used for distributing the power source and GND wirings in the chip, and onebump electrode 11 is electrically connected to a plurality ofbonding electrodes 1athrough therewirings 12 to decrease the number of the bump electrodes11 (to decrease the number of the external terminals). - In the wirings on the side of the board shown in FIG. 25, the connection is made using the surface layer only of the[0253]
module board 2, and thebump electrodes 11 are arranged without being inclined. Therefore, the wirings are accomplished by utilizing the bending and inclination of the wirings on the side of the board. - In the WPPs[0254]10 shown in FIG. 26, the pitch among the
bump electrodes 11 is slightly expanded to be larger than that of the bump arrangement of theWPPs 10 shown in FIG. 25, and the bump electrodes are arranged on themodule board 2 being inclined in the lengthwise direction or in the direction of the short side. - Therefore, the[0255]
common wirings 2eon the side of themodule board 2 are inclined relative to the lengthwise direction of thepackage bodies 13. As a result, thecommon wirings 2eare formed straight like thecommon wirings 2eshown in FIG. 24. - FIG. 27 illustrates a further modified example in which the pitch among the[0256]
bump electrodes 11 is slightly expanded to be larger than that of the bump arrangement of theWPPs 10 shown in FIG. 25. In this modified example, independent pins other than those of the I/O system are drawn out from the lower side. This is an example in which the bits are specially constituted to decrease the number of pins to thereby increase the gap among thecommon wirings 2e, the I/O pins and other independent pins having a narrow pitch (d1>d2 in FIG. 27). - The modified example shown in FIG. 27 exhibits such an effect that an increased number of wirings can be drawn among the pins since the gap is broadened among the common wirings. Therefore, the wirings on the[0257]
module board 2 can be used in common using the surface-layer wirings 2honly, without using the inner-layer wirings 2g(see FIG. 23) of themodule board 2. The I/O pins and independent pins such as of the power source have a narrow pitch. These pins may have a narrow pitch since the wirings are drawn downward, i.e., drawn to theconnection terminals 2awithout passing among the pins. - In FIG. 27, three surface-[0258]
layer wirings 2hrun between the pins when the wiring layout D is employed, and four surface-layer wirings 2hrun between the pins when the wiring layout E is employed. - In FIGS. 24, 25,[0259]26 and27, the mounting lands are not particularly indicated on the
module board 2 and the slit-like openings in the resist at right angles with thecommon wirings 2eare regarded to be false lands for connection by soldering, in order to increase the wiring density on themodule board 2 up to its limit. - The structure of the memory-[0260]
module 700 of theembodiment 3 in other respects and the method of manufacturing the memory-module 700 are the same as those of the memory-module 100 of theembodiment 1, and are not described here again. - In the foregoing was concretely described the invention accomplished by the present inventors by way of embodiments. However, the present invention is in no way limited to the above-mentioned embodiments only but can be modified in a variety of ways without departing from the spirit and scope of the invention.[0261]
- In the memory-[0262]
modules 100 to700 of the above-mentionedembodiments EEPROM 5 was the lead terminal semiconductor device having outer leads21. However, theEEPROM 5 which is a nonvolatile read-only memory may be formed in the same structure as the protruded terminal semiconductor device, i.e., as theWPP 10, and may be mounted. - In this case, however, the[0263]
EEPROM 5 of the WPP structure is not sealed by underfilling but theWPPs 10 which are the DRAMs only are underfilled. - That is, the[0264]
EEPROM 5 of the WPP structure is detachably mounted on themodule board 2. - This is because the[0265]
EEPROM 5 is produced maintaining a low yield and when it is detected to be defective upon electrically writing data therein, theEEPROM 5 is better replaced by a non-defective one. TheEEPROM 5 has a small chip size compared to the DRAM, causes small stress to exert on thebump electrodes 11, and maintains reliability to a sufficient degree even without being underfilled. Upon mounting theEEPROM 5 of the WPP structure, the mounting area can be decreased compared to when the SOP type device is mounted and the cost can be decreased to be lower than that of the SOP type device. - The above-mentioned[0266]
embodiments WPPs 10 on both the front and back surfaces of themodule board 2. However, the memory-module may be the one of the type mounting theWPPs 10 on one surface only. - The lead terminal semiconductor device mounted together with the WPPs[0267]10 (protruded terminal semiconductor devices) is not limited to
TSOP 20 but may be such a semiconductor device as QFP (quad flat package) or TCP (tape carrier package) in addition toTSOP 20. - The above-mentioned[0268]
embodiments bump electrodes 11 and are equipped with wiring portions for expanding the pitch among thebonding electrodes 1aof thesemiconductor chips 1 to be wider than the pitch among thebump electrodes 11. - FIGS. 28, 29 and[0269]30 illustrate modified examples of the protruded terminal semiconductor device other than the
WPP 10. - FIGS. 28A, 28B and[0270]28C illustrate a CSP (chip scale package)30 as a modified example of the protruded terminal semiconductor device.
- The[0271]
CSP 30 has a chip size nearly equal to, or slightly larger than, thesemiconductor chip 1, and is of the fan in structure that supports thesemiconductor chip 1 by atape board 32 by interposing anelastomer 31. - Further, a plurality of bump electrodes[0272]34 (protruded terminals) of solder or the like are formed as external terminals within an area of the
semiconductor chip 1, the connection leads32aprovided on thetape board 32 are electrically connected to thebonding electrodes 1aof thesemiconductor chip 1, and terminal pitch-expandingwirings 32bare formed on thetape board 32 to expand the pitch among thebump electrodes 34 to be wider than the pitch among thebonding electrodes 1aof thesemiconductor chip 1. - A sealing[0273]
portion 33 is formed on thebonding electrodes 1aof thesemiconductor chip 1. - FIGS. 29A and 29B illustrate a BGA (ball grid array)[0274]40 of the chip face-up mounting system as a modified example of the protruded terminal semiconductor device.
- The[0275]
BGA 40 is the one in which thesemiconductor chip 1 is secured to aBGA board 42 in a face-up manner through a die-bonding material 45, and thebonding electrodes 1aof thesemiconductor chip 1 are electrically connected to theboard electrodes 42fof theBGA board 42 throughbonding wires 41 of gold or the like material. - Further, a plurality of bump electrodes[0276]44 (protruded terminals) of solder or the like material are arranged as external terminals like a grid on the back surface of the
BGA board 42, and terminal pitch-expandingwirings 42aare formed on theBGA board 42 to expand the pitch among thebump electrodes 44 to be wider than the pitch among thebonding electrodes 1aof thesemiconductor chip 1. - The terminal pitch-expanding[0277]
wirings 42aincludesignal wirings 42b, GND plane42c,Vdd plane 42dand throughholes 42e. - Further, a molded[0278]
portion 43 is formed for sealing thesemiconductor chip 1 and thebonding wires 41 with a resin. - FIGS. 30A, 30B and[0279]30C illustrate a BGA (ball grid array)50 of the chip face-down mounting system as a modified example of the protruded terminal semiconductor device.
- The[0280]
BGA 50 is of the flip-chip structure in which thesemiconductor chip 1 is mounted on theBGA board 52 in a face-down manner viasmall bumps 51, and thebonding electrodes 1aof thesemiconductor chip 1 are electrically connected to the electrodes of theBGA board 52 through the small bumps51. - Further, the bump electrodes[0281]54 (protruded terminals) of solder or the like material are arranged as external terminals like a grid on the back surface of the
BGA board 52, and terminal pitch-expandingwirings 52a(see FIG. 30C) are formed on theBGA board 52 to expand the pitch among thebump electrodes 54 to be wider than the pitch among thebonding electrodes 1a(see FIG. 29) of thesemiconductor chip 1. - A gap between the[0282]
semiconductor chip 1 and theBGA board 52, i.e., the periphery of thesmall bumps 51, is underfilled with a resin to form a sealedportion 53. - In the[0283]
CSP 30 shown in FIG. 28,BGA 40 shown in FIG. 29 andBGA 50 shown in FIG. 30, too, the terminal pitch-expandingwirings bump electrodes semiconductor chip 1, which, therefore, can be mounted by reflowing on themodule board 2 or the like. - Briefly described below are the advantages obtained by the representative examples of the inventions disclosed in this application.[0284]
- (1) Upon mounting the protruded terminal semiconductor devices on the module board of the memory-module, it becomes possible to greatly decrease the mounting areas compared to mounting the lead terminal semiconductor devices having semiconductor chips that are individually treated. This makes it possible to effect the mounting requiring the least areas so far as the semiconductor chips are mounted and, hence, to greatly increase the module capacity.[0285]
- (2) The WPPs are mounted as the protruded terminal semiconductor devices while expanding the pitch among the bump electrodes which are the external terminals to be wider than the pitch among those of the flip chips, making it possible to expand the wiring rules on the module board and, hence, to realize a highly densely mounted memory-module suppressing the cost.[0286]
- (3) The bonding electrodes of the semiconductor chip can be connected to the bump electrodes which are the external terminals of the WPPs through wirings of lengths shorter than those of the SMD parts such as TSOPS. This enables the memory-module to cope with high-speed operations and, hence, to cope with high-speed buses.[0287]
- (4) Since the WPPs in the memory-module are sealed by underfilling, the whole chip surfaces are strongly secured to exhibit improved shock resistance. Therefore, the chips are prevented from being cracked.[0288]
- (5) The WPPs are sealed by underfilling and are mounted on the module board in a state where the back surfaces of the semiconductor chips are exposed and, besides, the whole main surfaces of the semiconductor chips are secured to the module board by underfill-sealing, enabling the heat resistance of the memory-module to be decreased. As a result, the memory-module exhibits improved heat-radiating performance and extended life.[0289]
Claims (24)
1. A memory-module comprising:
protruded terminal semiconductor devices having protruded terminals as external terminals, mounted via the protruded terminals, and are provided with wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes of semiconductor chips;
lead terminal semiconductor devices having outer leads as external terminals, and mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips; and
a module board supporting the protruded terminal semiconductor devices and the lead terminal semiconductor devices;
wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices are mounted in a mixed manner on the module board.
2. A memory-module comprising:
protruded terminal semiconductor devices having protruded terminals as external terminals, mounted via the protruded terminals, and are provided with rewirings which are wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes in the areas of semiconductor chips;
lead terminal semiconductor devices having outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips; and
a module board supporting the protruded terminal semiconductor devices and the lead terminal semiconductor devices;
wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices are mounted in a mixed manner on the module board.
3. A memory-module according toclaim 2 , wherein DRAMs are mounted as the protruded terminal semiconductor devices, registers and frequency control means are mounted as the lead terminal semiconductor devices, and the protruded terminal semiconductor devices are arranged on both sides with the registers and the frequency control means being sandwiched therebetween.
4. A memory-module according toclaim 2 , wherein DRAMs and nonvolatile read-only memories are mounted as the protruded terminal semiconductor devices, the DRAMs being sealed with a resin that is underfilled between the semiconductor device bodies and the module board, and the nonvolatile read-only memories being allowed to be removed from the module board.
5. A memory-module according toclaim 2 , wherein the semiconductor chips incorporated in the protruded terminal semiconductor devices are the DRAMs having a rectangular shape on a plane, a free space without protruded terminals is formed near the centers of the DRAMs in the lengthwise direction, capacitors are mounted neighboring the free space of the semiconductor chips, and power source wirings for the capacitors are formed on the surface layer or on the inner layer of the module board facing the free space of the semiconductor chip.
6. A memory-module according toclaim 1 , wherein a plurality of the protruded terminal semiconductor devices are mounted in a matrix arrangement, and memory selection means are mounted in a plural number being corresponded to the rows or the columns, the memory selection means being the lead terminal semiconductor devices that work to switch the connection of input/output signals of the plurality of protruded terminal semiconductor devices for every the row or the column.
7. A memory-module according toclaim 2 , wherein a plurality of the protruded terminal semiconductor devices are mounted in a matrix arrangement, and memory selection means are mounted in a plural number being corresponded to the rows or the columns, the memory selection means being the lead terminal semiconductor devices that work to switch the connection of input/output signals of the plurality of protruded terminal semiconductor devices for every the row or the column.
8. A memory-module according toclaim 2 , wherein a plurality of the protruded terminal semiconductor devices are provided with a group of common protruded terminals that are connected in common to the protruded terminal semiconductor devices and a group of independent protruded terminals that are independently connected to the protruded terminal semiconductor devices, the plurality of protruded terminal semiconductor devices having the group of independent protruded terminals arranged at the end on one side of the semiconductor device bodies are mounted on the module board with their group of independent protruded terminals being faced to the side of the connection terminals that are the external terminals of the module board, and wirings are formed on the module board to connect the group of common protruded terminals of the plurality of the protruded terminal semiconductor devices.
9. A memory-module according toclaim 2 , wherein the plurality of the protruded terminal semiconductor devices are arranged in a sequence maintaining an equal pitch on the module board, and the lead terminal semiconductor devices are mounted near the protruded terminal semiconductor device.
10. A memory-module according toclaim 2 , wherein the plurality of the protruded terminal semiconductor devices are arranged in groups each consisting of two semiconductor devices or four semiconductor devices in a matrix arrangement of two rows and two columns on the module board.
11. A memory-module according toclaim 2 , wherein the lead terminal semiconductor devices are mounted on the module board on the side of the connection terminals which are the external terminals, and the protruded terminal semiconductor devices are mounted on the module board on the side opposite to the connection terminals being sealed with a resin that is underfilled between the semiconductor device bodies and the module board.
12. A memory-module according toclaim 2 , wherein the protruded terminal semiconductor devices are mounted at the peripheries along the two opposing sides or at four corners of the semiconductor device bodies by being sealed with a resin that is underfilled between the semiconductor device bodies and the module board.
13. A memory-module according toclaim 2 , wherein the plurality of the protruded terminal semiconductor devices are mounted being divided into groups each consisting of a plurality of devices on a plurality of regions of the module board along the direction in which are arranged a plurality of connection terminals that are the external terminals, the plurality of the protruded terminal semiconductor devices in each region are sealed in a continuing manner with a resin that is underfilled between the semiconductor device bodies and the module board, and non-mounting portions are formed on both sides thereof.
14. A method of manufacturing a memory-module comprising:
a step for preparing protruded terminal semiconductor devices having protruded terminals as external terminals, and wiring portions for expanding the pitch of the protruded terminals to be wider than the pitch of the bonding electrodes of semiconductor chips;
a step for preparing lead terminal semiconductor devices having outer leads which are the external terminals electrically connected to the bonding electrodes of the semiconductor chips;
a step for arranging the protruded terminal semiconductor devices and the lead terminal semiconductor devices on a module board; and
a step for simultaneously reflowing the protruded terminal semiconductor devices and the lead terminal semiconductor devices to mount them on the module board;
wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices are mounted in a mixed manner on the module board.
15. A method of manufacturing a memory-module comprising:
a step for preparing protruded terminal semiconductor devices of a chip size having protruded terminals as external terminals, and rewirings which are wiring portions for expanding the pitch of the protruded terminals to be wider than the pitch of the bonding electrodes in the areas of semiconductor chips;
a step for preparing lead terminal semiconductor devices having outer leads which are the external terminals electrically connected to the bonding electrodes of the semiconductor chips;
a step for arranging the protruded terminal semiconductor devices and the lead terminal semiconductor devices on a module board; and
a step for simultaneously reflowing the protruded terminal semiconductor devices and the lead terminal semiconductor devices to mount them on the module board;
wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices are mounted in a mixed manner on the module board.
16. A method of manufacturing a memory-module according toclaim 15 , wherein the plurality of the protruded terminal semiconductor devices are mounted in a sequence maintaining an equal pitch on the module board, and an underfiller resin is linearly applied onto the plurality of protruded terminal semiconductor devices arranged in a sequence to effect the sealing between the semiconductor device bodies of the plurality of protruded terminal semiconductor devices and the module board.
17. A method of manufacturing a memory-module according toclaim 15 , wherein the plurality of the protruded terminal semiconductor devices are mounted on the module board in groups each consisting of two semiconductor devices or four semiconductor devices in a matrix arrangement of two rows and two columns, and an underfiller resin is applied onto the outer peripheries of the plurality of protruded terminal semiconductor devices along the long sides thereof to effect the sealing between the semiconductor device bodies of the plurality of protruded terminal semiconductor devices and the module board.
18. A method of manufacturing a memory-module according toclaim 15 , wherein the plurality of the protruded terminal semiconductor devices are mounted on the module board in groups each consisting of two semiconductor devices or four semiconductor devices in a matrix arrangement of two rows and two columns, and an underfiller resin is applied onto the outer peripheries of the two opposing outer sides of the semiconductor device bodies of the plurality of protruded terminal semiconductor devices to effect the sealing between the semiconductor device bodies of the plurality of protruded terminal semiconductor devices and the module board.
19. A method of manufacturing a memory-module comprising:
a step for preparing protruded terminal semiconductor devices of a chip size having protruded terminals as external terminals, and rewirings which are wiring portions for expanding the pitch of the protruded terminals to be wider than the pitch of the bonding electrodes in the areas of semiconductor chips;
a step for preparing lead terminal semiconductor devices having outer leads which are the external terminals electrically connected to the bonding electrodes of the semiconductor chips;
a step for arranging the protruded terminal semiconductor devices and the lead terminal semiconductor devices on a module board, and reflowing the protruded terminal semiconductor devices and the lead terminal semiconductor devices to mount them on both the front and back surfaces of the module board; and
a step for applying an underfiller resin onto the protruded terminal semiconductor devices on both the front and back surfaces of the module board one surface by one surface to effect the sealing between the semiconductor device bodies of the protruded terminal semiconductor devices and the module board, and heating both the front and back surfaces of the module board at one time to simultaneously cure the resin on both the front and back surfaces;
wherein the protruded terminal semiconductor devices and the lead terminal semiconductor devices are mounted in a mixed manner on the module board.
20. A memory-module according toclaim 8 , wherein a gap among the common protruded terminals is larger than a gap among the independent protruded terminals.
21. A memory-module comprising:
a board and a plurality of semiconductor devices mounted thereon, the semiconductor devices including protruded terminal semiconductor devices and lead terminal semiconductor devices which are mounted thereon in a mixed manner;
the protruded terminal semiconductor devices including a semiconductor chip with a plurality of bonding pads on the main surface thereof, wiring portions for expanding the pitch among the bonding pads to be wider than the pitch among the bonding pads, and a plurality of protruded terminals formed at the ends of the wiring portions maintaining a pitch wider than the pitch among the bonding pads, the semiconductor chip being mounted on the board via the protruded terminals; and
the lead terminal semiconductor devices including a semiconductor chip with a plurality of bonding pads on the main surface thereof, a plurality of leads each being constituted by an inner portion and an outer portion, wires for electrically connecting the bonding pads to the inner portions of the leads, and a sealing member for sealing the semiconductor chip, the inner portions and the wires, and the lead terminal semiconductor devices being mounted on the board via the outer portions of the leads protruding beyond the sealing member.
22. A memory-module according toclaim 1 , wherein the gaps between the protruded terminal semiconductor devices and the board are sealed with a resin.
23. A memory-module comprising:
a board and a plurality of semiconductor devices mounted thereon, the semiconductor devices including protruded terminal semiconductor devices and lead terminal semiconductor devices which are mounted thereon in a mixed manner;
the protruded terminal semiconductor devices including a semiconductor chip with a plurality of bonding pads on the main surface thereof, rewirings which are wiring portions for expanding the pitch among the bonding pads to be wider than the pitch among the bonding pads, and a plurality of protruded terminals formed at the ends of the rewirings maintaining a pitch wider than the pitch among the bonding pads on a main surface region of the semiconductor chip, the semiconductor chip being mounted on the board via the protruded terminals; and
the lead terminal semiconductor devices including a semiconductor chip with a plurality of bonding pads on the main surface thereof, a plurality of leads each being constituted by an inner portion and an outer portion, wires for electrically connecting the bonding pads to the inner portions of the leads, and a sealing member for sealing the semiconductor chip, the inner portions and the wires, and the lead terminal semiconductor devices being mounted on the board via the outer portions of the leads protruding beyond the sealing member.
24. A memory-module according toclaim 2 , wherein the gaps between the protruded terminal semiconductor devices and the board are sealed with a resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/029,979US20030116835A1 (en) | 1999-02-26 | 2001-12-31 | Memory-module and a method of manufacturing the same |
Applications Claiming Priority (4)
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| JP11-50292 | 1999-02-26 | ||
| JP05029299AJP3914651B2 (en) | 1999-02-26 | 1999-02-26 | Memory module and manufacturing method thereof |
| US49961800A | 2000-02-07 | 2000-02-07 | |
| US10/029,979US20030116835A1 (en) | 1999-02-26 | 2001-12-31 | Memory-module and a method of manufacturing the same |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US49961800AContinuation | 1999-02-26 | 2000-02-07 |
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| US20030116835A1true US20030116835A1 (en) | 2003-06-26 |
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| US10/326,149Expired - Fee RelatedUS7102221B2 (en) | 1999-02-26 | 2002-12-23 | Memory-Module with an increased density for mounting semiconductor chips |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/326,149Expired - Fee RelatedUS7102221B2 (en) | 1999-02-26 | 2002-12-23 | Memory-Module with an increased density for mounting semiconductor chips |
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| US (2) | US20030116835A1 (en) |
| JP (1) | JP3914651B2 (en) |
| KR (1) | KR100616055B1 (en) |
| CN (1) | CN1222037C (en) |
| TW (1) | TW498505B (en) |
Cited By (43)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040161865A1 (en)* | 2003-02-19 | 2004-08-19 | Yu-Lung Yu | Wafer level testing and bumping process |
| US7033861B1 (en) | 2005-05-18 | 2006-04-25 | Staktek Group L.P. | Stacked module systems and method |
| US20060091529A1 (en)* | 2004-09-03 | 2006-05-04 | Staktek Group L.P. | High capacity thin module system and method |
| US20060125067A1 (en)* | 2004-09-03 | 2006-06-15 | Staktek Group L.P. | Flex circuit constructions for high capacity circuit module systems and methods |
| US7193310B2 (en) | 2001-12-14 | 2007-03-20 | Stuktek Group L.P. | Stacking system and method |
| US7202555B2 (en) | 2001-10-26 | 2007-04-10 | Staktek Group L.P. | Pitch change and chip scale stacking system and method |
| US20070091704A1 (en)* | 2005-10-26 | 2007-04-26 | Siva Raghuram | Memory module with an electronic printed circuit board and a plurality of semiconductor chips of the same type |
| US20070111606A1 (en)* | 2004-09-03 | 2007-05-17 | Staktek Group L.P., A Texas Limited Partnership | Buffered Thin Module System and Method |
| US20070115017A1 (en)* | 2004-09-03 | 2007-05-24 | Staktek Group L.P. | Thin Module System and Method |
| US7289327B2 (en) | 2006-02-27 | 2007-10-30 | Stakick Group L.P. | Active cooling methods and apparatus for modules |
| US7304382B2 (en) | 2006-01-11 | 2007-12-04 | Staktek Group L.P. | Managed memory component |
| US7324352B2 (en) | 2004-09-03 | 2008-01-29 | Staktek Group L.P. | High capacity thin module system and method |
| US7423885B2 (en) | 2004-09-03 | 2008-09-09 | Entorian Technologies, Lp | Die module system |
| US7442050B1 (en) | 2005-08-29 | 2008-10-28 | Netlist, Inc. | Circuit card with flexible connection for memory module with heat spreader |
| US7446410B2 (en) | 2004-09-03 | 2008-11-04 | Entorian Technologies, Lp | Circuit module with thermal casing systems |
| US7451421B1 (en) | 2005-11-01 | 2008-11-11 | Xilinx, Inc. | Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies |
| US7468553B2 (en) | 2006-10-20 | 2008-12-23 | Entorian Technologies, Lp | Stackable micropackages and stacked modules |
| US7468893B2 (en)* | 2004-09-03 | 2008-12-23 | Entorian Technologies, Lp | Thin module system and method |
| US20080316712A1 (en)* | 2004-04-09 | 2008-12-25 | Pauley Robert S | High density module having at least two substrates and at least one thermally conductive layer therebetween |
| US7491576B1 (en)* | 2005-11-01 | 2009-02-17 | Xilinx, Inc. | Yield-enhancing methods of providing a family of scaled integrated circuits |
| US7508058B2 (en) | 2006-01-11 | 2009-03-24 | Entorian Technologies, Lp | Stacked integrated circuit module |
| US7508069B2 (en) | 2006-01-11 | 2009-03-24 | Entorian Technologies, Lp | Managed memory component |
| US7511969B2 (en) | 2006-02-02 | 2009-03-31 | Entorian Technologies, Lp | Composite core circuit module system and method |
| US7522421B2 (en) | 2004-09-03 | 2009-04-21 | Entorian Technologies, Lp | Split core circuit module |
| US20090109642A1 (en)* | 2007-10-26 | 2009-04-30 | Samsung Electronics Co., Ltd. | Semiconductor modules and electronic devices using the same |
| US7542297B2 (en) | 2004-09-03 | 2009-06-02 | Entorian Technologies, Lp | Optimized mounting area circuit module system and method |
| US7576995B2 (en) | 2005-11-04 | 2009-08-18 | Entorian Technologies, Lp | Flex circuit apparatus and method for adding capacitance while conserving circuit board surface area |
| US7579687B2 (en) | 2004-09-03 | 2009-08-25 | Entorian Technologies, Lp | Circuit module turbulence enhancement systems and methods |
| US7595550B2 (en) | 2001-10-26 | 2009-09-29 | Entorian Technologies, Lp | Flex-based circuit module |
| US7606049B2 (en)* | 2004-09-03 | 2009-10-20 | Entorian Technologies, Lp | Module thermal management system and method |
| US7605454B2 (en) | 2006-01-11 | 2009-10-20 | Entorian Technologies, Lp | Memory card and method for devising |
| US7606050B2 (en) | 2004-09-03 | 2009-10-20 | Entorian Technologies, Lp | Compact module system and method |
| US7606040B2 (en) | 2004-09-03 | 2009-10-20 | Entorian Technologies, Lp | Memory module system and method |
| US7608920B2 (en) | 2006-01-11 | 2009-10-27 | Entorian Technologies, Lp | Memory card and method for devising |
| US7619893B1 (en) | 2006-02-17 | 2009-11-17 | Netlist, Inc. | Heat spreader for electronic modules |
| US20100000773A1 (en)* | 2006-09-22 | 2010-01-07 | Matsushita Electric Industrial Co., Ltd. | Electronic component mounting structure |
| US7656678B2 (en) | 2001-10-26 | 2010-02-02 | Entorian Technologies, Lp | Stacked module systems |
| US7760513B2 (en) | 2004-09-03 | 2010-07-20 | Entorian Technologies Lp | Modified core for circuit module system and method |
| US8018723B1 (en) | 2008-04-30 | 2011-09-13 | Netlist, Inc. | Heat dissipation for electronic modules |
| US20120133055A1 (en)* | 2010-11-25 | 2012-05-31 | Renesas Electronics Corporation | Semiconductor chip and semiconductor device |
| US20120250264A1 (en)* | 2011-03-28 | 2012-10-04 | Elpida Memory, Inc. | Memory module having memory chip and register buffer |
| US9372956B1 (en) | 2014-11-10 | 2016-06-21 | Xilinx, Inc. | Increased usable programmable device dice |
| US12041719B2 (en) | 2021-03-23 | 2024-07-16 | Kioxia Corporation | Memory system |
Families Citing this family (48)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW577152B (en) | 2000-12-18 | 2004-02-21 | Hitachi Ltd | Semiconductor integrated circuit device |
| DE60305006T2 (en)* | 2003-05-08 | 2006-11-02 | Infineon Technologies Ag | CIRCUIT MODULE WITH CLOSED GROUPS OF OVERLAPPING SEMICONDUCTOR CHIPS |
| JP4689202B2 (en)* | 2004-07-07 | 2011-05-25 | ルネサスエレクトロニクス株式会社 | Driving device and display device |
| US7547213B2 (en)* | 2004-08-26 | 2009-06-16 | Micron Technology, Inc. | Memory modules and methods for manufacturing memory modules |
| KR100702016B1 (en)* | 2005-02-02 | 2007-03-30 | 삼성전자주식회사 | Printed Circuit Board of Double Sided Memory Module and Double Sided Memory Module Using Same |
| US7332818B2 (en)* | 2005-05-12 | 2008-02-19 | Endicott Interconnect Technologies, Inc. | Multi-chip electronic package with reduced line skew and circuitized substrate for use therein |
| US7170183B1 (en)* | 2005-05-13 | 2007-01-30 | Amkor Technology, Inc. | Wafer level stacked package |
| KR100671950B1 (en)* | 2005-06-17 | 2007-01-24 | 주식회사 유니세미콘 | Stack package |
| KR100715287B1 (en) | 2006-04-26 | 2007-05-08 | 삼성전자주식회사 | Semiconductor memory module |
| US7473568B2 (en)* | 2006-05-17 | 2009-01-06 | Kingston Technology Corp. | Memory-module manufacturing method with memory-chip burn-in and full functional testing delayed until module burn-in |
| JP4389228B2 (en)* | 2006-11-29 | 2009-12-24 | エルピーダメモリ株式会社 | Memory module |
| KR101817328B1 (en)* | 2011-02-01 | 2018-02-22 | 삼성전자주식회사 | Method of manufacturing semiconductor module |
| JP5396415B2 (en) | 2011-02-23 | 2014-01-22 | 株式会社東芝 | Semiconductor device |
| US8823165B2 (en) | 2011-07-12 | 2014-09-02 | Invensas Corporation | Memory module in a package |
| US8502390B2 (en) | 2011-07-12 | 2013-08-06 | Tessera, Inc. | De-skewed multi-die packages |
| US8513817B2 (en) | 2011-07-12 | 2013-08-20 | Invensas Corporation | Memory module in a package |
| WO2013052345A1 (en)* | 2011-10-03 | 2013-04-11 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
| US8653646B2 (en) | 2011-10-03 | 2014-02-18 | Invensas Corporation | Stub minimization using duplicate sets of terminals for wirebond assemblies without windows |
| US8436457B2 (en) | 2011-10-03 | 2013-05-07 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
| US8405207B1 (en) | 2011-10-03 | 2013-03-26 | Invensas Corporation | Stub minimization for wirebond assemblies without windows |
| US8436477B2 (en) | 2011-10-03 | 2013-05-07 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate |
| JP5947904B2 (en) | 2011-10-03 | 2016-07-06 | インヴェンサス・コーポレイション | Stub minimization for multi-die wirebond assemblies with orthogonal windows |
| TWI515864B (en) | 2011-10-03 | 2016-01-01 | 英帆薩斯公司 | Stub minimization with terminal grids offset from center of package |
| US8441111B2 (en) | 2011-10-03 | 2013-05-14 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
| US8525327B2 (en) | 2011-10-03 | 2013-09-03 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
| KR101894823B1 (en) | 2011-10-03 | 2018-09-04 | 인벤사스 코포레이션 | Stub minimization for multi-die wirebond assemblies with parallel windows |
| KR101964045B1 (en)* | 2012-04-12 | 2019-04-01 | 삼성전자주식회사 | Semiconductor Memory Modules and Methods of Fabricating the Same |
| US8982566B2 (en)* | 2012-05-16 | 2015-03-17 | Nanya Technology Corporation | Memory module and electrical connector for the same |
| US8848392B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support module and microelectronic assembly |
| US8848391B2 (en) | 2012-08-27 | 2014-09-30 | Invensas Corporation | Co-support component and microelectronic assembly |
| US8787034B2 (en) | 2012-08-27 | 2014-07-22 | Invensas Corporation | Co-support system and microelectronic assembly |
| US9368477B2 (en) | 2012-08-27 | 2016-06-14 | Invensas Corporation | Co-support circuit panel and microelectronic packages |
| US9070423B2 (en) | 2013-06-11 | 2015-06-30 | Invensas Corporation | Single package dual channel memory with co-support |
| US9123555B2 (en) | 2013-10-25 | 2015-09-01 | Invensas Corporation | Co-support for XFD packaging |
| US9281296B2 (en) | 2014-07-31 | 2016-03-08 | Invensas Corporation | Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design |
| US9691437B2 (en) | 2014-09-25 | 2017-06-27 | Invensas Corporation | Compact microelectronic assembly having reduced spacing between controller and memory packages |
| JP6545447B2 (en)* | 2014-10-31 | 2019-07-17 | 川崎重工業株式会社 | Control circuit board and robot control device |
| US11257527B2 (en) | 2015-05-06 | 2022-02-22 | SK Hynix Inc. | Memory module with battery and electronic system having the memory module |
| KR20160131171A (en) | 2015-05-06 | 2016-11-16 | 에스케이하이닉스 주식회사 | Memory module including battery |
| KR102433013B1 (en) | 2015-08-11 | 2022-08-17 | 삼성전자주식회사 | Memory module and solid state disk having the same |
| US9484080B1 (en) | 2015-11-09 | 2016-11-01 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
| US9679613B1 (en) | 2016-05-06 | 2017-06-13 | Invensas Corporation | TFD I/O partition for high-speed, high-density applications |
| US10558525B2 (en)* | 2016-06-30 | 2020-02-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of correcting errors in a memory array and a system for implementing the same |
| US10068866B2 (en)* | 2016-09-29 | 2018-09-04 | Intel Corporation | Integrated circuit package having rectangular aspect ratio |
| US10109941B1 (en)* | 2017-06-30 | 2018-10-23 | Intel Corporation | Stepped slot connector to enable low height platforms |
| JP6381769B2 (en)* | 2017-11-22 | 2018-08-29 | 東芝メモリ株式会社 | Semiconductor memory device |
| KR102781129B1 (en) | 2020-08-06 | 2025-03-12 | 삼성전자주식회사 | Semiconductor chip module |
| US11984391B1 (en)* | 2023-10-13 | 2024-05-14 | Auradine, Inc. | Circuit board assembly having circuit board with adjacent chips immersed in dielectric liquid and method of making the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5604379A (en)* | 1994-09-21 | 1997-02-18 | Sharp Kabushiki Kaisha | Semiconductor device having external electrodes formed in concave portions of an anisotropic conductive film |
| US5925931A (en)* | 1996-10-31 | 1999-07-20 | Casio Computer Co., Ltd. | Semiconductor device having interconnect lines and connection electrodes formed in groove portions of an insulating layer |
| US6038135A (en)* | 1995-06-30 | 2000-03-14 | Fujitsu Limited | Wiring board and semiconductor device |
| US6287893B1 (en)* | 1997-10-20 | 2001-09-11 | Flip Chip Technologies, L.L.C. | Method for forming chip scale package |
| US6344696B2 (en)* | 1997-10-03 | 2002-02-05 | Nec Corporation | Chip size package semiconductor device and method of forming the same |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4774635A (en)* | 1986-05-27 | 1988-09-27 | American Telephone And Telegraph Company At&T Bell Laboratories | Semiconductor package with high density I/O lead connection |
| JP2645068B2 (en) | 1988-04-08 | 1997-08-25 | 株式会社東芝 | Memory module |
| US5541448A (en)* | 1991-10-16 | 1996-07-30 | Texas Instruments Inc. | Electronic circuit card |
| JP3242765B2 (en) | 1993-09-09 | 2001-12-25 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| US6111317A (en)* | 1996-01-18 | 2000-08-29 | Kabushiki Kaisha Toshiba | Flip-chip connection type semiconductor integrated circuit device |
| JP3718008B2 (en)* | 1996-02-26 | 2005-11-16 | 株式会社日立製作所 | Memory module and manufacturing method thereof |
| US5661677A (en)* | 1996-05-15 | 1997-08-26 | Micron Electronics, Inc. | Circuit and method for on-board programming of PRD Serial EEPROMS |
| US5719449A (en)* | 1996-09-30 | 1998-02-17 | Lucent Technologies Inc. | Flip-chip integrated circuit with improved testability |
| US6008538A (en)* | 1996-10-08 | 1999-12-28 | Micron Technology, Inc. | Method and apparatus providing redundancy for fabricating highly reliable memory modules |
| US5841686A (en)* | 1996-11-22 | 1998-11-24 | Ma Laboratories, Inc. | Dual-bank memory module with shared capacitors and R-C elements integrated into the module substrate |
| US5923611A (en)* | 1996-12-20 | 1999-07-13 | Micron Technology, Inc. | Memory having a plurality of external clock signal inputs |
| JP3397067B2 (en) | 1997-01-24 | 2003-04-14 | 株式会社日立製作所 | CPU module and information processing device |
| US6069793A (en)* | 1997-01-24 | 2000-05-30 | Hitachi, Ltd. | Circuit module and information processing apparatus |
| US5982654A (en)* | 1998-07-20 | 1999-11-09 | Micron Technology, Inc. | System for connecting semiconductor devices |
| JP2000100814A (en)* | 1998-09-18 | 2000-04-07 | Hitachi Ltd | Semiconductor device |
| US6347394B1 (en)* | 1998-11-04 | 2002-02-12 | Micron Technology, Inc. | Buffering circuit embedded in an integrated circuit device module used for buffering clocks and other input signals |
| JP2000164792A (en) | 1998-11-30 | 2000-06-16 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
| US6307769B1 (en)* | 1999-09-02 | 2001-10-23 | Micron Technology, Inc. | Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices |
- 1999
- 1999-02-26JPJP05029299Apatent/JP3914651B2/ennot_activeExpired - Fee Related
- 2000
- 2000-02-21TWTW089102969Apatent/TW498505B/ennot_activeIP Right Cessation
- 2000-02-24KRKR1020000009005Apatent/KR100616055B1/ennot_activeExpired - Fee Related
- 2000-02-25CNCNB00102664XApatent/CN1222037C/ennot_activeExpired - Fee Related
- 2001
- 2001-12-31USUS10/029,979patent/US20030116835A1/ennot_activeAbandoned
- 2002
- 2002-12-23USUS10/326,149patent/US7102221B2/ennot_activeExpired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5604379A (en)* | 1994-09-21 | 1997-02-18 | Sharp Kabushiki Kaisha | Semiconductor device having external electrodes formed in concave portions of an anisotropic conductive film |
| US6038135A (en)* | 1995-06-30 | 2000-03-14 | Fujitsu Limited | Wiring board and semiconductor device |
| US5925931A (en)* | 1996-10-31 | 1999-07-20 | Casio Computer Co., Ltd. | Semiconductor device having interconnect lines and connection electrodes formed in groove portions of an insulating layer |
| US6344696B2 (en)* | 1997-10-03 | 2002-02-05 | Nec Corporation | Chip size package semiconductor device and method of forming the same |
| US6287893B1 (en)* | 1997-10-20 | 2001-09-11 | Flip Chip Technologies, L.L.C. | Method for forming chip scale package |
Cited By (71)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7202555B2 (en) | 2001-10-26 | 2007-04-10 | Staktek Group L.P. | Pitch change and chip scale stacking system and method |
| US7656678B2 (en) | 2001-10-26 | 2010-02-02 | Entorian Technologies, Lp | Stacked module systems |
| US7595550B2 (en) | 2001-10-26 | 2009-09-29 | Entorian Technologies, Lp | Flex-based circuit module |
| US7193310B2 (en) | 2001-12-14 | 2007-03-20 | Stuktek Group L.P. | Stacking system and method |
| US6869809B2 (en)* | 2003-02-19 | 2005-03-22 | Via Technologies, Inc. | Wafer level testing and bumping process |
| US20040161865A1 (en)* | 2003-02-19 | 2004-08-19 | Yu-Lung Yu | Wafer level testing and bumping process |
| US20080316712A1 (en)* | 2004-04-09 | 2008-12-25 | Pauley Robert S | High density module having at least two substrates and at least one thermally conductive layer therebetween |
| US8345427B2 (en) | 2004-04-09 | 2013-01-01 | Netlist, Inc. | Module having at least two surfaces and at least one thermally conductive layer therebetween |
| US20110110047A1 (en)* | 2004-04-09 | 2011-05-12 | Netlist, Inc. | Module having at least two surfaces and at least one thermally conductive layer therebetween |
| US7839645B2 (en) | 2004-04-09 | 2010-11-23 | Netlist, Inc. | Module having at least two surfaces and at least one thermally conductive layer therebetween |
| US20100110642A1 (en)* | 2004-04-09 | 2010-05-06 | Netlist, Inc. | Module having at least two surfaces and at least one thermally conductive layer therebetween |
| US7630202B2 (en) | 2004-04-09 | 2009-12-08 | Netlist, Inc. | High density module having at least two substrates and at least one thermally conductive layer therebetween |
| US7579687B2 (en) | 2004-09-03 | 2009-08-25 | Entorian Technologies, Lp | Circuit module turbulence enhancement systems and methods |
| US20060091529A1 (en)* | 2004-09-03 | 2006-05-04 | Staktek Group L.P. | High capacity thin module system and method |
| US7423885B2 (en) | 2004-09-03 | 2008-09-09 | Entorian Technologies, Lp | Die module system |
| US20060125067A1 (en)* | 2004-09-03 | 2006-06-15 | Staktek Group L.P. | Flex circuit constructions for high capacity circuit module systems and methods |
| US7443023B2 (en)* | 2004-09-03 | 2008-10-28 | Entorian Technologies, Lp | High capacity thin module system |
| US7446410B2 (en) | 2004-09-03 | 2008-11-04 | Entorian Technologies, Lp | Circuit module with thermal casing systems |
| US7768796B2 (en) | 2004-09-03 | 2010-08-03 | Entorian Technologies L.P. | Die module system |
| US7459784B2 (en) | 2004-09-03 | 2008-12-02 | Entorian Technologies, Lp | High capacity thin module system |
| US7760513B2 (en) | 2004-09-03 | 2010-07-20 | Entorian Technologies Lp | Modified core for circuit module system and method |
| US7468893B2 (en)* | 2004-09-03 | 2008-12-23 | Entorian Technologies, Lp | Thin module system and method |
| US7324352B2 (en) | 2004-09-03 | 2008-01-29 | Staktek Group L.P. | High capacity thin module system and method |
| US7480152B2 (en)* | 2004-09-03 | 2009-01-20 | Entorian Technologies, Lp | Thin module system and method |
| US7737549B2 (en) | 2004-09-03 | 2010-06-15 | Entorian Technologies Lp | Circuit module with thermal casing systems |
| US20070111606A1 (en)* | 2004-09-03 | 2007-05-17 | Staktek Group L.P., A Texas Limited Partnership | Buffered Thin Module System and Method |
| US20070115017A1 (en)* | 2004-09-03 | 2007-05-24 | Staktek Group L.P. | Thin Module System and Method |
| US7626259B2 (en) | 2004-09-03 | 2009-12-01 | Entorian Technologies, Lp | Heat sink for a high capacity thin module system |
| US7511968B2 (en)* | 2004-09-03 | 2009-03-31 | Entorian Technologies, Lp | Buffered thin module system and method |
| US7522425B2 (en) | 2004-09-03 | 2009-04-21 | Entorian Technologies, Lp | High capacity thin module system and method |
| US7522421B2 (en) | 2004-09-03 | 2009-04-21 | Entorian Technologies, Lp | Split core circuit module |
| US7616452B2 (en)* | 2004-09-03 | 2009-11-10 | Entorian Technologies, Lp | Flex circuit constructions for high capacity circuit module systems and methods |
| US7542297B2 (en) | 2004-09-03 | 2009-06-02 | Entorian Technologies, Lp | Optimized mounting area circuit module system and method |
| US7606042B2 (en) | 2004-09-03 | 2009-10-20 | Entorian Technologies, Lp | High capacity thin module system and method |
| US7606040B2 (en) | 2004-09-03 | 2009-10-20 | Entorian Technologies, Lp | Memory module system and method |
| US7606050B2 (en) | 2004-09-03 | 2009-10-20 | Entorian Technologies, Lp | Compact module system and method |
| US7602613B2 (en)* | 2004-09-03 | 2009-10-13 | Entorian Technologies, Lp | Thin module system and method |
| US7606049B2 (en)* | 2004-09-03 | 2009-10-20 | Entorian Technologies, Lp | Module thermal management system and method |
| US7033861B1 (en) | 2005-05-18 | 2006-04-25 | Staktek Group L.P. | Stacked module systems and method |
| US7442050B1 (en) | 2005-08-29 | 2008-10-28 | Netlist, Inc. | Circuit card with flexible connection for memory module with heat spreader |
| US8864500B1 (en) | 2005-08-29 | 2014-10-21 | Netlist, Inc. | Electronic module with flexible portion |
| US7811097B1 (en) | 2005-08-29 | 2010-10-12 | Netlist, Inc. | Circuit with flexible portion |
| US8033836B1 (en) | 2005-08-29 | 2011-10-11 | Netlist, Inc. | Circuit with flexible portion |
| US20070091704A1 (en)* | 2005-10-26 | 2007-04-26 | Siva Raghuram | Memory module with an electronic printed circuit board and a plurality of semiconductor chips of the same type |
| US7375971B2 (en)* | 2005-10-26 | 2008-05-20 | Infineon Technologies Ag | Memory module with an electronic printed circuit board and a plurality of semiconductor chips of the same type |
| US7491576B1 (en)* | 2005-11-01 | 2009-02-17 | Xilinx, Inc. | Yield-enhancing methods of providing a family of scaled integrated circuits |
| US8001511B1 (en) | 2005-11-01 | 2011-08-16 | Xilinx, Inc. | Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies |
| US7451421B1 (en) | 2005-11-01 | 2008-11-11 | Xilinx, Inc. | Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies |
| US7576995B2 (en) | 2005-11-04 | 2009-08-18 | Entorian Technologies, Lp | Flex circuit apparatus and method for adding capacitance while conserving circuit board surface area |
| US7608920B2 (en) | 2006-01-11 | 2009-10-27 | Entorian Technologies, Lp | Memory card and method for devising |
| US7508069B2 (en) | 2006-01-11 | 2009-03-24 | Entorian Technologies, Lp | Managed memory component |
| US7508058B2 (en) | 2006-01-11 | 2009-03-24 | Entorian Technologies, Lp | Stacked integrated circuit module |
| US7605454B2 (en) | 2006-01-11 | 2009-10-20 | Entorian Technologies, Lp | Memory card and method for devising |
| US7304382B2 (en) | 2006-01-11 | 2007-12-04 | Staktek Group L.P. | Managed memory component |
| US7511969B2 (en) | 2006-02-02 | 2009-03-31 | Entorian Technologies, Lp | Composite core circuit module system and method |
| US7839643B1 (en) | 2006-02-17 | 2010-11-23 | Netlist, Inc. | Heat spreader for memory modules |
| US7619893B1 (en) | 2006-02-17 | 2009-11-17 | Netlist, Inc. | Heat spreader for electronic modules |
| US8488325B1 (en) | 2006-02-17 | 2013-07-16 | Netlist, Inc. | Memory module having thermal conduits |
| US7289327B2 (en) | 2006-02-27 | 2007-10-30 | Stakick Group L.P. | Active cooling methods and apparatus for modules |
| US20100000773A1 (en)* | 2006-09-22 | 2010-01-07 | Matsushita Electric Industrial Co., Ltd. | Electronic component mounting structure |
| US8759688B2 (en)* | 2006-09-22 | 2014-06-24 | Panasonic Corporation | Electronic component mounting structure |
| US7468553B2 (en) | 2006-10-20 | 2008-12-23 | Entorian Technologies, Lp | Stackable micropackages and stacked modules |
| US20090109642A1 (en)* | 2007-10-26 | 2009-04-30 | Samsung Electronics Co., Ltd. | Semiconductor modules and electronic devices using the same |
| US8018723B1 (en) | 2008-04-30 | 2011-09-13 | Netlist, Inc. | Heat dissipation for electronic modules |
| US8705239B1 (en) | 2008-04-30 | 2014-04-22 | Netlist, Inc. | Heat dissipation for electronic modules |
| US20120133055A1 (en)* | 2010-11-25 | 2012-05-31 | Renesas Electronics Corporation | Semiconductor chip and semiconductor device |
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| US20120250264A1 (en)* | 2011-03-28 | 2012-10-04 | Elpida Memory, Inc. | Memory module having memory chip and register buffer |
| US9372956B1 (en) | 2014-11-10 | 2016-06-21 | Xilinx, Inc. | Increased usable programmable device dice |
| US12041719B2 (en) | 2021-03-23 | 2024-07-16 | Kioxia Corporation | Memory system |
| TWI865816B (en)* | 2021-03-23 | 2024-12-11 | 日商鎧俠股份有限公司 | Memory system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1222037C (en) | 2005-10-05 |
| KR20000058173A (en) | 2000-09-25 |
| US20030089978A1 (en) | 2003-05-15 |
| KR100616055B1 (en) | 2006-08-28 |
| JP2000252418A (en) | 2000-09-14 |
| CN1264924A (en) | 2000-08-30 |
| US7102221B2 (en) | 2006-09-05 |
| JP3914651B2 (en) | 2007-05-16 |
| TW498505B (en) | 2002-08-11 |
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