US20030112896A1 - Multi-channel communications transceiver - Google Patents

Abstract

A transceiver system according to the present invention transmits data utilizing the baseband and one or more frequency separated transmission bands. A baseband transmitter is combined with one or more transmitters that transmit data into one of the frequency separated transmission bands. A baseband receiver is combined with one or more receivers that receive data from the frequency separated transmission bands. Any combination of modulation systems can be utilized (e.g. PAM for the baseband and QAM for the frequency separated bands). A transceiver circuit or chip according to the present invention includes a transmitter and a receiver and communicates with a corresponding transceiver chip. In some embodiments, one baseband PAM transmitter is combined with one frequency separated QAM transmitter.

Description

RELATED APPLICATIONS
• The present disclosure is a continuation-in-part of U.S. application Ser. No. 10/071,771 to Sreen A. Raghavan, Thulasinath G. Manickam, Peter J. Sallaway, and Gerard E. Taylor, which is a continuation-in-part of U.S. application Ser. No. 09/965,242 to Sreen Raghavan, Thulasinath G. Manickam, and Peter J. Sallaway, filed Sep. 26, 2001, which is a continuation-in-part of U.S. application Ser. No. 09/904,432, by Sreen Raghavan, filed on Jul. 11, 2001, assigned to the same entity as is the present application, each of which are herein incorporated by reference in its entirety.[0001]
BACKGROUND
• 1. Field of the Invention[0002]
• The present invention is related to high-speed communications of data in a communication system and, in particular, to high data rate transmission of data between components in a communication system.[0003]
• 2. Discussion of Related Art[0004]
• Many conventional systems for transmitting data between components within a cabinet or between cabinets of components utilize copper or optical backplanes for transmission of digital data. For example, high data rate transceiver systems are utilized in many backplane environments, including optical switching devices, router systems, switches, chip-to-chip communications and storage area networking switches. Other environments that utilize high speed communication between components include inter-cabinet communications and chip-to-chip communications. Typical separations of components in such systems is between about 0.1 and about 10 meters.[0005]
• Existing techniques utilized in such environments typically use non-return to zero (NRZ) modulation to send and receive information over high-speed backplanes or for high data rate chip-to-chip interconnects. Typically, the transceiver for sending high-speed data over a backplane is called a serializer/deserializer, or SERDES, device.[0006]
• FIG. 1A shows a block diagram of a[0007]backplane environment100. Components101-1 through101-Q are coupled to transmit and receive data through input/output (I/O) ports102-1 through102-Q, respectively, tobackplane110. Conventionally, components101-1 through101-Q are SERDES devices.
• FIG. 1B shows a block diagram of a conventional transmitter portion of one of SERDES devices[0008]101-1 through101-Q on I/O ports102-1 through102-Q, respectively. Parallel data is received in abit encoder105.Bit encoder105 encodes the parallel data, for example by adding redundancy in the input data, to ensure a minimum rate of data transitions in the output data stream. Typical encoding schemes includerate 8/10 (8 bit input to 10 bit output) encoding. The parallel data is serialized in parallel toserial converter106. Output driver107 then receives the serialized data from parallel toserial converter106 and outputs, usually, a differential voltage signal for transmission overbackplane110. In addition, there is typically a phase locked loop (PLL)114 that provides the necessary clock signals forencoder105 and parallel-to-serial converter106. The input signal to PLL114 is a reference clock signal from asystem PLL103.
• FIG. 1C shows a conventional receiver[0009]108 of one of SERDES devices101-1 through101-Q on I/O ports102-1 through102-Q, respectively, of FIG. 1A.Input driver109 receives differential voltage signal frombackplane110 and outputs the analog data signal to clock and data recovery circuit113. Data recovery113 can, in some systems, perform equalization, recover the timing and output a serial bit stream of data to serial-to-parallel converter111. The serial data is input tobit decoder112 which converts the parallel data to parallel decoded data. Clock and data recovery circuit113 also outputs the necessary clock signals to serial-to-parallel converter111 andbit decoder112.
• A[0010]conventional SERDES system100 can enable serial data communication at data rates as high as 2.5 Gbps to 3.125 Gbps over a pair of FR4 copper traces in a copper backplane communication system. One of the biggest problems with existingSERDES systems100 is that they are very bandwidth inefficient, i.e., they require 3.125 GHz of bandwidth to transmit and receive2.5 Gbps of data over a single pair of copper wires. Therefore, it is very difficult to increase the data rates acrossbackplane bus110. Additionally, SERDESsystem100 requires the implementation of a high clock rate (3.125 GHz for 2.5 Gbps data rates) phase locked loop (PLL)114 implemented to transmit data and recover high clock rates in data recovery113. The timing window within which receiver108 needs to determine whether the received symbol indata recovery110 is a 1 or a 0 is about 320 ps for the higher data rate systems. This timing window creates extremely stringent requirements on the design of data recovery113 and PLL114, as they must have very low peak-to-peak jitter.
• [0011]Conventional SERDES system100 also suffers from other problems, including eye closure due to intersymbol interference (ISI) from the dispersion introduced bybackplane110. The ISI is a direct result of the fact that the copper traces ofbackplane110 attenuate higher frequency components in the transmitted signals more than the lower frequency components in the transmitted signal. Therefore, the higher the data rate the more ISI suffered by the transmitted data. In addition, electrical connectors and electrical connections (e.g., vias and other components) used in SERDESdevice100 cause reflections, which also cause ISI.
• To overcome these problems, equalization must be performed on the received signal in data recovery[0012]113. However, in existing very high data-rate communication systems, equalization is very difficult to perform, if not impossible due to the high baud rate. A more commonly utilized technique for combating ISI is known as “pre-emphasis”, or pre-equalization, performed inbit encoder105 and output driver107 during transmission. In some conventional systems, the amplitude of the low-frequencies in the transmitted signal is attenuated to compensate for the higher attenuation of the high frequency component by the transmission medium ofbus110. While this makes the receiver more robust to ISI, pre-emphasis reduces the overall noise tolerance of transmission overbackplane110 ofbackplane communication system100 due to the loss of signal-to-noise ratio (SNR). At higher data rates, conventional systems quickly become intractable due to the increased demands.
• Therefore, there is a need for a more robust system for transmitting data between components on a backplane or data bus at very high speeds.[0013]
SUMMARY
• In accordance with the present invention, a data transmission system is presented that allows very high data transmission rates over a data bus that utilizes the signal attenuation properties of the copper based backplane interconnect system. In addition, this transmission scheme does not result in increased intersymbol interference at the receiver despite transmitting data at a very high speed. The data transmission system includes a transmitter system and a receiver system coupled through a transmission medium. The transmitter system receives parallel data having N bits and separates the N bits into (K+1) subsets for transmission into the base band and K frequency separated channels on the transmission medium. The receiver system receives the data from the base band and the K frequency separated channels from the transmission medium and recovers the N parallel bits of data. In some embodiments, the N parallel bits are separated into (K+1) subsets of bits, the (K+1) subsets of bits are encoded into (K+1) symbols, K of which are up-converted to a carrier frequency appropriate to that channel. The summed output signal resulting from the summation of the K up-converted channels and the baseband channel is transmitted over the transmission medium.[0014]
• Transmitted data in each of the (K+1) channels can suffer from inter-symbol interference (ISI) as well as cross-channel interference due to harmonic generation in up-conversion and down-conversion processes in the transmitter and receiver. In accordance with the present invention, a receiver which corrects for cross-channel interference as well as for inter-symbol interference is presented.[0015]
• In some embodiments, the transmitter system includes (K+1) separate transmitters. Each of the (K+1) transmitters receives a subset of the N-bits and maps the subset of bits onto a symbol set. K of the transmitters modulate the symbols with a carrier signal at a frequency separated from that of others of the (K+1) transmitters. The summed signals from each of the (K+1) separate transmitters is transmitted over the transmission medium. The transmission medium can be any medium, including optical, infrared, wireless, twisted copper pair, or copper based backplane interconnect channel.[0016]
• In some embodiments, each of the (K+1) transmitters receives a subset of the N data bits, encodes the subset, maps the encoded subset onto a symbol set appropriate for that transmitter. K of the transmitters, for example, up-convert its analog symbol stream to a carrier frequency assigned to that transmitter. The remaining transmitter transmits into the base band. The output signal from each of the transmitters is then transmitted through the transmission medium to a receiver system having a receiver for recovering the data stream transmitted on each of the carrier frequencies.[0017]
• For example, in some embodiments each of the K up-converting transmitters receives the subset of bits and encodes them with a trellis encoder. One of the transmitters maps its subset of bits into a pulsed amplitude modulation (PAM) symbol set and the remaining K up-converting transmitters each maps its subset onto a quadrature-amplitude modulated (QAM) symbol set. In some embodiments, the symbols output from the QAM mapping are processed through a digital-to-analog converter before being up-converted to a carrier frequency to produce the output signal from the transmitter. The PAM transmitters can utilize a digital-to-analog converter to create the PAM symbol output voltage levels. Any combination of encoding and symbol mapping schemes can be utilized in the (K+1) transmitters.[0018]
• In some embodiments, a PAM channel and one or more QAM channels can be utilized such that there is no cross-channel interference between the QAM channels and the PAM channel. In some embodiments, a single QAM channel combined with a PAM channel can be utilized.[0019]
• Each of the output signals from the (K+1) transmitters are summed for transmission in (K+1) separate transmission channels on the transmission medium. The receiver receives the summed signals, with data transmitted at (K+1) separate channels. In some embodiments, the receiver down-converts the summed signals by the frequency of each of the (K) separate non-baseband channels to recover the symbols transmitted in each of the (K+1) separate channels. The baseband receiver can include a low-pass filter to separate the baseband channel from the higher frequency channels on the transmission medium. The subsets of digital data can then be recovered from the recovered symbols.[0020]
• The receiver system receives the combined signal, separates the signal by carrier frequency, and recovers the bits from each carrier frequency. In some embodiments, the signal received from the transmission medium is received into (K+1) parallel receivers. Each of the (K+1) receivers separates out the signal centered around the carrier frequency allocated to that channel by the transmitter or the baseband signal, equalizes the signal, and decodes the signal to retrieve the subset of the N bits assigned to that corresponding transmitter modulator.[0021]
• As a result, parallel streams of serial data bits are separated into separate subsets which are transmitted on different frequency bands to form separate channels on the transmission medium. Therefore, the data rate and the symbol rate transmitted in each of the separate channels can be much lower than the overall data transmission rate. The lower data rate and symbol rate in each channel provides for simpler receiver processing with many fewer problems (e.g., speed of components utilized for equalization and data recovery) than the high data rate transmissions. In addition, because the symbol rates are lower, the amount of receiver equalization needed on each of the (K+1) channels can be smaller, and can be implemented with simpler equalization structures. Because of the lower symbol rates, receiver signals can be processed with complex, optimal algorithms.[0022]
• A complex cross-channel correction algorithm according to the present invention can also be implemented. The cross-channel correction involves adjusting each of the signals of each of the channels by some portions of the signals from the other channels in order to eliminate the interference. The parameters of the cross-channel correction can be adaptively chosen to optimize receiver performance. In some embodiments, no cross-channel interference occurs between the baseband channel and the K high frequency channels and therefore no cross-channel correction is needed between the baseband channel and the K high frequency channels.[0023]
• Data transmission according to the present invention can utilize any combination of symbol mappings. For example, in some embodiments a baseband transmitter utilizing 4, 8, 16 or 32-PAM symbol mapping can be combined with one or more up-converting transmitters with 16, 32, 64, 128 or 256 QAM symbol mappers, for example. In some embodiments, an encoder can be used to encode any of the subset of bits, for example the most-significant bit before the bits are mapped onto a symbol set. For example, a 10 Gbps transceiver can utilize uncoded (no error correction coded) 16-PAM with baud rate of 1.25 GHz in combination with uncoded 16 QAM with baud rate 1.25 GHz. In another example, 4/5 trellis encoded 32-QAM can be combined with uncoded 16-PAM. In yet another example, uncoded 8-PAM can be combined with five (5) 6/7 trellis encoded 128-QAM to form a 10 Gbps transmission system. Many other examples can be utilized.[0024]
• In some embodiments, the output signals from each of the up-converting transmitters transmitting into the K high frequency channels are summed and the sum signal filtered with a high-pass filter to eliminate any baseband component before the output signal from the baseband transmitter is added. Further, the baseband transmitter can include a low-pass filter to eliminate any higher frequency component of the baseband transmitter's output signal which can interfere with the signals from the up-converting transmitters.[0025]
• A transmission system in accordance with the present invention can include a plurality of receivers and a cross-channel interference canceller coupled to each of the receivers for receiving signals from the high frequency channels. Each of the plurality of receivers receives signals from one of a plurality of transmission bands. One receiver receives signals from the base band channel and the remaining receive signals from higher frequency channels.[0026]
• In some embodiments, at least one of the plurality of receivers that receives signals from a higher frequency channel includes a down converter that converts an input signal from the one of the plurality of transmission bands to a base band. A filter coupled to receive signals from the down converter can substantially filter out signals not in the base band after down-conversion. Further, an analog-to-digital converter coupled to receive signals from the filter and generate digitized signals and an equalizer coupled to receive the digitized signals can be included. In some embodiments, a trellis decoder coupled to receive signals from the equalizer and generate recreated data, the recreated data being substantially the same data transmitted by a corresponding transmitter. In some embodiments, a cross-channel interference canceller can be coupled to receive output signals from each of the equalizers and to provide signals to a digital filter or the trellis decoder.[0027]
• In some embodiments, the receiver that receives signals from the base band channel includes a low pass filter to filter out signals at high frequencies (e.g., the remaining channels), an analog to digital converter, an equalizer, and a data recovery circuit. In some embodiments, the equalizer can have adaptively chosen equalization parameters.[0028]
• These and other embodiments are further discussed below with respect to the following figures.[0029]
SHORT DESCRIPTION OF THE FIGURES
• FIGS. 1A, 1B and[0030]1C show block diagrams for a conventional system of transmitting data over a backplane.
• FIG. 2A shows a block diagram of a transmission system according to the present invention.[0031]
• FIG. 2B shows a block diagram of a transmitter according to the present invention.[0032]
• FIG. 2C shows a block diagram of a receiver according to the present invention.[0033]
• FIG. 3 shows a graph of attenuation versus transmission band on the transmission medium according to the present invention.[0034]
• FIG. 4 shows a block diagram of an embodiment of a transmission modulator according to the present invention.[0035]
• FIG. 5A shows a block diagram of an embodiment of a receiver according to the present invention.[0036]
• FIG. 5B shows a block diagram of a down-conversion module of a receiver as shown in FIG. 5A.[0037]
• FIG. 5C shows an embodiment of a block diagram of an analog filter of a receiver as shown in FIG. 5A.[0038]
• FIG. 5D shows an embodiment of a digital filter of a receiver as shown in FIG. 5A.[0039]
• FIG. 5E shows an embodiment of a second digital filter of a receiver as shown in FIG. 5A.[0040]
• FIG. 5F shows an embodiment of a cross-channel interference canceller of the receiver shown in FIG. 5A in accordance with the present invention.[0041]
• FIG. 6A shows a schematic diagram of a trellis encoder according to the present invention.[0042]
• FIG. 6B shows a schematic diagram of a symbol mapper according to the present invention.[0043]
• FIG. 6C shows a schematic diagram of a 128 QAM constellation.[0044]
• FIG. 6D shows filtering of the output signal from a digital to analog converter according to the present invention.[0045]
• FIG. 6E shows raised square root cosine filter response.[0046]
• FIG. 7 shows a block diagram of an embodiment of a tracking and error-recovery circuit of the receiver shown in FIG. 5A.[0047]
• FIGS. 8A and 8B show a block diagram of an embodiment of an automatic gain control circuit of a receiver demodulator according to the present invention.[0048]
• FIG. 9 shows a block diagram of a transceiver chip according to the present invention.[0049]
• FIGS. 10A, 10B and[0050]10C illustrate an embodiment of a trellis decoder.
• FIG. 11 shows an embodiment of a baseband transmitter according to the present invention.[0051]
• FIG. 12A shows an embodiment of a baseband receiver according to the present invention.[0052]
• FIGS. 12B through 12C show embodiments of components of the embodiment of the baseband receiver shown in FIG. 12A.[0053]
• In the figures, elements designated with the same identifications on separate figures are considered to have the same or similar functions.[0054]
DETAILED DESCRIPTION
• FIG. 2A shows a block diagram of a[0055]transmission system200 according to the present invention.System200 includes any number of components201-1 through201-P, with component201-p representing an arbitrary one of components201-1 through201-P, coupled through atransmission medium250.Transmission medium250 may couple component201-p to all of the components201-1 through201-P or may couple component201-p to selected ones of components201-1 through201-P. In some embodiments, components201-1 through201-P are coupled through FR4 copper traces.
• [0056]System200 can represent any backplane system, any chassis-to-chassis digital communication system, or any chip-to-chip interconnect with components201-1 through201-P representing individual cards, cabinets, or chips, respectively.
• [0057]Transmission channel250 can represent any transmission channel, including optical channels, wireless channels, or metallic conductor channels such as copper wire or FR4 copper traces. Typically,transmission channel250 attenuates higher frequency signals more than lower frequency signals. As a result, intersymbol interference problems are greater for high data rate transmissions than for low data rate transmissions. In addition, cross-talk from neighboring signals increases with transmission frequency.
• Components[0058]201-1 through201-P include transmitter systems210-1 through210-P, respectively, and receiver systems220-1 through220-P, respectively. In operation, one of transmitter systems210-1 through210-P from one of components201-1 through201-P is in communication with one of receiver systems220-1 through220-P from a different one of components201-1 through201-P. Further, in some embodiments, timing for all of components201-1 through201-P can be provided by a phase-locked-loop (PLL)203 synchronized to a transmit source clock signal. In some embodiments,PLL203 provides a reference clock signal and each of components201-1 through201-P can include any number of phase locked loops to provide internal timing signals.
• In some systems, for example backplane systems or cabinet interconnects, the transmission distance through[0059]transmission channel250, i.e. the physical separation between components201-1 through201-P, can be as low as 1 to 1.5 meters. In some chip-to-chip environments, the physical separation between components201-1 though201-P can be much less (for example a few millimeters or a few centimeters). In some embodiments of the present invention, separations between components201-1 through201-P as high as about100 meters can be realized. Furthermore, in someembodiments transmission channel250 can be multiple twisted copper pair carrying differential signals between components201-1 through201-P. In some embodiments, components201-1 through201-P can share wires so that fewer wires can be utilized. In some embodiments, however, dedicated twisted copper pair can be coupled between at least some of components201-1 through201-P. Further,transmission medium250 can be an optical medium, wireless medium, or data bus medium.
• FIG. 2B shows a block diagram of an embodiment of transmitter system[0060]210-p an arbitrary one of transmitter systems210-1 through210-P. Transmitter system210-p receives an N-bit parallel data signal at abit allocation block211.Bit allocation block211 also receives the reference clock signal fromPLL203.Bit allocation block211 segregates the N input bits into K+1 individual channels such that there are n₁through n_Kbits input to transmitters212-1 through212-K, respectively, and n₀bits input tobaseband transmitter217.Transmitter217 and transmitters212-1 through212-K transmit into (K+1) channels. In some embodiments, each of the N bits is assigned to one of the K+1 individual channels so that the sum of n₀through n_Kis the total number of bits N. In some embodiments,bit allocation block211 may include error pre-coding, redundancy, or other overall encoding such that the number of bits output, i.e.$\sum _{i=0}^Kn_i,$

  
• is greater than N.[0061]
• Each of transmitters[0062]212-1 through212-K encodes the digital data input to it and outputs a signal modulated at a different carrier frequency. Therefore, the n_kdigital data bits input to transmitter212-k, an arbitrary one of transmitters212-1 through212-K, is output as an analog signal in a kth transmission channel at a carrier frequency f_k. Additionally,baseband transmitter217 transmits into the baseband channel.
• FIG. 3 shows schematically the transport function for a typical transmission channel[0063]250 (FIG. 2A), H(f). As is shown, the attenuation at higher frequencies is greater than the attenuation at lower frequencies. Transmitters212-1 through212-K transmit analog data at carrier frequencies centered about frequencies f₁through f_K, respectively. Therefore, transmitters212-1 through212-K transmit into transmission channels301-1 through301-K, respectively.Transmitter217 transmits into transmission channel301-0, which is centered at 0 frequency. In some embodiments, the width of each of transmission channels301-0 through301-K can be the same. The width of the bands of each of transmission channels301-0 through301-K can be narrow enough so that there is little to no overlap between adjacent ones of transmission channels301-0 through301-K. In some embodiments, since the attenuation for the lower frequency channels is much smaller than the attenuation for the higher frequency channels, lower frequency channels can be bit-loaded to carry a higher number of bits per baud interval than the number of bits per baud interval that can be carried at higher carrier frequencies.
• As shown in FIG. 2B, the analog output signal from each of transmitters[0064]212-1 through212-K, y₁(t) through y_K(t), then represents the transmission signal in each of channels301-1 through301-K, respectively. Signals y₁(t) through y_K(t), then, are input tosummer213 and the summed analog signal output fromsummer213 can be input to ahigh pass filter215. The output signal fromhigh pass filter215 is input tosummer216 where it is summed with the baseband signal y₀(t) frombaseband transmitter217.High pass filter215 prevents transmitters212-1 through212-K from transmitting signals into the baseband channel and reduces or eliminates the need to consider cross-channel interference between signals produced bybaseband transmitter217 and those generated by transmitters212-1 through212-K.
• The output signal from[0065]summer216, z(t), is input to anoutput driver214. In some embodiments,output driver214 generates a differential transmit signal corresponding to signal z(t) for transmission overtransmission medium250.Output driver214, iftransmission medium250 is an optical medium, can also be an optical driver modulating the intensity of an optical signal in response to the signal z(t).
• FIG. 2C shows an embodiment of a receiver system[0066]220-p which can be an arbitrary one of receiver systems220-1 through220-P of FIG. 2A. Receiver system220-p can receive a differential receive signal, which originated from one of transmitter systems210-1 through210-P (typically not transmitter210-p), into aninput buffer224. In some embodiments, an optical signal can be received atinput buffer224, in whichcase input buffer224 includes an optical detector. The output signal frominput buffer224, Z(t), is closely related to the output signal z(t) ofsummer213. However, the signal Z(t) shows the effects of transmission throughtransmission medium250 on z(t), including intersymbol interference (ISI).
• The signal Z(t) is input to each of receivers[0067]222-1 through222-K and intobaseband receiver223. Receivers222-1 through222-K demodulate the signals from each of the transmission channels301-1 through301-K, respectively, and recovers the bit stream from each of carrier frequencies f₁through f_K, respectively.Baseband receiver223 recovers the bit stream which has been transmitted into the baseband channel. The output signals from each of receivers222-1 through222-K, then, include n₁through n_Kparallel bits, respectively, and the output signal frombaseband receiver223 include n₀parallel bits. The output signals are input to bit parsing221 where the transmitted signal having N parallel bits is reconstructed. Receiver system220-p also receives the reference clock signal fromPLL203, which can be used to generate internal timing signals. Furthermore, receiver system220-p outputs a receive clock signal with the N-bit output signal from bit parsing221.
• Further, demodulators (receivers)[0068]222-1 through222-K are coupled so that cross-channel interference can be cancelled. In embodiments wherefilter215 of transmitter210-p is not present or does not completely remove the baseband from the output signal ofadder213, then cross-channel interference in the baseband channel also will need to be considered. As discussed further below, due to the mixers in the up-conversion process, multiple harmonics of each signal may be generated from each of transmitters212-1 through212-K. For example, in some embodiments transmitters212-1 through212-K transmit at carrier frequencies f₁through f_Kequal to f₀, 2f₀. . . Kf₀, respectively. Thebaseband transmitter213 transmits at the baseband frequency,e.g. transmitter213 transmits with no carrier.
• Due to the harmonics in the mixer, the signal transmitted at carrier frequency f[0069]₁will also be transmitted in the base band and at frequencies 2f₁, 3f₁. . . Additionally, the signal transmitted at carrier frequency f₂will also be transmitted in the base band and at 2f₂, 3f₂, . . . Therefore, any time any of the bandwidth of any harmonics of the channels overlap with other channels or the other channel's harmonics, significant cross-channel symbol interference can occur due to harmonics in the mixers of transmitters212-1 through212-K. For example, in the case where the carrier frequencies are multiples of f₀,channel1 transmitting at f₀will also transmit at 0, 2f₀, 3f₀, . . . , i.e. into each of the other channels. Additionally, the down converters also create harmonics, which means that some of the transmission of the third channel will be down-converted into the first channel, for example. Therefore, further cross-channel interference can be generated in the down-conversion process of receivers221-1 through222-K. Embodiments of the present invention correct for the cross-channel symbol interference as well as the inter-symbol interference. Note that it is well known that if the duty cycle of the harmonic wave that is being mixed with an input signal is 50%, only odd harmonics will be generated. Even harmonics require higher or lower duty cycles.
• In some embodiments, N-bits of high-speed parallel digital data per time period is input to[0070]bit allocation211 of transmitter system210-p along with a reference clock signal. Data is transmitted at a transmit clock rate of CK1, which can be determined by an internal phase-locked-loop from the reference clock signal. Each of these input signals of N-bits can change at the rate of a transmit clock signal CK1. The transmit clock signal CK1 can be less than or equal to ηGHz/N, where η represents the total desired bit rate for transmission of data from transmitter system210-p overtransmission medium250. The resultant maximum aggregate input data rate, then, equals ηGbps. The ηGbps of aggregate input data is then split into K+1 sub-channels301-0 through301-K (see FIG. 3) which are generated bytransmitters217 and212-1 through212-K, respectively, such that:$\begin{array}{cc}\sum _{k=0}^KB_kn_k=\eta \mathrm{Gbps},& \left(1\right)\end{array}$

  
• where n[0071]_kis the number of bits transmitted through the kth transmission band, centered about frequency f_kfor k equal to 1 or greater and the base band for k=0, with a symbol baud rate on the k^thsub-channel being equal to B_k.
• In some embodiments of the invention, each of[0072]transmitters217 and212-1 through212-K operate at the same baud rate B_k. Furthermore, the center frequency of transmitter212-k (corresponding to channel k), or one of its harmonics, is substantially the same as harmonics of the center frequencies of other ones of transmitters212-1 through212-K. One skilled in the art will recognize that in other embodiments of the invention one or both of these conditions may not be satisfied.
• In some embodiments of the invention, each of the K+1 sub-channels[0073]301-0 through301-K can have the same baud rate B. In general, the baud rate B_kof one sub-channel301-k, which is an arbitrary one of sub-channels301-0 through301-K, can differ from the baud rate of other sub-channels. Additionally, bit-loading can be accomplished by choosing symbol sets which carry a larger number of bits of data for transmission channels at lower frequencies and symbol sets which carry a lower number of bits of data for transmission channels at higher frequencies (i.e., n_kis higher for lower frequencies).
• In the case of a copper backplane interconnect channel of trace length l<2 meters, for example, the signal-to-noise ratio of the lower carrier frequency channels is substantially greater than the signal-to-noise ratio available on the higher sub-channels because the signal attenuation on the copper trace increases with frequency and because the channel noise resulting from alien signal cross-talk increases with frequency. These properties of the copper interconnect channel can be exploited to “load” the bits/baud of the K sub-channels so that the overall throughput of the interconnect system is maximized. For example, digital communication signaling schemes (modulation+coding), see, e.g. Bernard Sklar, Digital Communications, Fundamentals and Applications (Prentice-Hall, Inc., 1988), can be utilized that provide higher bit density per baud interval over channels occupying the lower region of the frequency spectrum, and that result in lower bit density over channels that occupy higher frequencies. This “bit-loading” is especially important when the data rates over copper interconnect channel need to be increased, for example to a rate in excess of 10 Gbps per differential copper pair.[0074]
• FIG. 4 shows an embodiment of transmitter[0075]212-k, an arbitrary one of transmitters212-1 through212-K. Transmitter212-k receives n_kbits per baud interval, 1/B_k, for transmission into sub-channel301-k. The n_kbits are received inscrambler401.Scrambler401 scrambles the n_kbits and outputs a scrambled signal of n_kbits, which “whitens” the data.
• The output signal of n[0076]_kparallel bits is then input toencoder402. Although any encoding scheme can be utilized,encoder402 can be a trellis encoder for the purpose of providing error correction capabilities. Trellis coding allows for redundancy in data transmission without increase of baud rate, or channel bandwidth. Trellis coding is further discussed in, for example, Bernard Sklar, Digital Communications, Fundamentals and Applications (Prentice-Hall, Inc.,1988), G. Ungerboeck., “Trellis Coding Modulation with Redundant Signal Sets, Part I. Introduction,” IEEE Communications Magazine, vol. 25, no. 2, February 1987, pp. 5-11, and G. Ungerboeck., “Trellis Coding Modulation with Redundant Signal Sets, Part II. State of the Art,” IEEE Communications Magazine, vol. 25, no. 2, February 1987, pp. 12-21. Other encoding schemes include block coding schemes such as Reed-Solomon encoders, and BCH encoders, see, e.g., G. C. Clark, Jr., and J. B. Cain., Error Correction Coding for Digital Communications (Plenum Press, New York, 1981), however they result in an increase of channel bandwidth usage. Typically, the signal output fromencoder402 includes more bits than n_k, n_k+1e. In some embodiments,encoder402 can be a trellis encoder which adds one additional bit, in other words encoder402 can be a rate n_k/n_k+1 encoder, see, e.g., G. Ungerboeck., “Trellis Coding Modulation with Redundant Signal Sets, Part I. Introduction,” IEEE Communications Magazine, vol. 25, no. 2, Februray 1987, pp. 5-11, and G. Ungerboeck., “Trellis Coding Modulation with Redundant Signal Sets, Part II. State of the Art,” IEEE Communications Magazine, vol. 25, no. 2, February 1987, pp. 12-21. In some embodiments, additional bits can be added to insure a minimum rate of transitions so that timing recovery can be efficiently accomplished at receiver220-p.
• FIG. 6A shows an embodiment of[0077]encoder402.Encoder402 of FIG. 6A is an n_k/n_k+1 trellis encoder.Encoder402 of FIG. 6A performs a rate ½ convolutional coding on the most-significant-bit (MSB) of the n_kbit input signal. The MSB is input to delay601. The output signal fromdelay601 is input to delay602. The MSB and the output signal fromdelay602 are input to XOR adder603. The output from XOR adder603 provides a coded bit. The MSB, the output signal fromdelay601, and the output signal fromdelay602 are XORed in adder604 to provide another coded bit. The two coded bits are joined with the remaining n_k−1 bits to form a n_k+1 bit output signal.Delays601 and602 are each clocked at the symbol baud rate B. One skilled in the art will recognize that other embodiments ofencoder402 can be utilized with embodiments of this invention.
• In transmitter[0078]212-k of FIG. 4, the output signal fromencoder402 is input tosymbol mapper403.Symbol mapper403 can include any symbol mapping scheme for mapping the parallel bit signal fromencoder402 onto symbol values for transmission. In some embodiments,symbol mapper403 is a QAM mapper which maps the (n_k+le) bits fromencoder402 onto a symbol set with at least 2^(n_k+le)symbols. As shown in FIG. 6A, le=1 in the output signal fromencoder402. A trellis encoder in conjunction with a QAM mapper can provide a trellis encoded QAM modulation for sub-channel301-k.
• FIG. 6B shows an embodiment of[0079]symbol mapper403.Symbol mapper403 receives the n_k+1 data bits fromencoder402 and generates a symbol, which can include an in-phase component I_kand a quadrature component Q_k. In some embodiments,symbol mapper403 includes a look-up table605 which maps the n_k+1 input bits to the complex output symbol represented by I_kand Q_k.
• Table I shows an example symbol look-up table for conversion of a 7-bit data signal into a 128-symbol QAM scheme. Table entries are in decimal format with the in-phase values along the bottom row and the quadrature values represented along the last column. From Table I, a decimal value of 96, for example, results in an I value of −1 and a Q value of −1.[0080]
• In some embodiments,[0081]encoder402 could be a 16 state,rate 2/3 encoder, encoding the 2 most significant bits (MSBs) of the n_kbit input signal. In general, any pair of bits could be chosen for encoding in this example. This 16 state encoder could determine its future state from the current state and the 2 incoming bits. If the old state is 4 bits, x=[x3 x2 x1 x0 ] and the incoming bits are [y1 y0], the next state could be 4 bits, z=[z3 z2 z1 z0]=[x1 x0 y1 y0]. The values x3 and z3 are the most significant bits (MSBs) of the state. The transition from the old state to the next state can define the 3 bit output of the encoder as shown in table II. In table II, the notation a

  

  b, means that the transition from old_state=a to next_state=b. The encoded 3-bits corresponding to that transition in this example is listed as the encoded value.
• The encoded output bits from[0082]encoder402 are input tomapper403. In an example where n_k=6 and le=1, 7 bits fromencoder402 are input tomapper403. Ifencoder402 is the 16 state,rate 2/3 encoder discussed above, the 3 bit output ofencoder402 can be the 3 MSBs and the 4 uncoded bits can be the least significant bits (LSBs). An example ofmapper403 can be found in table III.
• In some embodiments, a 16 symbol QAM scheme can be utilized. In those embodiments, 4 bits with no encoding (or 3 bits in an 3/4 encoding scheme) can be directly mapped onto 16 QAM symbols. In some embodiments, 4 bits can be encoded (with a 4/5 encoding scheme) into a 32 QAM symbol set. In general, any size symbol set can be utilized.[0083]
• In some embodiments, the QAM mapping can be segregated into groups of four as is shown in FIG. 6C. In some embodiments, with a 128 QAM system, then n[0084]_k+1 is 7 (referred to as 6/7 encoding). The two control bits fromencoder402 are arranged so that in groups of four symbols, the two control bits determine placement in the group.Control bits00 and11 andcontrol bits01 and10 are in opposite comers of the groupings of four. This leads to a 6 dB gain in decoding at the receiver using this mapping scheme. Furthermore, the remaining five bits determine the actual grouping of four.
• The output signal from[0085]symbol mapper403 can be a complex signal represented by in-phase signal I_k(n) and a quadrature signal Q_k(n), where n represents the nth clock cycle of the clock signal CK1, whose frequency equals the baud rate B_k. Each of signals I_k(n) and Q_k(n) are digital signals representing the values of the symbols they represent. In some embodiments, a QAM mapper onto a constellation with 128 symbols can be utilized. An embodiment of a 128-symbol QAM constellation is shown in Table I. Other constellations and mappings are well known to those skilled in the art, see, e.g., Bernard Sklar, Digital Communications, Fundamentals and Applications (Prentice-Hall, Inc., 1988) and E. A. Lee and D. G. Messerschmitt, Digital Communications (Kluwer Academic Publishers, 1988). The number of distinct combinations of I_k(n) and Q_k(n), then, represents the number of symbols in the symbol set of the QAM mapping and their values represent the constellation of the QAM mapping. Further examples of QAM symbol sets include 16 QAM symbol sets (16-QAM) and 4/5 encoded 32-QAM symbol sets (4/5 encoded 32 QAM).
• The signals from[0086]symbol mapper403, I_k(n) and Q_k(n), are input to digital-to-analog converters (DACs)406 and407, respectively.DACs406 and407 operate at the same clock rate assymbol mapper403. In some embodiments, therefore,DACs406 and407 are clocked at the symbol rate, which is the transmission clock frequency B_k.
• The analog output signals from[0087]DACs406 and407, represented by I_k(t) and Q_k(t), respectively, can be input to low-pass filters408 and409, respectively. Low pass filters408 and409 are analog filters that pass the symbols represented by I_k(t) and Q_k(t) in the base band while rejecting the multiple frequency range reflections of the base band signal. FIG. 6D shows a schematic diagram of the ideal requirements forfilters408 and409. The filter function h(f) cuts off to include all of the base band signal while rejecting all of the higher frequency reflections of the base band signal created byDACs406 and407.
• An example embodiment of[0088]filters408 and409 can be described by a two-zero, five-pole filter function of the form$\begin{array}{cc}{H}_{\mathrm{TX}}\left(s\right)=\frac{{\mathrm{<figure-callout\; label="b"\; filenames="US20030112896A1-20030619-D00006.png,US20030112896A1-20030619-D00009.png"\; state="\{\{state\}\}">b</figure-callout>}}_2s^2+{\mathrm{<figure-callout\; label="b"\; filenames="US20030112896A1-20030619-D00001.png,US20030112896A1-20030619-D00005.png"\; state="\{\{state\}\}">b</figure-callout>}}_1s+b_0}{{\mathrm{<figure-callout\; label="s"\; filenames="US20030112896A1-20030619-D00012.png"\; state="\{\{state\}\}">s</figure-callout>}}^5+a_4{\mathrm{<figure-callout\; label="s"\; filenames="US20030112896A1-20030619-D00013.png"\; state="\{\{state\}\}">s</figure-callout>}}^4\cdots +a_0},& \left(2\right)\end{array}$

  
• where s=j(2πf) (j is {square root}{square root over (−1)}) and the coefficients b[0089]₂, b₁, b₀, and a₄through a₀are the parameters offilters408 and409. The parameters forfilters408 and409, then, can be found by minimizing the cost function$\begin{array}{cc}{\int }_0^{\infty }{H_{\mathrm{DAC}}\left(f\right)H_{\mathrm{TX}}\left(s\right)-H_{\mathrm{RRC}}\left(f\right){}^{-\mathrm{j2\pi }f\tau }}^2W\left(f\right)f,& \left(3\right)\end{array}$

  
• where H[0090]_DAC(f) is the response ofDACs406 and407, which can be given by$\begin{array}{cc}{H}_{\mathrm{DAC}}\left(f\right)=\frac{\sin \left(\pi {\mathrm{fT}}_k\right)}{\pi f},& \left(4\right)\end{array}$

  
• where T[0091]_kis the symbol period, W(f) is a weighting function, H_RRC(f) is a target overall response and τ is the time delay on the target response. The cost function is minimized with respect to the parameters of the filter (e.g., coefficients b₂, b₁, b₀, and a₄through a₀) and the time delay τ. FIG. 6E shows an example of a target overall response function H_RRC(f), which is a square-root raised cosine function. The function H_RRC(f) can be determined by a parameter α_kalong with thebaud rate frequency 1/T_k(which is the baud rate B_kfor transmitter212-k). The parameter α_kis the excess bandwidth of the target function H_RRC(f). In some embodiments, α_kcan be set to 0. In some embodiments of the invention, α_kcan be set to 0.6.
• The weight function W(f) can be chosen such that the stop band rejection of H[0092]_TX(s) is less than about −50 dB. Initially, W(f) can be chosen to be unity in thepass band frequency 0<f<(1+γ_k)/2T_kand zero in the stop band frequency f>(1+γ_k)/2T_k, where γ_kis the excess bandwidth factor of the kth channel. The minimization of the cost function ofEquation 3 can be continued further by increasing W(f) in the stop band until the rejection ofanalog filters408 and409 is less than −50 dB.
• In some embodiments, the overall impulse response of the transmit signal is a convolution of the impulse response of[0093]DACs406 and407 and the impulse response of transmitanalog filters408 and409, i.e.
• h_k^Tx(t)=h_k^f(t){circle over (x)}h_k^DAC(t),  (5)
• where h[0094]_k^f(t) is the response of the filter and h_k^DAC(t) is the response ofDACs406 and407. In some embodiments, the DAC response h_k^DAC(t) is a sinc function in the frequency domain and a rectangular pulse in the time domain. As shown inEquation 5, the overall response is a convolution offilters408 and409 with the response ofDACs406 and407. The overall filter response can be close to the target response H_RRC(f) when h_k^TX(t) is determined with the cost function ofEquation 3.
• The output signals from low-[0095]pass filters408 and409, designated I_k^LPF(t) and Q_k^LPF(t), respectively, are then up-converted to a center frequency f_kto generate the output signal of y_k(t), the kth channel signal. The output signal from low-pass filter408, I_k^LPF(t), is multiplied by cos(2πf_kt) inmultiplier410. The output signal from low-pass filter409, Q_k^LPF(t), is multiplied by sin(2πf_kt) inmultiplier411. The signal sin(2πf_kt) can be generated by PLL414 based on the reference clock signal and the signal cos(2πf_kt) can be generated by a π/2 phase shifter413.
• However, since[0096]mixers410 and411 are typically not ideal mixers and the harmonic sine wave input tomixer410, and the resulting cosine wave input tomixer411, often varies from a sine wave, signals having harmonics of the frequency f_kare also produced. Often, the harmonic signals input tomixers410 and411 may more closely resemble square-wave signals than harmonic sine wave signals. Even if the “sine wave input” is a true sine wave, the most commonly utilized mixers, such as Gilbert Cells, may act as a band-limited switch, resulting in a harmonic signal with alternating positive and negative voltages with frequency the same as the “sine wave input” signal. Therefore, the output signals fromfilters408 and409 are still multiplied by signals that more closely resemble square waves than sine waves. As a result, signals having frequency 2f_k, 3f_k, . . . are also produced, as well as signals in the base band (0f_k). Although the amplitude of these signals may be attenuated with higher harmonics, they are non-negligible in the output signal. Additionally, even harmonics (i.e., 0f_k, 2f_k, 4f_k. . . ) are absent if the duty cycle of the harmonic sine wave input to mixers is 50%. Otherwise, some component of all of the harmonics will be present.
• The output signals from[0097]multipliers410 and411 are summed insummer412 to form$\begin{array}{cc}\begin{array}{c}{y}_k\left(t\right)={\xi }_{\mathrm{<figure-callout\; label="k"\; filenames="US20030112896A1-20030619-D00008.png,US20030112896A1-20030619-D00009.png"\; state="\{\{state\}\}">k</figure-callout>}}^0I_k^{\mathrm{LPF}}\left(t\right)-{\mathrm{<figure-callout\; label="\zeta \; k"\; filenames="US20030112896A1-20030619-D00008.png,US20030112896A1-20030619-D00009.png"\; state="\{\{state\}\}">\zeta </figure-callout>}}_k^{}Q_k^{\mathrm{LPF}}\left(t\right)+\\ \sum _{n>0}\left({\xi }_k^nI_k^{\mathrm{LPF}}\cos \left(2\pi {\mathrm{nf}}_kt\right)-{\zeta }_k^nQ_k^{\mathrm{LPF}}\sin \left(2\pi {\mathrm{nf}}_kt\right)\right)\left(k\ge 1\right).\end{array}& \left(6\right)\end{array}$

  
• where ξ[0098]_kⁿand ζ_kⁿis the contribution of the nth harmonic to y_k(t). If the duty cycle of the harmonic input signals tomixers410 and411 is near 50%, the even harmonics are low and the odd harmonics are approximately given by ξ_kⁿ=I_k^LPF/n and ζ_k^n=Q_k^LPF/n for odd n.
• FIG. 11 shows an embodiment of[0099]baseband transmitter217.Transmitter217 may include ascrambler1104 andencoder1105.Scrambler1104 can be similar to that described asscrambler401 described above and functions to whiten the data. In some embodiments,scrambler1104 may utilize a different function for scrambling the incoming bits than that described above asscrambler401. Encoder1105 can be similar to that described asencoder402 above and encodes the n₀bits input totransmitter217 to n₀+l bits. The output signal fromencoder1105 is then input tosymbol mapper1101.Symbol mapper1101 converts the n₀+l parallel bits into a symbol for transmission. In some embodiments,symbol mapper1101 can be a PAM encoder. The PAM symbol set can be of any size. In some embodiments, for example, a 16 level symbol set (16-PAM) can be utilized to represent n₀+l=4 parallel bits. Encoder1105 can provide 3/4 encoding or no encoding. The output signal fromsymbol mapper1101 is input to digital-to-analog converter1102 which converts the symbol set determined bysymbol mapper1101 into the corresponding output voltages.
• In some embodiments, the analog output signal from[0100]DAC1102 is prefiltered throughfilter1103. In some embodiments,filter1103 may prepare the output signal for transmission through medium250 (see FIG. 2A) so that the signal received by a receiver is corrected for distortions caused by the channel. For example, if the baseband channel oftransmission medium250 is known to have a transfer function of (1+D(z)), then filter1103 may execute a transfer function equal to 1/(1+D(z)) in order to cancel the transfer function oftransmission medium250. The output signal fromfilter1103 can be input to low-pass filter1106.Filter1106 removes the higher frequency content, which may interfere with transmissions on the higher frequency channels. The output signal fromfilter1106 is the base band signal y₀(t). With a combination oflow pass filter1106 andhigh pass filter215 coupled tosummer213, cross-channel interference between the base band channel, channel301-0, and higher frequency channels301-1 through301-K can be minimized or eliminated.
• The overall output of transmitter[0101]210-p (FIG. 2B), the output fromsummer216, is then given by$\begin{array}{cc}z\left(t\right)=\sum _{n=0}^Ky_n\left(t\right).& \left(7\right)\end{array}$

  
• In an example where the frequencies f[0102]₁through f_Kare given by frequencies f₀through (Kf₀), respectively, then, the overall output signal z(t) is given by:$\begin{array}{cc}\begin{array}{c}z\left(t\right)=y_0\left(t\right)+\sum _{k=1}^K\left({\xi }_k^0I_k^{\mathrm{LPF}}\left(t\right)-{\zeta }_k^0Q_k^{\mathrm{LPF}}\right)+\\ {\xi }_1^1I_1^{\mathrm{LPF}}\left(t\right)\cos {\omega }_0t-{\zeta }_1^1Q_1^{\mathrm{LPF}}\left(t\right)\sin {\omega }_0t+\\ \left({\xi }_1^2I_1^{\mathrm{LPF}}\left(t\right)+{\xi }_2^1I_2^{\mathrm{LPF}}\left(t\right)\right)\cos 2{\omega }_0t-\\ \left({\zeta }_1^2Q_1^{\mathrm{LPF}}\left(t\right)+{\zeta }_2^1Q_2^{\mathrm{LPF}}\left(t\right)\right)\sin 2{\omega }_0t+\\ \left({\xi }_1^3I_1^{\mathrm{LPF}}\left(t\right)+{\zeta }_3^1I_3^{\mathrm{LPF}}\left(t\right)\right)\cos 3{\omega }_0t-\\ \left({\zeta }_1^3Q_1^{\mathrm{LPF}}\left(t\right)+{\zeta }_3^1Q_3^{\mathrm{LPF}}\left(t\right)\right)\sin 3{\omega }_0t+\\ \left({\xi }_1^4I_1^{\mathrm{LPF}}\left(t\right)+{\xi }_2^2I_2^{\mathrm{LPF}}\left(t\right)+{\xi }_4^1I_4^{\mathrm{LPF}}\left(t\right)\right)\cos 4{\omega }_0t-\\ \left({\zeta }_1^4Q_1^{\mathrm{LPF}}\left(t\right)+{\zeta }_2^2Q_2^{\mathrm{LPF}}\left(t\right)+{\zeta }_4^1Q_4^{\mathrm{LPF}}\left(t\right)\right)\cos 4{\omega }_0t+\cdots \\ =y_0\left(t\right)+\sum _{k=1}^K\left({\xi }_k^0I_k^{\mathrm{LPF}}\left(t\right)-{\zeta }_k^0Q_k^{\mathrm{LPF}}\left(t\right)\right)+\\ \sum _{M=1}^{\infty }\sum _{\forall k,n\in k^{*}n=M}\left({\xi }_k^nI_k^{\mathrm{LPF}}\left(t\right)\cos M{\omega }_0t-{\zeta }_k^nQ_k^{\mathrm{LPF}}\left(t\right)\sin M{\omega }_0t\right)\end{array}& \left(8\right)\end{array}$

  
• where ω[0103]₀is 2πf₀and where I_k^LPF(t) and Q_k^LPF(t) are 0 for all k>K.
• As shown in[0104]Equation 8, the signal on channel one is replicated into all of higher K channels, the baseband, and into harmonic frequencies beyond the base band and the K channels.Filter215 can remove the contribution to the baseband channel from transmitters212-1 through212-K. The signal on channel two, for example, is also transmitted onchannels4,6,8, . . . , and the baseband. The signal onchannel3 is transmitted onchannels6,9,12, . . . and the base band. In general, the signal on channel k will be mixed into channels2k,3k, . . . and the baseband. Further, the attenuation of the signals with higher harmonics in some systems can be such that the signal from channel k is non negligible for a large number of harmonics, potentially up to the bandwidth of the process, which can be 30-40 GHz.
• In some embodiments of the invention, a high pass filter[0105]215 (see FIG. 2B) receives the signal fromsummer213.High pass filter215 can, for example, be a first-order high-pass filter with 3 dB attenuation at f₁/2.Filter215 removes the DC harmonics, i.e. the baseband transmissions, from the transmitter. In embodiments with a separate baseband transmission, then, cross-channel coupling into the baseband is minimized or eliminated. Further, removing the baseband harmonics from the transmitted signals simplifies cross-channel cancellation at receiver220-p. In embodiments wherehigh pass filter215 exists, the baseband contribution from each of transmitters212-1 through212-K,$\sum _{k=1}^K\left({\mathrm{<figure-callout\; label="\xi \; k"\; filenames="US20030112896A1-20030619-D00008.png,US20030112896A1-20030619-D00009.png"\; state="\{\{state\}\}">\xi </figure-callout>}}_k^{}I_k^{\mathrm{LPF}}\left(t\right)-{\mathrm{<figure-callout\; label="\zeta \; k"\; filenames="US20030112896A1-20030619-D00008.png,US20030112896A1-20030619-D00009.png"\; state="\{\{state\}\}">\zeta </figure-callout>}}_k^{}Q_k^{\mathrm{LPF}}\left(t\right)\right),$

  
• is filtered out and becomes close to 0. The output signal from transmitter[0106]210-p then becomes$\begin{array}{cc}{z}^{\prime }\left(t\right)={\mathrm{<figure-callout\; label="y"\; filenames="US20030112896A1-20030619-D00008.png,US20030112896A1-20030619-D00009.png"\; state="\{\{state\}\}">y</figure-callout>}}_0\left(t\right)+\sum _{M=1}^{\infty }\sum _{\forall k,n\in k^{*}n=M}\left({\xi }_k^nI_k^{\mathrm{LPF}}\left(t\right)\cos M{\omega }_0t-{\zeta }_k^nQ_k^{\mathrm{LPF}}\left(t\right)\sin M{\omega }_0t\right).& \left(9\right)\end{array}$

  
• In some embodiments, B[0107]_kand γ_kcan be the same for all channels and the center frequencies of channels301-1 through301-K, frequencies f₁through f_K, respectively, can be chosen by
• f_k=B_kk(1+γ_k);1≦k≦K.  (10)
• In some embodiments, other center frequencies can be chosen, for example:[0108]
• f₁≧0.5B_k(1+γ_k)
• (f_k−f_k−1)≧B_k(1+γ_k);k≧2.  (11)
• The parameter γ[0109]_kis the excess bandwidth factor. The bandwidth of the k-th channel, then , is (1+γ_k)B_k. In general, the center frequencies of channels301-1 through301-K can be any separated set of frequencies which substantially separate (i.e., minimizing overlap between channels) in frequency the transmission bands of transmission channels301-1 through301-K.
• In many embodiments, however, the frequencies f[0110]₁through f_Kare chosen as multiplies of a single frequency f₀which can fulfillequations 10 and/or 11 and results in the harmonic mixing of channels as shown inEquation 8 and 9.
• In some embodiments of the invention,[0111]DACs406 and407 of the embodiment of transmitter212-k shown in FIG. 4 may be moved to receive the output ofsummer412. Further, in someembodiments DACs406 and407 can be replaced by a single DAC to receive the output ofsummer213. However, such DACs should have very high sampling rates. One advantage of utilizing high-sampling rate DACs is that ideal mixing could take place and the number of harmonics that need to be cancelled can be greatly reduced or even eliminated.
• As an example, then, embodiments of transmitter[0112]210-p capable of 10 Gbps transmission can be formed. In that case, η=10, i.e., an overall throughput of 10 Gbps from the transmitter to the receiver. Some embodiments, for example, can have (K+1)=8 channels301-0 through301-7. Channels301-1 through301-7 can be 6/7 trellis encoded 128 QAM with the baud rate on each channel B_kbeing 1.25 GHz/6 or about 208.333 Msymbols/sec. Channel301-0, the baseband channel, can be PAM-8 with no error correction coding (i.e., uncoded PAM-8) with baud rate B₀being 416.667 Msymbols/sec. In other words, n_k=6; 1≦k≦7 andencoder402 is a 6/7 rate trellis encoder. In this example, channels301-1 thorugh301-7 can be transmitted at frequencies 2f₀, 3f₀, 4f₀, 5f₀, 6f₀, 7f₀and 8f₀, respectively, where f₀can be example, 1.5*B_kor 312.5 MHz.
• In another example embodiment, 10 Gbps (η=10) can utilize (K+1)=2 channels[0113]301-0 and301-1. Channel301-1 can be, for example, 16 QAM with no error correction coding (i.e., uncoded 16-QAM) with baud rate B₁of 1.25 GHz and Channel301-0 can be, for example, 16-PAM with no error correction coding (i.e., uncoded 16-PAM) with baud rate B₀at 1.25 GHz. The baud rate for both the PAM channel and the QAM channel is then 1.25 Gsps. The throughput is 5 Gbps each for a total transmission rate of 10 Gbps. With an excess bandwidth of the channels of about 50%, the center frequency of the QAM channel can be f₁≧(1.5)*1.25 GHz or above about 1.8 GHz.
• In another example embodiment, 10 Gbps can utilize (K+1)=2 channels[0114]301-0 and301-1 as above with channel301-1 being a 4/5 trellis encoded 32 QAM with a baud rate B, of 1.25 GHz with channel301-0 being uncoded 16-PAM with baud rate B₀1.25 GHz. Again, the center frequency of channel301-1 can be f₁≧(1.5)*1.25 GHz or above about 1.8 GHz.
• In yet another example, (K+1)=6 channels, channels[0115]301-0 through301-5, can be utilized. Channels301-1 thorugh301-5 can be 6/7 trellis encoded 128-QAM with baud rate B_kof 1.25 GHz/6 or 208 MHz. Channel301-0, the baseband channel, can be 3/4 encoded 16 PAM or uncoded 8-PAM with baud rate B₀=1.25 GHz. The center frequencies of channels301-1 through301-5 can be 4f₀, 5f₀, 6f₀, 7f₀, and 8f₀, respectively, with f₀being about 312.5 MHz.
• In some embodiments,[0116]DACs406 and407 of each of transmitters212-1 through212-K can each be 4 bit DACs. A schematic diagram of an embodiment oftrellis encoder402 and an embodiment of the resultant 128-QAM constellation mapping are shown in FIGS. 6A, 6B, and6C, respectively. An example of a 128 symbol QAM mapping table is shown as Table I. The above describedtrellis encoder402, in this embodiment, provides an asymptotic coding gain of about 6 dB over uncoded 128-QAM modulation with the same data rate, see, e.g., G. Ungerboeck., “Trellis Coding Modulation with Redundant Signal Sets, Part I. Introduction,” IEEE Communications Magazine, vol. 25, no. 2, February 1987, pp. 5-11, and G. Ungerboeck., “Trellis Coding Modulation with Redundant Signal Sets, Part II. State of the Art,” IEEE Communications Magazine, vol. 25, no. 2, February 1987, pp. 12-21.
• FIG. 5A shows an example of one of receiver systems[0117]220-p where receiver system220-p is an arbitrary one of receiver systems220-1 through220-P ofsystem200. Receiver system220-p includes receivers221-1 through221-K andbaseband receiver223 to form a (K+1)-channel receiver. As shown in FIG. 2C, the output signals fromreceiver input buffer224, Z(t), is received in each of receivers222-1 through222-K and223. The signal Z(t), then, is the transmitted signal z(t) after transmission throughmedium250. As shown in FIG. 3, the attenuation of signals at each of the K carrier frequencies after transmission throughmedium250 can be different. Additionally, the signal Z(t) suffers from inter-symbol interference caused by the dispersive effects ofmedium250. The dispersive effects cause the signals received within a particular timing cycle to be mixed with those signals at that carrier frequency received at previous timing cycles. Therefore, in addition to cross-channel interference effects caused by the harmonic generation in mixers of the transmitter (an arbitrary one of which being designated transmitter210-p), but also the signals for each channel are temporally mixed through dispersion effects inmedium250.
• Signal Z(t) is then received into each of receivers[0118]222-1 through222-K. As shown in FIG. 5A, receiver222-k, an arbitrary one of receivers222-1 through222-K, for example, receives the signal Z(t) into down converter560-k which, in the embodiment shown in FIG. 5A, down converts the channel transmitted at frequency f_kback into the baseband and recovers in-phase and quadrature components Z_k^Iand Z_k^Q, respectively.
• FIG. 5A shows an embodiment of down-converter[0119]560-k. Signal Z(t) is received in multipliers501-k and502-k where it is down-converted to baseband to obtain an in-phase component Z_k^I(t) and a quadrature component Z_k^Q(t). Multiplier501-k multiplies signal Z(t) with cos(2π{circumflex over (f)}_kt) and multiplier502-k multiplies signal Z(t) with sin(2π{circumflex over (f)}_kt), where {circumflex over (f)}_kcan be the locally generated estimate of the carrier center frequency f_kfrom the corresponding transmitter. The clock signals within component201-p an arbitrary one of components201-1 through201-P, which are generated based on the reference signal fromPLL230 as shown in FIG. 2A, will have the same frequencies. However, the frequencies between differing ones of components201-1 through201-P can be slightly different. Therefore, {f_k} denotes the set of frequencies at the transmitter and {{circumflex over (f)}_k} denotes the set of frequencies at the receiver.
• In some embodiments, component[0120]201-p is a slave component where the frequencies {{circumflex over (f)}_k} can be adjusted to match those of the component that includes the transmitter, which is also one of components201-1 through201-P. In some embodiments, component201-p is a master component, in which case the transmitter of the component communicating with component201-p adjusts frequencies {f^k} to match those of {{circumflex over (f)}_k}. Arbitration in any given communication link between receiver220-p of component201-p and a transmitter in one of the other of components201-1 through201-P can be accomplished in several ways. In some embodiments, priority may be set between pairs of components201-1 through201-P so that the master/slave relationship between those pairs is pre-determined. In some embodiments, an overall system control chooses at the start of each communication which component is master and which is slave. In some embodiments, the two components may negotiate, for example by each randomly choosing one of the k channels on which to transmit and designating the one that transmits on the lowest numbered channel as master. In any event, in any transmission either the transmitter adjusts {f^k} or the receiver adjusts {{circumflex over (f)}_k} depending on which has been designated master and which slave upon start of the communications
• As shown in FIG. 5A, PLL[0121]523 generates the clock signals for each of receivers222-1 through222-K andreceiver223 and, in particular, generates the sin(2π{circumflex over (f)}_kt) signal for receiver222-k. The cos(2π{circumflex over (f)}_kt) signal can be generated by π/2 phase shifter524-k. PLL523 generates the sampling clock signal utilized in analog to digital converters (ADCs)506-k and507-k as well as other timing signals utilized in receivers222-1 through222-K andreceiver223. PLL523 also generates an RX CLK signal for output with the n_kbit output signal from receiver222-k.
• Down converters[0122]560-1 through560-K also generate harmonics for very much the same reasons that harmonics are generated in transmitters212-1 through212-K. Therefore, down converter560-k will down-convert into the base band signals from signals havingcenter frequencies 0, {circumflex over (f)}_k, 2 {circumflex over (f)}_k, 3 {circumflex over (f)}_k, . . . For example, if {circumflex over (f)}₁through {circumflex over (f)}_Kcorrespond to frequencies {circumflex over (f)}₀through K {circumflex over (f)}₀, then the down conversion process for down converter560-1 will result in the output signals Z₁^Iand Z₁^Qincluding interference contributions from the received signals from all of the other channels. Additionally, the output signals Z₂^Iand Z₂^Qinclude contributions from channels withfrequencies 0, 2 {circumflex over (f)}₀, 4 {circumflex over (f)}₀, 6 {circumflex over (f)}₀. . . and those channels with harmonics at these frequencies. For example, if a channel has a center frequency at 3f₀and transmits a second harmonic at 6f₀, then the receiver will bring signals at 6 {circumflex over (f)}₀back to the baseband by the third harmonic of the mixer for the channel at 2 {circumflex over (f)}₀. Therefore, signals from channel k=3 need to be cancelled from signals transmitted on channel k=2. Each of the channels also include the cross-channel interference generated by the transmitter mixers and the dispersive interference created by the channel. If the baseband component of the harmonics is not filtered in filter215 (FIG. 2B) out between the transmit and receive mixers, then every channel could put a copy of its transmit signal onto the baseband and every channel will receive the baseband signal at the receive side.
• PLL[0123]523 can be a free-running loop generating clock signals for receiver222-k based on a reference clock signal. In some embodiments transmitter212-k of transmitter and demodulator222-k of the receiver system220-p because they are part of different ones of components201-1 through201-P, are at different clock signals. This means that the digital PLLs for timing recovery and carrier recovery correct both phase and frequency offsets between the transmitter clock signals and receiver clock signals. Within one of components201-1 through201-P, a transmitter/receiver pair (i.e., transmitter210-p and receiver220-p of component201-p) can operate with the same PLL and therefore will operate with the same clock signals. Components201-i and201-j, where i and j refer to different ones of components201-1 through201-P, in general may operate at different clock signal frequencies.
• Therefore, in some embodiments the signals Z[0124]_k^Iand Z_k^Qoutput from down converter560-k suffer the effects of cross-channel interference resulting from harmonic generation in the transmitter mixers, the effects of cross-channel interference resulting from harmonic generation in the receiver mixers, and the effects of temporal, intersymbol interference, resulting from dispersion in the transport media. As an additional complicating factor, in some embodiments the transmitter and receiver clocks can be different. Therefore, as an example, in embodiments where f₁through f_Kof the transmitter correspond to frequencies f₀through Kf₀, respectively, then {circumflex over (f)}₁through {circumflex over (f)}_Kof the receiver will correspond to frequencies (f₀+Δ) through K(f₀+Δ), where Δ represents the frequency shift between PLL523 of receiver220-p and the PLL of the transmitter component. The transmitter mixers then cause cross-channel interference by mixing the signals transmitted at frequency f_kinto 2f_k, 3f_k. . . (2kf₀, 3kf₀. . . in one example). The receiver mixers cause cross-channel interference by down-converting the signals received at {circumflex over (f)}_k, 2 {circumflex over (f)}_k, 3 {circumflex over (f)}_k. . . to the baseband. If the frequencies {circumflex over (f)}₀is f₀+Δ, then the harmonics will be down-converted to a baseband shifted in frequency by kΔ, 2kΔ, 3kΔ, . . . , respectively.
• In some embodiments of the invention, receiver[0125]220-p includes afrequency shift563 which supplies a reference clock signal to PLL523. The reference clock signal supplied to PLL523 can be frequency shifted so that Δ becomes 0. The frequency supplied to PLL523 byfrequency shift563 can be digitally created and the input parameters tofrequency shift563 can be adaptively chosen to match the receiver frequency with the transmitter frequency. Embodiments of frequency adjustments infrequency shift563 and PLL523 are further discussed below.
• As shown in FIG. 5A, the output signals from down-converter[0126]560-k, Z_k^Iand Z_k^Q, are input to analog filter561-2. An embodiment of analog filter561-2 is shown in FIG. 5C. The signals Z_k^Iand Z_k^Qare input to offset corrections530-k and531-k, respectively. DC offset corrections530-k and531-k provide a DC offset for each of the outputs Z_k^Iand Z_k^Qfrom down-converter560-k to correct for any leakage onto signal Z(t) from the sine and cosine signals provided by PLL523, plus any DC offset in filters504-k and505-k and ADCs506-k and507-k. Leakage onto Z(t) can, in some cases, provide a significant DC signal component of the output signals Z_k^Iand Z_k^Qfrom down-converter560-k. In some embodiments, offsets530-k and531-k can offset by the same amount. In some embodiments, different offset values, DCOI and DCOQ in FIG. 5C, can be provided for each of the output signals Z_k^Iand Z_k^Qfrom down-converter560-k. The DC offset values can be adaptively chosen in blocks543-k and544-k. In some embodiments, after an initial start-up procedure, the DC offset values are fixed.
• In some embodiments, the DC offsets, DCOI and DCOQ inputs to offsets[0127]530-k and531-k, respectively, can be generated by providing a low frequency integration of the output signal from analog-to-digital converters (ADCs)506-k and507-k (FIG. 5A). In FIG. 5C, for example, low-frequency integrator543-k receives the output signal from of ADC506-k, R_k^I, and provides the DCOI input signal to offset530-k; integrator544-k receives the output signal from ADC507-k, R_k^Q, and provides the DCOQ input signal to offset531-k. The low frequency integration of integrators544-k and543-k provides signals that set the average output signal of each of ADCs506-k and507-k to zero. In some embodiments of the invention, integrators543-k and544-k hold the offset values DCOI and DCOQ, respectively, constant after a set period time of integration when receiver222-k is first started.
• The output signals Z[0128]_k^Iand Z_k^Qfrom down-converter560-k, or from offsets530-k and531-k in embodiments with offsets, can be input to low-pass filters504-k and505-k. Low-pass filters504-k and505-k are analog filters that filter out signals not associated with the baseband signal (i.e., signals from the remaining bands of transmitter210-p) for the kth transmission band. Low pass filters504-k and505-k, however, do not remove the interference caused by harmonic generation in transmit and receive mixers involved in the up-conversion and down-conversion process.
• Filters[0129]504-k and505-k again, in some embodiments, can be parameterized by the two-zero, five-pole filter design described byEquation 2,$\begin{array}{cc}{H}_{\mathrm{RX}}\left(s\right)=\frac{{\mathrm{<figure-callout\; label="b"\; filenames="US20030112896A1-20030619-D00006.png,US20030112896A1-20030619-D00009.png"\; state="\{\{state\}\}">b</figure-callout>}}_2s^2+{\mathrm{<figure-callout\; label="b"\; filenames="US20030112896A1-20030619-D00001.png,US20030112896A1-20030619-D00005.png"\; state="\{\{state\}\}">b</figure-callout>}}_1s+b_0}{{\mathrm{<figure-callout\; label="s"\; filenames="US20030112896A1-20030619-D00012.png"\; state="\{\{state\}\}">s</figure-callout>}}^5+a_4s^4+\dots +a_0}.& \left(12\right)\end{array}$

  
• Furthermore, the parameters b[0130]₂, b₁, b₀, and a₄through a₀can be found by minimizing the cost function$\begin{array}{cc}{\int }_0^{\infty }{H_{\mathrm{RX}}\left(s\right)-H_{\mathrm{RRC}}\left(f\right){}^{-j2\pi f\tau }}^2W\left(f\right)f.& \left(13\right)\end{array}$

  
• The cost function is minimized with respect to the parameters of the filter and the time delay τ. Again in Equation 13, the weighting function W(f) can be chosen such that the stop band rejection of H[0131]_RX(s) is less than −50 dB. Furthermore, the function H_RRC(f) is the square root raised cosine function shown in FIG. 6E. As shown in FIG. 6E, the function H_RRC(f) is characterized by a parameter α_kandbaud frequency 1/T_k. The parameter α_kis the excess bandwidth of the target function H_RRC(f). In some embodiments, α_kcan be 0. In some embodiments, α_kcan be 0.6. In general, the parameter α_kcan be any value, with smaller values providing better filtering but larger values being easier to implement. The parameter T_kis related to the baud rate, T_k=1/B_k.
• In some embodiments ofthe invention, filters[0132]504-k and505-k can be determined by minimizing the function$\begin{array}{cc}{\int }_0^{\infty }{H_{\mathrm{DAC}}\left(f\right)H_{\mathrm{TX}}\left(s\right)H_{\mathrm{RX}}\left(s\right)-H_{\mathrm{RC}}\left(f\right){}^{-j2\pi f\tau }}^2W\left(f\right)f,& \left(14\right)\end{array}$

  
• where the function H[0133]_RC(f) is a square-root raised cosine function. The function H_RC(f) is characterized by the parameters α_kand 1/T_k. Equation 14 includes the effects of the transmit digital toanalog converters406 and407 (FIG. 4) as well as the analog transmitfilters408 and409 (FIG. 4) to set the overall response offilters408 and409, filters504-k and505-k, and transmitter digital toanalog converters406 and407 to the target response function H_RC(f). In some embodiments, H_TX(f) and H_RX(f) can be the same.
• The output signals from low-pass filters[0134]504-k and505-k can, in some embodiments, be amplified in variable gain amplifiers521-k and522-k, respectively. In some embodiments, the gains g_k^1(I)and g_k^1(Q)of amplifiers521-k and522-k, respectively, are set such that the dynamic range of analog-to-digital converters506-k and507-k, respectively, is filled. The output signals from amplifiers521-k and522-k, then, are
• r_k^I(t)=LPF[Z(t)cos(2π{circumflex over (f)}_kt)]g_k^1(I)
• r_k^Q(t)=LPF[Z(t)sin(2π{circumflex over (f)}_kt)]g_k^1(Q),  (15)
• where g[0135]_k^1(I)and g_k^1(Q)represents the gain of amplifiers521-k and522-k, respectively. The gains of amplifiers521-k and522-k can be set in an automatic gain control circuit (AGC)520-k. An embodiment of automatic gain circuit520-k where g_k^1(I)and g_k^1(Q)are set equal to one another is shown in FIGS. 8A and 8B. In some embodiments, amplifiers521-k and522-k can be before or incorporated within filters504-k and505-k, respectively.
• As shown in FIG. 5A, the signals output from analog filter[0136]561-k, signals r_k^I(t) and r_k^Q(t), are input to analog-to-digital converters (ADC)506-k and507-k, respectively, which forms digitized signals R_k^I(t) and R_k^Q(t) corresponding with the analog signals r_k^I(t) and r_k^Q(t), respectively. In some embodiments, ADCs506-k and507-k operate at a sampling rate that is the same as the transmission symbol rate, e.g. the QAM symbol rate. In some embodiments, ADCs506-k and507-k can operate at higher rates, for example twice the QAM symbol rate. The timing clock signal SCLK, as well as the sine and cosine functions ofEquation 15, is determined by PLL523. In outputs with η=10, K=8, and n_k=6, as described above, ADCs506-k and507-k can operate at a rate of about 208 Msymbols/sec or, in embodiments with K=16, about 104 Msymbols/sec. In some embodiments, ADCs506-k and507-k can be 8-bit ADCs. However, for 128 QAM operation, anything more than 7 bits can be utilized.
• In some embodiments, the gain of amplifiers[0137]521-k and522-k of analog filters560-k can be set by automatic gain control circuit (AGC)520-k (see FIG. 5C). Gain control circuit520-k can receive the digital output signals from ADCs506-k and507-k, R_k^I(n) and R_k^Q(n), respectively, and determines the gain g¹_k(n+1) for each of amplifiers521-k and522-k (i.e., in this embodiment g^1(I)_k(n) and g^1(Q)_k(n) are equal). FIGS. 8A and 8B show some embodiments of AGC520-k. The embodiment of AGC520-k shown in FIG. 8A includes an AGC phase detector801 and anintegrator802. Phase detector801 estimates whether or not the mean-squared-power of signals R_k^I(t) and R_k^Q(t) are at a pre-determined threshold value and, if not, provides a correction signal to adjust the amplitudes of signals r_k^I(t)and r_k^Q(t). The output signal from phase detector801 can be given by
• p_k^g(n)=[G_th−(R_k^I(n)²+R_k^Q(n)²)],   (16)
• where G[0138]_this the mean squared power of the signals input to ADCs506-k and507-k once AGC520-k converges. The output signal from phase detector801, p_k^g(n), is then input tointegrator802.Integrator802 digitally adjusts the gain g_kaccording to
• g_k¹(n+1)=g_k¹(n)+α_gp_k^g(n),  (17)
• where α[0139]_gdetermines the rate of adaptation of the AGC algorithm. The constant α_gcan be chosen to be a negative power of 2 for ease of implementation.
• The embodiment of phase detector[0140]520-k shown in FIG. 8B includes twophase detectors803 and804 which calculate the mean squared powers of R_k^I(n) and R_k^Q(n) separately and compare them with thresholds G_th^Iand G_th^Q, respectively. The output signals fromphase detectors803 and804 can be given by
• p_k^g−I(n)=[G_th^I−(R_k^I(n)²)]
• p_k^g−Q(n)=[G_th^Q−(R_k^Q(n)²)],  (18)
• respectively. The output signals from[0141]detectors803 and804 can then be integrated in integrators805 and806 according to
• g_k^1−I(n+1)=g_k^1−I(n)+α_g^Ip_k^g−I(n),
• and[0142]
• g_k^1−Q(n+1)=g_k^1−Q(n)+α_g^Qp_k^g−Q(n),  (19)
• where α[0143]_g^Iand α_g^Qdetermine the rate of adaptation of the AGC algorithm as in Equation 17 above.
• In some embodiments AGC[0144]520-k can include a peak detection algorithm so that the gain values g_k^1(I)and g_k^1(Q)are determined from the peak values of R_k^Iand R_k^Q, respectively. Again, the peak values of R_k^Iand R_k^Qcan be compared with threshold values and the gain values g_k^1(I)and g_k^1(Q)adjusted accordingly.
• As shown in FIG. 5A, the output signals from ADCs[0145]506-k and507-k, R_k^Iand R_k^Q, respectively, are input to a first digital filter562-k. An embodiment of first digital filter562-k is shown in FIG. 5D. In some embodiments of the invention, the in-phase and quadrature data paths may suffer from small differences in phase and small differences in gain. Therefore, in some embodiments a phase and amplitude correction is included in digital filter562-k. In order to correct the phase and amplitude between the in-phase and quadrature data paths, one of the values R_k^I(n) and R_k^Q(n) is assumed to be of the correct phase and amplitude. The opposite value is then corrected. In the embodiment shown in FIG. 5D, R_k^I(n) is assumed to be correct and R_k^Q(n) is corrected. The phase error can be corrected by using the approximation for small θ_k^cwhere sin θ_k^cis approximately θ_k^c, and cos θ_k^cis approximately one. This correction can be implemented by subtracting in summer536-k the value θ_k^cR_k^I(n) calculated in multiplier535-k to R_k^Q(n). The amplitude of R_k^Q(n) can be corrected by adding a small portion η_k^cof R_k^Q(n), calculated in multiplier533-k, in summer536-k. The value η_k^ccan be determined in tracking and recovery block517-k by integrating the difference in magnitude of the output signals from summer534-k and536-k, F_k^I(n) and F_k^Q(n), in a very low frequency integration block (for example several kHz), such that$\begin{array}{cc}{\eta }_k^c=\int \left(F_k^I\left(n\right)-F_k^Q\left(n\right)\right)n.& \left(20\right)\end{array}$

  
• The value θ[0146]_k^ccan be chosen in tracking and recovery block517-k by$\begin{array}{cc}{\theta }_k^c=\int \left(\mathrm{sign}\left(F_k^I\left(n\right)\right)F_k^Q\left(n\right)+\mathrm{sign}\left(F_k^Q\left(n\right)\right)F_k^I\left(n\right)\right)n.& \left(21\right)\end{array}$

  
• Additionally, an arithmetic offset can be implemented by subtracting the value OFFSET[0147]₁^Iin summer534-k to R_k^I(n) and subtracting the value OFFSET₁^Qin summer536-k. The offset values OFFSET₁^Iand OFFSET₁^Qcan be adaptively chosen in tracking and recovery block517-k by integrating the output signals from summer534-k and summer536-k, F_k^I(n) and F_k^Q(n), respectively, in a low frequency integration. The offsets implemented in summer534-k and536-k offset the dc offset not corrected in analog filter561-k, e.g. by offsets530-k and531-k, for example, as well as arithmetic errors in summers534-k,536-k and multipliers535-k and533-k.
• The output signals from summers[0148]534-k and536-k, then, can be given by
• F_k^I(n)=R_k^I(n)−OFFSET_1,k^I,
• and[0149]
• F_k^Q(n)=(1+η_k^c)R_k^Q(n)−θ_k^cR_k^I(n)−OFFSET_1,k^Q.  (22)
• In some embodiments, the parameters OFFSET[0150]_1,k^I, OFFSET_1,k^Q, η_k^cand θ_k^cvary for each cycle n. Additionally, the parameters can be different for each of the k receivers222-1 through222-k.
• The output signals from summers[0151]534-k and536-k, F_k^I(n) and F_k^Q(n), respectively, are then input to a phase rotation circuit512-k. Phase rotation512-k rotates signals F_k^I(n) and F_k^Q(n) according to the output of a carrier phase and frequency offset correction circuit, which depends on the difference between {circumflex over (f)}_kand f_k, and the relative phase of the transmit mixers (multipliers410 and411) and the receive mixers (multipliers501-k and502-k) and transmission channel250 (FIG. 2A). The rotation angle θ^_k^I(n) is computed in carrier tracking and timing recovery block517. The resultant output signals of carrierphase rotation circuit512, D_k^I(n) and D_k^Q(n), can be given by:
• D_k^I(n)=F_k^I(n)cos({circumflex over (θ)}_k^I(n))+F_k^Q(n)sin(θ^_k^I(n))
• D_k^Q(n)=F_k^Q(n)cos({circumflex over (θ)}_k^I(n))−F_k^I(n)sin(θ^_k^I(n)).  (23)
• The output signals from rotation circuit[0152]512-k, D_k^I(n) and D_k^Q(n), are then input to a complex adaptive equalizer513-k to counter the intersymbol interference caused by frequency dependent channel attenuation, and the reflections due to connectors and vias that exist in communication system200 (which can be a backplane communication system, an inter-cabinet communication system, or a chip-to-chip communication system) and both transmit and receive low pass filters, e.g. filters408 and409 of FIG. 4 and filters504-k and505-k of FIG. 5C.
• It should be noted that because of the frequency division multiplexing of data signals, as is accomplished in transmitter system[0153]210-p and receiver system220-p, the amount of equalization needed in any one of channels301-0 through301-K is minimal. In some embodiments, such as the 16-channel, 6 bit per channel, 10 Gbps example, only about 1-2 dB of transmission channel magnitude distortion needs to be equalized. In 8 channel embodiments, 3-4 dB of distortion needs to be equalized. In other words, the number of taps required in a transport function for equalizer513-k can be minimal (e.g., 1-4 complex taps) in some embodiments of the present invention, which can simplify receiver220-p considerably. In some embodiments of the invention,equalizer513 can have any number of taps.
• Complex Equalizer[0154]513-k can be either a linear equalizer (i.e., having a feed-forward section only) or a decision feed-back equalizer (i.e., having a feed-forward and a feedback portion). The coefficients of the equalizer transfer function are complex-valued and can be adaptive. In some embodiments, the complex equalizer coefficients that operate on signals D_k^Iand D_k^Qare the same, but in other embodiments the complex equalizer coefficients are allowed to be different for D_k^Iand D_k^Q.
• Additionally, the feed-forward portion of an adaptive equalizer (either a linear equalizer or decision feed-back equalizer) can be preceded by a non-adaptive all-pole filter with[0155]transfer function 1/A(z). In some embodiments, the coefficients of A(z), which can be found by a minimum mean squared error technique, can be real-valued, for example
• A(Z)=1.0+0.75Z⁻¹+0.0625Z⁻²+0.0234375Z⁻³+0.09375Z⁻⁴,  (24)
• which can be rewritten as[0156]$\begin{array}{cc}A\left(Z\right)=1+0.75Z^{-1}+\frac{1}{16}Z^{-2}+\left(\frac{1}{64}+\frac{1}{128}\right)Z^{-3}+\left(\frac{1}{16}+\frac{1}{32}\right)Z^{-4}.& \left(25\right)\end{array}$

  
• The resulting transfer function H(z)=1/A(z) can be implemented in a linear equalizer or a decision feedback equalizer. In some embodiments, however, complex adaptive equalizer[0157]513-k includes adaptively chosen parameters.
• In general, complex adaptive equalizer[0158]513-k can be a decision feedback equalizer (DFE) or a linear equalizer. See, e.g., Edward A. Lee, and David G. Messerschmitt, Digital Communication, pp. 371-402 (Kluwer Academic Publishers, 1988). The in-phase and quadrature output signals fromadaptive equalizer513 in embodiments with linear equalization can be given by:$\begin{array}{cc}{E}_k^I\left(n\right)=\sum _{j=-M}^NC_k^{x,I}\left(j,n\right)D_k^I\left(n-j\right)-C_k^{y,I}\left(j,n\right)D_k^Q\left(n-j\right)\mathrm{and}E_k^Q\left(n\right)=\sum _{j=-M}^NC_k^{x,Q}\left(j,n\right)D_k^Q\left(n-j\right)+C_k^{y,Q}\left(j,n\right)D_k^I\left(n-j\right).& \left(26\right)\end{array}$

  
• where j refers to the tap Z[0159]^{31 j}. The complex adaptive equalizer coefficients C_k^x,I(j,n), C_k^y,I(j,n), C_k^x,Q(j,n) and C_k^y,Q(j,n) can be updated according to the least mean squares (LMS) algorithm as described in Bernard Sklar, Digital Communications, Fundamentals and Applications (Prentice-Hall, Inc.,1988), for example. In some embodiments, equalizer coefficients C_k^x,I(j,n) and C_k^x,Q(j,n) are the same and equalizer coefficients C_k^y,Q(j,n) and C_k^y,Q(j,n) are the same.
• In some embodiments of the invention, the center coefficients of the feed-forward part of equalizer[0160]513-k, C_k^x,I(0,n), C_k^y,I(0,n), C_k^x,Q(0,n) and C_k^y,Q(0,n) can each be fixed at 1 and 0, respectively, to avoid interaction with the adaptation of gain coefficients g_k^2(I)and g_k^2(Q)used in amplifiers537-k and538-k of a second digital filter563-k and the carrier phase correction performed in phase rotator512-k. Additionally, in some embodiments the coefficients C_k^x,I(−1,n), C_k^y,I(−1,n), C_k^x,Q(−1,n) and C_k^y,Q(−1,n) can be fixed at constant values to avoid interaction with the adaptation of the phase parameter τ^_kby tracking and timing recovery517-k. For example, the parameters C_k^x,I(−1,n) and C_k^x,Q(−1,n) can be −¼-{fraction (1/16)}, which is −0.3125, and the parameters C_k^y,I(−1,n) and C_k^y,Q(−1,n) can be −{fraction (1/64)}, which is −0.015625. In some embodiments, one set of parameters, for example C_k^x,I(−1,n) and C_k^x,Q(−1,n), are fixed while the other set of parameters, for example C_k^y,I(−1,n) and C_k^y,Q(−1,n), can be adaptively chosen.
• In some embodiments of the invention, for example, C[0161]_k^x,I(−1,n) and C_k^y,I(−1,n) are fixed and the timing recover loop of adaptive parameters517-2 for determining the phase parameter τ^_kutilizes errors e_k^Ionly (see FIG. 7). In that way, adaptively choosing parameters in the Q channel do not interact with the timing loop. In some embodiments, the opposite can be utilized (i.e., C_k^x,Q(−1,n) and C_k^y,Q(−1,n) are fixed and the timing loop determines the phase parameter τ^_kfrom error parameter e_k^Q).
• The output signals from each of digital filters[0162]562-1 through562-K, signals E₁^I(n) and E₁^Q(n) through E_K^I(n) and E_K^Q(n), respectively, are input to cross-channel interference filter570. Cross-channel interference canceller570 removes the effects of cross-channel interference. Cross-channel interference can result, for example, from harmonic generation in the transmitter and receiver mixers, as has been previously discussed. As described in the embodiment of digital filter562-k shown in FIG. 5D, equalization for intersymbol interference can be performed in digital filter562-k. In some embodiments of the invention, cross-channel interference filter570 may be placed before equalizer513-k (in other words, equalizer513-k may be placed in digital filter563-2 instead of digital filter562-2).
• The output signals from digital filter[0163]562-2, E_k^I(n) and E_k^Q(n), for each of receivers222-1 through222-K are input to cross-channel interference filter570. An embodiment of cross-channel interference canceller570 is shown in FIG. 5F. For convenience of discussion, the input signals E_k^I(n) and E_k^Q(n) are combined into a complex value E_k(n)=E_k^I(n)+iE_k^Q(n) (where i is {square root}{square root over (−1)}). Each of the complex values E₁through E_Kis input to a summer571-1 through571-K, respectively, where contributions from all of the other channels are removed. The output signals from summers571-1 through571-K, H₁through H_K, respectively, are the output signals from cross-channel interference filter570. Again, the complex value H_k(n) is H_k¹(n)+iH_k^Q(n), representing the in-phase and quadrature output signals.
• The signal E[0164]_kis also input to blocks572-k,1 through572-k,k−1 and blocks572-k,k+1 to572-k,K. Block572-k,l, an arbitrary one of blocks572-1,2 through572-K, K−1, performs a transfer function Q_k,lwhich determines the amount of signal E_kwhich should be removed from E_lto form H_l. Further, delays573-1 through573-K delay signals E₁through E_Kfor a set number of cycles N to center the cancellations in time. Therefore, the output signals H₁through H_Kcan be determined as$\begin{array}{cc}\left(\begin{array}{c}{H}_1\\ {\mathrm{<figure-callout\; label="H"\; filenames="US20030112896A1-20030619-D00006.png,US20030112896A1-20030619-D00009.png"\; state="\{\{state\}\}">H</figure-callout>}}_2\\ ⋮\\ H_k\\ ⋮\\ H_K\end{array}\right)=\left(\begin{array}{cccccc}{Z}^{-\mathrm{<figure-callout\; label="N"\; filenames="US20030112896A1-20030619-D00008.png,US20030112896A1-20030619-D00009.png"\; state="\{\{state\}\}">N</figure-callout>}}& 0& \cdots & 0& \cdots & 0\\ 0& Z^{-N}& \cdots & 0& \cdots & 0\\ ⋮& ⋮& ⋰& ⋮& \cdots & ⋮\\ 0& 0& \cdots & Z^{-N}& \cdots & 0\\ ⋮& ⋮& \cdots & ⋮& ⋰& ⋮\\ 0& 0& \cdots & 0& \cdots & Z^{-N}\end{array}\right)\left(\begin{array}{c}{E}_1\\ {\mathrm{<figure-callout\; label="E"\; filenames="US20030112896A1-20030619-D00006.png,US20030112896A1-20030619-D00009.png"\; state="\{\{state\}\}">E</figure-callout>}}_2\\ ⋮\\ E_k\\ ⋮\\ E_K\end{array}\right)-\left(\begin{array}{cccccc}0& {\mathrm{<figure-callout\; label="Q"\; filenames="US20030112896A1-20030619-D00006.png,US20030112896A1-20030619-D00009.png"\; state="\{\{state\}\}"><figure-callout\; label="Q"\; filenames="US20030112896A1-20030619-D00001.png,US20030112896A1-20030619-D00005.png"\; state="\{\{state\}\}">Q</figure-callout></figure-callout>}}_{2,1}& \cdots & Q_{k,1}& \cdots & Q_{K,1}\\ {\mathrm{<figure-callout\; label="Q"\; filenames="US20030112896A1-20030619-D00001.png,US20030112896A1-20030619-D00005.png"\; state="\{\{state\}\}"><figure-callout\; label="Q"\; filenames="US20030112896A1-20030619-D00006.png,US20030112896A1-20030619-D00009.png"\; state="\{\{state\}\}">Q</figure-callout></figure-callout>}}_{1,2}& 0& \cdots & Q_{k,2}& \cdots & Q_{K,2}\\ ⋮& ⋮& ⋰& ⋮& ⋮& ⋮\\ {\mathrm{<figure-callout\; label="Q"\; filenames="US20030112896A1-20030619-D00001.png,US20030112896A1-20030619-D00005.png"\; state="\{\{state\}\}">Q</figure-callout>}}_{1,\mathrm{<figure-callout\; label="k\; Q"\; filenames="US20030112896A1-20030619-D00006.png,US20030112896A1-20030619-D00009.png"\; state="\{\{state\}\}">k</figure-callout>}}& Q_{}{}_{2,k}& \cdots & 0& \cdots & Q_{K,k}\\ ⋮& ⋮& ⋮& ⋮& ⋰& ⋮\\ {\mathrm{<figure-callout\; label="Q"\; filenames="US20030112896A1-20030619-D00001.png,US20030112896A1-20030619-D00005.png"\; state="\{\{state\}\}">Q</figure-callout>}}_{1,\mathrm{<figure-callout\; label="K\; Q"\; filenames="US20030112896A1-20030619-D00006.png,US20030112896A1-20030619-D00009.png"\; state="\{\{state\}\}">K</figure-callout>}}& Q_{}{}_{2,K}& \cdots & Q_{k,K}& \cdots & 0\end{array}\right)\left(\begin{array}{c}{E}_1\\ {\mathrm{<figure-callout\; label="E"\; filenames="US20030112896A1-20030619-D00006.png,US20030112896A1-20030619-D00009.png"\; state="\{\{state\}\}">E</figure-callout>}}_2\\ ⋮\\ E_k\\ ⋮\\ E_K\end{array}\right),& \left(27\right)\end{array}$

  
• where Z[0165]⁻¹represents a once cycle delay. The transfer functions Q_k,lcan have any number of taps and, in general, can be given by
• Q_k,l=σ_k,l⁰+σ_k,l¹Z⁻¹+σ_k,l²Z⁻²+ . . . +σ_k,l^MZ^−M.  (28)
• In general, each of the functions Q[0166]_k,lcan have a different number of taps M and N can be different for each channel In some embodiments, the number of taps M for each function Q_k,lcan be the same. In some embodiments, delays can be added in order to match the timing between all of the channels. Further, in general delays573-1 through573-K can delay signals E₁through E_Kby a different number of cycles. In some embodiments, where each of functions Q_k,lincludes M delays, each of delays573-1 through573-K includes N=M/2 delays where N is rounded to the nearest integer.
• The coefficients σ[0167]_k,l⁰through σ_k,l^Mcan be adaptively chosen in cross-channeladaptive parameter block571 as shown in FIG. 5A in order to optimize the performance of receiver system220-p. In some embodiments, M is chosen to be 5. In some embodiments, transfer function Q_k,lmay be constants, M=0. Cross-channeladaptive parameter block571 is further discussed below.
• Therefore, in cross channel interference canceller[0168]570 the cross channel interference is subtracted from the output signals from digital filters562-1 through562-K as indicated by Equation 26. The output signals from cross-channel interference canceller570 for an arbitrary one of receivers222-k, H_k^Iand H_k^Q, can be input to a second digital filter563-k. An embodiment of second digital filter563-k is shown in FIG. 5E.
• The parameters σ[0169]_k,l^mof Equation 28 can be adaptively chosen. In the adaptation algorithm, the real and imaginary parts of σ_k,l^mcan be adjusted separately. The adaptive adjustments of parameters σ_k,l^mis further discussed below.
• As shown in FIG. 5E, the signals H[0170]_k^Iand H_k^Qcan be input to AGC controlled amplifiers537-k and538-k, respectively. The gains of amplifiers537-k and538-k, g_k^2(I)and g_k^2(Q), respectively, are set such that the output signals from amplifiers537-k and538-k yield appropriate levels for the symbol set. The gain values g_k^2(I)and g_k^2(Q)are set in tracking and timing recovery517-k and can be determined in much the same fashion as in AGC520-k of FIG. 5C. In the embodiment shown in FIG. 7, the gain values g_k^2(I)and g_k^2(Q)are determined based on the sign of the determined symbol from decision unit516-k and the error signal. These calculations are discussed further below.
• The output signals from amplifiers[0171]537-k and538-k can be input to quadrature correction540-k. Quadrature correction540-k corrects for the phase error between the in-phase and quadrature mixers at the transmitter. The angle θ^_k⁽²⁾(n) of the phase error can be adaptively chosen in tracking and timing recovery517. The value θ^_k⁽²⁾(n) can be changed very slowly and can be almost constant.
• Additionally, arithmetic offsets OFFSET[0172]_2Iand OFFSET₂^Qcan be subtracted in summers541-k and542-k, respectively. The values of OFFSET₂^Iand OFFSET₂^Qcan be adaptively chosen in tracking and timing recovery517-k. In some embodiments, the OFFSET₂^Iand OFFSET₂^Qcan be set by integrating the output signals of summers541-k and542-k, G_k^I(n) and G_k^Q(n), respectively. Alternatively, as shown in FIG. 7, OFFSET_2k^Iand OFFSET₂^Qcan be set such that the error at decision unit516-k is zero. In that embodiment, data dependent jitter can be reduced. In some embodiments, tracking and timing recovery517-k integrates the error values between the output samples from decision unit516-k and the output signals G_k^I(n) and G_k^Q(n) to minimize the error values.
• The output signals G[0173]_k^I(n) and G_k^Q(n), then, are given by
• G_k^I(n)=g_k^2−IE_k^I(n)−OFFSET₂^I
• G_k^Q(n)=g_k^2−QE_k^Q(n)−g_k^2−IE_k^I(n)θ^_k⁽²⁾−OFFSET₂^Q.  (29)
• FIG. 7 shows an embodiment of Tracking and Timing Recovery[0174]517-k. Tracking and timing recovery517-k inputs decision values â_k^I(n) and â_k^Q(n), which are decisions of the symbol values based on the signals G_k^I(n) and G_k^Q(n) in decision unit516-k, and error values e_k^I(n) and e_k^Q(n) based on the decided values â_k^I(n) and â_k^Q(n) and the values G_k^I(n) and G_k^Q(n). In some embodiments, the error values e_k^I(n) and e_k^Q(n) are the differences between the decided values â_k^I(n) and â_k^Q(n) and the values G_k^I(n) and G_k^Q(n). The coefficients of equalizer513-k of first digital filter562-k are computed in coefficient update702-k.
• The coefficients of Equalizer[0175]513-k of FIG. 5D are updated in tracking and timing recovery block517-k. In a multi-top equalizer, for example, equalizer coefficients can be updated according to the following update equations:$\begin{array}{cc}{C}_k^x\left(j,n+1\right)=C_k^x\left(j,n\right)-\mu \left[e_k^I\left(n\right)D_k^I\left(n-j\right)+e_k^Q\left(n\right)D_k^Q\left(n-j\right)\right]\mathrm{and}C_k^y\left(j,n+1\right)=C_k^y\left(j,n\right)-\mu \left[e_k^Q\left(n\right)D_k^I\left(n-j\right)-e_k^I\left(n\right)D_k^Q\left(n-j\right)\right],& \left(30\right)\end{array}$

  
• where μ is the constant that determines the rate of adaptation of the coefficients, j indicates the tap of the coefficient, and e[0176]_k^I(n) and e_k^Q(n) are estimated error values. The constant μ is chosen to control the rate of adaptation, and, in some embodiments, is in the range of 2⁻⁸to 2⁻¹⁴. In some embodiments, the coefficient μ can be different for the update equation for C_k^xand the update equation for C_k^y. The estimated error values, which are computed by decision block516-k, can be computed according to:
• e_k^I(n)=G_k^I(n)−â_k^I(n)
• and[0177]
• e_k^Q(n)=G_k^Q(n)−â_k^Q(n),  (31)
• where G[0178]_k^I(n) and G_k^Q(n) are corrected values of E_k^I(n) and E_k^Q(n), respectively, and {â_k^I(n),â_k^Q(n)} is the decision set based on the sample set {G_k^I(n),G_k^Q(n)}, and represents the closest QAM symbol in Euclidean distance to the sample set. See, e.g., Edward A. Lee, and David G. Messerschmitt, Digital Communication, pp. 371-402 (Kluwer Academic Publishers, 1988). A decision set {â_k^I(n),â_k^Q(n)} can be computed based on sample set {G_k^I(n),G_k^Q(n)} in decision unit516-k and the results received into tracking and timing recovery circuit517 where the estimated error values of Equation 30 and the resulting coefficient updates of Equation 30 are computed.
• FIG. 7 shows a block diagram of equalizer coefficient update, carrier tracking and timing recovery block[0179]517-k. Block517-k includes coefficient update block702-k. Errors e_k^I(n) and e_k^Q(n) are computed in decision block516-k according to Equation 30. Coefficient update702-k receives errors e_k^I(n) and e_k^Q(n) signals D_k^I(n) and D_k^Q(n) from phase rotator circuit512-k shown in FIG. 5D and calculates updated equalizer coefficients for complex adaptive equalizer513-k shown in FIG. 5D according to Equation 30.
• Tracking and timing recovery circuit[0180]517-k can also include a carrier recovery loop for controlling carrier phase rotation circuit512-k shown in FIG. 5D and a timing recovery loop for controlling the phase of sampling clock signal SCLK from PLL523. In some embodiments, the timing recovery loop for determining τ_k(n+1) in tracking and timing recovery517 can be implemented as a 2^ndorder digital phase locked loop as shown in FIG. 7.
• The errors e[0181]_k^I(n) and e_k^Q(n) and the decisions â_k^I(n) and â_k^Q(n) from decision unit516-k are input to phase detector703-k. Phase detector703-k can produce an estimate of the phase error p_k^τ, in some embodiments according to the following equation:$\begin{array}{cc}{p}_k^{\tau }\left(n\right)=\left[e_k^I\left(n-1\right){\hat{a}}_k^I\left(n\right)-e_k^I\left(n\right){\hat{a}}_k^I\left(n-1\right)\right]+\left[e_k^Q\left(n-1\right){\hat{a}}_k^Q\left(n\right)-e_k^Q\left(n\right){\hat{a}}_k^Q\left(n-1\right)\right].& \left(32\right)\end{array}$

  
• Alternatively, the phase error p[0182]_k^τ can be calculated from$\begin{array}{cc}{p}_n^{\tau }\left(n\right)=e_k^I\left(n-1\right)\left[{\hat{a}}_k^I\left(n\right)-{\hat{a}}_k^I\left(n-2\right)\right]+e_k^Q\left(n-1\right)\left[{\hat{a}}_k^Q\left(n\right)-{\hat{a}}_k^Q\left(n-2\right)\right],& \left(33\right)\end{array}$

  
• which can be simpler to implement than Equation 32. In embodiments where the phase correction τ^[0183]_kis calculated from e_k^Ionly or from e_k^Qonly, as discussed above, then the terms containing e_k^Qor the terms containing e_k^I, respectively, are dropped from Equations 32 and 33.
• The output signal from phase detector[0184]703-k, p_k^τ, can then be input to a 2^ndorder loop filter, which in some embodiments can have a transfer function given by$\begin{array}{cc}L\left(z\right)={\alpha }_{\tau }+{\beta }_{\tau }\frac{z^{-1}}{1-z^{-1}}& \left(34\right)\end{array}$

  
• where α[0185]_τ and β_τ are the loop filter coefficients that determine the timing recovery loop bandwidth and damping factor. In some embodiments, a loop bandwidth equal to 1% of baud rate, and damping factor equal to 1 can be implemented. The loop bandwidth and damping factors can depend not only on loop filter coefficients, but also on phase detector slope, and the digital integrator gain. Thus, the output signal L_k^τ(n) from loop filter705-k is given by
• L_k^τ(n)=α_τp_k^τ(n)+I_k^τ(n),
• where[0186]
• I_k^τ(n)=I_k^τ(n−1)+β_τp_k^τ(n−1).  (35)
• The output signal from loop filter[0187]705-k, L_k^τ(n), is then input to a digitally implemented integrator707-k, the output of which is the phase correction τ{circumflex over (0 )}_k(n) given by
• {circumflex over (τ)}_k(n+1)={circumflex over (τ)}_k(n)+L_k^τ(n).  (36)
• The phase correction τ^[0188]_k(n) is then received by PLL523, as described above.
• The carrier phase recovery loop which computes the parameter θ^ utilized in phase rotation[0189]512-k can also be implemented as a 2^ndorder digital phase locked loop as shown in FIG. 7. Phase detector704-k receives decision values {â_k^I(n),â_k^Q(n)} and error signals {e_k^I(n),e_k^Q(n)} from decision unit516-k, and produces an estimate of the phase error. In some embodiments, the estimate of the phase error p_k^θ(n) performed by phase detector704-k can be given by:$\begin{array}{cc}{p}_k^{\theta }\left(n\right)=\left[e_k^Q\left(n\right)\mathrm{sign}\left\{{\hat{a}}_k^I\left(n\right)\right\}-e_k^I\left(n\right)\mathrm{sign}\left\{{\hat{a}}_k^Q\left(n\right)\right\}\right],\mathrm{where}& \left(37\right)\\ \mathrm{sign}\left(x\right)=\{\begin{array}{cc}1& \mathrm{if}x\ge 0\\ -1& \mathrm{if}x<0\end{array}.& \left(38\right)\end{array}$

  

   sign(x)=1 ifx≧0−1 ifx<0.  (38)
• The output signal from phase detector[0190]704-k can be input to a 2^ndorder loop filter706-k with a transfer function given by$\begin{array}{cc}L\left(z\right)={\alpha }_{\theta }+{\beta }_{\theta }\frac{z^{-1}}{1-z^{-1}},& \left(39\right)\end{array}$

  
• where α[0191]_θ and β_θ are the loop filter coefficients that determine the carrier tracking loop bandwidth and the damping factor. Thus, the output signal from loop filter706-k is given by
• L_k^θ(n)=α_θp_k^θ(n)+I_k^θ(n)
• where[0192]
• I_k^θ(n)=I_k^θ(n−1)+β_θp_k^θ(n−1).  (40)
• The output signal from loop filter[0193]706-k is then input to a digitally implemented integrator708-k. The output signal fromintegrator708, θ^_k(n+1), is then given by
• {circumflex over (θ)}_k(n+1)={circumflex over (θ)}_k(n)+L_k^θ(n).  (41)
• The carrier tracking loop output signal θ^[0194]_k((n), output from integrator708-k, is then input to phase rotation circuit512-k of FIG. 5D.
• Further, as shown in FIG. 7, the parameter θ[0195]_k^c(n+1) can be calculated by phase detector720-k and integrator722-k as described inEquation 21. As described above, the parameter η_k^c(n+1) input into multiplier533-k shown in FIG. 5D can be calculated byblocks723 andintegration block724 according toEquation 20.
• As shown in Blocks[0196]725-k and726-k, the offset values OFFSET₁^Iand OFFSET₁^Qinput to summers534-k and536-k, respectively, of the embodiment of digital filter562-k shown in FIG. 5D can be determined by integrating the signals F_k^I(n) and F_k^Q(n), respectively. Similarly, the offset values OFFSET₂^Iand OFFSET₂^Qinput to sununers541-k and542-k, respectively, of digital filter563-k shown in FIG. 5E can be calculated by integrating the signals G_k^I(n) and G_k^Q(n), respectively. The embodiment of adaptive parameter block517-k shown in FIG. 7 calculates OFFSET₂^Iand OFFSET₂^Qby integrating the error signals e_k^I(n) and e_k^Q(n), respectively.
• Further, the coefficient θ^[0197]_k⁽²⁾to quadrature correction540-k of FIG. 5E can be calculated by phase detector729-k and integrator731-k. The output signal from phase detector729-k can be calculated by$\begin{array}{cc}{P}_k^{\mathrm{\theta 2}}=-\mathrm{sign}\left({\hat{a}}_k^I\left(n\right)\right)e_k^Q\left(n\right)-\mathrm{sign}\left({\hat{a}}_k^Q\left(n\right)\right)e_k^I\left(n\right)& \left(42\right)\end{array}$

  
• The output signal from integrator[0198]731 -k, then, can be given by
• θ_k⁽²⁾(n+1)=θ_k⁽²⁾(n)+α_θP_k^θ2  (43)
• The gains g[0199]_k²⁻¹and g_k^2−Qcan be calculated by phase detector732 and integrator734. In some embodiments, phase detector732-k calculates the quantities
• and[0200]
• p_k^g2−I(n)=−e_k^I(n)sign(â_k^I(n))
• and[0201]
• p_k^g2−Q(n)=−e_k^Q)(n)sign(â_k^Q(n)).  (44)
• The output signals from integrator[0202]734-k, then, can be given by
• g_k^2−I(n+1)=g_k^2−I(n)+α_gp_k^g2−I
• and[0203]
• g_k^2−Q(n+1)=g_k^2−Q(n)+α_gp_k^g2−Q,  (45)
• where α[0204]_gdetermines how fast the gain values respond to changes.
• As show in FIG. 5A, cross-channel[0205]adaptive parameter block571 adaptively adjusts the parameters of cross-channel interference canceller570, all of the σ_k,Iⁱparameters of Equations 26 and 27. In an embodiment where the cross-channel transfer functions Q_k,lis a 5 tap function and K=8, there are 5*K*(K−1)=280 individual complex parameters σ_k,Iⁱto adjust in Equations 27 and 28.
• In some embodiments, cross-channel[0206]adaptive parameter block571 receives the complex input values E₁through E_K, where E_k, an arbitrary one of them, is given by E_k=E_k^I+iE_k^Q(see FIG. 5F), and error signals {e_k(n)=e_k^I(n)+ie_k^Q(n)} from decision unit516-k of each of receivers222-1 through222-K. On start-up of receiver system220-p, all of complex parameters σ_k,I^jcan be set to 0. Each of complex parameters σ_k,I^jcan then be updated according to
• σ_k,l^m,x(n+1)=σ_k,l^m,x(n)−ν_k,l^m,x(e₁^I(n)E_k^I(n−m)+e₁^Q(n)E_k^Q(n−m),  (b46)
• and[0207]
• σ_k,l^m,y(n+1)=σ_k,l^m,y(n)−ν_k,l^m,y(e₁^Q(n)E_k^I(n−m)−e₁^I(n)E_k^Q(n−m),  (47)
• where[0208]
• σ_k,1^m=σ_k,1^m,x+iσ_k,1^m,y,  (48)
• where ν[0209]_k,l^m=ν_k,1^m,x+iν_k,1^m,yis the complex update coefficient for parameter σ_k,1^mand controls how fast parameter σ_k,1^mcan change, in similar fashion as has been described with other update equations above. In some embodiments, all of the parameters ν_k,l^m,xand ν_k,l^m,yeach have values on the order of 10⁻³to 10⁻⁵.
• In some embodiments,[0210]frequency shift563 generates a reference signal input to PLL523 such that the frequency of component201-p with receiver system220-p, {circumflex over (f)}₁through {circumflex over (f)}_K, matches the frequency of the corresponding component201-q with transmitter system210-q, f₁through f_K, where component201-q is transmitting data to component201-p. In embodiments where f₁through f_Kcorrespond to frequencies f₀through Kf₀, respectively, thenfrequency shift563 shifts the frequency of a reference clock such that the frequency shift Δ is zero. The frequencies {circumflex over (f)}₁through {circumflex over (f)}_K, then, are also frequencies f₀through Kf₀. In some embodiments,frequency shift563 can receive input from any or all loop filters706-k (FIG. 7) and adjusts the frequency shift such that θ^_k⁽¹⁾through θ^_k^(K)remain a constant, for example 0 or any other angle. In some embodiments,frequency shift563 receives the output signals from any or all loop filters705-k.
• As shown in FIG. 5A, the output signals from digital filter[0211]563-k, equalized samples {G_k^I(n),G_k^Q(n)}, are input to trellis decoder514-k. Trellis decoding can be performed using the Viterbi algorithm, see, e.g., G. Ungerboeck., “Channel Coding with Multilevel/Phase Signals,” IEEE Transactions on Information Theory, vol. IT-28, January 1982, pp. 55-67, G. Ungerboeck., “Trellis Coding Modulation with Redundant Signal Sets, Part I. Introduction,” IEEE Communications Magazine, vol. 25, no. 2, February 1987, pp. 5-11, G. Ungerboeck., “Trellis Coding Modulation with Redundant Signal Sets, Part II. State of the Art,” IEEE Communications Magazine, vol. 25, no. 2, February 1987, pp. 12-21, or G. C. Clark, Jr., and J. B. Cain, Error Correction Coding for Digital Communications, pp.253-264(Plenum Press, New York, 1981). Additionally,trellis decoder514 converts from the QAM symbol set back to parallel bits. The output signal fromtrellis decoder514, which now contains n_kparallel bits, is input to descrambler515-k. Descrambler515-k of receiver demodulator222-k operates to reverse the scrambling operation ofscrambler401 of transmitter modulator212-k.
• As is shown in FIG. 2C, the output signals from each of demodulators[0212]222-1 through222-K are recombined into an N-bit parallel signal in bit parsing221. Additionally, the RX clock signal is output from bit parsing221.
• FIG. 10 shows an example embodiment of[0213]trellis decoder514 according to the present invention.Trellis decoder514 of FIG. 10A includes aslicer1001, abranch metric1002, an add-compare-select (ACS)block1003, a normalization andsaturation block1004, a trace back1005, and atrellis decision block1006. The output signal fromtrellis decoder514 is the received bits, which are substantially as transmitted by transmitter210-p.
• [0214]Slicer1001 receives the output signals G_k^I(n) and G_k^Q(n) from offsetblocks541 and542, respectively. FIG. 10B shows an embodiment ofslicer1001. The value G_k^I(n) is received in x andy slicers1010 and1011, respectively.Slicer1010 slices G_k^I(n) to a first set of symbol values whileslicer1011 slices G_k^I(n) to a second set of slicer values. For example, in a 128 QAM system as shown in Table I, x-slicer1010 can slice to the symbol values −11, −7, −3, 1, 5, and 9 and y-slicer1011 can slice to the symbol values −9, −5, −1, 3, 7, 11. In some embodiments, the number of bits can be reduced by mapping the decided symbols fromslicers1010 and1011 using table1016 and1021, respectively. The output signal from tables1016 and1021, then, are i_xand i_y, indicating decisions based on the input value G_k^I(n).

  TABLE II
  INPUT	0-8	9,10	11,12,13	>14
  OUTPUT	0	1	2	3

• The errors δi[0215]_xand δi_yare also calculated. The output signals fromslicers1010 and1011 are subtracted from the input signal G_k^I(n) insummers1015 and1020, respectively. In some embodiments, the output signals fromslicers1010 and1011 are input toblocks1014 and1019, respectively, before subtraction insummers1015 and1020.Blocks1014 and1019 represent shifts. In some embodiments, the input signals toslicers1010 and1011 are 8-bit signed numbers. Thevalue 8 slices to a perfect 1. Similarly, the value −56 slices to aperfect −7. So if the input signal is a −56 it would be sliced to −7. To calculate the error, we need to multiply the −7 by 8 before it is subtracted from the incoming signal. Multiplying by 8 is the same as a shift to the left by 3.
• The absolute values of the output signals from[0216]summers1015 and1020 are then taken by blocks1017 and1022, respectively. The output signal from ABS blocks1017 and1022 can be mapped into a set of values requiring a smaller number of bits by tables1018 and1023, as in Table II above, respectively, to generate δi_xand δi_y, respectively.
• The output signals corresponding to the quadrature data path, q[0217]_x, q_y, δq_xand δq_yare generated by substantially identical procedure by slicers1012,1013,summers1025,1030, and blocks1024,1026,1027,1028,1029,1031,1032 and1033.
• [0218]Branch metric1002 receives the error signals fromslicer1001 and calculates the signals δa, δb, δc, and δd. The branch metric values δa, δb, δc, and δd indicate the path metric errors. In some embodiments, the path metric errors δa, δb, δc, and δd can be calculated as
• δa=δi_x+δq_x,
• δb=δi_y+δq_x,
• δc=δi_x+δq_y,
• δd=δi_y+δq_y,  (49)
• Add-Compare[0219]Select1003 receives the path metrics δa, δb, δc, and δd along with state metric values s₀, s₁, s₂and s₃, which are calculated in normalization andsaturation block1004. In some embodiments, the output values ofACS1003 include path metrics p₀, p₁, p₂and p₃along with choice indicators c₀, c₁, c₂and c₃. The path metrics p₀, p₁, p₂and p₃can be given by
• p₀=MIN(s₀+δa, s₂+δd),
• p₁=MIN(s₀+δd, s₂+δa),
• p₂=MIN(s₁+δb, s₃+δc),
• and[0220]
• p₃=MIN(s₁+δc, s₃+δb),  (50)
• The choice indicators c[0221]₀, c₁, c₂and c₃indicate which of the values was chosen in each of the minimization inEquation 43.
• Normalization and[0222]saturation1004 receives the path metrics p₀, p₁, p₂and p₃and calculates the state metrics s₀, s₁, s₂and s₃. In some embodiments, if the path metrics are above a threshold value, the threshold value is subtracted from each of the path metrics. In some embodiments, the smallest path metric can be subtracted from each of the path metrics p₀, p₁, p₂and p₃. Normalization andSaturation block1004 also ensures that path metrics p₀, p₁, p₂and p₃are limited to a maximum value. For example, in an embodiment where p₀, p₁, p₂and p₃are a four-bit number (range 0-15), if p₀, p₁, p₂and p₃is greater than 15, then the corresponding path metric is limited to the maximum value of 15. Then, the state metrics for the next baud period, s₀, s₁, s₂, and s₃, are set to the path metrics p₀, p₁, p₂and p₃.
• [0223]Traceback1005 receives and stores the choice indicators c₀, c₁, c₂and c₃as well as the decided values fromslicer1001 in that baud period, i_x, i_y, q_x, and q_y. The choice indicators c₀, c₁, c₂and c₃indicate the previous state values. As shown in the state transition diagram of FIG. 10C, which indicates state transitions between the encoded bits, for each of the states 0-3, there are only two possible previous states 0-3. For example, if the current state is 1, the previous state was either 0 or 2. Although any traceback depth can be utilized intraceback1005, in some embodiments a traceback depth of 6 is utilized. With the use of mapping tables1016,1021,1026 and1031 reducing the number of bits required to store i_x, i_y, q_x, and q_y, (for example a total of 8 in 128 QAM systems) and the low number of bits required to store choice indicators c₀, c₁, c₂and c₃, a low number of bits is needed. For example, in some embodiments a total of 12 bits is utilized.
• For calculating the trellis output from trace back[0224]1005, the most recently stored memory locations are utilized first with the first choice being the state with the lowest state metric. The algorithm then traces back through the stored choice indications c₀, c₁, c₂and c₃to the end of the traceback memory (in some embodiments, the sixth state) and arrives at state S. In the example trellis discussed above, the MSB of the output is the LSB of the state, S. The final state S and the choice indicator c_swill determine which pair of symbols were transmitted (I_x/I_y, Q_x/Q_y). By reading the values of these symbols from the traceback memory, a look-up in, for example, Table I will result in a read value. The five least significant bits of the read value from the look-up table, e.g. Table I, becomes the five least significant bits of the output signal. The most significant bit was determined earlier and supplies the most significant bit (MSB).
• If the example 16 state encoder described earlier is used, then a standard 16 state trellis decoder using the Viterbi algorithm can be utilized in the decoding. The 2/3 bit encoding is illustrated in Table II for the most significant bits and a look-up table for a 7 bit data mapper is illustrated in Table III.[0225]
• FIG. 9 shows a[0226]transceiver chip900 according to the present invention.Transceiver chip900 includes transmitter210-p and receiver220-p formed on a single semiconductor chip. In some embodiments,transceiver chip900 is formed in silicon using CMOS technology.Transceiver chip900 can receive N bits into transmitter210-p and output N bits from receiver220-p. In some embodiments, different pins may be utilized for input bits and output bits, as shown in FIG. 9. In some embodiments, transmitter210-p and receiver220-p share the same N pins.Transmitter900 receives a reference clock signal and outputs a receive clock signal from receiver220-p. Further,transceiver220 includes output pins for transmitting and receiving differential signals. In some embodiments, transmitter210-p and receiver220-p share the same output pins and in some embodiments transmitter210-p and receiver220-p are coupled to separate output pins. In some embodiments,transceiver chip900 may be coupled to an optical driver for optical transmission.
• Although the digital algorithms described in this disclosure are presented as digital circuitry elements, one skilled in the art will recognize that these algorithms can also be performed by one or more digital processors executing software code to perform the same functions.[0227]
• FIG. 12A shows an embodiment of[0228]baseband receiver223.Baseband transmitter217 andbaseband receiver223 may, for example, form a PAM transceiver. The signal from medium250 (see FIG. 2A) is received byanalog processing1201.Analog processing1201, for example, can include a low-pass filter in order to separate the baseband signal from those signals transported with carrier frequencies, such as those transmitted by transmitters212-1 through212-K. Filter1201 can further include some analog correction of the signals, including anti-aliasing filters, base-line wander filters, or other filters.
• FIG. 12B shows an embodiment of[0229]analog processing1201. The input signal Z(t) is received by alow pass filter1210. The parameters oflow pass filter1210 can be fixed, however in some embodiments the filter can be adjusted dynamically, for example, byadaptive parameter control1207 of FIG. 12A. The output signal fromfilter1210 is input to amplifier1211. In some embodiments, the gain of amplifier1211, g_A,can be given by
• g_A(n+1)=g_A(n)+α_A(P_A−Th−P)  (51)
• where α[0230]_Ais a multiplier which controls convergence of the gain, P_A−THis a threshold value on peak power, and P is the mean squared power S², where S is the digitized signal fromADC1202. Amplifier1211, then, arranges that the range ofADC1202 is filled.
• The output signal from amplifier[0231]1211 can be input to offset1212. The offset value OFFSET_Acan be arranged byadaptive parameter control1207 such that the average output signal S fromADC1202 is zero. The offset value OFFSET_A, for example, can be given by
• OFFSET_A(n+1)=OFFSET_A(n)−α_OFFS,  (52)
• where α[0232]_OFFis again the multiplicative factor that controls convergence and S is the signal output fromADC converter1202.
• The output signal from[0233]analog processing1201 is input toADC1202 where it is digitized.ADC1202 can have any number of bits of resolution. At least a four bit ADC, for example, can be utilized in a 16-PAM system.ADC1202 can be clocked from a clock signal generated by receiver120-p in general, for example in PLL523 as shown in FIG. 5A. In some embodiments,adaptive parameter control1207 can generate a phase signal which can add a phase to the timing ofADC1202. In those embodiments, the phase signal Ph can be given by the same technique as described with the calculation of phase performed by phase detector703-k, loop filter705-k, and integrator707-k, shown in FIG. 7, for the in-phase signal.
• The output signal from[0234]ADC1202, S, can be input to adigital filter1203. Further filtering and shaping of the signal can occur indigital filter1203.Filter1203 can be, for example, a digital base-line wander filter, a digital automatic gain control circuit, an echo or next canceller, or any other filter. For example, if necessary,digital filter1203 can be part of cross channel interference filter570 (shown in FIG. 5A). The output signal fromdigital filter1203 is input toequalizer1204.
• [0235]Equalizer1204 equalizes the signal for intersymbol interference.Equalizer1203 can include a feed-forward section, a feed-back section, or a combination of feed-forward and feed-back sections. FIG. 12C shows an embodiment ofequalizer1204 with a combination of a feed-forward section1215 and feed-backsection1216. Each of feed-forward section1215 and feed-backsection1216 can include any number of taps. Each of the equalization parameters C₀through C_Mof feed-forward section1215 and B₁through B_Nof feed-backsection1216 can be adaptively chosen inadaptive parameter control1207 similarly to the methods previously discussed above.
• The output signal from[0236]equalizer1204 can then be input todata recovery1205.Data recovery1205 recovers the digital signal from the signals. In some embodiments,data recovery1205 is a PAM slicer. In some embodiments,data recovery1205 can also include an error correction decoder such as a trellis decoder, a Reed-Solomon decoder or other decoder. The output signal fromdata recovery1205 is then input to descrambler1206 so that the transmitted parallel bits are recovered.
• The embodiments of the invention described above are exemplary only and are not intended to be limiting. One skilled in the art will recognize various modifications to the embodiments disclosed that are intended to be within the scope and spirit of the present disclosure. As such, the invention is limited only by the following claims.[0237]

  TABLE I
  		47	111	43	107	59	123	63	127			11
  		15	79	11	75	27	91	31	95			9
  42	106	45	109	41	105	57	121	61	125	58	122	7
  10	74	13	77	9	73	25	89	29	93	26	90	5
  46	110	44	108	40	104	56	120	60	124	62	126	3
  14	78	12	76	8	72	24	88	28	92	30	94	1
  38	102	36	100	32	96	48	112	52	116	54	118	−1
  6	70	4	68	0	64	16	80	20	84	22	86	−3
  34	98	37	101	33	97	49	113	53	117	50	114	−5
  2	66	5	69	1	65	17	81	21	85	18	82	−7
  		39	103	35	99	51	115	55	119			−9
  		7	71	3	67	19	83	23	87			−11
  −11	−9	−7	−5	−3	−1	1	3	5	7	9	11	I/Q

• [0238]

  	TABLE II
  	State Transition	Encoded value
  	0=>0	0
  	3=>14
  	4=>1
  	7=>12
  	8=>2
  	11=>15
  	12=>3
  	15=>3
  	0=>1	1
  	3=>12
  	4=>3
  	7=>13
  	8=>0
  	11=>14
  	12=>2
  	15=>15
  	0=>2	6
  	3=>15
  	4=>0
  	7=>14
  	8=>3
  	11=>13
  	12=>1
  	15=>12
  	0=>3	7
  	3=>13
  	4=>2
  	7=>15
  	8=>1
  	11=>12
  	12=>0
  	15=>14
  	1=>6	2
  	2=>8
  	5=>5
  	6=>10
  	9=>7
  	10=>9
  	13=>4
  	14=>11
  	1=>5	3
  	2=>10
  	5=>7
  	6=>9
  	9=>4
  	10=>11
  	13=>6
  	14=>8
  	1=>7	4
  	2=>9
  	5=>4
  	6=>11
  	9=>6
  	10=>8
  	13=>5
  	14=>10
  	1=>4	5
  	2=>11
  	5=>6
  	6=>8
  	9=>5
  	10=>10
  	13=>7
  	14=>9

• [0239]

  TABLE III
  		24	88	3	67	29	93	0	64			11
  		56	120	35	99	61	125	32	96			9
  20	84	2	66	25	89	7	71	30	94	12	76	7
  52	116	34	98	57	121	39	103	62	126	44	108	5
  1	65	21	85	6	70	26	90	11	75	31	95	3
  33	97	53	117	38	102	58	122	43	107	63	127	1
  17	81	5	69	22	86	10	74	27	91	15	79	−1
  49	113	37	101	54	118	42	106	59	123	47	111	−3
  4	68	18	82	9	73	23	87	14	78	28	92	−5
  36	100	50	114	41	105	55	119	46	110	60	124	−7
  		8	72	19	83	13	77	16	80			−9
  		40	104	51	115	45	109	48	112			−11
  −11	−9	−7	−5	−3	−1	1	3	5	7	9	11	I/Q

Claims (50)

We claim:

1. A transmission system, comprising:

a baseband receiver to receiver a baseband signal from a transmitted signal; and

one or more down-converting receivers that receive a signal in the transmitted signal that was transmitted in a corresponding one or more frequency separated transmission band.

2. The system ofclaim 1, wherein at least one of the down-converting receivers comprises:

a down converter that converts the signal from the transmitted signal from the one of the plurality of transmission bands to a base band;

a filter coupled to receive signals from the down converter, the filter substantially filtering out signals not in the base band;

an analog-to-digital converter coupled to receive signals from the filter and generate digitized signals;

an equalizer coupled to receive the digitized signals.

3. The system ofclaim 2, wherein the down-converter creates an in-phase signal and a quadrature signal, the in-phase signal being the input signal multiplied by a cosine function at the frequency of the one of the plurality of transmission bands and the quadrature signal being the input signal multiplied by a sine function at the frequency of the one of the plurality of transmission bands.

4. The system ofclaim 2, wherein operating parameters of at least one of the down converter, the filter, the analog-to-digital converter, and the equalizer are adaptively chosen.

5. The system ofclaim 1, wherein the baseband receiver includes

an analog processing circuit to receive an input signal;

an analog-to-digital converter coupled to receive signals from the low-pass filter; and

a data recovery block coupled to receive signals from the analog-to-digital converter.

6. The system ofclaim 5, wherein the analog processing circuit includes a low-pass filter.

7. The system ofclaim 5, wherein the analog processing circuit includes an amplifier.

8. The system ofclaim 5, wherein the analog processing circuit includes an offset.

9. The system ofclaim 5, wherein the analog processing circuit receives adaptively chosen parameters from an adaptive parameter control circuit.

10. The system ofclaim 5, wherein a digital circuit is coupled between the analog to digital converter and the data recovery circuit.

11. The system ofclaim 10, wherein the digital circuit includes a digital gain block.

12. The system ofclaim 10, wherein the digital circuit includes a digital base-line correction block.

13. The system ofclaim 10, wherein the digital circuit includes an equalizer.

14. The system ofclaim 13, wherein the equalizer includes a decision feedback equalizer.

15. The system ofclaim 13, wherein the equalizer includes a linear equalizer.

16. The system ofclaim 10, wherein the digital circuit receives at least one parameter that is adaptively chosen in an adaptive parameter control circuit.

17. The system ofclaim 5, wherein the data recovery circuit is a slicer.

18. The system ofclaim 5, wherein the data recovery circuit includes a forward error correction decoding circuit.

19. The system ofclaim 18, wherein the forward error correction decoding circuit is a trellis decoder.

20. The system ofclaim 18, wherein the forward error correction decoding circuit is a Reed-Solomon decoding circuit.

21. The system ofclaim 4, further including a descrambler circuit coupled to receive signals from the data recovery circuit.

22. The system ofclaim 1, further including a cross-channel interference correction circuit coupled between the one or more down-converting receivers.

23. The system ofclaim 22 wherein the cross-channel interference correction circuit corrects for interference between transmissions in the baseband and transmissions in the frequency separated transmission bands.

24. The system ofclaim 22 wherein the cross-channel interference correction circuit is further coupled to the baseband receiver to correct transmissions in the baseband for interference from transmissions in the frequency separated transmission bands.

25. The system ofclaim 1, further including

a baseband transmitter that transmits data into the baseband; and

one or more up-converting transmitters that transmit data into one of the frequency separated transmission bands.

26. The system ofclaim 25, wherein at least one of the up-converting transmitters includes

a symbol mapper coupled to map a set of digital inputs to a symbol; and

an up-conversion circuit coupled to form a transmission signal from the symbol at a carrier frequency.

27. The system ofclaim 25, further including a summer wherein the output signal from the up-converting transmitters is summed to form a sum signal.

28. The system ofclaim 27, further including a second summer wherein the sum signal is summed with an output signal from the baseband transmitter to form the transmitted signal.

29. The system ofclaim 28, further including a high-pass filter coupled between the summer and the second summer to filter any base-band contribution out of the sum signal;

30. The system ofclaim 28, further including a low-pass filter coupled between the baseband transmitter and the second summer to filter any higher frequency component from the output signal from the baseband transmitter.

31. A method of transmitting data, comprising:

receiving a transmitted signal from a transmission medium into a baseband receiver and one or more down-converting receivers;

each of the down-converting receivers down-converting the transmission signal by a set carrier frequency to obtain a data signal for that down-converting receiver; and

the baseband receiver receiving a data signal from the baseband of the transmitted signal.

32. The method ofclaim 31, further including

forming a baseband signal in a baseband transmitter;

forming one or more frequency separated signals in one or more up-converting transmitters;

summing the baseband signal with the one or more frequency separated signals to form a sum signal; and

transmitting the sum signal over the transmission medium to form the transmitted signal.

33. The method ofclaim 32, further including filtering a sum of the one or more frequency separated signals with a high pass filter before summing.

34. The method ofclaim 32, further including filtering the baseband signal with a low pass filter before summing.

35. The method ofclaim 31, further including correcting for cross-channel interference.

36. The method ofclaim 35, wherein correcting for cross-channel interference includes correcting for interference between the down-converting receivers.

37. The method ofclaim 35, wherein correcting for cross-channel interference includes correcting for interference between the down-converting receivers and the baseband receiver.

38. The method ofclaim 35, wherein correcting for cross-channel interference includes:

receiving equalized signals from two or more of the baseband receiver and the down-converting receivers; and

subtracting components of the equalized signals from two or more of the baseband receiver and the down-converting receivers.

39. The method ofclaim 38, wherein subtracting components of the equalized signals includes providing a transfer function between each pair of the two or more of the baseband receiver and the down-converting receivers.

40. The method ofclaim 39 wherein coefficients of the transfer function are adaptively chosen.

41. A transmission system, comprising:

means for transmitting data into the baseband and one or more frequency separated transmission bands on a transmission medium;

means for receiving data from the transmission medium.

42. A transceiver chip, comprising:

a transmitter section, the transmitter section including

a baseband transmitter that transmits data onto a transmission medium in a baseband channel, and

one or more up-converting transmitters that transmits data onto the transmission medium in corresponding frequency separated channels;

a receiver section, the receiver section including

a baseband receiver that receives data from the transmission medium in the baseband channel, and

one or more down-converting receivers that receive data from the transmission medium from the corresponding frequency separated channels.

43. The transceiver chip ofclaim 42, wherein the receiver section includes a cross-channel interference correction circuit.

44. The transceiver chip ofclaim 41, wherein the transmitter section includes a low-pass filter coupled to the base-band transmitter, a high-pass filter coupled to receive a summed output signal from the one or more up-converting transmitters, and a summer coupled to sum signals from the low-pass filter and the high-pass filter.

45. The transceiver chip ofclaim 41, wherein the baseband transmitter is a PAM transmitter.

46. The transceiver chip ofclaim 41, wherein the one or more up-converting transmitters includes a QAM transmitter.

47. The transceiver chip ofclaim 41, wherein the baseband transmitter is an 8-PAM transmitter with no error correction coding and the one or more up-converting transmitters are each 6/7 trellis encoded 128 QAM.

48. The transceiver chip ofclaim 41, wherein the baseband transmitter is a 16-PAM transmitter and the one or more up-converting transmitter includes a 16-QAM transmitter.

49. The transceiver chip ofclaim 41, wherein the baseband transmitter is a 16 PAM transmitter and the one or more up-converting transmitter includes a 32-QAM transmitter.

50. The transceiver chip ofclaim 41, wherein the baseband transmitter is a 3/4 encoded 16 PAM transmitter and the one or more up-converting transmitter includes a 6/7 encoded 128-QAM transmitter.

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