US20030080388A1 - Lateral power mosfet for high switching speeds - Google Patents

Abstract

A lateral power metal-oxide-semiconductor field effect transistor (MOSFET) having a gate structure in which the insulated gate is coupled to the gate electrode through contacts at a plurality of locations. The source electrode includes first and second segments. The first segment is interposed between the drain electrode and the gate electrode and acts as a field plate.

Description

FIELD OF THE INVENTION
• The present invention relates to semiconductor devices fabricated in a silicon substrate. More specifically, the present invention relates to a high voltage field effect transistor with an improved gate design.[0001]
BACKGROUND OF THE INVENTION
• A common type of integrated circuit device is a metal-oxide-semiconductor field effect transistor (MOSFET). A MOSFET is a field effect device that includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate provided over the channel region. The gate includes a conductive gate structure disposed over and separated from the channel region with a thin oxide layer.[0002]
• Lateral field-effect transistors are widely used for high voltage circuit applications, e.g., greater than 200 volts. Examples of traditional lateral MOSFET device structures for power applications include U.S. Pat. Nos. 5,869,875, 5,821,144, 5,760,440, and 4,748,936. Each of these devices has a source region and a drain region separated by an intermediate region. A gate structure is disposed over a thin oxide layer over the metal-oxide-semiconductor (MOS) channel of the device. In the on state, a voltage is applied to the gate to cause a conduction channel to form between the source and drain regions, thereby allowing current to flow through the device. In the off state, the voltage on the gate is sufficiently low such that no conduction channel is formed in the substrate, and thus no current flow occurs. In this condition, high voltage is supported between the drain and source regions.[0003]
• Lateral power transistors are generally designed with source and drain regions that are elongated, or much longer than they are wide, and interdigitated. Such a device structure is disclosed in U.S. Pat. No. 6,084,277, which is assigned to the assignee of the present application. The '277 patent teaches a lateral power MOSFET or transistor having an improved gate design that provides a large safe operating area (SOA) performance level and high current capability with moderate gate speed to suppress switching noise. This is achieved by providing a metal gate electrode in parallel with the polysilicon gate structure along the length of the power MOSFET finger. The metal and polysilicon of the gate electrode and structure, respectively, are connected using metal contacts that are spaced apart along the gate structure. In one embodiment, the '277 patent teaches locating contacts at multiple locations between the gate electrode and gate structure along the power MOSFET finger to improve the propagation of the gate signal along the length of the finger for high switching speeds.[0004]
• One drawback associated with the lateral power transistor structure taught by the '277 patent is high gate-to-drain capacitance due to the proximate location of the gate and drain electrodes. The drain electrode serves as a drain field plate and the gate and/or source electrodes serve as source field plates to improve the breakdown voltage of these devices. Therefore, the extent and spacing of these electrodes is determined largely by breakdown voltage requirements. For instance, the '277 patent teaches an example device capable of sustaining 700 volts between the source and drain in the off state. Accordingly, this device includes a relatively large spacing between the drain and gate or source metal lines.[0005]
• But in the case where the device is designed for a much lower voltage, the closer spacing between the drain electrode and the gate electrode results in high gate-to-drain capacitance. A MOSFET designed with a breakdown voltage of 200 volts, for example, might have a spacing of less than 5 microns between the drain and gate electrode. Because these electrodes are commonly very long (e.g., 300-400 mm) the capacitance between the drain electrode and the gate or source electrode can be very large. This large capacitance degrades the high-speed switching performance of the transistor. High gate-to-drain capacitance is especially problematic because it is amplified by the gain of the transistor.[0006]
• Therefore, what is needed is a high voltage power transistor structure that achieves fast switching at high current conduction levels with good propagation of gate signal. Such a device should minimize drain-to-gate capacitance without increasing overall device size or cell pitch (i.e., silicon “footprint”).[0007]
BRIEF DESCRIPTION OF THE DRAWINGS
• The present invention is illustrated by way of example, and not limitation, in the figures of the accompanying drawings, wherein:[0008]
• FIGS.[0009]1A-1C are three different topological views of an interdigitated lateral power MOSFET in accordance with one embodiment of the present invention.
• FIG. 2 is a cross-sectional side view taken through cut lines A-A′ in the embodiment of FIG. 1A.[0010]
DETAILED DESCRIPTION
• A high-voltage lateral power MOSFET with reduced gate-to-drain capacitance for high switching speeds is described. In the following description, numerous specific details are set forth, such as material types, dimensions, structural features, etc., in order to provide a thorough understanding of the present invention. Practitioners having ordinary skill in the semiconductor arts will understand that the invention may be practiced without many of these details. In other instances, well-known elements, techniques, and processing steps have not been described in detail to avoid obscuring the invention.[0011]
• The field effect transistor of the present invention includes a metal gate electrode coupled with an insulated gate disposed over a channel region that separates elongated source and drain regions of the power MOSFET. In one embodiment the gate comprises polysilicon, and the gate electrode is coupled to the polysilicon gate using metal contacts (also known as vias) that are located at opposite ends of a portion of the insulated gate adjacent one side of the elongated source region. The source electrode includes two segments: a wide segment that carries most of the current flowing when the device is in the on state, and a narrow segment interposed between the drain electrode and the gate electrode that greatly reduces the drain-to-gate capacitance of the device.[0012]
• FIGS.[0013]1A-1C are a topological view of an interdigitated lateral power MOSFET in accordance with one embodiment of the present invention. FIG. 1A provides a view of the upper portion of the device, FIG. 1B is a view of the middle portion of the device, and FIG. 1C shows the lower portion of the same transistor device. Each of these views illustrates a computer-aided design (CAD) layout of the drain, gate and source electrodes, the location of the polysilicon gate structure, and the placement of a select number of contacts or vias. It should be understood that the drain and source contacts are not shown and the underlying substrate diffusion regions are also omitted from FIGS.1A-1C in the interest of clarity. (During the following description, FIGS.1A-1C should be viewed together with FIG. 2, which is a side view of the transistor taken through cut lines A-A′, for a more comprehensive understanding.)
• FIG. 1A illustrates the layout of the upper end of one embodiment of the interdigitated lateral power device of the present invention. The field-effect transistor of FIG. 1A includes an N-[0014]type source region44 disposed in a semiconductor substrate and connected to asource electrode21 by contacts (not shown in FIG. 1).Source electrode21 comprisessource electrode segments21A and21B.Source region44 is interposed in the semiconductor substrate between twodrain regions42, each of which is connected to adrain electrode22 by contacts (see FIG. 2).
• Both of the[0015]source electrode segments21A &21B are located betweendrain electrode segments22A and22B. FIG. 1C shows thesegments22A and22B merging into a single piece of metal at the bottom of the transistor. It is appreciated that the device layout structure of FIGS.1A-1C only shows a portion of the complete transistor in this embodiment. The full and complete device comprises a repeated pattern of the interdigitated source/drain/gate structures illustrated in the Figures. It is understood that since the drain and source structures are much longer than they are wide, they are often referred to as drain and source “fingers”.
• The[0016]polysilicon material28 that comprises the gate of the transistor is depicted in FIGS.1A-1C by dashed lines. The gate itself comprises twoparallel members28A and28B disposed overchannel region49, extending the length of the source finger. FIG. 1C shows thepolysilicon gate28 wrapping around the far end, or fingertip, of the source region where themember28A merges withmember28B.Members28A and28B many also be connected in the middle portion of the transistor, as shown in FIG. 1B.
• At the upper end of the transistor, the polysilicon material of the gate extends under[0017]source electrode21 and connects tometal line29 through a plurality ofcontacts30.Metal line29 couples with control or switching circuitry used to drive the transistor.
• As shown in FIG. 2, the two[0018]polysilicon gate members28A &28B are insulated from the underlying semiconductor material by agate dielectric layer48. Dielectric layer may comprise silicon dioxide, but other insulating materials, such as silicon nitride, may also be used. A portion of eachmember28A and28B extends over a thickerfield oxide layer41 for field plating purposes. Each of thepolysilicon gate members28A and28B is covered with aninterlayer dielectric40 that insulates the gate from the overlying metal gate and source electrodes, as can be seen in the cross-sectional side view of FIG. 2.
• The[0019]gate electrode25 contacts one end of the polysilicon gate adjacent the base of the source finger through contact31, as shown in FIG. 1A. In the illustrated embodiment, gate electrode runs lengthwise from one end ofgate member28A to the opposite end adjacent the fingertip of the source region. FIG. 1C showsgate electrode25 being connected to the opposite end ofgate member28A through a pair ofcontacts34. Note thatgate electrode25 ends adjacent the fingertip of the source and does not extend overgate member28B, which runs alongside the opposite side ofsource region44.
• It is appreciated that the connection of[0020]gate electrode25 in parallel withinsulated gate member28A advantageously distributes the applied gate signal along the length of each finger for improved high switching speed performance. Depending on the length of the source, drain, and gate fingers, one or more additional contacts may be located at intermediate points or regions of the insulated gate between the opposite ends of the finger. For example, FIG. 1B illustrates an optionaladditional contact33 connectinggate electrode25 togate member28A at an intermediate point approximately halfway between the two ends ofgate member28A.Gate member28B may also be connected togate member28A in proximity to contact33 to provide the same advantage in distribution of the gate signal alongmember28B.
• To accommodate the placement of[0021]contact33 the width of thegate electrode25 metal is made slightly wider to adequately surroundcontact33. To maintain design rule separation between the source and gate electrodes,source electrode segment21B is made slightly narrower by a corresponding dimension. Note that no change in the width ofsource electrode segment21A (ordrain electrodes22A &22B) is needed to accommodate the placement ofadditional contact33.
• The[0022]gate electrode25 is completely surrounded bysource electrode21. The wider, current-carrying portion of the source electrode is denoted assource electrode segment21B in FIGS.1A-1C.Segment21B carries the vast majority of the source current to the source bond pads (not shown) located at the upper end of the source finger. Thesource electrode segment21B also includes a laterally extended portion that overlapsgate member28B. This laterally extended portion is located on the side of the finger oppositegate electrode25 and functions as a field plate. The mainsource electrode segment21B is disposed substantially over and contacts thesubstrate source region44.
• The narrower portion of the source electrode is denoted as[0023]source electrode segment21A in FIGS.1A-1C.Source electrode segment21A is interposed betweengate electrode25 anddrain electrode22A. In the embodiment of FIGS.1A-1C,source electrode segment21A has no contacts to the underlying source diffusion, and does not carry a significant amount of source current. It functions as a source field plate and also reduces the drain-to-gate capacitance of the transistor. It should be understood that in other embodiments,source electrode segment21A may include contacts to the source diffusion region and/or may carry more significant amounts of source current.
• In addition, although each of the source, drain, and gate electrodes are shown in FIGS. 1 & 2 as comprising a single layer of metal, alternative embodiments may utilize multiple levels of conductor material for each or all of the electrodes.[0024]
• FIG. 1C illustrates[0025]source electrode segment21A wrapped around the source fingertip region of the transistor and connected to sourceelectrode segment21B. It should be understood that the connection betweensegments21A and21B at this end of the source finger is optional. That is, these two segments need not connect at this point. However,source electrode segment21A should be connected tosegment21B at some point in the layout so that both remain at substantially the same potential during device operation. This is consistent with the purpose ofsource segment21A to serve as a source field plate interposed between thegate electrode25 and thedrain electrode22.
• FIG. 2 shows a cross-sectional view of the lateral power transistor of FIGS.[0026]1A-1C taken through cut lines A-A′. This diagram shows thatdrain electrode22A extends down throughinterlayer dielectric40 to contact N+drain region42.Drain electrode22A also includes a field plate portion that extends laterally overinterlayer dielectric40 toward thesource electrode segment21A. In the illustrated embodiment, the distance between thedrain electrode22A and thesource electrode segment21A is the same as the distance (e.g., 3 microns) between thegate electrode25 andsource electrode segment21A. The same distance separates thegate electrode25 from thesource electrode segment21B, which extends down to the surface of the substrate to contact N-type source region44 and P+diffusion region45. This spacing is consistent with minimum design rules for an exemplary lateral power transistor having a 200V breakdown voltage.
• [0027]Drain diffusion region42 is disposed in N-well region51, which itself is a deep diffusion formed in P-substrate60.Source diffusion region44 is disposed in a P-well50 formed adjacent to N-well51 insubstrate60. Thechannel region49 is defined between the boundaries of the N-well region51 andsource region44. Thepolysilicon gate members28A and28B are formed over athin gate oxide48 abovechannel region49. Note that each ofgate members28A and28B include field plating that extends over thickerfield oxide layer41. The region between N+drain region42 andchannel49 is commonly referred to as the extended drain region of the device.
• It is appreciated that the foregoing details of the various regions formed in the semiconductor material beneath the top surface of the substrate are specific to the embodiment shown and are not deemed essential to the present invention. In other words, the layout structure of the metal electrodes and gate members may be utilized in transistors having different doped semiconductor regions of the device.[0028]

Claims (30)

I claim:

1. A field-effect transistor comprising:

elongated source and drain regions separated by a channel region;

an insulated gate disposed over the channel region;

a drain electrode coupled to the drain region;

a gate electrode coupled to the insulated gate through first and second contacts located at respective first and second contact regions of the insulated gate, the first and second regions being separated by a contact-free region; and

a source electrode coupled to the source region, the source electrode including first and second segments, the first segment being interposed between the drain electrode and the gate electrode.

2. The field-effect transistor according toclaim 1 wherein the second segment of the source electrode is disposed substantially over the source region.

3. The field-effect transistor according toclaim 2 wherein the drain electrode is disposed substantially over the drain region.

4. The field-effect transistor according toclaim 3 wherein the source and drain electrodes each include a field plate portion.

5. The field-effect transistor according toclaim 1 wherein the first and second segments are disposed on opposite sides of the gate electrode.

6. The field-effect transistor according toclaim 1 wherein the first and second segments surround the gate electrode.

7. The field-effect transistor according toclaim 1 wherein the second segment is wider than the first segment.

8. The field-effect transistor according toclaim 1 wherein the source and drain regions are interdigitated.

9. The field-effect transistor according toclaim 1 wherein the insulated gate has a first end and second end opposite the first end, the first contact region being located at the first end and the second contact region being located at the second end.

10. The field-effect transistor according toclaim 1 wherein the insulated gate has a first end and second end opposite the first end, the first contact region being located at the first end and the second contact region being located at an intermediate point between the first and second ends, and wherein the gate electrode is further coupled to the insulated gate through a third contact located at a third contact region of the insulated gate, the third contact region being located at the second end.

11. A lateral field-effect transistor comprising:

elongated source and drain regions separated by a channel region;

an insulated gate disposed over the channel region, the insulated gate having a first end region and a second end region opposite the first end region;

a drain electrode coupled to the drain region;

a gate electrode coupled to the insulated gate through first and second contacts located at the first and second end regions of the insulated gate, respectively; and

a source electrode coupled to the source region, the source electrode including first and second segments, the first segment being interposed between the drain electrode and the gate electrode.

12. The lateral field-effect transistor according toclaim 11 wherein the second segment of the source electrode is disposed substantially over the source region.

13. The lateral field-effect transistor according toclaim 12 wherein the drain electrode is disposed substantially over the drain region.

14. The lateral field-effect transistor according toclaim 11 wherein the source and drain electrodes each include a field plate portion.

15. The lateral field-effect transistor according toclaim 11 wherein the first and second segments are disposed on opposite sides of the gate electrode.

16. The lateral field-effect transistor according toclaim 11 wherein the first and second segments surround the gate electrode.

17. The lateral field-effect transistor according toclaim 11 wherein the second segment is wider than the first segment.

18. The lateral field-effect transistor according toclaim 11 wherein the source and drain regions are interdigitated.

19. The lateral field-effect transistor according toclaim 11 wherein the first segment of the source electrode is spaced equidistant from the gate and drain electrodes.

20. The lateral field-effect transistor according toclaim 11 wherein the insulated gate has an intermediate region between the first and second end regions, and wherein the gate electrode is further coupled to the insulated gate through a third contact located at the intermediate region.

21. A lateral power MOSFET comprising:

an elongated source region interdigitated between a pair of drain regions, the source region being separated from the pair of drain regions by a channel region, the elongated source region having a first and second ends;

an insulated gate disposed over the channel region, the insulated gate having a first portion that extends from adjacent the first end to adjacent the second end along one side of the elongated source region and a second portion that extends from adjacent the first end to adjacent the second end along an opposite side of the elongated source region;

a drain electrode coupled to the drain region;

a gate electrode coupled to the insulated gate through first and second contacts located at opposite ends of the first portion of the insulated gate; and

a source electrode coupled to the elongated source region, the source electrode including first and second elongated segments, the first elongated segment being interposed between the drain electrode and the gate electrode.

22. The lateral power MOSFET according toclaim 21 wherein the second segment of the source electrode is disposed substantially over the source region.

23. The lateral power MOSFET according toclaim 21 wherein the drain electrode is disposed substantially over the drain region.

24. The lateral power MOSFET according toclaim 21 wherein the source and drain electrodes each include a field plate portion.

25. The lateral power MOSFET according toclaim 21 wherein the first and second elongated segments are disposed on opposite sides of the gate electrode.

26. The lateral power MOSFET according toclaim 21 wherein the first and second elongated segments surround the gate electrode.

27. The lateral power MOSFET according toclaim 21 wherein the second elongated segment is wider than the first elongated segment.

28. The lateral power MOSFET according toclaim 21 wherein each of the pair of drain regions is elongated.

29. The lateral power MOSFET according toclaim 21 wherein the first segment of the source electrode is spaced equidistant from the gate and drain electrodes.

30. The lateral power MOSFET according toclaim 21 wherein the first portion of the insulated gate has an intermediate region between the opposite ends, and wherein the gate electrode is further coupled to the insulated gate through a third contact located at the intermediate region.

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