US20030048361A1 - Digital camera - Google Patents

Abstract

The invention relates to a digital camera and the methods for using a digital camera. The digital camera includes a programmable processor that provides for flexible operation of the digital camera. The programmable processor also provides the digital camera manufacturer the capability of economically configuring the digital camera as desired. The programmable processor also provides the digital camera user with on demand specialized imaging modes such as the capture mode and the cineview mode.

Description

BACKGROUND OF THE INVENTION
• 1. Field of the Invention[0001]
• The present invention generally relates to digital cameras. More particularly, improved digital camera architectures and components are described.[0002]
• 2. Description of the Related Art[0003]
• Recently, digital cameras have become very popular. The digital camera converts an optical image to electronic image data and digitally records the image data on a storage medium. When the image is reproduced, the recorded digital data is retrieved from the storage medium and displayed on a display device or printed out as a hard copy image.[0004]
• Referring initially to FIG. 1, conventional[0005]digital camera systems100 typically include adigital camera102 having anoptical lens104 for focusing light rays onto aimaging capture unit106. Theimaging capture unit106 typically relies upon an array of light sensitive photooptic cells108, capable of converting the light rays received from theoptical lens104 into representative analog signals. Most commonly, the photo optic cells take the form of charge coupled devices (CCDs), although other devices such as CMOS receptors may be used as well. As is well known in the art, eachCCD array108 must have associated with it a specific color filter array (CFA). In most applications, the CFA is an empirically derived pattern of individual color filters each associated with a specific CCD cell in the CCD array. Acolor converter circuit110 then uses a particular interpolation algorithm associated with the specific CFA to generate the analog signals representing the CCD manufacturer's predetermined concept of the proper color scheme of the image. Manual input controls103 (i.e., push-buttons, for example) provide manual inputs to astep controller105 suitably disposed to provide control signals to theimaging capture unit106. Such control signals are used to control such imaging parameters as f-stop, exposure, zoom, focus, and flash attachments, if appropriate.
• The analog signals representing the image are sent by the[0006]imaging capture unit106 first to an analog to digital (A/D)converter unit112. The A/D converter unit112 converts the representative analog signals into digital signals representative of the image. The digital signals are then passed to a digital signal processor (DSP)114 where they are converted to appropriate digital formats. Animage compression circuit116 as well as amemory118 both receive the appropriately formatted digital signals. Theimage compression circuit116 operates to digitally compress the received digital images in order to reduce the amount of resources required to further process the digital signals. One such formatting scheme referred to as JPEG is commonly used, although there are a wide variety of suitable picture formats. Once the image has been digitally compressed, it is sent by way of amemory interface120 to amemory slot122 capable of receiving amemory card124 suitable for storing the compressed digital signals.Such memory cards124 include “floppy” disks, flash EPROM cards, R/W compact disc (CD), SmartMedia and the like.
• Unfortunately, conventional digital cameras have several important limitations. One such limitation is the fact that the conventional digital camera may only use the color filter array (CFA) and its associated color interpolation algorithms. Any subsequent improvements in CCD array technology can not easily be incorporated into the conventional digital camera system.[0007]
• Lack of integration also provides for expensive and cumbersome digital cameras. As can be readily seen, the conventional[0008]digital camera system100 has many discrete functional blocks encompassing many different circuits. It is therefore relatively expensive for conventional digital cameras to provide image correction, color correction, image compression, as well as provide all appropriate control and timing signals in one unit.
• In addition, each CCD or CMOS imager has different clocking requirements, resolution, etc. That requires dedicated ASICs, or other dedicated logic, to properly drive them. This results in higher manufacturing cost and an inflexible camera architecture.[0009]
• It would be advantageous and therefore desirable to have available components that can be used by a variety of digital camera manufacturers, regardless of their specific image sensor, color interpolation scheme, etc.[0010]
SUMMARY OF THE INVENTION
• A digital image processor for use in a digital camera and methods of using a digital camera are disclosed. In one aspect of the invention, a digital image processor for use in a digital camera is disclosed. The digital camera has an image capture unit arranged to output analog signals that represent a captured image, a converter unit for converting analog representations of the captured image to digital representations of the image, a memory for storing digital representations of the image, and a processing unit capable of directing components included in the digital camera. The digital image processor includes an input data stream processor for pre-processing images received from the converter unit and storing the pre-processed images in the memory. The digital image processor also includes an output data stream processor arranged to receive pre-processed images and post-process the retrieved images into a viewable form.[0011]
• In another aspect of the invention, a method of forming a viewable representation of an image using a digital camera is disclosed. The method includes the following operations. First, an image is received at the image capture unit to form a captured image followed by outputting analog signals representative of the captured image from the image capture unit. Next, the analog signals are converted to digital image signals representative of the captured image. Next, the digital image signals are pre-processed to form a digital image, such that the preprocessing includes correcting non-uniformities in the captured image. Next, the pre-processed digital image is stored in a generally accessible memory that is part of the digital camera. Finally, the pre-processed digital image is retrieved from the memory and post-processed into a viewable form.[0012]
• Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.[0013]
BRIEF DESCRIPTION OF THE DRAWINGS
• The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings where like reference numerals refer to analogous or similar elements to facilitate ease of understanding and which;[0014]
• FIG. 1 is a block diagram of a conventional digital camera system;[0015]
• FIG. 2A is a block diagram of a digital camera system in accordance one embodiment of the invention;[0016]
• FIG. 2B is a block diagram of an implementation of the digital image processor shown in FIG. 2A;[0017]
• FIG. 3 is a block diagram of a digital camera system in accordance with another embodiment of the invention;[0018]
• FIG. 4 is block diagram of a digital image processor formed in accordance with an embodiment of the invention;[0019]
• FIG. 5 is a functional block diagram of a color interpolator in accordance with an embodiment of the invention;[0020]
• FIG. 6 is a flowchart detailing the color interpolation of a digital image by the color interpolation circuit in accordance with an embodiment of the invention;[0021]
• FIG. 7 is a block diagram of a universal state machine controller in accordance with an embodiment of the invention;[0022]
• FIG. 8A is a block diagram of a universal state machine controller in accordance with another embodiment of the invention;[0023]
• FIG. 8B is a representative non-symmetric clock signal in accordance with an embodiment of the invention;[0024]
• FIG. 9 is a block diagram of a programmable analog reference signal generator in accordance with an embodiment of the invention;[0025]
• FIG. 10A is a flowchart detailing authentication stamping of a digital image in accordance with an embodiment of the invention;[0026]
• FIG. 10B is a flowchart detailing verification of an authentication stamped digital image in accordance with an embodiment of the invention;[0027]
• FIG. 11 is a flowchart detailing the image processing of raw digital image data by a digital image processor in a digital camera system in accordance with an embodiment of the invention;[0028]
• FIG. 12 is a block diagram of a digital camera system in accordance with another embodiment of the invention;[0029]
• FIG. 13 is a block diagram of a digital camera system in accordance with yet another embodiment of the invention;[0030]
• FIG. 14 is a block diagram of a digital camera system in accordance with another embodiment of the invention; and[0031]
• FIG. 15 is a block diagram of a digital camera system in accordance with another embodiment of the invention.[0032]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• The present inventions relate generally to digital cameras. In various aspects of the invention, the digital camera includes a programmable processor capable of processing digital images. The processing may include, digital image correction and/or digital image authentication stamping, a programmable source of control and timing signals as well as the capability of providing an adaptive pixel color interpolator. In another aspect of the invention, the processor has a system bus architecture that provides the digital camera with enhanced flexibility.[0033]
• In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known structures or operations have not been described in detail in order to not unnecessarily obscure the present invention.[0034]
• Referring initially to FIG. 2A a digital camera system[0035]200 in accordance with one embodiment of the invention will be described. The digital camera system200 includes animaging unit202 connected to adigital image processor204 capable of producing digital signals representative of a captured image. Thedigital image processor204 is connected to alocal memory206 and is capable of performing digital image processing operations upon received digital images. Such processing operations include, but are not limited to, image correction, color correction, color interpolation, as well image compression and/or image file formatting. Thelocal memory206 is capable of fast storage and retrieval of selected digital image files.
• In one embodiment, the[0036]digital image processor204 is also capable of authentication stamping a particular digital image as well as deriving color weight factors useful in the operation of theimaging unit202. Amicroprocessor208 connected to thedigital image processor204 provides direction for the components included the digital camera system200. Asystem memory210 connected to thedigital image processor204 is capable of storing files that have passed through the image processor.
• The digital images upon which the[0037]digital image processor204 operates may be received from any appropriate source. Typically, raw digital images (i.e., those digital images that have not yet had any image processing) are provided by theimaging unit202. Since thesystem memory210 and the local memory are each capable of storing digital images, they too can be a source of digital images for thedigital image processor204. In this way, the digital camera system200 is capable of providing the user with digital images in any desired stage of processing.
• The[0038]digital image processor204 is also capable of generating a wide variety of control signals and/or timing signals. Such control signals and/or timing signals are useful in the operation of, for example, theimaging unit202. By providing image processing as well as acting as a source of control signals and/or timing signals, thedigital image processor204 reduces the number of components required in the digital camera system200 thereby, for example, commensurably reducing overall costs of manufacture.
• The digital camera system[0039]200 also includes optics (not shown) such as, for example a lens, capable of directing light from any object to theimaging unit202. The optics may include such optical systems as fiber optic transducers and fiber optic cables, refractive mirror assemblies, or any system or device capable of being optically coupled to theimaging unit202.
• FIG. 2B is a block diagram of a[0040]digital image processor250 in accordance with an embodiment of the invention. It should be noted that thedigital image processor250 is but one possible embodiment of thedigital image processor204 used in the digital camera system200 shown in FIG. 2A. Therefore, thedigital image processor250 shall be described in the context of the digital camera system200 and all references included therein.
• The[0041]digital image processor250 includes asystem bus252 capable of carrying various signals. Such signals include but are not limited to data signals, control signals, and digital image signals. In the described embodiment, thesystem bus252 receives raw digital images from theimage capture unit202. Thesystem bus252 also carries control signals generated by a programmablecontrol signal generator254. In one embodiment, the control signals so generated are supplied to theimaging unit202, as needed, to control stepper motors included therein, for example. A programmabletiming signal generator256 provides timing signals as needed. Such timing signals are useful in the operation of, for example, image sensors included in theimaging unit202. In addition, a programmablereference signal generator258 provides reference signals. Such reference signals include those used in the operation of, for example, any analog components included in the digital camera200.
• The[0042]digital image processor250 also includes first andsecond image processors260,262 connected to thesystem bus252. The image processors are structured such that they may provide processing in addition to or independently of one another. It should be noted that in alternative embodiments, thedigital image processors260,262 may include any number of digital image processors as may be desired or required for a particular application.
• A[0043]local memory interface264 connecting thesystem bus252 to thelocal memory206 provides the user of the digital camera system200 with the capability of quickly storing a particular digital image or series of images. Such digital images include those processed by thefirst image processor260 and/or thesecond image processor262. In one implementation, such digital images include those raw digital images received from theimaging unit202. Once stored in thelocal memory206, the digital images are selectively available for any purpose, such as for example, further digital image processing by any component connected either directly or indirectly to thesystem bus252.
• In one embodiment of the invention, the[0044]digital image processor250 includes anauthentication stamper266 used to generate an authenticity stamp. Typically, the authenticity stamp is useful in providing photographers and/or other end-users with the capability of determining the authenticity of any digital image so stamped. Acolor interpolator268 is included to provide appropriate color interpolation when full color interpolation of a digital image by thedigital image processor250 is desired. Alternatively, when the color interpolation performed by thecolor interpolator268 is performed by external mechanisms connected with the digital image processor250 (such as the microprocessor), thecolor interpolator268 may be bypassed. Amicroprocessor interface270 provides an interface between themicroprocessor208 and thesystem bus252.
• Referring next to FIG. 3, a[0045]digital camera system300 in accordance with another embodiment of the invention will be described. It should be noted that thedigital camera system300 is but one possible embodiment of the digital camera system200 shown in FIG. 2A. Thedigital camera system300 includes animage capture unit302, an A/D converter308 that converts captured images to representative digital signals and a configurable digitalimage process controller310 arranged to perform some processing of the digital images and to provide various clocking and control signals to theimage capture unit302 and/or A/D converter308. Thedigital camera system300 further includes alocal memory311 for quickly storing digital images, amicroprocessor312, asystem memory314, avideo DRAM316 for storing video images, avideo display controller317, adisplay318 having atouch screen319, and an I/O block320.
• The[0046]image capture unit302 includes animage conditioner304 for conditioning the light received from the optical system before it is received at animage sensor306. Such conditioning can include image focusing, image enlargement (referred to as zooming), image exposure, and any other suitable conditioning found useful in the formation of digital images. Theimage sensor306 typically includes a grid, or array, of photosites. The photosites can be any device capable of converting incident light (in the form of photons) into useable electrical signals. Typically, these photosites are formed of a semiconductor material and include charge coupled devices (CCD) as well as complementary metal oxide semiconductor (CMOS) devices. Generally, each of the photosites is associated with what is referred to in the art as a pixel (short for picture element). The resolution of theimage sensor306 is then determined by how many photosites are placed upon its surface. This resolution is specified in one of two ways-by its dimensions in pixels or by the total number of pixels in its images. For example, the same digital camera may claim to be 1200×800 pixels, or 960-thousand pixels.
• Each of the photosites in the[0047]image sensor306 convert light into an associated electrical signal. Typically, the associated electrical signal so produced is related to the intensity (i.e., number of photons) of the light and not necessarily the color (i.e., frequency) of the light which falls upon the surface of the photosite. Therefore, in order to simulate the primary colors of red, blue, and green, for example, an associated color filter array (CFA) (also referred to as a color mask) must be placed in proximity to the photosite array. One such CFA is shown in Table 1 for a representative 4×4 CCD array.

  	TABLE 1
  	RGRG
  	GBGB
  	RGRG
  	GBGB

• The color filter array shown in Table 1 (known in the art as a “Beyer” pattern) illustrates one particular approach to forming a CFA where each photosite (and its associated pixel) has an associated single color filter. After exposure, the electrical signal generated by each photosite is converted to a digital signal taking the form of, for example, an 8-, 10-, or 12-bit binary number, other wise referred to as pixel color value. To create a 24-bit image, for example, interpolation is used whereby neighboring pixel color values are used to calculate the values of the other two colors for each pixel. By combining these two interpolated colors with the color measured by the photosite directly, the original color of every pixel is calculated.[0048]
• During operation of the[0049]image sensor306, each of the photosites included in theimage sensor306 generates an associated analog (electrical) signal representative of a portion of the image rendered by theimage controller306. The analog signals are then fed to an analog-to-digital (A/D)converter308. The A/D converter308 converts the received analog signals representative of the captured image into corresponding digital signals. The corresponding raw digital signals are then carried by an interface bus to thedigital image processor310. At some point in the processing of a raw captured image, the image is typically color interpolated by the digital image processor. As will be described in more detail below, one feature of the digital image processor illustrated in FIG. 3 is that it includes a programmable color interpolator that may be programmed to implement a wide variety of different desired color interpolation schemes.
• In the embodiment shown, the[0050]digital image processor310 is connected to themicroprocessor312. It should be noted that a wide variety of microprocessors may be used and in some implementations, it may be desirable to combine the functionalities of thedigital image processor310 andmicroprocessor312. One useful function provided by themicroprocessor312 referred to as data packetizing provides for efficient transmission and storage of the digital image data. In one implementation, themicroprocessor312 arranges the digital image data into discrete units such as data words formed of n data bits. In another implementation, themicroprocessor312 may packetize the digital image data into data packets having associated header portions and data portions.
• The[0051]microprocessor312 is capable of directing the retrieval of digital images stored in either thesystem memory314 or thelocal memory311. Once retrieved, themicroprocessor312 is capable of directing the sending of the digital images to any number and type of output devices that may be provided on the camera. In one implementation, the digital images may be sent by way of an I/O bus to the I/O block320. In the described embodiment, the I/O block320 includes I/O ports such as a parallel port, a serial port, a USB port, a TV signal output port, a PCMCIA port, as well as a modem port. Themicroprocessor312 is also capable of directing thevideo controller317 to store digital video images in thevideo DRAM316 which are then sent way of a display bus to thedisplay318 for viewing. Thetouch screen319 overlaying thedisplay318 is typically used to input display coordinate data to themicroprocessor312. Such coordinate display data is useful in coordinating user inputs resulting in improved ease of use of thedigital camera300. It should be noted that themicroprocessor312 is capable of parallel execution of these and any other instructions suitable for the operation of thedigital image processor310.
• The[0052]digital image processor310 also provides image sensor control signals to theimage sensor306 by way of an optics control bus. Such image sensor control signals include but are not limited to those suitable for synchronizing the array of photosites included in theimage sensor306. When the array of photosites in theimage sensor306 is a CCD array, the CCD array requires clock signals that synchronize, for example, the reading of charge data in of each the rows in the CCD array and its associated data register. These clock signals, otherwise referred to as pixel clock signals, may include other pixel clock signals used to synchronize the CCD array. In addition to providing a programmable source of image sensor control signals, thedigital image processor310 provides a programmable source of reference signals carried by the interface bus useful in the operation of, for example, the A/D converter308.
• Referring next to FIG. 4, one embodiment of a[0053]digital image processor310 will be described. It should be noted that thedigital image processor400 is but one possible implementation of thedigital image processors310 shown in FIG. 3. Typically, the integrated circuit in which thedigital image processor400 is formed is an application specific integrated circuit (ASIC) having various functional blocks and memory blocks included therein. However, in alternative embodiments it may be implemented in any suitable form including software and programmable logic and combinations of forms.
• The[0054]configurable image controller400 includes a pre-processor402, a post-processor404, alocal memory interface416, a programmableuniversal controller428 and asystem CPU interface450, all of which communicate over system bus404. Raw image data that is received by theimage controller400 is first passed to thepre-processing stage402, which typically does at least some preprocessing of the image data before it is stored in memory, displayed or otherwise handled.
• In the illustrated embodiment, the[0055]pre-processing stage402 includes auniformity corrector408, asampling filter410, amodulation transformer412 and aditherer414. Theuniformity corrector408 performs digital image uniformity correction using, for example, Photo Response Non-Uniformity (PRNU) correction and white balancing. Theuniformity corrector408 is arranged to correct non-uniformities in the image sensor and typically uses a PRNU coefficient stored in thesystem memory314 to correct any sensor based non-uniformities in the received digital image. In the described embodiment, theuniformity corrector408 is placed first since it corrects sensor errors and it is expected that almost any digital camera incorporating the digital image processor will want to incorporate uniformity correction. In the (believed to be unlikely) event that no uniformity correction is desired, then the scaling coefficients can be set appropriately, or, alternatively, theuniformity corrector408 can be bypassed.
• After the uniformity correction has been applied, the received image data may be handled in a variety of ways under the direction of the microprocessor depending upon the desires of a particular camera manufacturer. One operational mode that may be desired is referred to herein as a “capture mode” which is arranged to rapidly store digital images in the[0056]local memory311. One appropriate capture mode may contemplate directly outputting images that have been processed by theuniformity corrector408 to thelocal memory311. This may be particularly useful when the camera it attempting to take a fast sequence of pictures. Alternatively, the stored digital image may be made available for immediate viewing on thedisplay318.
• Another operational mode that may be desired is referred to herein as a “cineview” mode. As will be appreciated by those familiar with digital cameras, many digital cameras do not use traditional optical viewfinders. Rather, images from the image sensor are presented at a relatively fast rate on a small display on the camera. Typically the images are color images that are presented at rates on the order of approximately 16 frames per second. The sampling (decimation)[0057]filter410 provided to permit quick image size reductions which may be desired to facilitate faster and more efficient viewing on smaller displays such as those found in viewfinders. By way of example if a captured image has dimensions of 1200 by 800 pixels, but the on-camera display is only 300 by 200 pixels, the amount of pixel data that needs to efficiently be transferred to the on-camera display to facilitate viewing is the smaller amount of data. Therefore, the sampling unit may be utilized to reduce the image file to appropriate size, which speeds the processing of the image file, as well as its delivery to the display. Thesampling filter410 is arranged to receive its inputs from theuniformity corrector408. Thesampling filter410 is programmable so that the amount of decimation may be either set by the manufacturer or programmed by the microprocessor. This permits the same sampling filter to be used with a wide variety of digital cameras which may have very different image sensing pixel arrays and very different on camera displays. The sampling filter may also be used to permit pictures having different image resolutions taken by a camera to be displayed on a single display.
• While still in the cineview mode, the output of the[0058]sampling filter410 is output to themodulation transformer412. Themodulation transformer412 connected to aditherer414 is capable of correcting image degradation caused by thesampling filter410. Themodulation transformer412 outputs the corrected digital image to theditherer414 which is arranged to perform anti-aliasing suitable to provide for better viewing on, for example, an LCD display. Theditherer414 outputs the resulting image to the system bus404 where it is available to display or even potentially, thelocal memory interface416 for storing in thelocal memory311. The pipelined architecture of the pre-processor permits the lower resolution images to be quickly processed, which is particularly desirable in the cineview mode so that the displayed images better simulate what a user might see through a conventional viewfinder.
• The post-processor[0059]406 includes a number of processing blocks that implement specific transformations and other processing of an image that a camera manufacturer may desire to provide with the camera. In the embodiment shown, the post-processor406 includes acolor interpolator422, anRGB reconstruction block424, adigital compressor426 and a colorpattern data buffer427. The post-processor is particularly useful in processing the digital images for printing or display
• The[0060]color interpolator422 provides color correction to the captured image. Specifically, as described above with reference to Table 1, each pixel of the raw captured images typically indicates the intensity of the incoming light at one specific primary color as determined by the color filter array chosen by the manufacture. Theinterpolator422 is then used to estimate the values of the other two colors for each pixel. To do this, color correction factors suitable for estimating the values of the other colors for each pixel are determined. The actual values of the color correction factors chosen are typically based on a variety of factors including the color filter array used, the type of interpolation desired, and the designers sense of optimal color balance. In one aspect of the invention, thecolor interpolator422 is capable of using color correction factors derived by, for example firmware in themicroprocessor312, associated with a CFA included in theimage sensor306. This feature and the structure of one embodiment of thecolor interpolator406 will be described in more detail below with reference to FIG. 5. By providing the capability of deriving color correction factors for any CFA, the configurableimage process controller310 may be used by any digital camera manufacturer, regardless of their specific image sensor, color interpolation scheme, etc., in a digital camera system. In this way, the configurableimage process controller310 will significantly reduce development time and costs, as well as component costs since specific ASICs no longer must be provided.
• When not RGB based, the color corrected digital images are first output to an[0061]RGB reconstruction block424 and then passed to adigital compressor426. Otherwise, the color corrected digital images are sent directly to thedigital compressor426. Such digital compression techniques include those techniques based upon color space conversion, such as for example JPEG. Once digitally compressed, the compressed image files are then passed to the system bus404 where, in one implementation, they may be stored in thesystem memory314 and/or thelocal memory311. A color pattern data buffer427 connected to the system bus404 capable of storing appropriate color interpolation input data is operatively connected to thecolor interpolator422. Such color interpolation input data may include the number of pixels in the image sensor array, the particular CFA used with the image sensor array, as well as any particular image filtering and other appropriate digital image filtering values.
• The described architectures provides camera manufactures with a great deal of flexibility in directing the data flow within the camera, as well as in defining the camera's functionalities and designs. For example, a raw digital image processed by the[0062]uniformity corrector408 may be directly stored directly in thelocal memory311 and later retrieved for further processing. Alternatively the image may be passed through thesampling filter410 and on through the pre-processor402 prior to either storage in thelocal memory311 or being passed for direct viewing on a viewfinder, for example. In this case, it may be desirable to provide a data buffer (not shown) to hold the image before thesampling filter410.
• Images that are stored in either memory may be retrieved and processed as desired. In some cases the processing may be direct while in others, it may be staged. For example, a PRNU and white balance processed image stored in memory may be retrieved and processed by the remainder of the pre-processor[0063]402, including thesampling filter410, the modulationtransfer function block412 as well as thedithering block414. In other situations, a stored image may be retrieved and passed to the post-processor406,authentication stamper418 or any of the other processing blocks that has direct or indirect access to the system bus.
• In still another operational mode, the post-processor[0064]406 may receive digital image files directly from the pre-processor402 by way of the system bus404. It should be noted that thepre-processor402 and the post-processor406 may concurrently process digital image files associated with different captured images.
• In the described embodiment, the[0065]system memory314 includes a system dynamic random access memory (DRAM), a system read only memory (ROM), random access memory (RAM), as well as any other appropriate volatile or non-volatile storage media. Such storage media includes but is not limited to memory cards such as, for example, “floppy” disks, flash EPROM cards, R/W compact disc (CD),SmartMedia™ and the like.
• It should be noted that due to the efficient architecture of the[0066]digital image processor300, all operations are parallel in nature in that all may be performed substantially simultaneously.
• As pointed out above, the primary purpose of the post-processor[0067]406 is to prepare the digital images for printing or display on an external device. In many circumstances, the camera's user may not have ready access to high quality printers suitable for printing photographs. Thus, it may be desirable for the user to send an electronic copy of a particular captured image to a commercial entity that prints the photograph. The post-processing necessary for such third party printing can be done bypost-processor406. However, it may be more efficiently, and perfectly done by the third party which may have more sophisticated processing abilities, such as the use of a more sophisticated color interpolator. Thus, the described camera also supports another operational mode referred to herein as an off-line processing mode. In this mode, digital images stored in thelocal memory311 or thesystem memory314 can be output to any appropriate I/O port included in the I/O block320. In this way, additional digital image processing available by external devices may be used to complete the digital image processing. Such digital image processing may include color correction, RGB reconstruction (if necessary), MTF, dithering, etc. In this way, the user is able to take advantage of digital image processing capabilities beyond those available using thedigital camera300 In addition, by digitally compressing the digital image(s) before being transmitted over, for example, the Internet, valuable time and resources are conserved.
• Still referring to FIG. 4, the programmable[0068]universal controller428 connected to the system bus404 is capable of selectively generating control and reference signals. Such control signals include but are not limited to those used to in the operation of stepper motors, for example, included in theimage conditioner304. Other signals include periodic signals (such as clock signals, both symmetric and non-symmetric) used in the operation of theimage sensor306. When theimage sensor306 includes a CCD array, these periodic signals include clock signals referred to as pixel clock signals useful in the operation of the CCD array. It should be noted that due to the programmable nature of the programmableuniversal controller428, a wide variety of image sensors can be accommodated by thedigital image processor310 without the need to resort to expensive and time consuming fitting procedures.
• The programmable[0069]universal controller428 is also capable of generating reference signals useful in the operation of analog components included in thedigital camera300. Such analog components for which the analog reference signals may be used include the A/D converter308. By way of example, in one embodiment, theimage capture unit302 includes an automatic range finder useful in determining the distance to the object being photographed. Typically, the range finder generates signals related to the measured distance which are sent to an evaluator which determines whether or not the object is within the proper range. If not, microstepper controller signals are fed back to appropriate motors that control image conditioners, such as focus and zoom. More particularly, in one example, based upon the evaluation, afocus signal generator430 and azoom signal generator434 generate appropriate micro-stepper control signals. These micro-stepper control signals are then fed to theimage conditioner304 by way of the optics control bus. In this way, the programmableuniversal controller428 provides for rapid and automatic focus and zoom control without substantially increasing the number of components within thedigital camera300. Additionally, thedigital image processor310 is capable of reading the digital image from theimage sensor306 and analyze a central portion of the array of photosites for proper focus.
• In one embodiment of the invention, a[0070]data buffer432 associated with thefocus signal generator430 takes the form of a look up table (LUT) having stored micro-stepper signal values corresponding to the received distance signals. Adata buffer436 associated with thezoom signal generator434 is also be a LUT having stored micro-stepper signal values associating the received distance signals to the proper zoom value. In addition to generating required micro-stepper controller signals, the programmableuniversal controller428 supplies periodic signals, such as for example, timing signals. Such timing signals may be generated in response signals received from, for example, an f-stop controller, a light meter, a shutter controller as well as an associated flash controller included in, for example, theimage conditioner304.
• By way of example, the[0071]image capture unit302 may include a photometer responsive to the level of ambient light. The photometer may have an ambient light level threshold below which signals are sent to the programmableuniversal controller428 indicating that the light level is insufficient to produce an image of desired quality. At this point, ashutter timing generator438 and an f-stop timing generator440, for example, generate appropriate timing signals using a clock and associated timing data.
• In one embodiment of the invention, the[0072]shutter timing generator438 and the f-stop timing generator440 are associated with a shutter timingdata buffer442 and a f-stoptiming data buffer444, respectively. The shutter timingdata buffer442 and the f-stoptiming data buffer444 are each capable of storing any data appropriate to the generation of the respective timing signals. Aclock circuit452 connected to the system bus404 is used by theshutter timing generator438 and the f-stop timing generator444, respectively, to generate the required control signals. In this way, thedigital image processor400 provides an integrated automatic approach to the operation of thedigital camera system300.
• In addition to providing timing and micro-stepper control signals, the programmable[0073]universal controller428 includes a universalstate machine controller446 capable of providing both symmetric and non-symmetric periodic signals. Such periodic signals may include clock signals such as those pixel clock signals used to synchronize the operation of, for example, an exemplary CCD array included in theimage sensor306. Such pixel clock signals include integration clocks, reset clocks, shift clocks, and any other periodic signals deemed appropriate by, for example, an exemplary CCD array manufacturer.
• The programmable[0074]universal controller428 also includes a universal analogreference signal generator448 capable of generating any required analog reference signals. These analog reference signals may be used in, for example, the operation of the A/D converter308. Both the universal analogreference signal generator448 and the universalstate machine controller446 have associated input data registers operatively connected to the system bus404.
• In one embodiment of the invention, the universal analog[0075]reference signal generator448 and the universalstate machine controller446 each have a set ofdata registers447 and449, respectively, for storing data appropriate to the operational mode of thedigital camera300. By way of example, in what is referred to herein as the cineview mode, a stream of digital images are processed at a rate sufficient to simulate motion (typically in the range of approximately 10 fps to approximately 20 fps). In order to provide proper control and timing signals, data suitable for operating thedigital camera300 in cineview mode are stored in associated ones of the data registers447 and the data registers449.
• The[0076]system CPU interface450 connects the system bus404 to themicroprocessor312 and provides access to all internal registers and data buffers included in thedigital image processor400. In this way, themicroprocessor312 may set all internal registers and/or data buffers as may be required for proper operation.
• FIG. 5 is a functional block diagram of a color interpolation circuit[0077]500 in accordance with an embodiment of the invention. It should be noted that the color interpolation circuit500 is but one possible embodiment of thecolor interpolator422 used in thedigital image processor400 shown in FIG. 4. In the described embodiment, the color interpolation circuit500 is capable of receiving a variety of color interpolation input data and determining the weights that are to be used in processing raw input pixel signals into re-sampled pixel signals that have full color at each location. The color interpolation input data may include the number of photosites (or pixels) on the active surface of the image sensor array, the associated color filter array (CFA), as well as any desired filtering of the re-sampled resulting image.
• The color interpolation circuit[0078]500 includes a pixelcolor weight generator502 capable of generating the pixel color weights that, taken together, form pixel color weight matrices used to generate the re-sampled image. The pixelcolor weight generator502 receives the color interpolation input data, such as the number of pixels in the image sensor array, the associated CFA of the particular image sensor array, as well as any desired filtering. The pixelcolor weight generator502 then uses the received color interpolation input data to form a multiplexed array of pixel color weights. The multiplexed array of pixel color weights are then stored in a pixel colorweight matrix buffer504 which forms an input to aconfigurable convolver506. Theconfigurable convolver506 in turn receives the raw image data and operates to form the re-sampled resulting image having full color at every pixel.
• FIG. 6 is a flowchart detailing the color interpolation[0079]600 of a digital image by the color interpolation circuit500 in accordance with an embodiment of the invention. It should be noted that the flowchart is but one possible embodiment of the color interpolation circuit500 used in thedigital image processor400 shown in FIG. 5. The color interpolation of the digital image begins with the pixel weight generator receiving appropriateimage sensor data610. The image sensor data may include the number of pixels in the image sensor array as well as the particular color filter array associated with the image sensor array. The input data may also include optional digital image filtering selected by the user. Once received, a determination is made if new pixel color weight factors are required620. If it is determined that new pixel color weight factors are required, they are generated630, in one embodiment of the invention, by firmware included in themicroprocessor312 using the image sensor input data. These pixel color weight factors may be generated by any number of techniques well known to those skilled in the art. One such technique referred to as bi-linear interpolation uses known pixel colors to derive the unknown pixel colors. Another well known technique referred to as bi-cubic interpolation may be used when higher color fidelity is required. Once the pixel color weight factors have been derived using any suitable technique, they are stored640 in a pixel color weight buffer where they are stored until needed. A configurable convolver then uses the stored pixel color weight factors to process650 received digital images to full color resulting images.
• FIG. 7 is a block diagram of a universal state machine controller[0080]700 in accordance with an embodiment of the invention. It should be noted that the universal state machine controller700 is but one possible embodiment of the universalstate machine controller446 used in thedigital image processor400 shown in FIG. 4. The universal state machine controller700 is capable of providing both symmetric and non-symmetric clock signals as well as pulse signals. By symmetric clock signals it is meant those clock signals having symmetric waveforms whereas non-symmetric clock signals have non-symmetric waveforms. Such clock signals may include those pixel clocks used to synchronize the operation of the CCD array included in theimage sensor306.
• The universal state machine controller[0081]700 includes afast clock702 capable of generating precise symmetric waveforms. Typically, the fast clock period is approximately 10 ns but may range as low as approximately 1 ns, or as may be required by the particular CCD array for which the clock signals are being generated. In the embodiment shown in FIG. 7, thefast clock702 forms an input to alogic unit704 havinginput lines706 through712 capable of carrying input signals derived from data stored in the data registers447. Such input signals are used by thelogic unit702 to form the desired symmetric or non-symmetric clock signal.
• To form a symmetric clock signal, one implementation of the universal state machine controller[0082]700 provides for theinput line706 to supply an initial state signal indicative of a high going clock signal or a low going clock signal. The input line508 supplies a period signal indicative of the number of ticks (each tick being equivalent to a single period of the fast clock702) for which the desired clock signal generated by the universal state machine controller700 extends. Theinput line710 supplies a first change signal indicative of the tick at which the polarity of the clock signal generated by the universal state machine controller700 changes (the half cycle of the clock signal).
• If, however, a non-symmetric clock signal is desired, the universal state machine controller[0083]700 provides for the input line512 to carry a second change signal indicative of the tick at which the clock signal changes polarity in reference to the first change signal.
• It should be noted that the[0084]logic unit704 may take the form of any programmable circuit. The programmable nature of thelogic block704 provides the universal state machine controller700 with a wide range of operable modes.
• FIG. 8A is a block diagram of a universal state machine controller[0085]800 in accordance with another embodiment of the invention. The universal state machine controller800 includes acounter buffer802 connected to afast clock804 capable of acting as a counter. Thecounter buffer802 is also operably connected to amemory unit806 capable of storing a representations of a desired clock signal waveform.
• In operation, a representation of the desired clock signal is stored in the[0086]memory unit806. One such representation shown in FIG. 8A provides the universal state machine controller800 with data sufficient to form the non-symmetric clock signal shown in FIG. 8B. The universal state machine controller800 forms the non-symmetric clock signal by applying the stored representation to thecounter buffer802. Thecounter buffer802 in turn acts in conjunction with thefast clock804 to form the associated non-symmetric clock signal. It should be noted that in this particular example, a logical “1” stored in thememory806 corresponds to logical CLOCK HIGH while a logical “0” corresponds to a logical CLOCK LOW.
• It should also be noted that the[0087]counter buffer802 and thememory806 can be any form of memory capable of storing data consistent with the operation of the universal state machine controller800. Such memories can include but are not limited to static random access memories, dynamic random access memories, and any other suitable volatile or non-volatile memory device.
• FIG. 9 is a block diagram of a programmable analog reference signal generator[0088]900 in accordance with an embodiment of the invention. It should be noted that the programmable analog reference signal generator900 is but one possible embodiment of the programmable analogreference signal generator448 used in thedigital image processor400 shown in FIG. 4. The programmable universal controller900 includes a universal analogreference signal generator902 coupled to aprogrammable data buffer904 capable of generating analog reference signals. It should be noted that theprogrammable data buffer904 is but one possible embodiment of the register set449 shown in FIG. 4.
• In one embodiment of the invention, the universal analog[0089]reference signal generator902 takes the form of a pulse width modulation (PWM) block represented asPWM906. ThePWM906 uses data stored in theprogrammable data buffer904 in conjunction with afast clock908 to generate any desired analog reference signal. The analog reference signals generated can be selectively formed to meet the requirements of the particular operating mode of thedigital camera300. In the case where thedigital camera300 is operating in the capture mode, theprogrammable data buffer904 can supply data appropriate to that mode of operation. In another case where thedigital camera300 is operating in, for example, the cineview mode, theprogrammable data buffer904 can supply appropriate data accordingly.
• FIG. 10A is a flowchart detailing authentication stamping of a digital image in accordance with an embodiment of the invention. It should be noted that the flowchart is but one possible embodiment of the[0090]authentication stamper418 used in thedigital image processor400 shown in FIG. 4. Therefore, the authentication stamping shall be described in context of thedigital image processor400 and all references included therein. First, a digital image to be authentication stamped along with associated useful authenticating information (sometimes referred to as private camera information) are obtained1005. The digital image to be authentication stamped and the authenticating information are then processed1010 using for example, a one way HASH algorithm. The resulting image digest1015 is encrypted1020 using a secure key to form andigital authentication stamp1025 which is appended to thedigital image1030.
• FIG. 10B is a flowchart detailing verification of an authentication stamped digital image in accordance with an embodiment of the invention. First, a digital image having an associated authenticity stamp is received[0091]1050. Next, a first image digest is formed by decrypting the associated authenticity stamp using apublic key1055. A second image digest is also formed by processing the digital image to be verified, using for example a one-way HASH algorithm1060. Next, the first image digest and the second image digest are compared1065. Finally, verification of the digital image based upon the comparing of the image digests is performed1070. In one implementation of the invention, if the image digests are equal, then the digital image is verified. Alternatively, if the image digests are not equal then the digital image is not verified.
• The digital authentication stamp is useful for many purposes including, for example, authenticating the source camera, image author, and image date of any digital image so stamped. It should be noted that the secure key is associated with only the[0092]digital camera system300 into which thedigital image processor400 is installed. Any other digital camera system into which thedigital image processor400 is installed with have a different secure key. In this way, any digital image produced by a particular digital camera system may be uniquely ascribed to only that particular digital camera system. In other implementations, theauthentication stamper418 may include user specific information such as, for example, user name, user address, camera serial number, manufacturing date and/or code that may be used to further identify the source of the digital image of interest.
• FIG. 11 is a flowchart detailing the image processing[0093]1100 of raw digital image data by adigital image processor400 in adigital camera system300 in accordance with an embodiment of the invention. The image processing of raw digital image data begins with an image sensor within the digital camera generating a raw analog digital data which is then converted to raw digital image data by a converter. A preprocessor receives the rawdigital image data1105. The first processing stage then corrects1110 any non-uniformities in the digital image. Such non-uniformities correction may be accomplished using PRNU and white balance techniques where PRNU coefficients are stored in memory. Next, if the digital camera is operating incapture mode1115, the corrected digital image is stored inmemory1120. If, however, the digital camera is not operating incapture mode1115, then it is determined if the corrected digital image is to be authentication stamped1125. If the corrected digital image is to be authentication stamped, then the corrected digital image is forwarded to theauthentication stamper1130. If it is determined that the image is not to be authentication stamped1125, then the corrected digital image is fully pre-processed by thepreprocessor1135. Next, it is determined if the digital image is to be post processed on-chip1140. By on-chip it is meant that post processing is performed by the digital image processor. If it is determined that the post processing is performed off-chip, the digital images are sent to anoff chip processor1145. If it is determined that the post processing is to be done on-chip1140, it is then determined if new pixel color weight factors are required1150. If it is determined that new pixel color weight factors are required, then appropriate image sensor data is received1155 and used to derive newpixel weight factors1160 associated with the image sensor. In either case, the digital image is then color corrected1165 and the color corrected digital image is output to thesystem bus1170.
• FIG. 12 is a block diagram of a[0094]digital camera system1200 in accordance with another embodiment of the invention. Thedigital camera system1200 is formed of thedigital camera system300 shown in FIG. 3 wherein themicroprocessor312 has been replaced by specialized processors. Such specialized processors include avideo processor1202 capable of processing viewable images as well as asystem processor1204 capable of directing the operations of thedigital camera system1200. By providing specialized processors, thedigital camera system1200 is well suited for use in more specialized applications where particular processing needs are important. An application requiring high speed video processing unavailable with more general application processors would be well served by thedigital camera system1200.
• FIG. 13 is a block diagram of a[0095]digital camera system1300 in accordance with yet another embodiment of the invention. Thedigital camera system1300 is formed of thedigital camera system300 wherein themicroprocessor312 and thedigital image processor310 have been combined into amicroprocessor1302. In this arrangement, thedigital camera system1300 has a higher degree of integration providing for fewer components in the manufacture of thedigital camera system1300.
• It should also be noted that the digital image processor is capable of supporting any suitable number imaging arrays included in an associated image sensor. As an example, in one embodiment of the invention,[0096]
• FIG. 14 is a block diagram of a[0097]digital image processor1400 in accordance with an embodiment of the invention. Thedigital image processor1400 is capable of processing raw digital images from an image sensor that includes 3 imaging arrays where each imaging array is arranged to respond to, for example, a single primary color. As shown in FIG. 14, thedigital image processor1400 is a straightforward modification of thedigital image processor400 shown in FIG. 4 and thedigital camera300 shown in FIG. 3. Thedigital image processor1400 provides for that the raw digital images from three image sensors are received and processed simultaneously. Three separate pre-processors402-1,402-2, and402-3 each receive separate raw digital images from an associated image sensor and process each accordingly. The processed image is then combined using, for example, firmware included in themicroprocessor312 before being stored in thelocal memory311 and/or thesystem memory314. In this way, a camera manufacturer is capable of producing a digital camera capable of producing very precise color photography without resorting to expensive and time consuming fitting procedures. It should be noted that theauthenticity stamper418 has been omitted for sake of clarity only and it may in fact be used to authenticate stamp any image processed by thedigital image processor1400.
• FIG. 15 is a block diagram of a[0098]digital image processor1500 capable of processing digital images from three image sensors in accordance with another embodiment of the invention. Thedigital image processor1500 is capable of processing the raw digital images from three image processors using amultiplexer1502 connected to three data buffers1504-1 through1504-3 capable of staging raw digital images from the three image sensors included in the digital camera. The three raw digital images staged in the data buffers1504-1,1504-2, and1504-3 are received at themultiplexer1502 based upon a selection signal generated by a selector1506. Once selected, the raw digital image is passed to thepre-processor402 for suitable processing.
• The invention has numerous advantages. One advantage of the invention is that the digital image processor can be used by any digital camera manufacturer, regardless of their specific image sensor, color interpolation scheme, etc., in a digital camera. The digital image processor will also significantly reduce development time and costs, as well as component costs since specific ASICs no longer must be provided.[0099]
• Another advantage of the invention is that the system bus architecture provides for flexible operation of the digital camera. The system bus architecture also provides the digital camera manufacturer the capability of economically configuring the digital camera as desired. In this way, the camera manufacturer is able to offer a wide variety of digital camera configurations without the need to resort to expensive and time consuming fitting procedures.[0100]
• Yet another advantage of the invention is that it provides the digital camera user with on demand specialized imaging modes such as the capture mode and the cineview mode. Providing these specialized imaging modes makes the taking of quality photos using the digital camera much easier. In addition, these and other specialized imaging modes, makes the use of the digital camera more cost and time effective since the user is less likely to waste time and effort on photos which will not be used.[0101]
• Although the foregoing invention has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are may alternative ways of implementing the present invention. For example, the system bus has been described as carrying data signals, control signals, and digital image signals. In alternative embodiments, a separate control or other bus could be provided to carry some of these signals. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, and equivalents as fall within the spirit and scope of the present invention.[0102]

Claims (33)

What is claimed is:

1. A digital image processor for use in a digital camera having an image capture unit arranged to output analog signals that represent the captured image, a converter unit for converting analog representations of the captured image to digital representations of the image, a memory for storing digital representations of the image, and a processing unit capable of directing components included in the digital camera, the digital image processor comprising:

an input data stream processor for pre-processing images received from the converter unit and storing the pre-processed images in the memory; and

an output data stream processor arranged to receive pre-processed images and post-process the retrieved images into a viewable form.

2. A digital image processor as recited inclaim 1 further comprising a system bus within the digital image processor, wherein the input data stream processor, the output data stream processor and the memory are coupled to the system bus.

3. A digital image processor as recited inclaim 2, wherein the output data stream processor includes a color interpolator arranged to derive an unknown pixel color value associated with a first pixel based upon at least one known pixel color value associated with at least one other pixel using pixel color weight factors associated with the image sensor.

4. A digital image processor as recited inclaim 3 further including a color pattern setting buffer connected to the color interpolator capable of storing image sensor data associated with the image sensor included in the image capture unit, the image sensor data being used to derive the associated pixel color weight factors.

5. A digital image processor for use in a digital camera as recited inclaim 3, wherein the output data stream processor further includes an RGB reconstructor connected to the color interpolator capable of converting the digital image to an RGB format as needed.

6. A digital image processor for use in a digital camera as recited inclaim 5, wherein the output data stream processor further includes a digital image compressor connected to the color interpolator and the RGB reconstructor capable of appropriately compressing digital image files.

7. A digital image processor as recited inclaim 6 wherein the color interpolator, the RGB reconstructor, and the compressor are each connected to the system bus.

8. A digital image processor as recited inclaim 1, wherein the input data stream processor does not include any color interpolation.

9. A digital image processor as recited inclaim 2, further comprising a programmable universal controller arranged to generate operational signals useful in the operation of components included in the digital camera.

10. A digital image processor as recited inclaim 9, wherein the programmable universal controller includes an image sensor controller for generating signals useful for synchronizing the image sensor.

11. A digital image processor as recited inclaim 10, wherein the image sensor controller includes a programmable clock generator that may be programmed to generate both symmetric clock signals and non-symmetric clock signals.

12. A digital image processor as recited inclaim 11, wherein the programmable clock generator is arranged to receive a fast clock signal and includes a programmable logic block having a programmable clock register, wherein the programmable clock register may be programmed using data stored in the programmable logic block to create a desired symmetric or non-symmetric clock signal based at least in part upon the fast clock signal.

13. A digital image processor as recited inclaim 11, wherein the programmable clock generator includes a counter buffer arranged to receive a fast clock signal, the counter buffer being connected to a memory unit, wherein the memory unit includes programmable data registers capable of storing clock signal characterizing data used by the counter buffer to create a desired symmetric clock signal or a desired non-symmetric clock signal based at least in part upon the fast clock signal.

14. A digital image processor as recited inclaim 13, wherein the clock signal characterizing data includes a clock tick value and an associated clock signal output value.

15. A digital image processor as recited inclaim 10, wherein the programmable universal controller further includes a programmable analog reference signal generator for generating analog reference signals useful in the operation of analog components included in the digital camera.

16. A digital image processor as recited inclaim 15, wherein the programmable analog reference signal generator includes:

a programmable register for storing analog reference signal characterizing data; and

a pulse width modulation (PWM) block that uses the analog reference signal characterizing data stored in the programmable register and the fast clock signal to create the desired analog reference signal.

17. A digital image processor recited inclaim 2, wherein the input data stream processor includes a non-uniformity corrector capable of correcting non-uniformities included in the digital representations of the image received from the converter unit.

18. A digital image processor recited inclaim 17, wherein the input data stream processor further includes:

a programmable sampling filter connected to the non-uniformity corrector being capable of systematically selecting portions of the corrected digital image received from the non-uniformity corrector;

a modular transformer connected to the programmable sampling filter being capable of at least correcting aberrations in the sampled digital image received from the programmable sampling filter; and

a ditherer connected to the modular transformer being capable of at least correcting any aliasing in the digital image received from the modular transformer.

19. A digital image processor recited inclaim 18, wherein the digital image processor further includes an authenticity stamping unit connected to the non-uniformity corrector and the system bus.

20. A digital image processor recited inclaim 19, wherein the authenticity stamping unit includes an authenticity stamper connected to a secure key buffer for storing a secure key, the authenticity stamper being capable of encryptically combining digital camera identification and the secure key with an associated non-uniformity corrected digital image.

21. A digital image processor as recited inclaim 20, further comprising:

a memory interface controller connected to the system bus, the memory interface controller being capable of providing control signals suitable for controlling the storing of image data in and the retrieving image data from the memory;

a central processing unit (CPU) interface operatively connected to the system bus for managing communications between the digital image processor and a digital camera system CPU; and

system clock connected to the system bus, the system clock being capable of providing clock signals.

22. A digital image processor as recited inclaim 21, wherein the non-uniformity corrector sends a first corrected digital image directly to the programmable sampling filter which, in turn, sends the sampled digital image to the system bus, the sampled digital image being capable of display on a viewer in a cineview mode, the cineview mode being capable of providing the digital camera with “through the lens viewing”.

23. A digital image processor as recited inclaim 22, wherein the non-uniformity corrector outputs an associated second corrected digital image to the system bus, the second digital image, in turn, being capable of storage in the memory in a capture mode.

24. A digital image processor as recited inclaim 23, wherein the digital camera further includes an input/output (1/0) block suitable for coupling the microprocessor to external devices.

25. A digital image processor as recited inclaim 2, wherein the output data stream processor is arranged such that its operation does not interfere with the operation of the input data stream processor or taking pictures using the digital camera.

26. A digital camera comprising:

an image capture unit capable arranged to output analog signals that represent a captured image;

a converter unit for converting analog representations of the captured image to digital representations of the image in the form of pixels;

a digital image processor for use in a digital camera as recited inclaim 1; and

memory for storing the digital representations of the image.

27. A method of processing a digital image using a digital camera that includes an image capture unit and a digital image processor, the method comprising:

receiving a image at the image capture unit to form a captured image and outputting analog signals representative of the captured image from the image capture unit;

converting the analog signals to digital image signals representative captured image;

pre-processing the digital image signals to form a digital image, wherein the preprocessing includes correcting non-uniformities in the captured image;

storing the pre-processed digital image in a generally accessible memory that is part of the digital camera; and

retrieving the pre-processed digital image from the memory and post processing the pre-processed digital image into a viewable form.

28. A method of processing a digital image using a digital camera as recited inclaim 27, wherein the post-processing is done is a first mode of operation and in a second mode of operation the method further includes:

sampling the pre-processed digital image to reduce the size of the preprocessed digital image to a size suitable for display on a viewer display located on the camera;

supplying the sampled digital image to the viewer display.

29. A method of processing a digital image using a digital camera as recited inclaim 27 further comprising incorporating an authenticity stamp into the digital image.

30. A method of processing a digital image using a digital camera as recited inclaim 29 wherein the incorporation of the authenticity stamp is done as part of the pre-processing.

31. A method of processing a digital image using a digital camera as recited inclaim 27, wherein the post-processing includes:

color correcting the pre-processed digital image;

digitally compressing the color corrected digital image; and

storing the compressed digital image in memory.

32. A method of processing a digital image using a digital camera as recited inclaim 31, wherein the color correcting includes deriving an unknown pixel color value associated with a first pixel based upon at least one known pixel color value associated with at least one other pixel using pixel color weight factors associated with the image sensor.

33. A method of processing a digital image using a digital camera as recited inclaim 27 wherein wherein the post-processing is done is a first mode of operation and in a second mode of operation the method further includes outputting the pre-processed digital image to a device external to the digital camera to facilitate post-processing the digital image in an off-chip processing mode.

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