US20030040166A1 - Apparatus and method for stacking integrated circuits - Google Patents

Abstract

A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack.

Description

RELATED APPLICATIONS
• The present application claims priority benefit under 35 USC §119(e) from U.S. Provisional Application No. 60/293,766 filed May 25, 2001, entitled “STACKED MEMORY” and U.S.[0001]Provisional Application 60/294,389 filed May 29, 2001, entitled “STACKED MEMORY”, which are herein incorporated by reference. The present application is related to applicant's co-pending application Ser. No. ______ (Attorney docket No. SIMTECH.250A) entitled “APPARATUS AND METHODS FOR STACKING INTEGRATED CIRCUIT DEVICES WITH INTERCONNECTED STACKING STRUCTURE” which is concurrently filed herewith.
BACKGROUND OF THE INVENTION
• 1. Field of the Invention[0002]
• The invention relates to the vertical stacking of integrated circuits to increase the density of components on a printed circuit board without increased footprint. More particularly, the present invention relates to apparatus and methods for the vertical stacking of memory integrated circuits on a surface mount printed circuit board.[0003]
• 2. Description of the Related Art[0004]
• Modern electronic devices, such as computers and the like, typically include integrated circuits commonly referred to and will be referred to herein as “chips”. Integrated circuits or chips are microcircuits formed on a semiconductor substrate and packaged in a ceramic, plastic or epoxy package having multiple external terminals or “pins”. The microcircuits are wire-bonded within the package to the external terminals or pins. When the pins of the chip packages are connected to the printed circuit board, the integrated circuits are electrically connected to other integrated circuits and electrical components through or by way of traces on the printed circuit board to form system level electronic circuits.[0005]
• With advances in semiconductor device processing has come a continuing increase in device count and density within chips and this has driven a corresponding increase in the count and density of the external conducting pads. Current technology places a limit on how small external contacts can be made and how closely they can be placed adjacent one another while still maintaining circuit integrity. Limits are imposed, both by the limitations of machinery to form ever-smaller conductive elements and by the reduction in production yield as the limits are pushed.[0006]
• Additionally, as modern electronic devices are driven to ever increasing functionality and decreasing size, the printed circuit boards within the electronic devices are driven to increased integrated circuit densities. The desire to provide the capability of integrated circuits to be used in relatively small devices limits the extent to which multiple chips can be laterally interconnected while still fitting within the device. Lateral extension and interconnection of chips tends to lead to relatively long interconnects or traces between chips which increases the signal propagation delay and thus, decreases the circuit operating speed. Further, lengthy traces increase both the radio-frequency interference (RFI), and electromagnetic interference (EMI) emitted from the printed circuit board.[0007]
• From the foregoing, it can be appreciated that there is an ongoing need for structures and methods for interconnecting chips that increase circuit density without increasing the chip footprint and with minimal increase in interconnection length.[0008]
SUMMARY OF THE INVENTION
• The aforementioned needs are satisfied by the invention in which one aspect is various structures and methods for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack. The structures and methods include the aspect that the footprint of the stack does not exceed the sum of the individual footprints of the chips in the stack.[0009]
• A certain aspect of the invention is a chip stack assembly comprising a substrate that defines a plurality of surface mount pads, a first chip having a first set of contacts extending outward, a second chip having a second set of contacts extending outward therefrom, at least one support member positioned on the substrate having a first surface with a first set of mounting pads positioned thereon and a second surface having a second set of mounting pads positioned thereon wherein the first and second surfaces are displaced from each other by a first distance in a first direction and wherein the first set of contacts are attached to the first set of mounting pads and the second set of contacts are attached to the second set of mounting pads such that the first and second chips are supported so as to be displaced from each other in the first direction and wherein the at least one support member further includes at least one interconnect that interconnects at least one contact of the first and second set of contacts so as to electrically interconnect the at least one contact of first and second set of contacts and wherein the at least one support member further includes at least one via connection that extends in the first direction through the at least one support member to the substrate so that at least one individual contact of the first set of contacts can be electrically coupled to the surface mount pad of the substrate while being electrically isolated from the second set of contacts.[0010]
• The invention is also a method of mounting a plurality of chips into a stacked configuration, the method comprising attaching a first set of contacts of a first chip to a first set of mounting pads formed on a first surface of a support structure, attaching a second set of contacts of a second chip to a second set of mounting pads formed on a second surface of the support structure, wherein attaching the first and second sets of contacts to the support structure results in the first and second chips being positioned in a stacked orientation with respect to each other, electrically interconnecting at least one selected contact of first and second sets of contacts using the support structure, electrically connecting the at least one contact of the first and second set of contacts to a mounting pad on a substrate such that the electrically interconnected at least one contact receives a common signal, forming an isolated pathway from at least one other of the first set of contacts to a mounting pad on the substrate; and electrically connecting at least one other contact from the first set of contacts to a mounting pad formed on the substrate using the isolated pathway so that the at least one other contact is electrically isolated from the second set of contacts such that the at least one other contact receives an individual signal.[0011]
• An additional aspect of the invention is a chip stack for mounting on a substrate having a plurality of contact pads comprising at least a first and a second chip and a conducting interconnecting means for interconnecting the chips and maintaining the chips in a stacked configuration so that the chips are interconnected with at least one contact on the first and second chips being electrically interconnected and wherein the interconnecting means interconnects the at least one of the contacts of the first chip to a contact pad on the substrate in a manner that isolates the contact of the first chip from the contacts of the second chip.[0012]
• The invention also includes the aspects of a chip stack of at least one preformed support structure interconnecting a first chip to a second chip wherein the support structure comprises a member having a first surface and a second surface, a plurality of surface mount pads disposed along the first surface and the second surface of the member, a plurality of vias disposed between the first surface and the second surface of the member; and a plurality of conducting elements wherein the conducting elements interconnect the surface mount pads and the vias.[0013]
• Yet another aspect of the invention is a chip stack module comprising a first chip comprising a first set of common contacts and a first set of individual contacts, a second chip comprising a second set of common contacts and a second set of individual contacts, and an interconnecting structure wherein the interconnecting structure further includes at least one interconnect and at least one via connection whereby the interconnecting structure interconnects the first and second chips wherein the first set of common contacts is electrically connected to the second set of common contacts and the first set of individual contacts and does not electrically connect to the second set of individual contacts, the first set of common contacts, and the second set of common contacts.[0014]
• An additional aspect of the invention is a chip stack comprising a first chip having a generally planar formed top surface and first set of contacts formed in a first pattern comprising a first set of signals and a second set of signals, a second chip having the generally planar formed top surface and a second set of contacts formed in the first pattern comprising a third set of signals and a fourth set of signals, a support structure having a first side and a second side comprising a first set of surface mount pads on the first side, a second set of surface mount pads on the second side, a plurality of conducting elements, a plurality of vias positioned through the support structure from the first side to the second side and spaced from the conducting elements, whereby the conducting elements electrically interconnect the first and third sets of contacts, and the vias electrically conduct the fourth set of contacts without interconnecting the fourth set of contacts to the first, second and third sets of contacts, when the support structure is positioned between stacked first and second chips.[0015]
• For purposes of summarizing the invention, certain aspects, advantages and novel features of the invention have been described herein. Of course, it is to be understood that not necessarily all such aspects, advantages or features will be embodied in any particular embodiment of the invention.[0016]
• These and other objects and advantages of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings.[0017]
BRIEF DESCRIPTION OF THE DRAWINGS
• A general architecture that implements the various features of the invention will now be described with reference to the drawings. The drawings and the associated descriptions are provided to illustrate embodiments of the invention and not to limit the scope of the invention. Throughout the drawings, reference numbers are re-used to indicate correspondence between referenced elements.[0018]
• FIG. 1A is a perspective view illustrating a memory chip stack module of the present invention of a preformed support structure vertically interconnecting a first chip to a second chip, according to aspects of an embodiment of the invention;[0019]
• FIG. 1B is a detail, perspective view of a portion of the preformed support structure of FIG. 1A illustrating the connection path of an individually accessed signal, according to aspects of an embodiment of the invention;[0020]
• FIG. 1C is a detail, perspective view of a portion of the preformed support structure of FIG. 1A illustrating the connection path of a common signal, according to aspects of an embodiment of the invention;[0021]
• FIG. 2A is a top view the memory chip stack module of FIG. 1A, according to aspects of an embodiment of the invention;[0022]
• FIG. 2B is a side view the memory chip stack module of FIG. 1A, according to aspects of an embodiment of the invention;[0023]
• FIG. 2C is a front view of the memory chip stack module of FIG. 1A, further illustrating the preformed support structure vertically connecting the first chip with the second chip, according to aspects of an embodiment of the invention;[0024]
• FIG. 2D is a footprint of the memory chip stack module of FIG. 1A illustrating the area of the chip stack on a printed circuit board, according to aspects of an embodiment of the invention;[0025]
• FIG. 2E is a detail of the chip stack module footprint of FIG. 2D further illustrating spacing between pads of the chip stack module, according to aspects of an embodiment of the invention;[0026]
• FIG. 3A is a pin location map of the memory chip stack of FIG. 1A, according to aspects of an embodiment of the invention;[0027]
• FIG. 3B is pin symbol table of the memory chip stack of FIG. 1A, according to aspects of an embodiment of the invention;[0028]
• FIG. 3C is a pin function table of the memory chip stack of FIG. 1A, according to aspects of an embodiment of the invention;[0029]
• FIG. 4 is a functional block diagram of the memory chip stack of FIG. 1A, according to aspects of an embodiment of the invention;[0030]
• FIG. 5A is a front view of a chip stack module illustrating widened preformed support structures vertically connecting a first chip, a second chip, a third chip, and a fourth chip, according to aspects of an embodiment of the invention;[0031]
• FIG. 5B is an enlarged detail of the chip stack module of FIG. 5A illustrating the connection path of isolated signals, according to aspects of an embodiment of the invention;[0032]
• FIG. 5C is a detail, perspective view of a portion of the preformed support structures of FIG. 5B, according to aspects of an embodiment of the invention;[0033]
• FIG. 5D is a bottom surface view of a portion of the chip stack module of FIG. 5A illustrating the connection path of isolated signals, according to aspects of an embodiment of the invention;[0034]
• FIG. 5E is a detail of a footprint of the chip stack module of FIG. 5A, according to aspects of an embodiment of the invention;[0035]
• FIG. 6A is a front view of a chip stack tower illustrating a chip stack module mounted onto a ball grid array printed circuit board, according to aspects of an embodiment of the invention; and[0036]
• FIG. 6B is a is a detail, perspective view of a portion of the ball grid array printed circuit board of FIG. 6A and the preformed support structure mounted thereon, according to aspects of an embodiment of the invention.[0037]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
• In accordance with one embodiment of the present invention, one multi-chip memory module design is described herein. In order to fully specify this preferred design, various embodiment specific details are set forth, such as the number of memory chips in the module, the capacity, the number of data bits, the pin-outs of the memory chips, the module footprint, and the like. It should be understood, however, that these details are provided only to illustrate one embodiment, and are not intended to limit the scope of the present invention.[0038]
• FIG. 1A illustrates a perspective view of a[0039]chip stack module10 comprising two surface mount chips12,14 stacked in accordance with the present invention. Thechip stack module10 further comprises a support member orsupport structure16. Thesupport structure16 holds together and conductively interconnects the vertically stackedchips12,14. Thechip stack module10 is configured to be surface mounted to a printed circuit board that has surface mount pads thereon. Thechip stack module10 further comprises a width B, a height C, and a spacing D betweenstacked chips12,14
• Surface mount chips[0040]12,14 comprise apin1indicator18, a plurality ofsurface contacts20, and a width G. In one embodiment, thesurface contacts20 are distributed in two rows ofcontacts20, each row disposed along an opposing side of thechip12,14 as is generally well known in the art.
• The[0041]support structure16 in this embodiment comprises aframe22 and a plurality ofsurface mount pads24. Frame members across a front side withoutsurface contacts20 ofchips12,14 are not shown in FIG. 1A in order to illustrate the stacking ofchips12,14. In another embodiment,frame22 comprises two rails positioned parallel to each other and perpendicular to a top surface of thechips12,14. Thesurface mount pads24 are distributed in two rows on each opposing side offrame22 with a top row ofsurface mount pads24 placed along a top surface of theframe22 and a bottom row ofsurface mount pads24 placed along a bottom surface of theframe22, as shown in FIG. 1B. The top row ofsurface mount pads24 aligns over and directly opposes the bottom row ofsurface mount pads24. Spacing and alignment of each row ofsurface mount pads24 corresponds to the spacing and alignment of the rows ofsurface contacts20 of thechips12,14.
• The[0042]frame22 may comprise a two-layer printed circuit board made of a rigid, non-conducting material such as glass epoxy, FR4, and the like. Theframe22 further comprises the length A, a width E and a height F.
• In one embodiment, the height F of the[0043]frame22 is approximately equal to the thickness of onechip12,14 so that thestacked chips12,14 are nearly touching when the memorychip stack module10 is assembled. Close spacing D betweenstacked chips12,14 advantageously provides thechip stack module10 with a low profile, which is desirable in densely populated electronic devices. Alternatively, in another embodiment, the height F of theframe22 may be advantageously adjusted to increase the spacing D betweenstacked chips12,14, as may be desirable in certain applications to facilitate the cooling of the chips.
• When, in one embodiment,[0044]chip stack module10 is assembled,surface contacts20 of the signals common to bothchips12,14 are conductively interconnected and all memory locations on bothchips12,14 can be utilized. However, for proper operation of thechip stack module10, some signals on eachchip12,14 are individually accessed and not interconnected. In an embodiment utilizing functionally identicalstacked chips12,14, thesurface contact20 of the isolated signal ofchip12 is directly below the surface contact of the corresponding isolated signal ofchip14. Similarly, thesurface contact20 of the common signal ofchip12 is directly below the surface contact of the corresponding common signal ofchip14. FIGS. 1B and 1C illustrate a conducting a path for an isolated signal and a common signal, respectively.
• FIG. 1B illustrates a perspective view of an enlarged portion of the[0045]support structure16 of the present invention.Support structure16 comprises theframe22, thesurface mount pads24, a plurality conductive traces26 and32, a plurality ofvias28, and a plurality of solder bumps30.Vias28 comprise via holes or openings filled withconductive material29 such thatvias28 are electrically conductive from a top surface of the via28 to a bottom surface of the via28.
• FIG. 1B further illustrates a conducting path through the[0046]frame22 for the isolated signal ofchip14.Conductive trace26 on a top surface offrame22 interconnects thesurface mount pad24 to the top surface of via28.Conductive trace32 on a bottom surface offrame22 interconnects the bottom surface of the via28 to thesolder bump30. When thechip stack module10 is assembled, the individually accessed signal ofchip14 conductively connects throughsurface contact20 tosolder bump30. Additionally, when thechip stack module10 is mounted to the printed circuit board, thesolder bump30 conductively connects to the printed circuit board. Thus, the isolated signal ofchip14 conductively connects to the printed circuit board without interconnecting to any other signal onchips12,14. Thesurface contact20 of the corresponding isolated signal ofchip12 conductively connects to thesurface mount pad24 on the bottom surface of theframe22 directly below that of the isolated signal ofchip14. When thechip stack module10 is mounted to the printed circuit board, thesurface contact20 of the corresponding isolated signal ofchip12 conductively connects to the printed circuit board. The short conductive paths of the isolated signals ofchips12,14 minimize propagation delays and timing problems.
• FIG. 1C illustrates a perspective view of an enlarged portion of the[0047]support structure16 of the present invention.Support structure16 comprises theframe22, thesurface mount pads24 comprising a firstsurface mount pad25 and a secondsurface mount pad27, the plurality conductive traces26, a plurality ofconductive traces34, and the plurality ofvias28.Vias28 comprise via holes or openings filled withconductive material29 such thatvias28 are electrically conductive from the top surface of the via28 to the bottom surface of the via28.
• FIG. 1C further illustrates a conducting path through the[0048]frame22 for the common signal ofchips12,14.Conductive trace26 on the top surface offrame22 interconnects the firstsurface mount pad25 to the top surface of the via28.Conductive trace34 on the bottom surface offrame22 interconnects the bottom surface of the via28 to the secondsurface mount pad27 directly below the firstsurface mount pad25 on theframe22.Surface mount pads25,27 are conductively connected. When thechip stack module10 is assembled, the common signal ofchip14 conductively connects throughsurface contact20 to surfacemount pad25, through the via28, to surfacemount pad27. The corresponding common signal ofchip12 conductively connects through thecorresponding surface contact20 to surfacemount pad27. When thechip stack module10 is mounted on the printed circuit board, thesurface contact20 of the corresponding common signal ofchip12 is conductively connected to the printed circuit board. Thus, the common signals ofchips12,14 are conductively connected to each other and the printed circuit board. The short conductive paths of the common signals ofchips12,14 minimize propagation delays and timing problems.
• In one embodiment of[0049]frame22,surface mount pads24 andconductive traces26 are formed on the top surface, andsurface mount pads24 andconductive traces32 and34 are formed on the bottom surface using a film etching process. Via holes or openings are then drilled through theframe22 with the via holes or openings positioned substantially perpendicular to the conductive traces26,32,34. A plating process is then used to formconductive material29 into via cylinders within thevias28, to interconnect the viacylinders29 to theappropriate traces26,32,34, and to interconnect thesurface mount pads24 to theappropriate traces26,34. To provide good electrical conductivity, thetraces26,32,34 and thesurface mount pads24 are plated with approximately 1.4 mil thick conductive material, such as copper or the like, and thevias28 are plated with approximately 1 mil thick conductive material, such as copper or the like.
• In one embodiment of[0050]frame22, solder bumps30 are formed on the bottom surface of theframe22. The solder bumps30 may comprise substantially hemispherical bumps of solder. In other embodiments the solder bumps30 may comprise solder, a conductive adhesive material such as conductive epoxy, and the like, and may be shaped round, approximately spherical, approximately hemispherical, and the like. The solder bumps30 are formed so as to substantially approximate the thickness of thesurface contact20 after thechip stack module10 is mounted to the printed circuit board. This allows thechip stack module10 to be approximately level when mounted to the printed circuit board. Additionally, the solder bumps30 provide conductive material to aid in mechanically connecting thechip stack module10 to the substrate or printed circuit board.
• FIG. 1A illustrates the positioning relationship between the[0051]chips12,14 and thesupport structure16. Referring to FIG. 1A, thesupport structure16 is positioned over thesurface contacts20 along a first edge and a second edge ofchip12. Thesurface mount pads24 along a bottom surface of thesupport structure16 are aligned with thesurface contacts20 along the first edge and the second edge ofchip12.Chip14 is positioned over thesupport structure16, such that thesurface contacts20 along a first edge and a second edge ofchip14 align with thesurface mount pads24 along a top surface of thesupport structure16. Additionally,chip14 is positioned overchip12 such that thepin1indicator18 onchip14 is aligned and directly over thepin1indicator18 onchip12. The assembledchip stack module10 is processed so as to induce conductive material, such as a high temperature solder, to connect to thesurface contacts20 andsurface mount pads24. High temperature solder, such as SN63-PB37 and SN96-AG4, both by AIM Products, and the like, may be used so that thechip stack module10 can be subsequently mounted to the substrate or printed circuit board using a solder with a lower melting point without melting the conductive material connecting thechips12,14 and thesupport structure16 together. Other conductive materials that may be used are silver, copper, and the like.
• FIGS. 2A, 2B, and[0052]2C show a top view, a side view, and a front view, respectively, of thechip stack module10 shown in FIG. 1A. As illustrated in FIG. 2A, thechip stack module10 comprises a length A, a distance H between an end of theframe22 and a longitudinal centerline of afirst surface contact20 of thesecond chip14, a distance I between the longitudinal centerlines of any twoadjacent surface contacts20, and a surface contact width J. In the side view ofchip stack module10, FIG. 2B illustrates the height C.
• In one embodiment, the length A of the[0053]chip stack module10 is such that theframe22 accommodates thesurface mount pads24 corresponding to thesurface contacts20 on each side of thechips12,14. In another embodiment, the frame length A and/or the frame width E may be adjusted to accommodate other sizes and packages of integrated circuits. As illustrated in FIGS. 1A and 2A, thechip stack module10 occupies only slightly more area on the substrate or printed circuit board as would a single one of thechips12,14.
• FIG. 2C illustrates the[0054]chip stack module10 mounted on a substrate or printedcircuit board90. It can be seen that the width B of thechip stack module10 is much less than the width that twochips12,14 would require if placed side by side on the substrate or printed circuit board. Of course, in other embodiments, the width B of the chip stack module may change to accommodate chip stacks of greater than two chips and chips with different packages and pin configurations than thechips12,14 of thechip stack module10 specified herein.
• FIG. 2C further illustrates the structure of the[0055]chip stack module10.Chip14 is stacked on top ofchip12 andsupport structure16 is interposed between thesurface contacts20 of the stackedchips12,14 such that thesurface mount pads24 align with thesurface contacts20. FIG. 2C also illustrates the solder bumps30 andsurface contacts20 on the bottom surface of thesupport structure16. The solder bumps30 are offset from thesurface contacts20 and are used to conduct isolated signals fromchip14 to the printedcircuit board90. Thesurface contacts20 have a thickness which is interposed between thesurface mount pad24 on the bottom surface of thesupport structure16 and the printedcircuit board90. The solder bumps30 also have a thickness or radius, which is also interposed between the bottom surface of thesupport structure16 and the printedcircuit board90. The solder bumps30 are formed so as to substantially approximate the thickness of thesurface contacts20.
• FIG. 2D illustrates a[0056]footprint40 of thechip stack module10. Thefootprint40 comprises a plurality ofsurface mount pads36,38 on the substrate or printedcircuit board90 so as to be able to mechanically and conductively connect thechip stack module10 to the printedcircuit board90.Surface mount pads36,38 corresponds to thesurface mount pads24 and solder bumps30 on the bottom surface of the stackedchip module10, respectively. Thefootprint40 of thechip stack module10 further comprises a distance K between an inside edge of thesurface mount pad36 and the inside edge of the opposingsurface mount pad36, a distance L between an outside edge of thesurface mount pad36 and the outside edge of the opposingsurface mount pad36, and a distance M between a centerline of thesolder bump footprint38 in a first row ofsolder bump footprints38 and the centerline of thesolder bump footprint38 in a second row ofsolder bump footprints38. Thefootprint40 of thechip stack module10 further comprises a distance N between a longitudinal centerline of thesurface mount pad36 to the longitudinal centerline of the adjacentsurface mount pad36.
• In one implementation, when the[0057]chip stack module10 is mounted on the printedcircuit board90,surface contact20 ofchip12 is positioned onsurface mount pad36 offootprint40. Alternately, it may be appreciated that aseparate solder bump30 conductively connected to thesurface contact20 ofchip12 may be positioned onsolder bump footprint38.
• As can be seen from FIGS. 2A, 2C, and[0058]2D, thefootprint40 of thechip stack module10 requires much less area of the printedcircuit board90 than the area that would be required by bothchips12,14 mounted individually and laterally on the printedcircuit board90. Thechip stack module10 allows the chip density to increase without increasing the size of the printedcircuit board90.
• FIG. 2E illustrates an enlarged detail of the[0059]footprint40 of FIG. 2D.Surface mount pads36 comprise a length O and a width P. Thesolder bump footprint38 comprises a diameter Q. Thefootprint40 further comprises a distance R between the outside edge of thesurface mount pad36 and the centerline of thesolder bump footprint38, and a distance S between the longitudinal centerline of thesurface mount pad36 and the centerline of thesolder bump footprint38. The distance R between the outside edge of thesurface mount pad36 and the centerline of thefootprint38 corresponds to the aforementioned offset between the row ofsurface mount pads24 and the row solder bumps30 on theframe22.
• In one embodiment,[0060]chip stack module10 comprises an 81-terminal 4M bit×32 bit memory chip stack module comprising two vertically stackedmemory chips12,14. Thememory chips12,14 are conventional 66-pin surface mount TSOP-II (thin small outline package) DDR SDRAM (double data rate synchronous dynamic random access memory) integrated circuits, available from Micron, Samsung, Elpida, and the like. Eachmemory chip12,14 has a capacity of 4M bits×16 bits×4 banks of memory and comprises a plurality ofsurface contacts20 distributed in two rows of 33 pins in each row, along opposing sides of the chips as is generally well known in the art. In this embodiment, the length A and height F of theframe22, the number ofsurface mount pads24, the spacing of thesurface mount pads24 along theframe22, and the like, is such as to accommodate the standard 66-pin, 400 mil TSOP-II packages of thechips12,14. Spacing and alignment of each row ofsurface mount pads24 on theframe22 corresponds to each row of 33surface contacts20 of thechips12,14.
• Table A shows approximate dimensions A through S as illustrated in FIGS. 1A, 2A,[0061]2B,2C,2D, and2E, for one embodiment whereinchips12,14 are packaged in TSOP-II packages. All dimensions are approximate and are in inches. Dimensional tolerances are +/−0.004 inches.

  	TABLE A
  	A	0.890
  	B	0.568
  	C	0.090
  	D	0.005
  	E	0.064
  	F	0.043
  	G	0.440
  	H	0.030
  	I	0.026
  	J	0.012
  	K	0.379
  	L	0.4910
  	M	0.5310
  	N	0.026
  	O	0.056
  	P	0.016
  	Q	0.020
  	R	0.020
  	S	0.013

• Of course, in other embodiments, the above dimensions may change to accommodate chip stack modules of greater than two chips and chips with different packages and pin configurations than the[0062]chips12,14 of thechip stack module10 specified herein.
• FIGS. 3A, 3B, and[0063]3C illustrate a pin location diagram, a pin configuration table, and a pin function table, respectively, of the memorychip stack module10. As described earlier, the 81-terminal memorychip stack module10 is one embodiment of the present invention and is a 4M×32 bits×4 banks of DDR SDRAM consisting of two 2.5V CMOS 4M×16 bits×4 banks DDR SDRAMs in 66-pin 400-mil TSOP-II packages. In one embodiment, thememory chips12,14 are interconnected such that both 4M bit×16bit memory chips12,14 are selected simultaneously with eachmemory chip12,14 supplying or storing 16 bits of data. Also described earlier, some signals on eachmemory chip12,14 are individually accessed and not interconnected in order for memorychip stack module10 to operate properly. From the pin location diagram shown in FIG. 3A, the signals on pins67-81 connect fromchip14 through solder bumps30 to the substrate or printed circuit board and are electrically isolated from the signals onchip12, aligned and located directly beneath. Referring to FIGS. 3B and 3C, the signals on memorychip stack module10 pins67-81 comprise data in/out signals from the upper 16 bits of the 32-bit word and a data mask signal.
• FIG. 4 is a functional block diagram of the memory[0064]chip stack module10 and illustrates the interconnection ofmemory chips12 and14 within the memorychip stack module10. Pin symbols are shown to the left of FIG. 4. Referring to FIGS. 3C and 4, common signals such as address pins (A0-A12, BA0, BA1), control pins (/RAS, /CAS, /WE, /CS, CKE), clock (CK, /CK), and voltage reference (VREF) ofchips12,14 are connected together while individual signals such as data pins (DQ0-DQ31) and control pins (LDM0-1, UDM0-1, LDQS0-1, UDQS0-1) are not interconnected.
• The aforementioned description is one embodiment of the chip stack module of the present invention. It is possible to stack chips with different packaging than described above. Modifications in the frame dimensions, number of surface mount contacts, number of vias, number of solder bumps, and number of interconnecting traces of the support structures, and the like, can be made to accommodate stacking chips packaged in industry standard surface mount packages such as quadruple flat packs, and the like, custom surface mount packages, and the like.[0065]
• In another embodiment, the stacking method and apparatus described herein are used for stacking chips, such as SRAM and Flash RAM memory chips, and the like, and non-memory chips, such as buffer chips, logic driver chips, and the like.[0066]
• Another embodiment of the present invention comprises stacking chips in stacks of greater than two chips. The vertically stacked chips are held together and conductively connected by support structures. The support structures and chips are layered such that a first support structure is positioned over a first chip. Surface mount pads on a bottom surface of the first support structure are over and align with the surface contacts of the first chip. A second chip is positioned over the first support structure such that the surface contacts of the second chip are over and align with surface mount contacts on a top surface of the first support structure. A second support structure is positioned over the second chip. The surface mount pads on the bottom surface of the second support structure are over and align with the surface contacts of the second chip. A third chip is positioned over the second support structure such that the surface contacts of the third chip are aligned and over the surface mount pads on the top surface of the second support structure. It will be appreciated that in additional embodiments, additional layers of support structures and chips could be formed to extend the height of and the number of chips in the[0067]chip stack module10 in the manner previously described.
• FIG. 5A illustrates the structure of a[0068]chip stack module50 comprising greater than two vertically stacked chips, according to one embodiment of the present invention. FIG. 5A shows a front view of thechip stack module50 comprising vertically stackedchips51,52,53,54 andsupport structures55,56,57.Stacked chips51,52,53,54 comprisesurface contacts20 distributed along a first and a second edge of eachchip51,52,53,54 as is well known in the art. Thesupport structures55,56,57 in this embodiment comprises theframe22. Frame members across sides ofchips51,52,53,54 withoutsurface contacts20 are not shown in FIG. 5A in order to illustrate the stacking ofchips51,52,53,54.Support structures55,56,57 comprise a row ofsurface mount pads24 disposed linearly along a top surface and a row ofsurface mount pads24 disposed linearly along a bottom surface of eachsupport structure55,56,57. In another embodiment,support structures55,56,57 can be frames, pairs of rails, or the like.Support structure55 is interposed betweenstacked chips51,52;support structure56 is interposed betweenstacked chips52,53; andsupport structure57 is interposed betweenstacked chips53,54. Thesupport structures55,56,57 are interposed betweenstacked chips51,52,53,54 such that thesurface mount pads24 on the bottom surfaces ofsupport structures55,56,57 are over and align with thesurface contacts20 ofchips51,52,53, respectively. In a similar manner, thesurface mount pads24 of the top surfaces ofsupport structures55,56,57 are under and align with thesurface contacts20 ofchips52,53,54, respectively. The assembledchip stack module50 is processed so as to induce conductive material, such as the aforementioned high temperature solder, to connect to thesurface contacts20 andsurface mount pads24 so that thechip stack module50 can be subsequently mounted to the substrate or printed circuit board using a solder with a lower melting point without melting the conductive material connecting thechips51,52,53,54 and thesupport structures55,56,57 together. Other conductive materials that may be used are silver, copper, and the like.
• A further embodiment of the present invention comprises a widened frame to accommodate additional vias and solder bumps to conductively isolate signals from greater than two stacked chips. In one aforementioned embodiment, vias[0069]28, filled withconductive material29, disposed vertically through thesupport structure22 and solder bumps30 on the bottom surface of thesupport structure22 conduct signals from theupper chip14 of the two chip stack to the printed circuit board without conductively connecting the signal to any other signals from theupper chip14 orlower chip12 in the twochip stack module10. In an embodiment comprising greater than two stacked chips, signals from the additional chips are conducted byadditional vias28 and solder bumps30 through the stackedsupport structures16 to the printedcircuit board90 without conductively connecting the signal to any other signals in the chip stack module. The additional solder bumps30 are offset from thesurface mount pads24 and each other on thesupport structures16. The width E of thesupport structure16 may be increased to accommodate as many solder bumps30 and vias28 as are required to conduct signals from the chip stack module to thesubstrate90 without electrically connecting to any other signals.
• FIG. 5B shows an enlarged detail of the[0070]chip stack module50 of FIG. 5A illustrating the connection path of isolated signals, according to aspects of an embodiment of the invention.Chip stack module50 is shown mounted to printedcircuit board90 comprisingsurface mount pads36 andsolder bump footprints38.Support structure57 further comprises afirst solder bump60, asecond solder bump61, and athird solder bump62 ofsupport structure57, conductive traces26,32, and via67. Similarly,support structure56 further comprises thefirst solder bump60, thesecond solder bump61, and thethird solder bump62 ofsupport structure56, conductive traces26,32, and vias68,70.Support structure56 further comprises a solder bumpsurface mount pad81. Likewise,support structure55 further comprises thefirst solder bump60, thesecond solder bump61, and thethird solder bump62 ofsupport structure55, conductive traces26,32, and vias69,71,72.Support structure55 further comprises a solder bumpsurface mount pad82,83.Chips51,52,53,54 each further comprise a first isolated signal on a firstisolated surface contact66,65,64,63, respectively. Vias67-72 comprise a via opening filled withconductive material29 such that the vias67-72 are electrically conductive from a top surface of vias67-72 to a bottom surface of vias67-72, respectively.
• FIG. 5B shows a side view of[0071]chip stack module50. Thetraces26 located on top surfaces of thesupport structures55,56,57 and thetraces32 located on bottom surfaces of thesupport structures55,56,57 are not shown. Thetraces26,32 and the solderbump surface contact81 are further discussed with reference to FIG. 5C
• Referring to FIG. 5B, the[0072]isolated surface contact63 ofchip54 conductively connects to thesurface mount pad24 on the top surface ofsupport structure57.Conductive trace26 conductively connects thesurface mount pad24 on the top surface ofsupport structure57 to the top surface of via67 andconductive trace32 conductively connects the bottom surface of via67 to thefirst solder bump60 ofsupport structure57. Thefirst solder bump60 ofsupport structure57 conductively connects to the solder bumpsurface mount pad81 on the top surface ofsupport structure56.Conductive trace26 conductively connects the solder bumpsurface mount pad81 on the top surface ofsupport structure56 to the top surface of via68.Conductive trace32 conductively connects the bottom surface of via68 to thefirst solder bump60 ofsupport structure56. Thefirst solder bump60 ofsupport structure56 conductively connects to a solder bumpsurface mount pad82 on the top surface ofsupport structure55.Conductive trace26 conductively connects the solder bumpsurface mount pad82 on the top surface ofsupport structure55 to the top surface of via69.Conductive trace32 conductively connects the bottom surface of via69 to thefirst solder bump60 ofsupport structure55. Thefirst solder bump60 ofsupport structure55 conductively connects to the correspondingsolder bump footprint38 of the printedcircuit board90. Thus, the first isolated signal ofchip54 conductively connects to the printedcircuit board90 throughtraces26,32, vias67,68,69, first solder bumps60 ofsupport structures55,56,57 and corresponding solder bumpsurface mount pads81,82 ofsupport structures56,55, respectively, without interconnecting to any other signal onchips51,52,53,54.
• In a similar manner, the first isolated signal of[0073]chip53 on the firstisolated surface contact64 conductively connects to thesolder bump footprint38 on printedcircuit board90 throughtraces26,32, vias70,71, second solder bumps ofsupport structures55,56, and the corresponding solder bumpsurface mount pad83 ofsupport structure55.
• Likewise, the first isolated signal of[0074]chip52 on the firstisolated surface contact65 conductively connects to thesolder bump footprint38 on printedcircuit board90 throughtraces26,32, via72, and the third solder bump ofsupport structure55. The first isolated signal ofchip51 on the firstisolated surface contact66 conductively connects directly to thesurface mount pad36 on the printedcircuit board90.
• In one embodiment, the width E of the[0075]frame22 increases to accommodate the additional solder bumps60,61, solder bump surface mount contacts81-83, and vias67-71. In another embodiment, the additional solder bumps60,61, solder bump surface mount contacts81-83, and vias67-71 may be located along theframe22 in such a manner as not to increase width E of theframe22.
• FIG. 5C illustrates a detail, perspective view of a portion of the preformed[0076]support structures56,57 of FIG. 5B, according to aspects of an embodiment of the invention.Support structure56 comprisessurface mount pads24, traces26, vias68,70, solder bumpsurface mount pad81, traces32, and thefirst solder bump60, thesecond solder bump61, and thethird solder bump62 ofsupport structure56. As shown in FIG. 5B, theisolated surface contact63 ofchip54 conductively connects from thesurface mount pad24 on the top surface ofsupport structure57 throughconductive trace26 to the top surface of via67. Referring to FIG. 5C,conductive trace32 connects thefirst solder bump60 ofsupport structure57 to the bottom surface of via67. Thefirst solder bump60 ofsupport structure57 conductively connects with the solder bumpsurface mount pad81 on the top surface ofsupport structure56.Conductive trace26 on the top surface ofsupport structure56 conductively connects solder bumpsurface mount pad81 to a top surface of via68.Conductive trace32 on the bottom surface ofsupport structure56 conductively connects a bottom surface of via68 to thefirst solder bump60 on thesupport structure56.
• To complete the conductive path to the printed[0077]circuit board90, refer to FIG. 2B. Thefirst solder bump60 on thesupport structure56 conductively connects through the solder bumpsurface mount pad82 on the top surface ofsupport structure55, throughtrace26 on the top surface ofsupport structure55, via69,trace32 on the bottom surface ofsupport structure55 to thefirst solder bump60 ofsupport structure55. Thefirst solder bump60 ofsupport structure55 conductively connects to the printedcircuit board90 throughsolder bump footprint38.
• Solder bumps[0078]60,61,62 and solder bumpsurface mount pads80 are positioned onsupport structures55,56,57 such that the solder bumps60,61,62 on the bottom surface ofsupport structures55,56,57 are over and align with solder bumpsurface mount pads80 on top surfaces of thesupport structure55,56, or57 which is located below and adjacent. More specifically, in one embodiment, thefirst solder bump60 ofsupport structure57 is over and aligns withsolder bump footprint81. Thefirst solder bump60 ofsupport structure56 is over and aligns withsolder bump footprint82 and thesecond solder bump61 ofsupport structure57 is over and aligns withsolder bump footprint83.
• FIG. 5C further illustrates the conduction path of the first isolated signal of[0079]chip53 on the firstisolated surface contact64 through thesupport structure56. The first isolated signal ofchip53 on the firstisolated surface contact64 conductively connects to thesurface mount pad24 on the top surface ofsupport structure56, shown in FIG. 5B. Referring to FIG. 5C,conductive trace26 on the top surface ofsupport structure56 conductively connects thesurface mount pad24 to the top surface of via70.Conductive trace32 on the bottom surface ofsupport structure56 conductively connects the bottom surface of via70 to thesecond solder bump61 ofsupport structure56.
• As illustrated in FIGS. 5B and 5C, the solder bump surface mount pads[0080]81-83 and the solder bumps60-62 are offset from vias67-72. The solder bump surface mounts pads81-83 conductively connect to the top surfaces of vias67-72 throughtraces26 and the solder bumps60-62 conductively connect to the bottom surfaces of vias67-72 throughtraces32. However, in another embodiment, it is to be appreciated that a conductive pad may be located on the via to avoidconductive traces26,32 in some circumstances.
• FIG. 5D shows a bottom surface view of a portion of the[0081]chip stack module50 of FIG. 5A further illustrating the connection path of isolated signals, according to aspects of an embodiment of the invention. The bottom ofchip stack module50 comprisessurface contacts20 fromchip51 andsupport structure55.Support structure55 comprises theframe22,surface mount pads24, vias28, conductive traces32,34, thefirst solder bump60, thesecond solder bump61, and thethird solder bump62. Referring to FIG. 5D, thesurface contacts20 are conductively connected to thesurface mount pads24. Conductive traces28 conductively connectvias28 to thesurface mount pads24 for interconnected signals common tochips51,52,53,54. Conductive traces32 conductively connectvias28 to the solder bumps60,61,62 for the individually accessed signal ofchips52,53,54.
• FIG. 5E is shows a detail of a footprint of the[0082]chip stack module50 of FIG. 5A, according to aspects of an embodiment of the invention. The footprint comprisessurface mount pads36 corresponding to thesurface mount pads24 andsurface mount pads38 corresponding to the solder bumps60,61,62 of thechip stack module50. FIG. 5E illustrates the aforementioned offset between thesurface mount pads36 and a first row ofsurface mount pads38. FIG. 5E further illustrates the spacing between rows ofsurface mount pads38 according to aspects of an embodiment of the invention.
• FIG. 6A illustrates a front view of a[0083]chip stack tower100 comprising thechip stack module50 mounted onto asubstrate110, according to aspects of an embodiment of the invention. The chip interconnections, signal paths, and footprint ofchip stack module50 are described in detail in FIGS.5A-5E. Thesubstrate110 can be utilized to connect thechip stack module50 to the printedcircuit board90. Thesubstrate110 is an intermediate printed circuit board and has a footprint. The intermediate printedcircuit board110 may mount to the printedcircuit board90 using a ball grid array on to a plurality ofsurface contacts112, as illustrated in FIG. 6A. In another embodiment, theintermediate circuit board110 may mount to the printedcircuit board90 using surface mount pads, surface mount contacts, pins, and the like. Thechip stack tower100 allows the area occupied by theframe22 in thechip stack module50 to be utilized for running traces or the like, on the printedcircuit board90. The height of thechip stack tower100, however, is greater than the height of thechip stack module50 by the thickness of the intermediate printedcircuit board110.
• FIG. 6B is a is a detail, perspective view of a portion of the ball grid array printed[0084]circuit board110 of FIG. 6A and the preformedsupport structure55 mounted thereon, according to aspects of an embodiment of the invention. The printedcircuit board110 comprises a plurality of surface mount pads114, a plurality oftraces116, a plurality ofvias118, a plurality ofsolder mount pads120, and a plurality ofsolder balls122. The surface mount pads114 receive thechip contact20 and thesolder mount pads120 receive the solder bumps60,61,62 of thesupport structure55. Thetraces116 and vias118 are utilized in routing the signals through the printedcircuit board110 to a bottom surface of the printedcircuit board110. Thesolder balls122 on the bottom surface of the printedcircuit board110 mount and conductively connect thechip stack tower100 to the printedcircuit board90. The signal routing through the printedcircuit board110 and utilization of the surface mount pads114, traces116, vias118, andsurface mount pads120 is very similar to the signal routing through thechip stack module50, which is described in detail in connection with FIG. 5C and would be obvious to one skilled in the art.
• While certain embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.[0085]

Claims (33)

What is claimed is:

1. A chip stack assembly comprising:

a substrate that defines a plurality of surface mount pads;

a first chip having a first set of contacts extending outward;

a second chip having a second set of contacts extending outward therefrom;

at least one support member positioned on the substrate having a first surface with a first set of mounting pads positioned thereon and a second surface having a second set of mounting pads positioned thereon wherein the first and second surfaces are displaced from each other by a first distance in a first direction and wherein the first set of contacts are attached to the first set of mounting pads and the second set of contacts are attached to the second set of mounting pads such that the first and second chips are supported so as to be displaced from each other in the first direction,

and wherein the at least one support member further includes at least one interconnect that interconnects at least one contact of the first and second set of contacts so as to electrically interconnect the at least one contact of first and second set of contacts and wherein the at least one support member further includes at least one via connection that extends in the first direction through the at least one support member to the substrate so that at least one individual contact of the first set of contacts can be electrically coupled to the surface mount pad of the substrate while being electrically isolated from the second set of contacts.

2. The assembly ofclaim 1, wherein the first and second surfaces of the at least one support member are substantially parallel to each other.

3. The assembly ofclaim 1, wherein the at least one support member comprises a plurality of support members.

4. The assembly ofclaim 1, wherein the at least one support member comprises a printed circuit board.

5. The assembly ofclaim 1, wherein the at least one via connection comprises:

a conductive trace positioned on the first surface that is electrically coupled to the mounting pad that is coupled to the individual contact of the first set of contacts;

a conductive element extending through a via opening formed between the first and second surfaces of the at least one support member so as to be electrically connected to the conductive trace;

a solder bump formed on the second surface of the at least one support member adjacent the via opening so as to be electrically connected to the conductive element, and wherein the solder bump is positioned so as to be electrically coupled to the surface mount pad of the substrate.

6. The assembly ofclaim 1, wherein the at least one interconnect that interconnects at least one contact of the first and second set of contacts comprises a via interconnection that extends through the at least one support structure.

7. The assembly ofclaim 1 further comprising:

a third chip having a third set of contacts extending outward therefrom;

a second support member positioned on the at least one support member, the second support member having a third surface with a third set of mounting pads positioned thereon and a fourth surface having a fourth set of mounting pads positioned thereon wherein the third and fourth surfaces are displaced from each other by the first distance in the first direction and wherein the first set of contacts are attached to the third set of mounting pads and the third set of contacts are attached to the fourth set of mounting pads such that the first and third chips are supported so as to be displaced from each other in the first direction,

and wherein the second support member further includes at least one interconnect that interconnects at least one contact of the first and third set of contacts so as to electrically interconnect the at least one contact of first, second, and third set of contacts,

and wherein the at least one support member further includes a second via connection that extends in the first direction through the at least one support member to the substrate and wherein the second support member further includes at least one via connection that extends in the first direction through the second support member, to the second via of the at least one support structure to the substrate so that at least one individual contact of the third set of contacts can be electrically coupled to the surface mount pad of the substrate while being electrically isolated from the first and second set of contacts.

8. The assembly ofclaim 7 wherein the at least one via connection and the second via connection are displaced from each other by a second distance in a second direction and whereby the second direction is substantially perpendicular to the first direction.

9. A method of mounting a plurality of chips into a stacked configuration, the method comprising:

attaching a first set of contacts of a first chip to a first set of mounting pads formed on a first surface of a support structure;

attaching a second set of contacts of a second chip to a second set of mounting pads formed on a second surface of the support structure, wherein attaching the first and second sets of contacts to the support structure results in the first and second chips being positioned in a stacked orientation with respect to each other;

electrically interconnecting at least one selected contact of first and second sets of contacts using the support structure;

electrically connecting the at least one contact of the first and second set of contacts to a mounting pad on a substrate such that the electrically interconnected at least one contact receives a conmmon signal;

forming an isolated pathway from at least one other of the first set of contacts to a mounting pad on the substrate; and

electrically connecting at least one other contact from the first set of contacts to a mounting pad formed on the substrate using the isolated pathway so that the at least one other contact is electrically isolated from the second set of contacts such that the at least one other contact receives an individual signal.

10. The method ofclaim 9, wherein attaching the first set of contacts and attaching the second set of contacts comprises attaching the first set of contacts to an upper surface of the support structure and attaching the second set of contacts to a lower surface of the support structure so that the contacts are separated by the thickness of the support structure.

11. The method ofclaim 10, wherein electrically interconnecting the at least one selected contact of the first and second sets of contacts using the support structure comprises:

forming a via that extends between the first and second surface of the support structure;

electrically interconnecting the at least one selected contacts of the first and second set of contacts using the via.

12. The method ofclaim 10, wherein forming an isolated pathway comprises:

forming a via that extends through the support structure;

positioning a conductor within the via; and

connecting the conductor within the via to the at least one other contact from the first set of contacts and to the mounting pad on the substrate.

13. The method ofclaim 10 further comprising:

attaching a third set of contacts of a third chip to a third set of mounting pads formed on a third surface of a second support structure;

attaching the first set of contacts of the first chip to a fourth set of mounting pads formed on a fourth surface of the second support structure, wherein attaching the first and third sets of contacts to the second support structure results in the first, second, and third chips being positioned in a stacked orientation with respect to each other;

electrically interconnecting at least one selected contact of first and third sets of contacts using the second support structure;

electrically interconnecting at least one selected contact of the second set of contacts and the at least one selected contact of the first set of contacts;

electrically connecting the at least one selected contact of the first, second and third sets of contacts to a mounting pad on a substrate such that the electrically interconnected at least one selected contact receives a common signal;

forming an isolated pathway from at least one other of the third set of contacts to a mounting pad on the substrate; and

electrically connecting at least one other contact from the third set of contacts to a mounting pad formed on the substrate using the isolated pathway so that the at least one other contact is electrically isolated from the first and second sets of contacts such that the at least one other contact from the third set of contacts receives an individual signal.

14. A chip stack for mounting on a substrate having a plurality of contact pads comprising at least a first and a second chip and a conducting interconnecting means for interconnecting the chips and maintaining the chips in a stacked configuration so that the chips are interconnected with at least one contact on the first and second chips being electrically interconnected and wherein the interconnecting means interconnects the at least one of the contacts of the first chip to a contact pad on the substrate in a manner that isolates the contact of the first chip from the contacts of the second chip.

15. The chip stack ofclaim 14, wherein the interconnecting means comprises a support structure having a first and a second side wherein the first side is positioned proximate the substrate to permit electrical connection between the support structure and the substrate and wherein the second side is substantially parallel to the first side.

16. The chip stack ofclaim 15, wherein the support structure includes a plurality of vias extending between the first and second side wherein at least one via extends between the first and second side to permit electrical connection of the at least one contact of the first chip to the contact pad on the substrate in a manner that isolates the contact of the first chip from the contacts of the second chip.

17. The chip stack ofclaim 16, wherein the at least one of the vias extends to permit electrical interconnection between the at least one contacts on the first and second chip.

18. A chip stack of at least one preformed support structure interconnecting a first chip to a second chip wherein the support structure comprises:

a member having a first surface and a second surface;

a plurality of surface mount pads disposed along the first surface and the second surface of the member;

a plurality of vias disposed between the first surface and the second surface of the member; and

a plurality of conducting elements wherein the conducting elements interconnect the surface mount pads and the vias.

19. The member ofclaim 18 wherein the first and second surfaces are substantially parallel to each other.

20. The chip stack ofclaim 18 wherein the at least one preformed support structure comprises a plurality of support structures.

21. The chip stack ofclaim 18 wherein the first chip and the second chip comprise memory chips.

22. The chip stack ofclaim 18 wherein the member is a printed circuit board.

23. A chip stack module comprising:

a first chip comprising a first set of common contacts and a first set of individual contacts;

a second chip comprising a second set of common contacts and a second set of individual contacts; and

an interconnecting structure wherein the interconnecting structure further includes at least one interconnect and at least one via connection whereby the interconnecting structure interconnects the first and second chips wherein the first set of common contacts is electrically connected to the second set of common contacts and the first set of individual contacts and does not electrically connect to the second set of individual contacts, the first set of common contacts, and the second set of common contacts.

24. The chip stack module ofclaim 23 wherein the first and second chips are memory chips.

25. The chip stack module ofclaim 23 wherein the first and second chips are functionally identical.

26. The chip stack module ofclaim 23 wherein the first set of individual contacts and the second set of common contacts of the second chip are conductively connected to a printed circuit board.

27. The chip stack module ofclaim 23 wherein the interconnecting structure is a printed circuit board.

28. The chip stack module ofclaim 23, wherein interconnecting structure provides a support surface so as to maintain the first and second chips in a stacked configuration and wherein the support surface defines a first and second surface with the contacts of the first chip being connected to the first surface and the contacts of the second chip being connected to the second surface.

29. The chip stack module ofclaim 28, wherein the interconnecting structure comprises a plurality of vias that extend from the first surface to the second surface wherein a first set of vias interconnect common contacts and a second set of vias provide for isolated electrical connection of the first set of individual contacts to a structure located adjacent the second side of the interconnecting structure.

30. A chip stack comprising:

a first chip having a generally planar formed top surface and first set of contacts formed in a first pattern comprising a first set of signals and a second set of signals;

a second chip having the generally planar formed top surface and a second set of contacts formed in the first pattern comprising a third set of signals and a fourth set of signals;

a support structure having a first side and a second side comprising:

a first set of surface mount pads on the first side;

a second set of surface mount pads on the second side;

a plurality of conducting elements;

a plurality of vias positioned through the support structure from the first side to the second side and spaced from the conducting elements;

whereby the conducting elements electrically interconnect the first and third sets of contacts, and the vias electrically conduct the fourth set of contacts without interconnecting the fourth set of contacts to the first, second and third sets of contacts, when the support structure is positioned between stacked first and second chips.

31. The chip stack ofclaim 30 further comprising a second support structure and a third chip.

32. The first chip and the second chip ofclaim 30 further comprising memory chips.

33. The chip stack ofclaim 30 wherein the first set of surface mount pads are conductively connected to a plurality of surface mount pads of a printed wiring board.

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