US20030008484A1 - Angled implant process - Google Patents

Abstract

Different symmetrical and asymmetrical devices are formed on the same chip using non-critical block masks and angled implants. A barrier is selectively formed adjacent one side of a structure and this barrier blocks dopant implanted at an angle toward the structure. Other structures have no barrier or have two barriers. Source and drain engineering can be performed for LDD, halo, and other desired implants.

Description

FIELD OF THE INVENTION
• This invention relates to angled ion implants. More particularly, it relates to a method of producing a symmetrical and an asymmetrical semiconductor device using angled ion implantation.[0001]
BACKGROUND OF THE INVENTION
• Semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), produced with angled ion implantation techniques are often constructed symmetrically. This allows great flexibility in the layout of multiple devices as the source and drain are interchangeable (and both sides of the gate are consequently referred to simply as the “source/drain”).[0002]
• For some applications, this type of device symmetry is highly desirable or essential. Devices produced by angled ion implantation are generally made symmetric by rotating the semiconductor device to allow the angled implant beam to implant from all sides of the gate. This results in a series of symmetrical implants and a symmetrical device.[0003]
• High voltage devices have required a graded lightly doped drain (LDD) implant while low voltage devices favor an abrupt implant, such as an extension type implant, as is well known in the art. Low voltage devices also often have a halo or a more heavily doped halo than high voltage devices. Such high and low voltage devices are frequently fabricated on the same chip. They generally have different gate dielectric thicknesses, channel lengths, and use separate masking steps and implants for the source/drain design.[0004]
• For other applications, performance can be improved if the semiconductor device is constructed asymmetrically. For example, for MOSFETs having an LDD region and a halo region, the LDD is desirable exclusively on the drain side and the halo is desirable exclusively on the source side of the gate.[0005]
• The addition of an LDD region degrades device performance because it increases series resistance and overlap capacitance. Since the lightly doped LDD region is strictly required only on the drain side of the device to mitigate hot carrier degradation, the LDD on the source side of a symmetrical device adds series resistance and capacitance with no additional benefit. Device performance can be improved if the LDD implant could be blocked from the source side thereby making an asymmetrical device. Furthermore, where a particular device is never subjected to high voltages, blocking the LDD implant from both sides may also be advantageous.[0006]
• However, a very accurately-aligned critical mask capable of blocking the implant beam from the source side, but not blocking it from the drain side, has been needed to provide the desired asymmetrical device. To block the implant on one side, but not on the other side of the gate requires aligning the critical mask to within the width of the gate. This has required alignment tolerance within one half the width of the gate. Obtaining such critical alignment is an expensive and error-prone procedure.[0007]
• Alternatively, the LDD implant may be produced through a single ion implant beam which places the implant under one side of the gate. Thus, the desired LDD is formed when the appropriate ion implant beam is directed at an angle towards the drain side of the gate. To produce many asymmetrical devices on the same semiconductor substrate requires that all of the devices be oriented in the same direction so that a single ion implant step can produce all of the LDD regions desired on the same side of the gate while avoiding implant on the opposite side.[0008]
• It can be seen that controlled device asymmetry is possible if all the devices are oriented in the same direction and the opposite direction rotation is omitted. However, orienting all of the devices in the same direction significantly limits layout flexibility.[0009]
• The same problem is encountered when constructing a halo implant only on the source side of the device. If the halo implant is placed on the drain side, it increases junction capacitance and peak electric field. Achieving halo implants only on the source side has heretofore required the same choice between an expensive critical mask with alignment comparable to half the gate width or an angle implant with uniform device orientation such that all of the devices have the source on the same side.[0010]
• Therefore, an improved process to provide implants is needed and this solution is provided by the following invention.[0011]
SUMMARY OF THE INVENTION
• It is therefore an object of the present invention to selectively provide different implants on different devices or on different sides of the same device on a semiconductor wafer.[0012]
• It is a further object of the present invention to form both symmetrical and asymmetrical semiconductor devices on a semiconductor wafer.[0013]
• It is a feature of the present invention to use a single non-critical mask to selectively form barriers adjacent semiconductor devices or adjacent one side of certain devices to shadow ion implant beams.[0014]
• It is an advantage of the present invention that the location of ion implant can be controlled without adding critical masks or reducing layout flexibility.[0015]
• It is an advantage of the present invention to provide asymmetrical devices without added critical masks or reducing layout flexibility.[0016]
• These and other objects, features, and advantages of the invention are accomplished by a method for selectively blocking angled ion implants on a semiconductor substrate. The method includes providing a semiconductor substrate having a surface. A first structure and a second structure are formed on the surface of the substrate. A first barrier is selectively formed adjacent a first side of the first structure. A dopant is implanted at an angle, however the barrier shadows the dopant from a portion of the first structure and no barrier shadows dopant from a corresponding portion of the second structure.[0017]
• The present invention also includes symmetrical and asymmetrical semiconductor devices on the same wafer. Most typically, this will include a field effect transistor, having an LDD on the drain side of the gate, but not on the source side of the gate, or having a halo on the source side of the gate, but not on the drain side of the gate, or both; or a second set of devices having no halo implant in the source/drain, or a set of devices having no LDD implant in the source/drain.[0018]
• Although the present invention may find application in various types of ion implanted semiconductor devices, the invention will be described here in connection with its application in MOSFET technology in which the structures on the semiconductor surface are the gates of MOSFETs.[0019]
BRIEF DESCRIPTION OF THE DRAWINGS
• The foregoing and other objects, features, and advantages of the invention will be apparent from the following detailed description of the invention, as illustrated in the accompanying drawings, in which:[0020]
• FIGS. 1[0021]a-1care top views of semiconductor devices being implanted in accordance with the present invention.
• FIGS. 2[0022]a-2care cross-sectional views of the semiconductor devices taken along the line2-2 shown in FIGS. 1a-1c.
• FIGS. 3[0023]a,3care cross-sectional views of the semiconductor devices of FIGS. 1a,1cand2a,2cafter implant is complete.
• FIGS. 3[0024]b,3d, and3eare cross-sectional views of other semiconductor devices that can be made with the barrier and angle implant of the present invention after the implant is complete.
• FIGS. 4[0025]a-4care cross-sectional views of semiconductor devices made with a vertical LDD implant and an angled halo implant.
DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
• The present inventors recognized that providing a barrier next to some devices but not others allowed both symmetrical and asymmetrical devices to be formed at the same time without critical masks and without changing the way a chip is laid out. They also recognized that providing barriers on both sides of some devices allowed four kinds of symmetrical devices to be formed at the same time.[0026]
• Commonly assigned U.S. Pat. No. 6,083,794 by Hook et al., teaches a barrier on one side of a gate to block angle implant from that side, while implant angled toward the other side reaches the other side of the gate, thereby forming an asymmetrical semiconductor device. The present invention extends this idea to provide different devices on a single chip without the need for any more critical masks.[0027]
• [0028]Semiconductor surface10 has structures, such asgates12a,12b,12coffield effect transistors13a,13b,13chaving sides14 and16 as shown in FIGS. 1a-1cand2a2c. Additional transistors (not shown) will usually be positioned in an array aroundtransistors13a,13b,13c. In most implementations, the additional transistors will be laid out in four mirror image orthogonal orientations. Two or more oftransistors13a,13b,13ccan be formed onsurface10 of the same chip using the same non-critical mask and the same angled implant, as further described herein below. They are shown in separate figures for clarity but they can all be on the same surface.
• Four separate 90° rotations provide angled ion implant beams[0029]24,26,30 and32 as shown in FIGS. 1a-1c. Generally,semiconductor surface10 will be rotated 90° between each implant.Implants30,32 arriving from directions parallel tosides14 and16 ofgates12a,12b,12cadd negligibly to the source/drain doping but will not penetrate belowcorner22 andcorner28, and will not create LDD or halo structures.Implants30,32 may be used, however, to form LDD or halo structures on other devices on thesame semiconductor surface10 having an orientation at 90° or 270° to the devices shown in FIGS. 1a-c.
• Three devices are compared in FIGS. 1[0030]a-cand in FIGS. 2a-c.Symmetrical device13areceiving allimplants24,26,30,32 on bothsides14,16 is shown in FIGS. 1a,2a.Barrier18, of an ion absorbing material, such as photoresist, having height h is positioned distance d away fromside14 ofgate12bas shown in FIG. 2bto provideasymmetrical device13bhavingion implant26 onside16 but noion implant24 onside14.Barrier19 having height h is positioned distance d away fromside16 as shown in FIG. 2cto provide anothersymmetrical device13cwhereimplants24,26 are all blocked from bothsides14,16. The effects of ion implantation insemiconductor surface10 and the resulting semiconductor devices produced by the present invention are shown in corresponding FIGS. 3a,3c. FIGS. 3b,3d, and3eshow other semiconductor devices that can similarly be formed using the process of the present invention or two such processes. The semiconductor devices all include source/drain regions54,56 or drainregion36,source region38, and shallow trench isolation (STI)regions40 and42 surrounding the device.
• Without any barrier, when ion implant beams[0031]24 and26 are directed tosides14 and16, respectively, the desired ion implants will occur under rightlower corner22 and leftlower corner28 ofgate12aofFET13aas shown in FIG. 2a. These desired ion implants produceLDD regions44 and60 in the source/drain regions54,56 ofgate12aof FIG. 3a. Ion implant beams30 and32 have no effect since they are not oriented in a proper direction to implant underneath eithercorner22 orcorner28.
• [0032]Halo regions46 and58 are similarly implanted with angle implant beams on both source/drain sides ofgate12awith no barrier present as shown in FIG. 3a.
• The halo implant is required only on the shorter channel-length devices and it may be safely omitted on long-channel devices. This is desirable as the device drain resistance may be improved by eliminating the halo implant. By using the barriers and angle implants of the present invention short symmetrical devices with halo implant may be simultaneously created with long symmetrical devices without halo implant.[0033]
• For many short-channel devices threshold voltage is determined primarily by the halo implant. Thus, by using the barriers and angle implants of the present invention, short symmetrical devices with different threshold voltages may be simultaneously created.[0034]
• [0035]Barrier18 of height h shown in FIG. 2bcasts a shadow fromupper corner20 coveringlower corner22 ofside14 ofgate12bofFET13b, whenion implant beam24 is directed atside14 at anangle01 measured relative tosemiconductor surface10. The maximum distance, d, thatbarrier18 may be placed away fromside14 ofgate12band still protectlower corner22 fromion implant beam24 is illustrated by FIG. 2b. Ifbarrier18 is placed any farther to the right, i.e. beyond maximum distance d,ion implant beam24 will not be fully blocked. Generally,barrier18 may be placed at any point betweenside14 ofgate12band maximum distance d.Barrier18 may also extend on the upper surface ofgate12bbetweenside14 andside16.Barrier18 cannot be placed to the left ofside16 because in this position the barrier would block desiredion implant beam26 directed towardside16 for providing desired ion implant under leftlower corner28 ofgate12b. Thus, ifgate12bhas a length L,barrier18 has an acceptable range of positions equal to L+d.
• If an additional implant at angle +must be provided with[0036]barrier18 in place to provide a dose alongedge14 thenbarrier18 must be spaced fromgate12bto allow for that other implant. The mask edge must then be located between h/tan φ and h/tan θ1.
• [0037]Barrier18 will normally be placed somewhere nearmid point34 of this range of positions, as shown in FIG. 2b. The alignment error inpositioning barrier18 atmid point34 may be as large as one half the sum of L plus d. The maximum distance d is given by the relationship of h divided by the tangent of angle θ1. By selecting angle θ1 and height h, the tolerance error for positioning the mask may be adjusted. The shallower the angle θ1 and the higher the height h ofbarrier18, the greater the maximum distance d and the greater the tolerance of the position error in placingbarrier18.
• Desired[0038]ion implant beam26 producesLDD region44 indrain region36 ofgate12bshown in FIG. 3b. There is no corresponding LDD region underneathcorner22 becausebarrier18 blockedion implant beam24. Ion implant beams30 and32 were not oriented in the proper direction to implant underneath eithercorner22 orcorner28.Barrier18 will block only one of the four beams, ie.ion implant beam24, so it can remain onsemiconductor surface10 during all four rotations of the implant process. If desired,LDD region44 could be formed only underside14, opposite to that shown in FIG. 3b, by constructingbarrier18 on the left side, i.e. on the drain side so that the shadow ofbarrier18 would shieldcorner28 ofgate12bfromion implant beam26, but would not shieldcorner22 ofgate12bfromion implant beam24.
• A[0039]halo region46 found only on the source side and not on the drain side is also shown in FIG. 3b. This makes the device doubly asymmetric.Halo region46 is formed by constructing a barrier on the left side, i.e. on the drain side so that the shadow of the barrier would shieldcorner28 ofgate12bfrom haloion implant beam26, but would not shieldcorner22 from haloion implant beam24.
• If desired,[0040]halo region46 could also be formed on the drain side by constructing a barrier, or by using the same barrier that was used to formLDD region44, on the source side so that the shadow of the barrier would shieldcorner22 from haloion implant beam24, but would not shieldcorner28 from haloion implant beam26. In this way, bothLDD region44 andhalo region46 are on the drain side ofgate12b. Likewise, bothLDD region44 andhalo region46 can be formed on the source side ofgate12bby constructing a barrier on the drain side ofgate12b. In addition, ifLDD region44 is formed on the source side ofgate12b,halo region46 could be formed on the drain side ofgate12bby constructing a barrier on the source side ofgate12b.
• To form the doubly asymmetrical device described above where[0041]halo region46 isopposite LDD region44, two masking steps are needed to separately provide a barrier on one side of the gate for the LDD implant and then a barrier on the other side for the halo implant.
• To provide a second symmetrical device, both[0042]sides14 and16 ofgate12care shadowed at the same time as shown in FIG. 2c. Similar to FIG. 2b, afirst barrier18 of height h casts a shadow from itsupper corner20 which coverslower corner22 onside14 whenion implant beam24 is directed atside14 and has angle θ1 measured relative tosemiconductor surface10. In addition,barrier19 of height h casts a shadow from itsupper corner21 which coverslower corner28 onside16 whenion implant beam26 is directed atside16 and has angle θ2 measured relative tosemiconductor surface10. Typically, the angles θ1 and θ2 of the ion implant beams are the same.
• The same criteria described herein above for distance and height with respect to one barrier, also apply for two barriers. Generally,[0043]barriers18,19 are placed at any point betweensides14 and16 ofgate12cand maximum distance d. Either one or both of the barriers may be placed extending onto the upper surface ofgate12cat any point betweenside14 andside16. In the case of one of the barriers placed on the upper surface ofgate12c, the barrier may extend beyond a side ofgate12c. For example, whenbarrier18 is formed at distance d away fromside14 as shown in FIG. 2c,barrier19 can be formed extending onto the upper surface ofgate12cand beyondside14. Likewise, whenbarrier19 is formed at distance d away fromside16, thenbarrier18 can be formed extending onto the upper surface ofgate12cand beyondside16. This allows for an even greater tolerance of the position error in placing the barriers. However, if a second implant is needed adjacent a side of the gate withbarrier18 or19 in place, then overlap with the gate is not permitted.
• Source/[0044]drain regions54,56 ofgate12cshown in FIG. 3care formed with vertical implants and have no LDD regions or halo regions underneath eithercorner22 orcorner28 due to the presence ofbarrier18 andbarrier19 blocking LDD and halo ion implant beams. Ion implant beams30 and32 are not oriented in the proper direction to implant underneath eithercorner22 orcorner28. Becausebarrier18 would block only one of the four beams (ion implant beam24) andbarrier19 would block another of the four beams (ion implant beam26), both barriers can remain on the semiconductor surface during all four rotations of the implant process.
• Thus, two symmetrical devices can be formed on a chip with one process. The first has LDD and halo, and the second has neither. Other symmetrical and asymmetrical devices with LDD and halo can be formed as well, as shown in FIGS. 3[0045]dand3e. A symmetrical device with no LDD and halo on both sides is formed on the same chip as one or more of the other devices, as shown in FIG. 3d. An asymmetrical device with LDD on the drain side and halo on both sides can also be formed, as shown in FIG. 3e.
• The present invention is not limited to LDD and halo implants. Various dopant doses and implant energies can be used with[0046]barrier18 andbarrier19 for providing source and drain engineering. Separate angle implants and barriers can be provided for each. Various symmetrical and asymmetrical devices can be formed on the chip by providing barriers on one side, both sides or no sides of particular devices.
• Semiconductor devices having source/drain regions that include[0047]symmetrical LDD regions44 and60 can also be formed using spacers with vertical ion implant (not shown), as well known in the art. The halo can still be provided with angle implant. A vertical ion implant for the LDD is directed at an angle of about 90° with respect tosemiconductor surface10. Thus, the present invention can combine vertical implants and angled implants to provide different source and drain engineering structures.
• Source/[0048]drain regions54,56 ofgate12ashown in FIG. 4ainclude LDD implants from standard vertical implants before spacers50,52 are applied. Source/drain regions54,56 also includehalo regions46 and58 formed by the method of the present invention as described with reference to FIGS. 1aand2a.Halo regions46 and58 are formed underneath bothcorner22 andcorner28 ofgate12ain FIG. 4aby having no barriers present to block ion implant beams24 and26. Thus, a symmetrical semiconductor device is formed with LDD and halo on both sides.
• [0049]Source region38 ofgate12bshown in FIG. 4bincludes ahalo region46 formed underneathcorner22. A barrier is formed ondrain side36 to blockion implant beam26 so a halo region is prevented from forming indrain region36. No barrier is formed on the source side soion implant beam24 is able to implant underneathcorner22. The method to formhalo region46 insource region38 is identical to that shown for the formation ofLDD region44 with reference to FIGS. 1band2b, exceptbarrier18 is onside16 ofgate12b. Likewise,halo region46 could be formed underneathcorner28 in FIG. 4bby constructing a barrier on the source side ofgate12b(as shown in FIGS. 1band2b) so that the shadow of the barrier would shieldcorner22 fromion implant beam24, but would not shieldcorner28 fromion implant beam26. In either case an asymmetrical semiconductor device is formed.
• Source/[0050]drain regions54,56 of FIG. 4cshow an absence of halo regions. As described with reference to FIGS. 1cand2c,barrier18 andbarrier19 are formed to block ion implant beams24 and26, respectively. In this way a symmetrical semiconductor device is formed without halos while other devices on the chip are formed without barriers and receive halo implants.
• For all of the above cases the total halo or LDD dose may be modulated by providing a portion of the dose at an angle near 90°.[0051]Barrier18 will not shadow this implant. The remainder of the dose is provided at an angle at whichbarrier18 is effective to shadow the implant. Thus, devices with greater or lesser doses of halo or LDD may be provided simultaneously with one masking step and two or more implant steps.
• A combination of any two or more of the various types of semiconductor devices shown in FIGS. 3[0052]a-eor FIGS. 4a-ccan be formed by the method of the present invention. That is, a non-critical masking step to provide a barrier adjacent a device is used to selectively control the location of implants into the various types of semiconductor devices being formed. The symmetrical semiconductor devices shown in FIGS. 3a,3c, and3dand the asymmetrical semiconductor devices shown in FIGS. 3band3ecan be formed on the same chip semiconductor surface by the method of the present invention.
• For other semiconductor devices at other orientations on the same surface, the barrier (or barriers) will simply be positioned relative to the other devices to shield the necessary side (or sides). Of course, all of these barriers will be laid down with a non-critical mask. For symmetrical devices with implants, no barrier will be laid down; for asymmetrical devices, one barrier will be laid down; and for devices where no implant is desired, two barriers will be laid down to shadow both sides of the gate.[0053]
• Typically, the construction of multiple semiconductor devices includes numerous masking steps. The construction of[0054]photoresist barriers18 and19 may often be incorporated into one of these non-critical masking steps without requiring additional process steps to implement this invention. Either photoresist or hard mask can be used to form the barriers.
• The invention is particularly well suited to making multiple symmetrical and asymmetrical devices on a single substrate at different orthogonal orientations using one or two non-critical masking steps to selectively control the location of an ion implant. The use of one non-critical masking step with angle implants allows for at least three different devices (2 symmetrical, 1 asymmetrical) to be formed, whereas the use of two non-critical masking steps with angle implants allows for at least nine different devices (4 symmetrical, 5 asymmetrical) to be formed. Thus, the present invention offers a greater flexibility in providing symmetrical and asymmetrical devices on a single substrate without requiring critical masks or restrictions in device layout.[0055]
• While the present invention has been particularly described, in conjunction with a specific preferred embodiment, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art in light of the foregoing description. It is therefore contemplated that the appended claims will embrace any such alternatives, modifications and variations as falling within the true scope and spirit of the present invention.[0056]

Claims (20)

Thus, having described the invention, what is claimed is:

1. A method of fabricating a semiconductor device, comprising the steps of

a) providing a semiconductor substrate comprising a surface;

b) forming a first structure and a second structure on said surface;

c) selectively providing a first barrier adjacent a first side of said first structure; and

d) implanting a dopant at an angle wherein said barrier shadows implanted dopant from a portion of said first structure wherein no barrier shadows implanted dopant from a corresponding portion of said second structure.

2. The method as recited inclaim 1, further comprising the step of selectively providing a second barrier adjacent a second side of said first structure, wherein in said implanting a dopant at an angle step (d) said second barrier shadows implanted dopant from said second side of said first structure.

3. The method as recited inclaim 2, wherein no barrier shadows implanted dopant from a corresponding portion of said second structure.

4. The method as recited inclaim 2, further comprising a barrier shadowing implanted dopant from a second side of said second structure.

5. The method as recited inclaim 2, wherein in said implanting step (d) said first structure is symmetric and said second structure is symmetric, wherein said first structure comprises an implant shadowed on two sides and said second structure receives said implant on two sides.

6. The method as recited inclaim 1, wherein said implanting step (d) is for providing a halo implant, an extension implant, or an LDD implant.

7. The method as recited inclaim 1, wherein said implanting step (d) comprises implanting at a first angle and then implanting at a second angle different from said first angle.

8. The method as recited inclaim 7, wherein said first angle is approximately vertical to provide a portion of the implant to all devices and said second angle is sufficient so a portion is blocked by said first barrier.

9. The method as recited inclaim 1, wherein in said implanting step (d) said first structure comprises a thicker dielectric or a longer channel or is used with a different applied voltage than said second structure.

10. The method as recited inclaim 1, wherein said first structure that has said dopant blocked has a different threshold voltage than said second structure receiving said dopant.

11. The method as recited inclaim 1, wherein said first structure comprises an FET.

12. The method as recited inclaim 1, wherein providing step (c) comprises providing said barrier of ion absorbing photoresist.

13. The method as recited inclaim 12, wherein providing step (c) comprises exposing said photoresist with a non-critical block mask.

14. The method as recited inclaim 1, further comprising the steps of:

e) removing the first barrier;

f) forming a new barrier adjacent a second side of said first structure; and

g) implanting a dopant at an angle wherein said new barrier shadows implanted dopant from a portion of said first structure.

15. The method as recited inclaim 14, wherein no barrier shadows implanted dopant from a corresponding portion of said second structure.

16. The method as recited inclaim 14, further comprising the step of selectively providing a barrier adjacent a second side of said second structure, wherein in said implanting a dopant at an angle step (g) said barrier shadows implanted dopant from said second side of said second structure.

17. The method as recited inclaim 14, wherein said implanting step (d) is for providing an LDD implant, and said implanting step (g) is for providing a halo implant.

18. The method as recited inclaim 14, wherein said implanting step (g) comprises implanting at a first angle and then implanting at a second angle different from said first angle.

19. The method as recited inclaim 18, wherein said first angle is approximately vertical to provide a portion of the implant to all devices and said second angle is sufficient so a portion is blocked by said first barrier.

20. The method as recited inclaim 14, wherein in said implanting step (g) said first structure comprises a thicker dielectric or a longer channel or is used with a different applied voltage than said second structure.

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