US20020181509A1 - Time and frequency synchronization in multi-input, multi-output (MIMO) systems - Google Patents

Abstract

In a communication system, and in particular a wireless Orthogonal Frequency Division Multiplexing (OFDM) communication system, the present invention provides systems for synchronizing data transmitted across a channel. The present invention may be used in a Multi-Input, Multi-Output (MIMO) system in which the data is transmitted from any number of transmitting antennas and received by any number of receiving antennas. The number of transmitting and receiving antennas does not necessarily have to be the same. Circuitry is provided for synchronizing the data in both the time domain and frequency domain. Time synchronization involves coarse time synchronization and fine time synchronization. Frequency synchronization involves coarse frequency offset estimation, fine frequency offset estimation, and frequency offset correction.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
• This application claims priority to copending U.S. provisional application entitled, “Synchronization for MIMO OFDM Systems,” having serial No. 60/286,180, filed Apr. 24, 2001, which is entirely incorporated herein by reference.[0001]
• This application is related to copending U.S. provisional application entitled “Parameter Estimation for MIMO OFDM Systems,” having serial No. 60/286,130, filed on Apr. 24, 2001, which is entirely incorporated herein by reference.[0002]
TECHNICAL FIELD OF THE INVENTION
• The present invention is generally related to wireless communication systems that employ Orthogonal Frequency Division Multiplexing (OFDM) and, more particularly, to an apparatus and method for providing time and frequency synchronization in a Multi-Input, Multi-Output (MIMO) OFDM system.[0003]
BACKGROUND OF THE INVENTION
• In wireless communication systems, recent developments have been made using technologies wherein multiple signals are simultaneously transmitted over a single transmission path. In Frequency Division Multiplexing (FDM), the frequency spectrum is divided into sub-channels. Information (e.g. voice, video, audio, text, etc.) is modulated and transmitted over these sub-channels at different sub-carrier frequencies.[0004]
• In Orthogonal Frequency Division Multiplexing (OFDM) schemes, the sub-carrier frequencies are spaced apart by precise frequency differences. Because of the ability of OFDM systems to overcome the multiple path effects of the channel, and to transmit and receive large amounts of information, much research has been performed to advance this technology. By using multiple transmitting antennas and multiple receiving antennas in OFDM systems, it is possible to increase the capacity of transmitted and received data while generally using the same amount of bandwidth as in a system with one transmit and one receive antenna.[0005]
• OFDM technologies are typically divided into two categories. The first category is the Single-Input, Single-Output (SISO) scheme, which utilizes a single transmitting antenna to transmit radio frequency (RF) signals and a single receiving antenna to receive the RF signals. The second category is the Multi-Input, Multi-Output (MIMO) scheme, which uses multiple transmitting antennas and multiple receiving antennas.[0006]
• In typical communication systems, training symbols, or preamble, at the beginning of data frames, are usually added as a prefix to the data symbols. The data symbols, of course, include the useful data or information (e.g., voice, data, video, etc.), which is meant to be transmitted to a remote location. The training symbols in SISO systems are used to provide synchronization of the received signals with respect to the transmitted signals, as well as to provide channel parameter estimation.[0007]
• Although training symbols used for SISO systems can be used to provide synchronization in a MIMO system, the training symbols cannot provide for channel parameter estimation in the MIMO system. In fact, no method or apparatus exists for MIMO systems that are capable of providing time and frequency synchronization as well as channel parameter estimation. Thus, a need exists for a method and apparatus that is capable of providing time and frequency synchronization in MIMO systems and can further perform channel estimation.[0008]
SUMMARY OF THE INVENTION
• The present invention provides systems and methods that overcome the deficiencies of the prior art as mentioned above. The present invention utilizes a sequence of training symbols or preambles that may be used in both Single-Input, Single-Output (SISO) and Multi-Input, Multi-Output (MIMO) systems, using any number of transmitting and receiving antennas. Also, the present invention can be used to synchronize a received data frame with a transmitted data frame in a MIMO system in both the time domain and frequency domains. In order to make MIMO systems operational, synchronization is essential. However, no scheme has been developed which is capable of time and frequency synchronization in MIMO systems. The present invention achieves synchronization in the time domain and frequency domain and, therefore, enables MIMO systems to operate acceptably.[0009]
• One MIMO Orthogonal Frequency Division Multiplexing (OFDM) system of the present invention includes a number of OFDM modulators, which provide data frames to be transmitted across a channel. The data frames of the present invention comprise one or more training symbols, a plurality of data symbols, and cyclic prefixes inserted between the data symbols. A number of transmitting antennas corresponding to the number of modulators is used to transmit the modulated signals over the channel. A number of receiving antennas is used to receive the transmitted signals. The received signals are demodulated by a number of OFDM demodulators corresponding to the number of receiving antennas and decoded by an OFDM decoder, which processes the data frames. By utilizing the structure embedded in the training symbols, the MIMO system of the present invention is capable of providing time and frequency synchronization as well as perform channel estimation.[0010]
• A method of the present invention is also provided, wherein synchronization is carried out in the time and frequency domains in a MIMO system. The method includes producing data frames comprising at least one training symbol, multiple data symbols and cyclic prefixes. The data frames are transmitted over the channel, received, and demodulated and processed. By processing the training symbol of the data frame, the data frame can be synchronized in both the time and frequency domains.[0011]
• Other systems, methods, features, and advantages of the present invention will become apparent to a person having skill in the art upon examination of the following drawings and detailed description. All such additional systems, methods, features, and advantages are within the scope of the present invention.[0012]
BRIEF DESCRIPTION OF THE DRAWINGS
• Many aspects of the invention can be better understood with reference to the following drawings. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.[0013]
• FIG. 1 is a block diagram illustrating an example embodiment of a Multi-Input, Multi-Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) system.[0014]
• FIG. 2 is a block diagram illustrating an example embodiment of the MIMO encoder shown in FIG. 1.[0015]
• FIG. 3 is a block diagram illustrating an example embodiment of one of the OFDM modulators shown in FIG. 1.[0016]
• FIG. 4 illustrates an example frame structure for a MIMO OFDM system.[0017]
• FIG. 5 is a block diagram illustrating an example matrix of a transmitted sequence structure and an example matrix of a received sequence structure using the modulator/demodulator arrangement shown in FIG. 1.[0018]
• FIG. 6 illustrates a three-dimensional representation of the received sequence structure in detail.[0019]
• FIG. 7 is a block diagram illustrating an example embodiment of one of the OFDM demodulators shown in FIG. 1.[0020]
• FIG. 8 is a block diagram illustrating an example embodiment of the synchronization circuit shown in FIG. 7.[0021]
• FIGS. 9A and 9B are block diagrams illustrating example embodiments of the coarse time synchronization circuit shown in FIG. 8.[0022]
• FIG. 10 is a block diagram illustrating an example embodiment of the first frequency offset estimation circuit shown in FIG. 8.[0023]
• FIG. 11 is a block diagram illustrating an example embodiment of the fine time synchronization circuit shown in FIG. 8.[0024]
• FIG. 12 is a block diagram illustrating an example embodiment of the second frequency offset estimation circuit shown in FIG. 8.[0025]
• FIG. 13 is a block diagram illustrating an example embodiment of the decoder shown in FIG. 1.[0026]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
• In FIG. 1, an example embodiment of a Multi-Input, Multi-Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM)[0027]communication system6 of the present invention is shown. Thecommunication system6 in this example embodiment may be implemented as a wireless system for the transmission and reception of data across awireless channel19. Thecommunication system6, for example, may be part of a wireless Local Area Network (LAN) system or wireless Metropolitan Area Network (MAN) system, cellular telephone system, or other type of radio or microwave frequency system incorporating either one-way or two-way communication over a range of distances. Thecommunication system6 may transmit in a range from 2 to 11 GHz, for example, such as in the unlicensed 5.8 GHz band using a bandwidth of about 3-6 MHz.
• It is also possible for the present invention to be used in a system that comprises an array of sub-channel communication links that carry a number of signals transmitted by a number of transmitting elements to each of a number of receiving elements. In this latter case, communication links, such as wires in a wiring harness or some alternative wired transmission system, for example, could be used over the distance between a data source and a receiver.[0028]
• In the example embodiment of FIG. 1, a[0029]transmitter8 transmits signals across thewireless channel19 and areceiver10 receives the transmitted signals. Thetransmitter8 comprises adata source12, which provides the original binary data to be transmitted from thetransmitter8. Thedata source12 may provide any type of data, such as, for example, voice, video, audio, text, etc. Thedata source12 applies the data to anencoder14, which encodes the data to allow for error correction. Theencoder14 further processes the data so that certain criterion for space-time processing and OFDM are satisfied. Theencoder14 separates the data onto multiple paths in thetransmitter8, each of which will hereinafter be referred to as a transmit diversity branch (TDB). The separate TDBs are input intoOFDM modulators16, each of which modulates the signal on the respective TDB for transmission by the transmittingantennas18. The present invention may be used in a Single-Input, Single-Output (SISO) system, which may be considered as a special case of MIMO wherein the number of transmitting and receiving antennas is one. In the SISO system example, separation of the data by theencoder14 is not necessary since only oneOFDM modulator16 andantenna18 is used.
• During the encoding by the[0030]encoder14 and modulating by theOFDM modulators16, data is normally bundled into groups such that the collection of each group of data is referred to as a “frame.” Details of the frame as used in the present invention will be described in more detail below with reference to FIG. 4. Each frame along each TDB is output from arespective OFDM modulator16. As illustrated in FIG. 1, any number ofOFDM modulators16 may be used. The number ofOFDM modulators16 andrespective transmitting antennas18 may be represented by a variable “Q.” The OFDM modulators16 modulate the respective frames at specific sub-carrier frequencies andrespective transmitting antennas18 transmit the modulated frames over thechannel19.
• On the side of the[0031]receiver10, a number “L” of receivingantennas20 receives the transmitted signals, which are demodulated by a number L ofrespective OFDM demodulators22. The number L may represent any number and is not necessarily the same as the number Q. In other words, the number Q of transmittingantennas18 may be different from the number L of receivingantennas20, or they may alternatively be the same. The outputs of thedemodulators22 are input into adecoder24, which combines and decodes the demodulated signals. Thedecoder24 outputs the original data, which may be received by a device (not shown) that uses the data.
• The[0032]communication system6 may comprise one or more processors, configured as hardware devices for executing software, particularly software stored in computer-readable memory. The processor can be any custom made or commercially available processor, a central processing unit (CPU), an auxiliary processor among several processors associated with a computer, a semiconductor based microprocessor (in the form of a microchip or chip set), a macroprocessor, or generally any device for executing software instructions. Examples of suitable commercially available microprocessors are as follows: a PA-RISC series microprocessor from Hewlett-Packard Company, an 80x86 or Pentium series microprocessor from Intel Corporation, a PowerPC microprocessor from IBM, a Sparc microprocessor from Sun Microsystems, Inc, a 68xxx series microprocessor from Motorola Corporation, or a 67xxx series Digital Signal Processor from the Texas Instruments Corporation.
• When the[0033]communication system6 is implemented in software, it should be noted that thecommunication system6 can be stored on any computer-readable medium for use by or in connection with any computer-related system or method. In the context of this document, a computer-readable medium is an electronic, magnetic, optical, or other physical device or means that can contain or store a computer program for use by or in connection with a computer related system or method. Thecommunication system6 can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. In the context of this document, a “computer-readable medium” can be any means that can store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. Examples of the computer-readable medium include the following: an electrical connection having one or more wires, a portable computer diskette, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM, EEPROM, or Flash memory), an optical fiber, and a portable compact disc read-only memory (CDROM). Note that the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
• In an alternative embodiment, where the[0034]communication system6 is implemented in hardware, the communication system can be implemented with any or a combination of the following technologies, which are each well known in the art: one or more discrete logic circuits having logic gates for implementing logic functions upon data signals, an application specific integrated circuit (ASIC) having an appropriate combination of logic gates, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.
• The[0035]encoder14 andOFDM modulators16 of thetransmitter8 will now be described with respect to FIGS. 2 and 3. FIG. 2 shows details of an example embodiment of theencoder14 shown in FIG. 1. Theencoder14 may be configured such that data from thedata source12 is encoded by achannel encoder26, which adds parity to the original data to produce channel encoded data. Thechannel encoder26 encodes the data using a scheme that is recognized by thedecoder24 of thereceiver10 and enables thedecoder24 to detect errors in the received data. Errors may arise as a result of environmental conditions of thechannel19 or noise inadvertently added by thetransmitter8 orreceiver10.
• The[0036]encoder14 further includes asymbol mapper28, which maps the channel-encoded data into data symbols. Thesymbol mapper28 groups a predetermined number of bits such that each group of bits constitutes a specific symbol chosen from a pre-determined alphabet. Thesymbol mapper28 further lays out a stream of data symbols within the structure of a frame.
• The[0037]encoder14 further includes a space-time processor30 that processes the data symbol stream received from thesymbol mapper28 and outputs the processed data symbols via the respective TDBs. The space-time processor30 encodes the data symbol stream in a manner such that thereceiver10 is capable of decoding the signals. The data symbols in the TDBs are distributed over Q lines that will eventually be transmitted at precise frequencies spaced apart from each other by a predetermined difference in frequency. By providing a specific frequency difference between the multiple sub-channels, orthogonality can be maintained, thereby preventing the OFDM demodulators22 from picking up frequencies other than their own designated frequency.
• Each TDB provides an input to a[0038]respective adder34. The other input into each of theadders34 is connected to the output of a pilot/training symbol inserter32, which provides pilot symbols and training symbols to be inserted into the frames on the TDBs. Symbols inserted periodically within the data symbols will be referred to herein as “pilot symbols.” These periodic pilot symbols may be inserted anywhere in the stream of the data symbols. If a continuous burst of symbols is inserted by the pilot/training symbol inserter32, this type of symbol will be referred to herein as “training symbols” which constitute the preamble. The training symbols preferably are inserted at the beginning of the frame. However, the training symbols may be inserted onto the frame in a location other than at the beginning of the frame, such as at the end or in the middle of the frame.
• The pilot/[0039]training symbol inserter32 may be configured so that it is capable of storing multiple sets of training symbols or pilot symbols. In this case, a particular set may be selected, for example, based on desirable communication criteria established by a user. The training symbols for each respective sub-channel may preferably be unique to the particular sub-channel. In order to accommodate amplitude differences between the sub-channels, the training symbols may be designed and adjusted to maintain a constant amplitude at the output of each sub-channel.
• Training symbols are preferably transmitted once for every frame. Training symbols are used for periodic calibration (synchronization and channel parameter estimation) whereas pilot symbols are used for minor adjustments to deal with the time-varying nature of the channel. The training symbols may be indicative of calibration values or known data values. These calibration values or known values may be transmitted across the channel, and used to calibrate the[0040]communication system6. Any necessary refinements may be made to thecommunication system6 if the received calibration values do not meet desirable specifications.
• Furthermore, the training symbols may be used as specific types of calibration values for calibrating particular channel parameters. By initially estimating these channel parameters, offsets in the time domain and frequency domain may be accounted for so as to calibrate the[0041]communication system6. The training sequence may or may not bypass an Inverse Discrete Fourier Transform (IDFT)stage38, which is a part of the embodiment of theOFDM modulator16 of FIG. 3. A training sequence that bypasses theIDFT stage38 and is directly input into a digital to analog converter (DAC)44 is referred to herein as a directly modulatable training sequence. Examples of such training sequences may be “chirp-like” sequences. These sequences cover each portion of the bandwidth used by thecommunication system6. Hence, channel response can be easily determined. In general, a chirp sequence in the time domain is given by the equation:
• S_n=cos(πn/N²)+jsin( πn²/N),n=0,1, . . . , N−1,
• where j is given by {square root}{square root over (−1)} and is used to denote the quadrature component of the signal. It should be noted that the term s[0042]_nrefers to a time domain signal on the side of thetransmitter8. Frequency domain signals on the transmitter side will hereinafter be referenced by capital letters S_k. Time and frequency domain signals on the receiver side will hereinafter be written as r_nand R_k, respectively. Other modifications of the chirp-like sequence may be Frank-Zadoff sequences, Chu sequences, Milewski sequences, Suehiro polyphase sequences, and sequences given by Ng et al. By observing the response of thereceiver10 to the chirp signals, the channel parameters maybe estimated.
• In the case when the[0043]IDFT stage38 is not bypassed, a training sequence may be generated by modulating each of the symbols on the TDBs with a known sequence of symbols in the frequency domain and passing the symbols through theIDFT stage38. Generally, such a known sequence of symbols is obtained from an alphabet which has its constituents on the unit circle in the complex domain and such that the resultant sequence in the time domain has a suitable Peak to Average Power Ratio (PAPR). An alphabet in communication systems is defined as a finite set of complex values that each of the symbols can assume. For example, an alphabet of a binary phase shift keying (BPSK) system consists of values +1 and −1 only. An alphabet for a quaternary phase shift keying (QPSK) system consists of thevalues 1+j, −1+j, 1−j, and −1−j. For example, the training sequence may be generated by modulating each of the tones of the OFDM block using a BPSK alphabet, which consists of symbols +1 and −1. The synchronization scheme may be very general such that any known sequence having suitable properties, such as low PAPR, may be used to form the training sequence.
• With reference again to FIG. 2, the[0044]adders34 add the training symbols and pilot symbols to the frame. Other embodiments may be used in place of theadders34 for combining the training symbols and pilot symbols with the data symbols in the frame. Furthermore, theadders34 may include additional inputs to allow for flexibility when adding the pilot/training symbols or in the combining of multiple training symbols or even selectable training symbols. After the training symbols are inserted into frames on the respective TDBs, the frames are output from theencoder14 and input inrespective OFDM modulators16.
• FIG. 3 shows an example embodiment of an[0045]OFDM modulator16, which receives signals along one of the TDBs. The number ofOFDM modulators16 is preferably equal to the number of transmittingantennas18. In SISO systems, there is only oneOFDM modulator16 and one transmittingantenna18. In MIMO systems, there may be any number ofOFDM modulators16 and transmittingantennas18.
• The respective signal from the[0046]encoder14 is input into a serial-to-parallel converter36 of theOFDM modulator16. The serial-to-parallel converter36 takes N symbols received in a serial format and converts them into a parallel format. The variable N will be referred to herein as the blocksize of the OFDM symbol. The N parallel symbols are processed by an Inverse Discrete Fourier Transform (IDFT)stage38, which transforms the frequency signals to the time domain. The N number of transformed symbols in the time domain will be referred to herein as samples.
• A method is proposed herein to design the training symbols such that the transforms of all the sequences from the[0047]IDFT stage38 will have a constant magnitude. By maintaining a constant magnitude at the output of each of the IDFT stages38 within their respective modulators, one of the main problems of OFDM, i.e., peak to average power ratio (PAPR), is solved. Thereceiver10 can thus more accurately estimate the channel parameters, which are used by thereceiver10 to synchronize the received signals in the time and frequency domains, as will be described below in more detail.
• The output from the[0048]IDFT stage38 is input into acyclic prefix inserter40, which inserts an additional number of samples for every N samples. The number of samples inserted by thecyclic prefix inserter40 will be referred to herein by the variable “G.” The G samples are intended to be inserted as guard intervals to separate the N adjacent data symbols from each other in time by a separation adequate to substantially eliminate Inter Symbol Interference (ISI). Thecyclic prefix inserter40 repeats G samples from a latter portion of the N samples output from theIDFT stage38 and inserts the G samples as a prefix to each of the data samples. Preferably, the time length of the cyclic prefix is greater than the maximum time delay of a transmitted signal across thechannel19. Since the nature of thechannel19 may be susceptible to a variation in the delay time from the transmittedantennas18 to the receivingantennas20, it may be desirable to increase, or even double, the length of cyclic prefixes of the preamble to ensure that the time delay of the channel does not exceed the time of the cyclic prefix, thereby eliminating ISI.
• The G+N samples, herein referred to as an OFDM symbol, are then converted from a parallel format to a serial format using parallel-to-[0049]serial converter42, and then inputted to a digital-to-analog converter (DAC)44 for conversion into analog signals. The output from theDAC44 is input into amixer48. Alocal oscillator46 provides a signal having the carrier frequency to the other input of themixer48 to up-convert the respective OFDM symbol from baseband to RF.
• After the respective frame has been mixed with a carrier frequency that is set by the respective[0050]local oscillator46, the frame is amplified by anamplifier50. As indicated above, one of the drawbacks to any OFDM signal is that it generally has a high PAPR. To accommodate this drawback, theamplifier50 may be backed off to prevent it from going into its non-linear region. However, the present invention may provide certain specific sequences that can be used in order to make the PAPR minimal or unity.
• Each[0051]OFDM modulator16 preferably comprises the same components as theOFDM modulator16 shown in FIG. 3. Other techniques for designing theOFDM modulators16 may be used in order to transmit the multiple frames across thechannel19 with minimal interference. Each frame output from therespective OFDM modulator16 is transmitted by arespective antenna18. Theantennas18 may be spaced apart from each other by any desirable separation. For example, the separation distance may be in a range from a few millimeters to several meters.
• FIG. 4 illustrates an example of a[0052]frame52 that is transmitted across thechannel19 from the transmittingantennas18 to the receivingantennas20. Theframe52 comprises apreamble54 comprising a number of training symbols N_Iand cyclic prefixes G. Thepreamble54 is inserted by the pilot/training symbol inserter32 as mentioned above. In addition, thedata frame52 comprises adata portion56 consisting of a plurality of OFDM data symbols N and cyclic prefixes G, which are inserted before each of the OFDM data symbols N. As previously mentioned, the pilot/training symbol inserter32 further inserts pilot symbols (not shown) intermittently within the OFDM data symbols N. The task of thepreamble54 and training symbols N_Iin the frame is to help thereceiver10 identify the arrival of theframe52 and hence perform time synchronization, frequency synchronization, and channel parameter estimation.
• The[0053]preamble54, in general, consists of Q or more training symbols, wherein each training symbol has a length of G+N_Isamples in time. The number of samples N_Iis established as a certain fraction of the number of data samples N in an OFDM block such that N_I=N/I, where I is an integer, such as 1, 2, 4 . . . . For example, N_Imay be {fraction (1/4)} N. If no predetermined N_Ihas been established, the variable N_Imay be given the value equal to N. The training symbol length may be shorter than the length of the symbols in thedata portion56, which has a length of G+N samples.
• FIG. 5 shows a portion of the MIMO[0054]OFDM communication system6 of FIG. 1 along with details of a signal transmission matrix S and a received demodulated OFDM sample matrix R. The signals of thecommunication system6 can be expressed using the equation:
• R_k,T×L=S_k,T×Qη_k,Q×L+W_k,T×L
• where R is a T×L received demodulated OFDM sample matrix, η is a Q×L matrix of channel coefficients that are indicative of the characteristics of the channel across which the signals are transmitted, S is a T×Q signal transmission matrix, and W is a T×L noise matrix that corrupts and distorts the received sample matrix R. In general, T may or may not be equal to Q and does not affect the synchronization procedure. Hence, for simplicity, the assumption is made herein that T is equal to Q.[0055]
• The signal transmission matrix S shown in FIG. 5 consists of Q OFDM symbols that are simultaneously transmitted from Q transmit[0056]antennas18 over Q or more OFDM symbol periods (T_s). For example, at a first time instance t, the OFDM symbols S₁, S₂, . . . S_Qare transmitted from the first to theQth antennas 18. At a second time instance t+T_S, the OFDM symbols S_Q+1, S_Q+2, . . . S_2Qare transmitted from thesame antennas18. The OFDM symbol transmissions are repeated at each time instance until all of the OFDM symbols of the matrix S have been transmitted.
• During the transmission of training symbols in an initial calibration mode, the S matrix consists of Q or more training symbols, each of which is less than or equal to the length of an OFDM symbol in the time dimension. The training symbols are simultaneously transmitted from the transmitting[0057]antennas18 as represented by equations (1) and (2), wherein the different antennas correspond to the space dimension.
• During the transmission of the data symbols, after the[0058]communication system6 has been calibrated, the S matrix consists of Q or more data symbols each occupying an OFDM symbol in the time dimension. The pilot/training symbol inserter32 inserts the pilot symbols within the data symbols. The data symbols are encoded, modulated, and transmitted from the transmittingantennas18.
• Each signal transmission matrix S of Q×Q OFDM symbols are transmitted over the[0059]communication channel19, which naturally comprises a matrix of channel coefficients η. Typically, thecommunication channel19 includes characteristics that distort and degrade the transmitted signal. In addition to the distortion and degradation of the transmitted signal, the communication system adds noise terms represented by the matrix W, before the signal transmission matrix S is received at the L receiveantennas20. The addition of noise further degrades the system performance.
• FIG. 5 further illustrates how each of the[0060]L receiving antennas20 receives each of the Q transmitted signals. For example, the first receiveantenna20 receives OFDM signals over channel impulse responses h₁₁, h₂₁, h₁₃. . . h_Q1from the first to theQth transmitting antennas18, respectively. The term h_1,Jrefers to the channel impulse response from the i^thtransmit to the j^threceive antenna in the time domain. The last receiveantenna20 receives the transmitted signals over the channel impulse responses h_1L, h_2L, h_3L, . . . h_QLfrom the first to theQth transmitting antennas18, respectively. For simplicity, only the signals received at the first andlast receiving antennas20 are shown. However, it should be understood that each receivingantenna20 receives the signals transmitted from theQ transmitting antennas18.
• The received signals are demodulated by the[0061]respective OFDM demodulators22, which provide the received demodulated OFDM sample matrix R. At a time instance t, the samples R₁, R_Q+1, . . . R_L−1)Q+1are received. At a next time instance t+Ts, the samples R₂, R_{Q+2 . .}. R_(L−1)Q+2are received. The samples are received at each time instance until all of the samples in the received demodulated OFDM sample matrix R are received. It should be noted that the time instances used for the matrices S and R are given the same variable, but, in essence, a delay occurs as is well known in the art.
• A significant task of the[0062]receiver10 is to estimate the time of arrival of the transmitted signal. This process is called “time synchronization.” In addition to time synchronization, OFDM systems typically require frequency synchronization as well. Because there usually exists a certain difference between the local oscillator frequencies of the transmitter and the receiver, the received signals experience a loss of sub-carrier orthogonality, which should typically be corrected in order to avoid degradation in system performance.
• FIG. 6 shows a detailed illustration of the received demodulated OFDM sample matrix R which consists of L columns and Q or more rows of OFDM symbols with respect to space and time, respectively. As shown, the matrix R consists of three dimensions, namely space, time and frequency. The frequency axis indicates the amplitude of the frequency component received at each receiving[0063]antenna20 from each transmittingantenna18. Each of the matrices R and η can be seen to consist of N matrices of dimension Q×L or Q×L vectors of length N.
• In general, the training symbol length may be equal to the data symbol length. However, it is not necessary for the length of the training symbol in the preamble to be (N+G) since it is possible to estimate the characteristics of the channel even if the training symbol length is shortened to N[0064]_I+G such that (N_I+G)<(N+G). The variable N_Imay be set so as to establish a range of frequencies that may be estimated. For example, if N_I=N/4, then a frequency offset of 4 sub-carrier spacings can be estimated using the training symbol. However, the range to be established may depend upon the characteristics of the channel to be estimated also.
• Transmission of the training sequence of length N[0065]_Icorresponds to exciting every Ith sub-channel of an OFDM signal having a block size N. This means that no information is transmitted on the remaining (1−1/I)N sub-channels and the estimates of the channel for the sub-channels are derived from the ones that actually include information. This may result in a poor performance and hence it is left to the system designer to determine the length of the preamble.
• The sub-channels of the transmit sequence that bear no information are said to be zero-padded. Alternatively, the training sequence of length N[0066]_Imay be generated by first modulating every Ith sub-channel of the OFDM block by a known sequence of symbols and zero padding the rest. An N-point IDFT is taken to obtain N samples in the time domain, and finally only the first N_Isamples along with its cyclic prefix are transmitted. At the receiver after synchronization, the samples corresponding to the training sequence of length N_Iare repeated I times before being demodulated by the OFDM demodulators. In a number of alternative systems, many more sub-channels are zero padded to reduce the interference between the adjacent bands and to facilitate the system implementation. For example, in the systems based on the IEEE 802.16a/b standard, a total of 56 tones or sub-carriers are zero padded.
• The training sequence structure in the frequency domain is represented by its signal transmission matrix, which is configured in such a way so as to have certain properties that aid in synchronization and channel estimation. For example, the signal transmission matrix for a 2×2 system may be of the form:[0067]$\begin{array}{cc}{S}_k=\left[\begin{array}{cc}{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{1,\mathrm{<figure-callout\; label="k\; S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">k</figure-callout>}}& S_{}{}_{1,k}\\ -{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{1,k}^{*}& {\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{1,k}^{*}\end{array}\right],& \left(1\right)\end{array}$

  
• where * denotes a complex conjugate operation, and k is a sub-carrier or sub-channel index. The signal transmission matrix S for a 4×4 system may be of the form:[0068]$\begin{array}{cc}{S}_k=\left[\begin{array}{cccc}{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{1,\mathrm{<figure-callout\; label="k\; S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">k</figure-callout>}}& S_{}{}_{1,\mathrm{<figure-callout\; label="k\; S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">k</figure-callout>}}& S_{}{}_{1,\mathrm{<figure-callout\; label="k\; S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">k</figure-callout>}}& S_{}{}_{1,k}\\ -{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{1,\mathrm{<figure-callout\; label="k\; S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">k</figure-callout>}}& S_{}{}_{1,k}& -{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{1,\mathrm{<figure-callout\; label="k\; S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">k</figure-callout>}}& S_{}{}_{1,k}\\ -{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{1,\mathrm{<figure-callout\; label="k\; S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">k</figure-callout>}}& S_{}{}_{1,\mathrm{<figure-callout\; label="k\; S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">k</figure-callout>}}& S_{}{}_{1,k}& -{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{1,k}\\ -{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{1,k}& -{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{1,\mathrm{<figure-callout\; label="k\; S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">k</figure-callout>}}& S_{}{}_{1,\mathrm{<figure-callout\; label="k\; S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">k</figure-callout>}}& S_{}{}_{1,k}\end{array}\right],& \left(2\right)\end{array}$

  
• where S[0069]₁is the sequence in the frequency domain that has certain properties that satisfy the system requirements. Similarly, the signal transmission matrix S for a 3×3 system may be of the form:$\begin{array}{cc}{S}_k=\left[\begin{array}{ccc}{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{1,\mathrm{<figure-callout\; label="k\; S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">k</figure-callout>}}& S_{}{}_{2,k}& \frac{S_{3,k}}{\sqrt{2}}\\ -{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{2,k}^{*}& {\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{1,k}^{*}& \frac{S_{3,k}}{\sqrt{2}}\\ \frac{S_{3,k}^{*}}{\sqrt{2}}& \frac{S_{3,k}^{*}}{\sqrt{2}}& \frac{-{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{1,k}-{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{1,k}^{*}+{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{2,k}-{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{2,k}^{*}}{2}\\ \frac{S_{3,k}^{*}}{\sqrt{2}}& \frac{-S_{3,k}^{*}}{\sqrt{2}}& \frac{{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{2,k}+{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{2,k}^{*}+{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{1,k}-{\mathrm{<figure-callout\; label="S"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">S</figure-callout>}}_{1,k}^{*}}{2}\end{array}\right],& \left(3\right)\end{array}$

  
• where k=0,1, . . . , N−1. The rows of the signal transmission matrix represent the time dimension, the columns represent the space dimension and the index k represents the frequency dimension or the corresponding sub-carrier. The[0070]transmitter8 may create the matrix S_ksuch that it is unitary. If the vectors of the training sequences are derived from the points along the unit circle in the complex domain then the signal transmission matrices S_kshown in (1) and (2) are unitary. Besides making each of the transmission matrices S_kunitary, it also facilitates the system implementation and maintains a low PAPR of the sequence structure in the time domain. This is because the signal transmission matrices in the training mode and the data mode are exactly alike, which further simplifies the system implementation. The transmission of a unitary matrix aids in parameter estimation, as is described below.
• With reference again to FIG. 1, the L number of receiving[0071]antennas20 receive the Q number of transmitted signals and provide the received signals torespective OFDM demodulators22, which down-convert the signal back to baseband. The L number of receivingantennas20 are separated by a distance such that the received signals have minimum correlation and are as independent from each other as possible. The outputs from the L number ofOFDM demodulators22 are input into adecoder24, which combines the multiple signals and decodes them. In addition, thedecoder24 removes any correctable noise and distortion errors, as will be described below, and outputs signals representative of the original data.
• FIG. 7 illustrates an example embodiment of one of the[0072]OFDM demodulators22 of thereceiver10. Received signals from the receivingantenna20 are input into apre-amplifier57, which amplifies the received signals to a level at which further processing may be performed. The output of thepre-amplifier57 is connected to amixer58. Alocal oscillator59 provides a signal to themixer58 having a frequency designed to demodulate the received amplified signal. The demodulated signal is then output to an analog-to-digital converter (ADC)60, which converts the analog signals into discrete time samples. The discrete time samples are applied to asynchronization circuit61.
• An explanation will now be made to emphasize the significance of synchronization in an OFDM system. OFDM typically requires substantial synchronization in time as well as in frequency in order that transmitted signals can be recovered with adequate accuracy. Time synchronization involves determining the best possible time for the start of the received frame to closely match the start of the transmitted signal.[0073]
• Frequency synchronization involves maintaining orthogonality of the respective sub-carrier frequencies. Orthogonality refers to a condition of the sub-carrier frequencies wherein the “inner product” of the signals at different sub-carrier frequencies is zero. With respect to the inner product, reference is made, for example, to the time domain sequences s ,n wherein n=0, 1, . . . N−1 and the sub-carrier index k is equal to 1. When the sub-carrier index k is equal to 2, the time domain sequences S[0074]_2,nare transmitted. The inner product is equal to Σ(s_1,n)*(S_2,n) wherein n=0, 1, . . . N−1. When the inner product is not equal to zero, a loss of sub-channel orthogonality may result, thereby causing Inter Carrier Interference (ICI). Since the sub-channels are separated by a precise frequency difference to maintain orthogonality, any difference in frequencies between the transmitter and the receiver local oscillators may cause a loss of sub-channel orthogonality. Thesynchronization circuit61 corrects this loss of sub-channel orthogonality by finding an estimate of the difference between the frequencies of thelocal oscillators46 of thetransmitter8 and the frequencies of thelocal oscillators59 of thereceiver10. Thesynchronization circuit61 further corrects these frequency difference estimates.
• The[0075]synchronization circuit61 will now be explained with reference to FIG. 8. The input to thesynchronization circuit61, connected to the output of theADC60, is input into a coarsetime synchronization circuit66 and a frequency offsetcorrection circuit74. The coarsetime synchronization circuit66 determines the approximate start time of each received block of N+G samples by estimating the approximate starting time of the OFDM frame. The coarsetime synchronization circuit66 sends the coarsely synchronized signals to a first frequency offsetestimation circuit68. The coarsetime synchronization circuit66 sends a second output to the frequency offsetcorrection circuit74 and a third output back to thepre-amplifier57 for altering the gain of thepre-amplifier57.
• The first frequency offset[0076]estimation circuit68 estimates the frequency offset to within one-half of the sub-carrier spacings. An output from the first frequency offsetestimation circuit68 is sent to the frequency offsetcorrection circuit74. At this stage, the frequency offsetcorrection circuit74 performs an initial correction of the frequency offset, utilizing the signals received from theADC60, coarsetime synchronization circuit66, and the first frequency offsetestimation circuit68. The frequency offsetcorrection circuit74 sends the initial frequency corrected samples to acyclic prefix remover62, which is shown in FIG. 7. Thecyclic prefix remover62 removes the cyclic prefixes from the frames and sends the symbols, with the cyclic prefixes removed, to a serial-to-parallel converter63. The serial-to-parallel converter63 converts the serial stream to a parallel format and sends the parallel data to a Discrete Fourier Transform (DFT)stage64. TheDFT stage64 converts the time domain samples to the frequency domain, and returns an output to thesynchronization circuit61 to refine the synchronization in the time and frequency domain.
• With reference again to FIG. 8, the output from the[0077]DFT64 travels to a second frequency offsetestimation circuit70 and a finetime synchronization circuit72. The second frequency offsetestimation circuit70 receives the estimation of the frequency offset to within one-half the sub-carrier spacing form the first frequency offsetestimation circuit68 and the frequency domain samples from theDFT64. Using these input signals, the second frequency offsetestimation circuit70 provides an estimation of the frequency offset to an integer multiple of sub-carrier spacings.
• The second frequency offset[0078]estimation circuit70 provides an output to thelocal oscillator59 for adjusting the frequency of thelocal oscillator59 to the frequency of thelocal oscillator46 of thetransmitter8. The second frequency offsetestimation circuit70 sends a second output to the frequency offsetcorrection circuit74, which may further correct the frequency offset during a second stage, based on the offset estimated by the second frequency offsetestimation circuit70. Both the frequency offsetcorrection circuit74 and the second frequency offsetestimation circuit70 send outputs to the finetime synchronization circuit72, which calculates a more accurate start time of the received frame. Outputs from the frequency offsetcorrection circuit74 and finetime synchronization circuit72 are sent to thecyclic prefix remover62, which receives the signals that are further synchronized during the second stage of thesynchronization circuit61.
• The[0079]synchronization circuit61 may be utilized as many times as necessary to accurately synchronize thereceiver10 in the time and frequency domains. The known calibration values may be transmitted by thetransmitter8 for an amount of time until thesynchronization circuit61 has developed an accurate correction to compensate for time variations and frequency offsets that may be inherent in thecommunication system6 andchannel19. Once adequate synchronization has been obtained, frames carrying the user's data symbols may be transmitted with confidence that time and frequency synchronization will allow acceptable reception of the transmitted signals. With synchronization maintained, newly received symbols sent to thesynchronization circuit61 may bypass the synchronization and estimation circuits and pass through the frequency offsetcorrection circuit74 to synchronize the new symbols. Therefore, as time passes, thesynchronization circuit61 may make slight adjustments to account for any changes in thecommunication system6, but may reach a steady state when thecommunication system6 does not change.
• The individual circuits of the[0080]synchronization circuit61 will now be explained with reference to FIGS. 9A, 9B,10,11 and12. The coarsetime synchronization circuit66 determines the approximate start time of each received block of N+G samples. The coarsetime synchronization circuit66 may use circuitry which takes into account the periodicity inserted into the training symbol, or in other words, the periodic occurrences of the inserted cyclic prefixes in the data frame. The coarsetime synchronization circuit66 detects the location of the cyclic prefixes by observing the repetitious nature of the G samples. To reiterate, the G samples repeat a portion of the N samples, as explained above.
• The coarse[0081]time synchronization circuit66 may comprise circuitry capable of performing a technique that is hereinafter referred to as “auto-correlation.” The phase output from the auto-correlation circuit may be used in the example embodiment of the first frequency offsetestimation circuit68, as is described in more detail below. The technique of auto-correlation is accomplished by comparing the samples of a data stream with samples of the same data stream that are delayed by the number of samples N_I.
• An example embodiment of an auto-[0082]correlation circuit75 is shown in FIG. 9A. A received frame is demodulated into a data stream r_n, which is input into amixer76 and adelay circuit77. Thedelay circuit77 delays the data stream by N_Isamples such that a second input into themixer76 will be offset by N_Isamples. The delayed data stream is processed by acomplex conjugation circuit78, which outputs the processed data stream to the second input of themixer76.
• The[0083]mixer76 compares the data stream r_nwith the delayed and processed data stream. Since the delayed data stream is delayed by N_Isamples, the mixer compares the start of the preamble at the first G sample with a sample that is delayed N_Ifrom the start of the preamble. If the comparison between the data stream r_nand the delayed data stream reveals an alignment of the G samples of the cyclic prefix with the last G samples of the training symbol N_I, then themixer76 outputs a constructively added waveform. The output of themixer76 is input into a summingcircuit79, which sums the output of themixer76 over G samples and provides the magnitude and phase of the sum. The auto-correlation operation can be represented using the equation:${\phi }_n=\sum _{k=0}^{G-1}r_{n+k}^{*}·r_{n+k+N_I}$

  
• where the coarse time synchronization is achieved when φ[0084]_nattains a certain threshold value.
• In addition to auto-correlation, the coarse[0085]time synchronization circuit66 may also correct any undesirable fluctuations in the amplitude of the signals received by thereceiver10. Signals experiencing long-term amplitude fluctuations may be corrected by an automatic gain control (AGC) circuit, which may be part of the coarsetime synchronization circuit66. The AGC circuit may detect variations in the signal amplitudes and provide feedback signals to thepre-amplifier57 in order to maintain the received signals at a constant magnitude.
• As shown in FIG. 9B, an embodiment of an[0086]AGC circuit80 comprises aninstantaneous energy calculator82, which calculates the instantaneous energy using the formula:$p_n=\sum _{k=0}^{G-1}r_{n+k+N_I}^{*}r_{n+k+N_I}$

  
• An average of this instantaneous energy is taken over a period of time by a[0087]time averaging circuit84 and given to thepre-amplifier57 to correct the long term fluctuations in the amplitude of the received signal. The time averaging circuit can be represented using a formula such as:$P_{avg}=\frac{1}{M}\sum _{n=1}^MP_n,$

  
• where M can be any number large enough to average long term fluctuations in the OFDM signal. For example, M may be equal to 10(N+G).[0088]
• Furthermore, the coarse[0089]time synchronization circuit66 corrects short-term fluctuations in the signals by utilizing the training symbols, pilot symbols, and the instantaneous energy value p_ngenerated by theAGC circuit80. After the coarsetime synchronization circuit66 determines an approximate starting time, a more precise time synchronization is achieved by utilizing the finetime synchronization circuit72, which preferably follows in sequence after a frequency offset estimation operation, as will be described below.
• In addition to the feedback signal to the[0090]pre-amplifier57, the coarsetime synchronization circuit66 outputs the coarsely synchronized signals to the first frequency offset estimation circuit68 (FIG. 8) for carrying out the first step of frequency offset estimation and correction. In accordance with the present invention, frequency synchronization is preferably carried out in two steps. The first frequency offsetestimation circuit68 estimates any frequency offset of ±{fraction (1/2)} sub-carrier spacings where I=N/N_Iand N_Iis the length of the periodic sequence. In the simplest case, N_I=N and the first frequency offsetestimation circuit68 can correct frequency offset of one sub-carrier spacing. This frequency offset is derived from the phase output from the auto-correlation circuit75, when the auto-correlation reaches its peak or crosses a certain predetermined threshold.
• An example embodiment of the first frequency offset[0091]estimation circuit68 is illustrated in FIG. 10. The phase output from the auto-correlation circuit75 is input into an offsetestimation circuit86. The offsetestimation circuit86 estimates the frequency offset using a formula that may be expressed by:$\gamma =\frac{\mathrm{<figure-callout\; label="N"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">N</figure-callout>}}{2\pi N_I}\theta$

  
• If the range of the first frequency offset[0092]estimation circuit68 is not large enough, then the frequency offset estimation has to be performed in two stages. The first frequency offsetestimation circuit68 estimates the fractional portion of the frequency offset.
• The frequency offset of the integer multiples of the subcarrier spacings is performed by the second frequency offset[0093]estimation circuit70 by performing a cyclic cross-correlation in the frequency domain. The cyclic cross-correlation is made possible by the fact that the training sequence structure is designed such that the same sequence is transmitted from all the transmittingantennas18 in the first training symbol period. The second frequency offsetestimation circuit70 receives feedback from the output of a Discrete Fourier Transform (DFT) stage64 (FIG. 7), which converts the signal into the frequency domain, and is compared (cross-correlated) with the training symbol that was transmitted. If there is any residual frequency offset of an integer multiple of sub-carrier spacings, then the peak of the cross-correlation function will have shifted by an appropriate number of sub-carriers. Otherwise the peak will be at zero frequency. This residual frequency offset estimate is then applied to the frequency offsetcorrection circuit74 to correct the residual offset. The second frequency offsetestimation circuit70 can also be used to provide a feedback signal to correct and adjust the frequency of thelocal oscillator59.
• FIG. 11 illustrates an example of an embodiment of the way in which the second frequency offset[0094]estimation circuit70 shown in FIG. 8 can be configured. An output from theDFT64 is input as a frequency domain received symbol R_Ito abuffer88, which stores in memory N samples. Outputs from thebuffer88 are input intoN mixers90. Sequences S_Ifrom the first frequency offsetestimation circuit68 are input into anotherbuffer92, which stores the sequence S_Ihaving a length of N samples. Sequence S_Iis constructed by first repeating the sequence s₁in the time domain I times and then taking an N-point FFT of the repeated sequence. Outputs from thebuffer92 are input into complex conjugation circuits (CCCs)94 for performing complex conjugation operations. The outputs of theCCCs94 are input into second inputs into themixers90, which mixes the two sets of inputs. The outputs from themixers90 are sent to a summingcircuit96, which provide a function having the equation:$\begin{array}{cc}{\chi }_k=\sum _{n=0}^{N-1}\left(S_{I,{\left(k+n\right)}_N}^{*}{\mathrm{<figure-callout\; label="R"\; filenames="US20020181509A1-20021205-D00003.png,US20020181509A1-20021205-D00004.png"\; state="\{\{state\}\}">R</figure-callout>}}_{1,n}\right)& k=0,1,\dots ,N-1,\end{array}$

  
• k=0,1, . . . , N−1,
• where (k+n)N represents the modulo-N or the remainder operation such that if k+n=N, then (k+n)[0095]_N=0 and if k+n—N+1, then (k+n)_N=1. Hence, thebuffer92 circularly shifts the sequence N times and calculates the values of χ from k=0 toN−1. The index k at which X achieves its maximum gives the frequency offset estimate of the integral number of sub-carrier spacings.
• The output from the summing[0096]circuit96 is sent to the frequency offset correction circuit74 (FIG. 8), the finetime synchronization circuit72, and thelocal oscillator59. In response to this output, the frequency offsetcorrection circuit74 further corrects the frequency difference to synchronize the frequency with respect to the integer multiples. Thelocal oscillator59 responds by adjusting the sub-carrier frequency to minimize the frequency offset.
• The frequency offset[0097]correction circuit74 receives the estimates of the frequency offset from the first frequency offsetestimation circuit68 and the second frequency offsetestimation circuit70. In response to the estimates in the frequency offset, the frequency offsetcorrection circuit74 can correct the frequency offset in discrete time or partly in discrete time and partly by sending the correction factor to thelocal oscillator59.
• Fine time synchronization can then be achieved by using the fine[0098]time synchronization circuit72 to find the start of the useful portion of the OFDM block to within a few samples. Fine time synchronization can be performed by cross-correlating the transmitted training symbols with the received frequency offset corrected signals from the frequency offsetcorrection circuit74 and by recognizing a predetermined pattern. If different sequences are transmitted from different antennas, then Q such correlation circuits are needed and the magnitudes of their outputs are summed together. The peak of the summed magnitudes will indicate the fine time synchronization instant. In the example of the transmission matrix structure provided in equations (1) and (2), the same sequence is transmitted from all the transmittingantennas 18 in the first OFDM symbol period. Hence, for this case, only one such correlation circuit is required and the sequence that is stored in the buffer is the time domain counterpart of the sequence S₁.
• If deemed desirable, sequences with special properties can be transmitted from each antenna to further enhance the performance of the fine[0099]time synchronization circuit72. These properties could include the orthogonal nature of the transmitted sequences or any other variation on the sequences to be transmitted from different antennas.
• FIG. 12 illustrates an example embodiment of the fine[0100]time synchronization circuit72. In FIG. 12, abuffer100 comprises a memory device for storing N_Isamples. Thebuffer 100 receives the received samples r_nfrom the second frequency offsetestimation circuit70. Asecond buffer104 stores the time domain sequence s₁having the length N_I, wherein S_Iis the replica of the original transmitted sequence or a semblance of the transmitted sequence s₁. Each output from thebuffer100 is input into a first input of a number of N_Imixers102. The outputs from thebuffer104 are input into a number of N_ICCCs106, which perform complex conjugate operations on the outputs frombuffer104. Each output from theCCCs106 is input into a second input of the N_Imixers102. The N_Inumber of combined signals from themixers102 are input into a summingcircuit108, which sums the combined signals using equation:${\psi }_n=\sum _{k=0}^{N_I-1}s_k^{*}·r_{n+k}.$

  
• Fine time synchronization is achieved at a time instant n when the function Ψ attains a value greater than a predetermined threshold. The output from the summing[0101]circuit108 represents the output of thesynchronization circuit61 and is sent to a cyclic prefix remover62 (FIG. 7).
• The performance of the fine[0102]time synchronization circuit72 is dependent on the frequency offset estimation and correction. Presence of any frequency offset hampers the performance of the finetime synchronization circuit72. When no frequency offset exists, the timing information may be derived directly from the coarsetime synchronization circuit66. Also, coarse time synchronization can be modified to provide better estimates by averaging the results of the coarse time synchronization circuits from different OFDM demodulators and over different times. The finetime synchronization circuit72 provides an optimal time instant of the start of the received OFDM frame.
• The[0103]communication system6 may either employ Lsuch synchronization circuits61, one for eachOFDM demodulator22 or it may employ certain parts of the synchronization circuit for all theOFDM demodulators20 and certain parts that are common to theentire receiver10. For example, theOFDM modulators22 may include individualtime synchronization circuits66 and72 and frequency offsetcorrection circuit74, but may share common frequency offsetestimation circuits68 and70. Alternatively, thereceiver10 may simply comprise asingle synchronization circuit61.
• Reference will now be made again to FIG. 7. Once the fine[0104]time synchronization circuit72 achieves fine time synchronization, the frequency and time synchronized information is provided to thecyclic prefix remover62, which removes the cyclic prefixes inserted between each block of N symbols. The blocks of N samples are then serial-to-parallel converted using serial-to-parallel converter63 and the parallel signals are input to theDFT stage64, which converts the time domain samples back to the frequency domain, thus completing synchronization and demodulation by theOFDM demodulators22.
• Referring again to FIG. 1, the L number of demodulated signals from each of the L number of[0105]OFDM demodulators22 are then input into thedecoder24, which processes the demodulated signals. Thedecoder24 may be configured in the manner shown in the example embodiment of FIG. 13. Thedecoder24 comprises a space-time processor110 and aparameter estimator112. Both the space-time processor110 andparameter estimator112 receive the signals from each of the L number ofOFDM demodulators22.
• An output from the[0106]parameter estimator112 is input into asymbol demapper116 and a set of outputs is input into the space-time processor110. The output of the space-time processor110 is converted from parallel to serial by a parallel-to-serial converter114 and then input to thesymbol demapper116, which maps the symbols from the predetermined alphabet back to the data bits. The output from thesymbol demapper116 is input into achannel decoder118. Thechannel decoder118 decodes the data symbols by checking the parity that was added to the symbols prior to transmission. Thus, thechannel decoder118 detects and corrects errors in the data symbols and outputs the data in its original form. There can be an exchange of information between theparameter estimator112,symbol demapper116 andchannel decoder118 to create a feedback loop. If thechannel decoder118 detects too many errors in the training symbol such that correction of the errors is no longer possible, then an “excessive-error” indication is made to theparameter estimator112, which adjusts and corrects its estimates.
• The[0107]communication system6 of the present invention, including thesynchronization circuit61, can be implemented in hardware, software, firmware, or a combination thereof. In the embodiments of the present invention, thecommunication system6 can be implemented in software or firmware that is stored in a memory and that is executed by a suitable instruction execution system. If implemented in hardware, as in an alternative embodiment, the synchronization system can be implemented with any or a combination of the following technologies, which are all well known in the art: a discrete logic circuit having logic gates for implementing logic functions upon data signals, an application specific integrated circuit (ASIC) having appropriate combinational logic gates, a programmable gate array (PGA), a field programmable gate array (FPGA), digital signal processor (DSP), etc.
• It should be emphasized that the above-described embodiments of the present invention are merely possible examples of implementations, merely set forth for a clear understanding of the principles of the invention. Many variations and modifications may be made to the above-described embodiments of the invention without departing substantially from the principles of the invention. All such modifications and variations are intended to be included herein within the scope of this disclosure and protected by the following claims.[0108]

Claims (53)

We claim:

1. An apparatus for synchronizing a Multi-Input, Multi-Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) system, the apparatus comprising:

a number Q of OFDM modulators, each OFDM modulator producing a frame comprising at least one inserted symbol, a plurality of data symbols, and cyclic prefixes;

said number Q of transmitting antennas, each transmitting antenna connected to a respective OFDM modulator, for transmitting said frame over a channel;

a number L of receiving antennas for receiving the transmitted frames; and

said number L of OFDM demodulators, each OFDM demodulator corresponding to a respective receiving antenna, the L OFDM demodulators comprising a synchronization circuit, which processes the received frame in order to synchronize the received frame in the time domain and frequency domain.

2. The apparatus ofclaim 1, wherein the cyclic prefixes protect the data symbols against Inter Symbol Interference (ISI).

3. The apparatus ofclaim 1, wherein the at least one inserted symbol has at least one pilot symbol inserted within the data symbols or at least one training symbol inserted at the beginning of the frame.

4. The apparatus ofclaim 1, wherein the synchronization circuit comprises a circuit for finding the optimum time instant of the start of the demodulated frame.

5. The apparatus ofclaim 4, wherein the synchronization circuit comprises a coarse time synchronization circuit and a fine time synchronization circuit.

6. The apparatus ofclaim 5, wherein the coarse time synchronization circuit comprises a circuit for performing auto-correlation on the received frame over a particular window.

7. The apparatus ofclaim 5, wherein the coarse time synchronization circuit comprises a circuit for performing an automatic gain control operation.

8. The apparatus ofclaim 1, wherein each of the Q OFDM modulators comprises a transmitting local oscillator, each of the L OFDM demodulators comprises a receiving local oscillator, and the synchronization circuit comprises a first frequency offset estimation circuit and a second frequency offset estimation circuit for estimating the frequency difference between the transmitting local oscillator and the receiving local oscillator.

9. The apparatus ofclaim 8, wherein the second frequency offset estimation circuit is used to correct the frequency of the receiving local oscillator.

10. The apparatus ofclaim 8, wherein said synchronization circuit further comprises a frequency offset correction circuit that utilizes the estimates from said second frequency offset estimation circuit and said first frequency offset estimation circuit to correct the frequency offset in discrete time.

11. The apparatus ofclaim 1, wherein each of the Q OFDM modulators share a common transmitting local oscillator, each of the L OFDM demodulators share a common receiving local oscillator, and the synchronization circuit comprises first and second frequency offset estimation circuits for estimating the frequency difference between the transmitting local oscillator and the receiving local oscillator.

12. The apparatus ofclaim 1, wherein Q is equal to L.

13. The apparatus ofclaim 12, wherein Q is equal to one.

14. The apparatus ofclaim 1, wherein Q equals two.

15. The apparatus ofclaim 1, wherein Q is not equal to L.

16. The apparatus ofclaim 1 further comprising an OFDM encoder, wherein the OFDM encoder comprises:

a channel encoder;

a symbol mapper connected to an output of the channel encoder;

a space-time processor connected to an output of the symbol mapper, the space-time processor separating data into a plurality of sub-channels; and

a pilot/training symbol inserter, which inserts pilot symbols and training symbols onto the sub-channels.

17. The apparatus ofclaim 1, wherein each of the Q OFDM modulators comprises:

a serial-to-parallel converter;

an inverse discrete Fourier transform (IDFT) stage connected to an output of the serial-to-parallel converter;

a cyclic prefix inserter connected to an output of the IDFT stage;

a parallel-to-serial converter connected to an output of the cyclic prefix inserter;

a digital-to-analog converter (DAC) connected to an output of the parallel-to-serial converter;

a local oscillator;

a mixer having a first input and a second input, the first input connected to an output of the DAC, the second input connected to an output of the local oscillator; and

an amplifier connected to an output of the mixer.

18. The apparatus ofclaim 1, wherein each of the L OFDM demodulators comprises:

a pre-amplifier;

a local oscillator;

a mixer having a first input and a second input, the first input connected to an output of the pre-amplifier, the second input connected to an output of the local oscillator;

an analog-to-digital converter (ADC) connected to an output of the mixer;

the synchronization circuit, having one input connected to an output of the ADC;

a cyclic prefix remover connected to an output of the synchronization circuit;

a serial-to-parallel converter connected to an output of the cyclic prefix remover; and

a discrete Fourier transform (DFT) stage connected to an output of the serial-to-parallel converter, an output of the DFT stage connected to another input to the synchronization circuit.

19. The apparatus ofclaim 1, wherein the L OFDM demodulators share a single synchronization circuit.

20. The apparatus ofclaim 1, wherein each OFDM demodulator uses one of L synchronization circuits.

21. The apparatus ofclaim 1, wherein the synchronization circuit comprises a first portion that includes individual circuits such that each individual circuit is used exclusively by a respective OFDM demodulator, and a second portion that includes circuits that are shared by all of the L OFDM demodulators.

22. The apparatus ofclaim 21, wherein the second portion comprises a first frequency offset estimator circuit and a second frequency offset estimator circuit, and the first portion comprises a coarse time synchronization circuit, a fine time synchronization circuit, and a frequency offset correction circuit.

23. The apparatus ofclaim 21, wherein the second portion comprises a coarse time synchronization circuit, a first frequency offset estimator circuit, and a second frequency offset estimator circuit, and the first portion comprises a fine time synchronization circuit and a frequency offset correction circuit.

24. The apparatus ofclaim 21, wherein the first portion comprises coarse time synchronization circuits wherein the results of the different coarse time synchronization circuits are shared by the different OFDM demodulators.

25. The apparatus ofclaim 1 further comprising an OFDM decoder, wherein the OFDM decoder comprises:

a space-time processor that receives an output from each of the L OFDM demodulators;

a parameter estimator that receives an output from each of the L OFDM demodulators and estimates parameters of the channel;

a parallel-to-serial converter connected to an output of the space-time processor;

a symbol demapper having a first input and second input, the first input connected to an output of the parameter estimator, the second input connected to an output of the parallel-to-serial converter; and

a channel decoder connected to an output of the symbol demapper.

26. A synchronization circuit, incorporated within a demodulator of a Multi-Input, Multi-Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) system, wherein the synchronization circuit comprises:

a coarse time synchronization circuit;

a first frequency offset estimation circuit connected to a first output of the coarse time synchronization circuit;

a second frequency offset estimation circuit connected to a first output of the first frequency offset estimation circuit;

a fine time synchronization circuit having a first input connected to a first output of the second frequency offset estimation circuit; and

a frequency offset correction circuit having inputs connected to second outputs of the coarse time synchronization circuit, first frequency offset estimation circuit, and second frequency offset estimation circuit, and having an output connected to a second input to the fine time synchronization circuit.

27. The apparatus ofclaim 26, wherein the coarse time synchronization circuit is an auto-correlation circuit that comprises:

a delay circuit that receives a stream of data samples of the received frame;

a complex conjugation circuit connected to an output of the delay circuit;

a mixer having a first input and a second input, the first input receiving the stream of data samples, the second input connected to an output of the complex conjugation circuit; and

a summing circuit connected to an output of the mixer.

28. The apparatus ofclaim 26, wherein the first frequency offset estimation circuit comprises an offset correction circuit.

29. The apparatus ofclaim 26, wherein the second frequency offset estimation circuit is a cross-correlation circuit in the frequency domain that comprises:

a first buffer that receives and stores a portion of a stream of data samples from a Discrete Fourier Transform (DFT) stage, the first buffer having a plurality of outputs;

a second buffer that receives and stores a portion of a stream of data samples in the frequency domain from a transmitted sequence, the second buffer having a plurality of outputs;

a plurality of complex conjugation circuits connected to the plurality of outputs of the second buffer;

a plurality of mixers, each mixer having a first input and a second input, the first inputs connected to the outputs of the first buffer, the second inputs connected to outputs of the complex conjugation circuits; and

a summing circuit that sums the outputs of the mixers.

30. The apparatus ofclaim 26, wherein the fine time synchronization circuit is a cross-correlating pattern recognition circuit that comprises:

a first buffer that receives and stores a portion of a stream of data samples of the received frame, the first buffer having a plurality of outputs;

a second buffer that receives and stores a portion of a transmitted sequence in the time domain, the second buffer having a plurality of outputs;

a plurality of complex conjugation circuits connected to the plurality of outputs of the second buffer;

a plurality of mixers, each mixer having a first input and a second input, the first inputs connected to the outputs of the first buffer, the second inputs connected to outputs of the complex conjugation circuits; and

a summing circuit that sums the outputs of the mixers.

31. A method for synchronizing a Multi-Input Multi-Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) system in the time and frequency domains, the method comprising the steps of:

producing a frame of data comprising a training symbol that includes a synchronization component that aids in synchronization, a plurality of data symbols, and a plurality of cyclic prefixes;

transmitting the frame over a channel;

receiving the transmitted frame;

demodulating the received frame;

synchronizing the received demodulated frame to the transmitted frame such that the data symbols are synchronized in the time domain and frequency domain.

32. The method ofclaim 31, wherein the synchronizing in the time domain comprises coarse time synchronizing and fine time synchronizing.

33. The method ofclaim 32, wherein the synchronizing in the time domain includes averaging estimates over a period of time.

34. The method ofclaim 31, wherein the synchronizing in the frequency domain comprises estimating a frequency offset.

35. The method ofclaim 34, wherein the step of estimating the frequency offset comprises estimating the frequency offset to within one half of the sub-carrier spacing.

36. The method ofclaim 35, wherein the step of estimating the frequency offset further comprises the steps of:

repeating received samples of the received frame a number of times;

taking an N-point Fast Fourier Transform (FFT); and

performing a cross-correlation procedure in the frequency domain.

37. The method ofclaim 34, wherein the step of estimating the frequency offset comprises averaging the estimates over a number of frames, thereby improving the estimates.

38. The method ofclaim 34, wherein the step of estimating the frequency offset comprises taking the estimates from a number of different OFDM demodulators and averaging the estimates, thereby improving the estimates.

39. The method ofclaim 31, wherein the transmitting step includes transmitting the symbols from at least two antennas.

40. The method ofclaim 31, wherein the step of producing further comprises producing said training symbol with an orthogonal sequence, thereby enhancing the fine time synchronization performance.

41. The method ofclaim 31, wherein the step of producing further comprises adjusting the periodicity of the training symbol, thereby increasing the range of frequency offset estimation.

42. The method ofclaim 31, wherein the synchronization component aids in synchronization and in the estimation of channel parameters.

43. The method ofclaim 31, wherein the synchronization component comprises a preamble of a generalized length having a number of OFDM symbols less than a number of transmitting antennas.

44. The method ofclaim 31, wherein the synchronization component comprises a preamble of a generalized length having a number of OFDM symbols equal to a number of transmitting antennas.

45. The method ofclaim 31, wherein the synchronization component comprises a preamble of a generalized length having a number of OFDM symbols greater than a number of transmitting antennas.

46. The method ofclaim 31, wherein the synchronization component comprises a preamble whose signal transmission matrix resembles an existing space-time block code.

47. The method ofclaim 31, wherein the synchronization component includes chirp-like sequences.

48. The method ofclaim 47, wherein the chirp-like sequences include at least one of Frank-Zadoff sequences, Chu sequences, Milewski sequences, Suehiro polyphase sequences, and Ng et al. sequences.

49. The method ofclaim 31, wherein the step of producing a frame comprises producing the cyclic prefixes in a preamble and in the data symbols such that the cyclic prefixes in the preamble are longer than the cyclic prefixes in the data symbols, thereby countering an extended channel impulse response and improving synchronization.

50. The method ofclaim 31, further comprising the step of altering the training symbol to enhance the synchronization performance.

51. The method inclaim 31, wherein the coarse time synchronizing includes averaging the coarse time synchronized results over time.

52. The method ofclaim 31, further comprising the steps of:

generating an N-point representation of the transmitted sequence in the frequency domain;

repeating the time domain sequence a number of times; and

taking an N-point Fast Fourier Transform.

53. The method ofclaim 31, wherein the step of producing comprises producing a preamble whose signal transmission matrix resembles an existing space-time block code.

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