US20020180029A1 - Semiconductor device with intermediate connector - Google Patents

Abstract

A semiconductor element and a circuit substrate each having electrodes disposed at narrow pitch are electrically connected with high reliability by conductive paste. A semiconductor device with a semiconductor section and a circuit substrate electrically connected and a method for manufacturing such semiconductor device are provided. The manufacturing method includes processes of: forming semiconductor electrodes at the semiconductor section; forming substrate electrodes at the circuit substrate; firstly affixing one part of the semiconductor section and circuit substrate to an intermediate connector made of insulating material; forming via holes at intermediate connector according to positions of the semiconductor electrodes and positions of the substrate electrodes; electrically connecting each semiconductor electrode and each substrate electrode via each via hole; and secondly affixing the other part of the semiconductor section and circuit substrate to the intermediate connector.

Description

BACKGROUND OF THE INVENTION
• 1. Field of the Invention[0001]
• The present invention relates to a technology for mounting semiconductor elements to a circuit substrate at a high density.[0002]
• 2. Description of Background Arts[0003]
• The packaging density of semiconductor elements has been remarkably increased. In order to meet a decrease in packaging area and an increase in number of electrodes, various high-density packaging methods have been proposed in recent years. As one example, there is a method for facedown-mounting semiconductor elements with bumps formed at the electrode section to circuit substrates (U.S. Pat. No. 4,661,192, Laid-open Japanese patent publication No. 6-224259). FIG. 1 is a cross-sectional view of a conventional semiconductor device facedown-mounted.[0004]
• The conventional semiconductor device shown in FIG. 1 comprises a[0005]semiconductor element901,circuit substrate907, protrudingelectrode905 andconductive paste909 which electrically connects thesemiconductor element901 tocircuit substrate907, and sealingresin911.
• [0006]Circuit substrate907 is, for example, a multilayer circuit substrate with all the layers having an interstitial via hole (IVH) construction, and anelectrode913 is installed for securing electrical connections withsemiconductor element901. Tosemiconductor element901, a plurality ofelectrodes903 are formed. To each ofelectrodes903, protrudingelectrode905 is installed, andconductive paste909 covers part of it.Semiconductor901 andcircuit substrate907 are electrically connected by pressingconductive paste909 toelectrode913 by protrudingelectrode905. Sealingresin911 is filled betweensemiconductor element901 andcircuit substrate907 as if they fill the clearance of both. Thus,semiconductor element901 can be fixed tocircuit substrate907.
• Referring now FIGS. 2A through 2E, a packaging method of the conventional semiconductor device will be specifically described.[0007]
• FIG. 2A is a diagram showing the semiconductor element.[0008]Semiconductor element901 haselectrode903. First of all, onelectrode903,bump905 is formed using a wire bonding method. Bump905 has a 2-level protruding form. The procedure for forming the bump is described as follows. First of all, a ball formed at an Au wire head end is thermally crimped toelectrode903 and the lower level section of a 2-level protrusion is formed. Then, using an Au wire loop formed by moving a capillary, the upper level section is formed. Under this condition, the heights of the 2-level protruded bumps are not uniform and the evenness at the head end section also lacks. Consequently, pressurizing the 2-level protruded bump, the height is uniformalized and the head end section is leveled. In this way,bump905 is formed onelectrode903.
• FIG. 2B is a diagram showing[0009]semiconductor element901 withconductive paste909 applied. Theconductive paste909 is transferred and formed onbump905. Specifically, for example,conductive paste909 is applied on a rotating disk in a uniform thickness using a doctor blade method and against theconductive paste909 applied,bump905 is pressed and pulled up to carry out transferring.
• FIG. 2C is a diagram showing[0010]semiconductor element901 andcircuit substrate907 before aligning. Aligning is carried out by accurately connectingbump905 onsemiconductor element901 toelectrode913 oncircuit substrate907.
• FIG. 2D is a diagram showing[0011]semiconductor element901 andcircuit substrate907 after aligning.Conductive paste909 onbump905 is pressed againstelectrode913 oncircuit substrate907 andconductive paste909 is heated to harden. Thus,bump905 andelectrode913 are electrically and physically joined.
• FIG. 2E is a diagram showing[0012]semiconductor element901 andcircuit substrate907 after sealing withresin911. Resin911 is epoxy-based material. To the periphery ofsemiconductor element901 and the clearance betweensemiconductor element901 andcircuit substrate907,resin911 is injected and sealing is achieved by hardeningresin911. In this way, by resin-molding circuit substrate907 andsemiconductor element901, a conventional semiconductor device withsemiconductor element901 flip-chip bonded tocircuit substrate907 is completed.
• With respect to FIG. 2B, the amount of[0013]conductive paste909 transferred and formed on eachbump905 is inevitably varied to a certain degree for eachbump905. Consequently, whenelectrode903 ofsemiconductor element901 andelectrode913 ofcircuit substrate907 are electrically connected, pressingbump905 with a large transferring volume ofconductive paste909 againstelectrode913 may causeconductive paste905 to spread to adjacent electrodes or conductive paste and may result in shorting. This causes problems particularly when the clearances betweenelectrodes903 andelectrodes913 are narrow.
SUMMARY OF THE INVENTION
• It is an object of the present invention to electrically connect with high reliability a semiconductor element with electrodes disposed at a narrow pitch to a circuit substrate by conductive paste.[0014]
• According to the present invention, an intermediate connector is provided between a semiconductor section and a circuit substrate. Via holes are formed in the intermediate connector. Because inside each via hole, the conductive paste are sealed in to secure electrical connections between the semiconductor section and the circuit substrate, the conductive paste would not spread from the each via hole to the outside. Consequently, shorting of adjoining electrical connections can be prevented. Further, semiconductor elements with electrodes disposed at a narrow pitch and circuit substrates can be electrically connected with high reliability by conductive paste.[0015]
• The conductive paste is used for electrical connections between the semiconductor section and the circuit substrate. Thus, concentration of the stress applying only to the joining section of the semiconductor section and the circuit substrate can be relaxed. Consequently, stable electrical connections can be achieved with respect to dimensional changes caused by thermal shocks, etc.[0016]
• More specifically, a method for manufacturing a semiconductor device with a semiconductor section and a circuit substrate electrically connected, includes: a forming process which forms semiconductor electrodes at the semiconductor section, a forming process which forms substrate electrodes on the circuit substrate, a first affixing process which affixes one part of the semiconductor section and the circuit substrate to an intermediate connector made of insulating material, a forming process which forms via hole s in the intermediate connector according to positions of the semiconductor electrodes and positions of the substrate electrodes, a connecting process which electrically connects each of the semiconductor electrodes and each of the substrate electrodes via each of the via holes, and a second affixing process which affixes the other part of the semiconductor section and the circuit substrate to the intermediate connector. Therefore, the above object can be achieved.[0017]
• The connecting process may include: a forming process which forms bumps on at least one of the semiconductor electrodes and the substrate electrodes; a filling process which fills conductive paste into the each via hole; and a connecting process which buries each of the bumps in the conductive paste in the each via hole to electrically connect the each semiconductor electrode and the each substrate electrode via the each bump and the conductive paste.[0018]
• The forming process which forms via holes may include: a measuring process which measures at least one of positions of the semiconductor electrodes and positions of the substrate electrodes to obtain positional data; a specifying process which specifies positions on the intermediate connector based on the measured positional data; and a forming process which forms the each via hole at each of the specified positions on the intermediate connector.[0019]
• Each of the semiconductor electrodes and each of the substrate electrodes may be metal layers with films, each metal layer containing resin formed on the surface. Further, the forming process which forms the via holes may remove the films to expose the metal layers.[0020]
• The forming process which forms the via holes may form each wall surface inclined.[0021]
• The filling process may include: an injecting process which injects the conductive paste from the bottom to the opening section of the each via hole; and a scraping process which scraps away a predetermined volume of the conductive paste from the opening section.[0022]
• The injecting process may apply pressure to the conductive paste to discharge the conductive paste and injects the conductive paste from the bottom to the opening section of the each via hole.[0023]
• The first affixing process and the second affixing process may bring the intermediate connector in close contact with the semiconductor section and the circuit substrate by pressurizing and include a sealing process which seals the each via hole.[0024]
• The conductive paste may contain conductive particles and nonconductive resin. Further, the sealing process may include: a providing process which provides a clearance, through which the nonconductive resin alone to flow, at an interface between the intermediate connector and at least one part of the semiconductor section and the circuit substrate; and a densifying process which densifies the conductive paste by pressurizing and allowing the nonconductive resin to flow from the each via hole to seal the each via hole with the conductive particles remained.[0025]
• The intermediate connector may be further made of a material that contracts by pressurizing, and the first affixing process and the second affixing process may contract the intermediate connector by pressurizing to densify the conductive paste.[0026]
• The intermediate connector may be further made of thermosetting resin, and the first affixing process may harden part of the intermediate connector containing thermosetting resin by heating to affix the semiconductor section and the circuit substrate to the intermediate connector.[0027]
• The second affixing process may harden the intermediate connector by heating to affix the semiconductor section and the circuit substrate to the intermediate connector.[0028]
• The injecting process may apply pressure to the conductive paste to discharge with volume smaller than first volume of each via hole and greater than second volume obtained by subtracting volume of each bump from the first volume.[0029]
• The each bump may have a two-level protrusion form.[0030]
• Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.[0031]
BRIEF DESCRIPTION OF THE DRAWINGS
• This and other objects and features of the present invention will become clear from the subsequent description of a preferred embodiment thereof made with reference to the accompanying drawings, in which like parts are designated by like reference numerals and in which:[0032]
• FIG. 1 is a cross-sectional view of a facedown-mounted conventional semiconductor device;[0033]
• FIGS. 2A through 2E are diagrams explaining a mounting process of the conventional semiconductor device;[0034]
• FIG. 3A is a cross-sectional view of an overall construction of a semiconductor device according to Embodiment 1;[0035]
• FIG. 3B is a partial enlarged view of the semiconductor device;[0036]
• FIGS. 4A through 4F are diagrams explaining a first manufacturing process of the semiconductor device;[0037]
• FIG. 5A is an enlarged view around the via hole formed on an intermediate connector with an inclination;[0038]
• FIG. 5B is a cross-sectional view after removing an exposed section in the via hole of the surface-treated layer;[0039]
• FIGS. 6A through 6E are diagrams of a procedure for forming bumps with a diameter greater than a lower level section;[0040]
• FIG. 7 is a diagram of a semiconductor with mushroom-form bumps;[0041]
• FIG. 8A is a diagram of an intermediate connector with conductive paste filled into via holes before bonding the semiconductor element to the circuit substrate;[0042]
• FIG. 8B is a diagram of the intermediate connector after the semiconductor element and the circuit substrate are bonded;[0043]
• FIG. 9A is a diagram of the intermediate connector with conductive paste filled into via holes before bonding to semiconductor element after the circuit substrate is bonded;[0044]
• FIG. 9B is a diagram of the intermediate connector after bonding the circuit substrate to the semiconductor element;[0045]
• FIGS. 10A through 10F are diagrams explaining a second manufacturing process of the semiconductor device according to Embodiment 1;[0046]
• FIG. 11A is a cross-sectional view of a construction of a semiconductor device according to Embodiment 2;[0047]
• FIG. 11B is a partial enlarged view of the semiconductor device;[0048]
• FIGS. 12A through 12F are diagrams explaining a manufacturing process of the semiconductor device according to Embodiment 2;[0049]
• FIG. 13 is a cross sectional view of overall construction of the semiconductor device according to a varied form of Embodiment 2; and[0050]
• FIG. 14 is a cross sectional view of overall construction of a semiconductor device according to Embodiment 3.[0051]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• First of all, a semiconductor device according to the present invention has a semiconductor element and a circuit substrate electrically connected by using conductive paste and bumps. Furthermore, the semiconductor device according to the present invention has an intermediate connector closely adhering to the semiconductor element and the circuit substrate and provided with via holes formed according to positions of electrodes of the semiconductor element and positions of electrodes of the circuit substrate. Electrical connections between the semiconductor element and the circuit substrate are carried out by press-fitting bumps into conductive paste filled in the via hole inside. Since the conductive paste is confined in the via hole, it is possible to prevent the conductive paste to spread to adjoining electrical connections and cause shorting.[0052]
• Referring now to the attached drawings, Embodiments 1 through 3 according to the present invention will be described. Like constituent elements with the same functions are given like reference characters.[0053]
• (Embodiment 1)[0054]
• FIG. 3A is a cross-sectional diagram showing the overall construction of[0055]semiconductor device100 according to Embodiment 1.Semiconductor element100 comprisessemiconductor element101,intermediate connector107,circuit substrate113, and a plurality ofelectric connections120.
• [0056]Semiconductor element101 is an element mounted tocircuit substrate113 and is electrically and physically connected tocircuit substrate113 via eachelectrical connection120.
• [0057]Circuit substrate113 is a resin multilayer circuit substrate in which all the layers have an interstitial via hole (IVH) construction.Circuit substrate113 has a plurality of viaholes119 at optional positions ofcore123 that forms an insulation layer. FIG. 3B is a partial enlarged view ofsemiconductor device100. By fillingconductor125 in viaholes119, conductivity across wiringlayers121 provided on the front surface and the rear surface ofcore123, respectively, is secured. The use of a resin multilayer circuit substrate of all-layer IVH construction forcircuit substrate113 can contain wiring at still higher density. Furthermore, because the resin multilayer circuit substrate of all-layer IVH construction provides high pressure resistance, whensemiconductor element101 is mounted tocircuit substrate113 with pressure applied, the mounting yield ofsemiconductor element101 can be improved.
• [0058]Electric connections120 correspond to electrode103 as an external electrode ofsemiconductor element101, bump105 provided onelectrode103, andelectrode103, respectively, and compriseselectrode115 provided oncircuit substrate113 andconductive paste111 that connectsbump105 andelectrode115.Electric connections120 exist in a plurality.Corresponding electrode103 andelectrode115 are electrically connected by the use ofintermediate connectors107 later discussed. That is,semiconductor element101 and circuit substrate are electrically connected. By securing electrical connections betweensemiconductor element101 andcircuit substrate113 by the use ofbump105 andconductive paste111, even when stress such as thermal impact, etc. is applied tosemiconductor device100,conductive paste111 absorbs stress concentrated to connections betweensemiconductor element101 andcircuit substrate113 and prevents electrical connections from being lost. Consequently, stable electrical connections can be secured.
• [0059]Intermediate connector107 is placed betweensemiconductor element101 andcircuit substrate113.Intermediate connector107 has viaholes109 for connectingsemiconductor element101 andcircuit substrate113 at the position corresponding toelectrodes103 andelectrodes115. Inside each viahole109,conductive paste111 and bump105 installed toelectrode103 are disposed in such a manner so as to be enclosed by anelectrode103 and anelectrode115.Conductive paste111 has horizontal flowout suppressed by the wall surface of viahole109. Thus, it is possible to preventconductive paste111 from spreading to adjoiningelectrical connections120 and from causing shorting across adjoiningelectrical connections120. Consequently,electrical connections120 can be disposed at a narrow pitch andsemiconductor element101 andcircuit substrate113 can be connected at a high density.
• Without[0060]intermediate connector107, stress is concentrated to the portion wheresemiconductor element101 andcircuit substrate113 join when temperature stress such as thermal shock is applied. However, withintermediate connector107, such concentration of the stress can be suppressed. This is because that full surface ofsemiconductor element101 is affixed tointermediate connector107, and therefore, such concentration of the stress applying only to the joining section can be avoided. The stress is generated due to difference of thermal expansion coefficients betweensemiconductor element101 andcircuit substrate113. Thus, particularly,intermediate connector107 is preferably formed with material which has a thermal expansion coefficient between those ofsemiconductor element101 and thermal expansion coefficient ofcircuit substrate113. Providing this kind ofintermediate connector107 in such a manner to closely come into contact withsemiconductor element101 andcircuit substrate113 can absorb stress arising from the above-mentioned thermal expansion coefficient difference by theintermediate connector107. Thus, the stress applied to connections betweensemiconductor element101 andcircuit substrate113 can be still more reduced.
• [0061]Intermediate connector107 may be, for example, electrically insulating resin, such as bonding sheet, etc. However, it is still more preferable to use electrically insulating base material which can be compressible in the thickness direction by pressurizing and heating. This is because joining betweenbump105 andconductive paste111 andelectrode115 oncircuit substrate113 can be still more strengthened. A more specific description will be made later referring to FIG. 4F. For compressible electrically insulating base material, prepreg with uncured epoxy resin immersed in, for example, Aramid nonwoven fabric in such a manner to leave vacancies, or film base material with uncured epoxy resin impregnated in porous film base material in such a manner to leave vacancies may be used. Because this kind of compressible electrically insulating base material has vacancies in base material, the epoxy resin constituent flows by heating and pressurizing and the vacancies are filled with resin. As a result, the electrically insulating base material contracts in the thickness direction.
• Referring now to FIGS. 4A through 4F, a description will be made on the first manufacturing process of semiconductor device[0062]100 (FIG. 3A).
• FIG. 4A is a diagram showing[0063]semiconductor element101. First of all, onsemiconductor element101, one ormore electrodes103 as conductive metal layers for electrically connecting to the outside ofsemiconductor element101 are formed by, for example, sputtering. The material ofelectrode103 is generally same as the wiring material ofsemiconductor element101, and for example, aluminum containing traces of silicon or copper. Furthermore, on the surface of anelectrode103, a conductive metal layer of various electrode materials such as nickel, copper, gold, etc. may be provided.
• Then, on[0064]electrode103 formed in this way,Au bump105 in the form of a two-level protrusion is formed. The reason whybump105 is not formed onelectrode115 provided incircuit substrate113 but formed onelectrode103 is that sincesemiconductor element101 provides better surface flatness thancircuit substrate113,bumps105 with less variations can be formed, and as a result, stable electrical connections with less variations according toelectrical connections120 can be secured. The shapes and materials ofbump105 are not limited to these.
• The procedure for forming[0065]bump105 in the form of a two-level protrusion will be described as follows. First of all, a ball formed at the Au wire head end is thermally crimped and the lower level section of the two-level protrusion, that is, the level on the side in contact withelectrode103, is formed. Then, using the Au wire loop formed by moving the capillary, the upper level section (head end section) is formed. In the drawing, the bump diameter at the head end section is smaller than the bump diameter at the lower level section. Under this condition, the height of two-level protrusion bump105 is not uniform and the flatness of the head end section lacks. Consequently, the two-level protrusion bump105 is pressurized to uniformalize the height and flatten the head end section. In this way, bump105 is formed onelectrode103.
• Now, FIG. 4B is a diagram[0066]showing circuit substrate113 withintermediate connector107 affixed. After affixing tocircuit substrate113, on the surface opposite tointermediate connector107,cover film106 is provided. By providing film material on one surface ofintermediate connector107 andcover film106 on the opposite surface in advance and laminating the film base material to the desired position oncircuit substrate113,intermediate connector107 may be affixed tocircuit substrate113. For laminating conditions, it is desirable to prevent thermosetting resin contained inintermediate connector107 from being completely cured. This is intended to obtain satisfactory adhesion whensemiconductor element101 andintermediate connector107 are laminated and affixed in the subsequent process.
• FIG. 4C is a diagram showing[0067]intermediate connector107 with a plurality of viaholes109 formed. To be more exact, viahole109 passes throughcover film106 andintermediate connector107. viahole109 is preferably formed using a laser. Laser processing is carried out untilelectrode115 oncircuit substrate113 is exposed. It should be noted that viahole109 is preferably formed with an inclination provided on its wall surface. Providing an inclination on the wall surface of viahole109 enables easier filling ofconductive paste111 when the via hole is filled withconductive paste111. When viahole109 is formed using a laser, the material which has properties to absorb wavelength of the laser used for processing is used forcover film106. In general, for example, PET film and PEN film are used.
• FIG. 5A is an enlarged view around via[0068]hole109 formed with an inclination inintermediate connector107. Because the opening diameter oncover film106 side of viahole109, that is, on the side to whichconductive paste111 is injected is formed to be greater than the opening diameter at the bottom of viahole109, the wall surface of viahole109 inclines. Thus,110conductive paste111 can be more easily filled. As clear from the drawing, viahole109 is formed even throughcover film106.Electrode115 formed oncircuit substrate113 is a conductive metal layer, such as a copper layer in general. In order to prevent copper surface degradation and to improve the adhesion to resin, on the conductive metal layer surface, in general, surface-treatedlayer116 with coating treatment by Cr, Zn, Ni, etc., organic rust preventive film treatment, etc. provided exist. The outermost surface of surface-treatedlayer116 is metal oxide coating and resin layer. However, surface-treatedlayer116 arrests the contact of conductive particles in conductive paste111 (FIG. 4D) filled in viahole109 with the conductive metal layer. Consequently, at the bottom of viahole109, electrical connections are hampered. That is, trade-off exists in that surface-treatedlayer116 is necessary from the viewpoint of preventing surface degradation and securing adhesion of conductive metal layer,electrode115, but is not desirable from the viewpoint of electrical connections at the bottom of viahole109.
• In the present embodiment, surface-treated[0069]layer116 is removed when viahole109 is formed. This is because surface degradation, etc. ofelectrode115 does not occur after the conductive paste is filled in viahole109 even if surface-treatedlayer116 is removed. Thus, the conductive particles in the conductive paste can be securely brought in contact with the conductive metal layer. Surface-treatedlayer116 is removed by chemicals, ion milling or dry etching under vacuum, oxide film removal in the reducing atmosphere, blasting in the inert atmosphere such as nitrogen, argon, etc., or other physical processing. Because surface-treatedlayer116 is removed by melting, etc. in this way, electrical connections can be secured while it is no longer necessary to form surface-treatedlayer116 as thin as possible as is the case of conventional ones and manufacturing becomes easy. FIG. 5B is a diagram showing the removal result of the surface treatedlayer116 portion exposed in viahole109. Thus, it is understood thatelectrode115 is exposed in viahole109.
• Note that, when via[0070]hole109 is formed using a laser, surface-treatedlayer116 may be removed as soon as viahole109 is formed by controlling laser energy, pulse width, shot number, etc. Or, with the heat generated at laser processing, surface-treatedlayer116 may be diffused inside the conductive metal layer and the ratio of metal material (e.g. copper) exposed may be increased on the bottom of viahole109. By these techniques, electrical connections between conductive paste andelectrode115 can be securely achieved.
• By removing the surface-treated layer present on the surface of[0071]electrode115 as described above, the conductive metal layer ofelectrode115 can be exposed at electrical connection120 (FIG. 3B) only of wiring and electrodes oncircuit substrate113. Consequently, the above-mentioned trade-off can be solved.
• During laser processing, the position of[0072]intermediate connector107 to which the laser is irradiated should be determined by the use of the measured value of the position ofelectrode115. This is becausecircuit substrate113 withelectrode115 formed includes the organic resin and is likely to cause dimensional changes due to heat and pressure in the manufacturing process so as to put out errors for dimension of patterns of designedcircuit substrate113.
• The measured value of[0073]electrode115 can be obtained by measuring the position of reference point ofcircuit substrate113 as viewed, for example, from the top of thecircuit substrate113. For the reference point, a marker provided in advance incircuit substrate113 for position measurement may be used orreference electrode115 is set and the edge may be used. The displacement on the plane coordinates between the reference point measured in this way and the design reference point ofcircuit substrate113 is reflected to the design processing position data entered in advance to correct the processing position data. By laser processing based on the corrected processing position data, viahole109 can be formed highly accurately at the position ofintermediate connector107 corresponding toelectrode115. If it is possible to think that there is no displacement, the laser irradiation position may be determined using the design value.
• Furthermore, in the similar manner, measuring the position of[0074]bump105 provided atsemiconductor element101 and reflecting the position data to the processing position data for correction can form viahole109 more highly accurately. Because Thus correction, viahole109 can be exactly formed according to the position ofbump105 andelectrode115, the alignment allowance for aligning can be set to be small. Consequently, semiconductor device100 (FIG. 3A) with electric connections120 (FIG. 3B) disposed at a still narrower pitch can be achieved. Furthermore, measuring positions of bothelectrode115 and bump105 enables the determination ofsemiconductor element101 which is originally not allowed to positionbump105 toelectrode115. Consequently, the yield can be further improved. In addition, since this judgment is made beforesemiconductor element101 is mounted tocircuit substrate113,semiconductor element101 which is judged unable to be mounted can be reused for a semiconductor element to be mounted to anothercircuit substrate113.
• Then, FIG. 4D is a diagram showing via[0075]hole109 afterconductive paste111 is filled.Conductive paste111 includes thermosetting resin and conductive particles. Thermosetting resin is, for example, phenol and epoxy, and functions as a binder. Conductive particles preferably comprise at least one of gold, silver, copper, silver palladium, and these alloys and are dispersed in the thermosetting resin. Conductive particles have less degraded layer such as oxidation, etc. that interferes with joining on the surface and achieve highly reliable electric connection. Note that,cover film106 has a role of protection for preventingconductive paste111 from adhering to the surface ofintermediate connector107 in the paste filling process.
• FIG. 4E is a diagram[0076]showing circuit substrate113 after aligning the position tosemiconductor element101. By the alignment,semiconductor element101 can be built by laminating tointermediate connector107. In alignment, cover film106 (FIG. 4C) can be peeled off. Whencover film106 is peeled off,conductive paste111 tends to protrude from the surface ofintermediate connector107 as much as the thickness ofcover film106. This protrudedconductive paste111 has a fear of inducing shorting across adjoiningelectric sections120 whensemiconductor element101 is laminated tointermediate connector107. Consequently, the protruded section should be reduced as much as possible, and to achieve this,cover film106 as thin as possible to the limit that would not break during handling should be used. Peeling offcover film106 can prevent processing chips during laser processing from adhering to the surface ofintermediate connector107.
• It is preferable to scrape away[0077]conductive paste111 filled to the surface ofcover film106 by a soft squeegee such as rubber, etc. after fillingconductive paste111 into viahole109 and to fillconductive paste111 in a concave form with care to preventconductive paste111 from coming in contact withcover film106, in addition to reducing the thickness ofcover film106.
• When[0078]conductive paste111 is filled by filling squeegee printing, conductive paste is densely filled from the via hole bottom to the surface (opening section) and then, a specified volume of conductive paste is scraped away from the via hole opening section. By setting squeegee hardness, squeegee angle, and squeegee travel speed at each process, stable filling and scraping of conductive paste can be successfully achieved.
• It is also allowed to fill via hole[0079]9 withconductive paste111 by a dispense method. The “dispense method” is a method for discharging a specified volume ofconductive paste111 from a container containingconductive paste111 by external force such as air pressure, etc. By using the dispense method, each viahole109 can be filled withconductive paste111 with less variations and at the same time, the pressure at the time of discharge can be optionally set and minute viahole109 can be filled withconductive paste111 at high density by setting high discharge pressure. In addition, using the dispense method and the scrape-away process by a squeegee in combination can further suppress variations of the filling volume.
• The volume of[0080]conductive paste111 filled in viahole109 is preferably set to the value greater than the one obtained from subtracting the volume ofbump105 from the volume of viahole109 and smaller than the volume of viahole109. Setting the volume ofconductive paste111 filled in viahole109 to this range can compress and densifyconductive paste111 while suppressing stick-out ofconductive paste111 from viahole109 whenbump105 is buried inconductive paste111 in the subsequent process.
• FIG. 4F is a diagram[0081]showing circuit substrate113 withsemiconductor element101 laminated.Bump105 is buried inconductive paste111 in viahole109 andsemiconductor element101 is laminated onintermediate connector107. By heating and pressurizing thereafter, electrical connections can be secured betweenbump105,conductive paste111, andelectrode115 oncircuit substrate113.
• Forming an inclination on the wall surface of via[0082]hole109 allows the wall surface of viahole109 to serve as a guide for guidingbump105 at the time of heating and pressurizing. Consequently, even if the lamination position slightly deviates, bump105 would not come off fromelectrode115 oncircuit substrate113 as a result. In addition, because heating and pressurizing withbump105 buried inside viahole109, displacement between semiconductor/elment101 andcircuit substrate113 can be suppressed.
• When[0083]bump105 is buried inconductive paste111 in viahole109,bump105 has a wider surface in contact withconductive paste111 and electrical connection becomes more stabilized. Furthermore, a construction difficult to degrade connections betweenbump105 andconductive paste111 is achieved even when stress is concentrated to the connections, which is preferable. This is particularly conspicuous whenbump105 has a higher two-level protruding form than when the height is of one level. Furthermore, by heating and pressurizing in such occasion,conductive paste111 may be compressed withbump105 and conductive particles inconductive paste111 may be densified. Thus, electrical connections are still more stabilized betweenbump105 andconductive paste111 andelectrode115 oncircuit substrate113, which is preferable.
• When[0084]conductive paste111 is densified by heating and pressurizing, it is preferable to densify while sealing the opening section of viahole109 with a care to prevent conductive particles contained inconductive paste111 from flowing out in the plane direction, that is, in the spreading direction ofsemiconductor element101. That is, to densifyconductive paste111 by compressive force, a clearance that allows the resin components contained inconductive paste111 to flow out from the sealed section but conductive particles do not flow out is provided at the interface betweenintermediate connector107 andsemiconductor element101 or at the interface betweenintermediate connector107 andcircuit substrate113.
• The clearance provided at the interface between[0085]intermediate connector107 andsemiconductor element101 can be formed by coarsening the uncured resin surface exposed to the surface ofintermediate connector107 and setting the surface roughness to the particle size or smaller of conductive particles contained inconductive paste111. On the other hand, for the clearance provided at the interface betweenintermediate connector107 andcircuit substrate113, it would be much more convenient to coarsen the surface ofelectrode115 formed on the surface ofcircuit substrate113 in advance and provide a desired clearance at the interface withintermediate connector107. In addition, the same effects can be obtained when porous material containing vacancies inside is used forintermediate connector107 and resin components contained inconductive paste111 only are allowed to flow out inintermediate connector107.
• [0086]Intermediate connector107 disposed oncircuit substrate113 without completely curing the thermosetting resin in the process shown in FIG. 4B contracts in the thickness direction and compressesconductive paste111 more and at the same time completely cures in the heating and pressurizing process after buryingbump105 inconductive paste111 in the process of FIG. 4F. Thus, joining betweenbump105,conductive paste111, andelectrode115 oncircuit substrate113 can be still more strengthened. Consequently,semiconductor element101 andintermediate connector107 are still more strongly affixed and Thus strong adhesion, exfoliation ofsemiconductor element101 fromcircuit substrate113 is suppressed. It is more preferable to set the curing ratio of thermosetting resin ofintermediate connector107 to 50% or less under the conditions shown in FIG. 4B from the viewpoint of securing the adhesion withsemiconductor element101 in the heating and pressurizing process shown in FIG. 4F. The curing ratio can be controlled according to temperature and time.
• By the process described above, it is possible to obtain semiconductor device[0087]100 (FIG. 3A) according to embodiment 1. In FIG. 4A, it was described thatbump105 has the bump diameter at the head end section is smaller than the bump diameter at the lower end section. However, the bump diameter at the head end section may be greater than the bump diameter at the lower level section. Using the bump with the bump diameter greater at the head end section, it is possible to heighten the anchoring effects betweenconductive paste111 andbump105. Consequently, even when pulling force in the vertical direction is applied acrosssemiconductor element101 andcircuit substrate113, bonding betweenbump105 andconductive paste111 can be maintained. A procedure for forming this kind of bump will be described referring to FIGS. 6A through 6E.
• FIGS. 6A through 6E are diagrams showing a procedure for forming[0088]bump105 with a bump diameter greater than the lower level section. Here, a bump of a type different from the two-level protrusion will be described. FIG. 6A is a diagram showingsemiconductor element101. First of all, onsemiconductor element101,electrode103 is formed for electrically connecting to the outside ofsemiconductor element101.
• FIG. 6B shows[0089]semiconductor element101 with photo resist104 applied. Photo resist104 is applied to the surface ofsemiconductor element101 on whichelectrode103 is formed. Photo resist104 may be of a negative or a positive type.
• FIG. 6C shows photo resist[0090]104 with a pattern exposed to the light in a tapered form. This kind of pattern is obtained by exposing the pattern to photo resist104 using a photo mask and developing thereafter. To achieve a tapered form, appropriate exposure and developing conditions should be set. For example, when the negative type is used for photo resist104, the exposure and developing conditions should be set to achieve over-exposure. Thus, a pattern of a tapered form can be formed easily on photo resist104.
• Next, FIG. 6D shows[0091]metal105 formed by plating.Metal105 is the bump base material, that is,bump105 itself.Metal105 can be obtained by allowing exposedelectrode103 to deposit by plating. Bump105 can be flattened by carrying out deposition with care to prevent metal deposition material from protruding from the surface of photo resist104. It is desirable to use gold, silver, copper, and alloys of these for the metal deposition material by plating from the viewpoint of more stable joining with conductive paste111 (FIG. 3A).
• Lastly, FIG. 6E is a diagram showing[0092]semiconductor element101 withbump105 of a larger bump diameter at the head end section. Bump105 can be obtained by removing photo resist104 atsemiconductor element101 of FIG. 6D.
• In FIG. 6D, metal may be deposited in such a manner that the metal material protrudes on the surface of photo resist[0093]104. By allowing metal to be deposited in such a manner that the metal material protrudes, bump105 takes a mushroom form. FIG. 7 is a diagram showingsemiconductor element101 where mushroom-form bump105 is formed. Bybump105 being of a mushroom form, anchoring effects betweenconductive paste111 and bump105 are further improved and still more satisfactory connection stability can be secured.
• In addition, for[0094]intermediate connector107, the base material of 3-layer construction with adhesive layers provided on both surfaces of the film base material may be used. Whensemiconductor element101 is laminated onintermediate connector107, the film base material that serves the core ofintermediate connector107 can maintain its profile. Consequently, the wall surface of viahole109 suppresses the spread ofconductive paste111, compressive force is applied toconductive paste111, and the bond betweenbump105 andconductive paste111 andelectrode115 can be further strengthened. The adhesive layers provided on both surfaces of the film material affixintermediate connector107 tosemiconductor element101 andcircuit substrate113, respectively. Furthermore, since the adhesive layers contract in the thickness direction by pressurization and heating whensemiconductor element101 is laminated tointermediate connector107,conductive paste111 can be still more densified.
• When the 3-layer construction film base material is used for[0095]intermediate connector107, there exist still another advantage. That is, the thickness ofintermediate connector107 can be reduced. Whenelectric connections120 are disposed at a still narrower pitch, the diameter of viahole109 must be further reduced. In such event, reducing the diameter of viahole109 alone causes the aspect ratio of the diameter to the depth of viahole109 increases. On the other hand, when viahole109 is filled withconductive paste111, it is desirable that the aspect ratio is smaller. This is becauseconductive paste111 can be filled stably. Consequently, ifintermediate connector107 is formed by the use of film base material, the thickness can be reduced and the increase of the aspect ratio can be prevented. Furthermore,electrical connections120 can be disposed at a narrow pitch. Specifically, whenintermediate connector107 is formed by the use of film base material and viahole109 is made smaller, the thickness of film base material becomes super-thin as 50 μm or less.
• When the film base material becomes as thin as this level, it is difficult to handle[0096]intermediate connector107 independently. For example, ifintermediate connector107 has a certain thickness, it is not necessary to placeintermediate connector107 in advance oncircuit substrate113 in FIG. 4B. That is, it is possible to laminate and affixsemiconductor element101 andcircuit substrate113 after forming a via hole inintermediate connector107 and is filled withconductive paste111. However, whenintermediate connector107 is extremely thin, this process cannot be adopted. FIG. 8A is a diagram showingintermediate connector107 with the via hole filled withconductive paste111 before affixingsemiconductor element101 to circuit substrate. Sinceintermediate connector107 is thin,conductive paste111 protrudes from both ends of the via hole provided to theintermediate connector107. Whensemiconductor element101 is affixed tocircuit substrate113 by the use of this kind ofintermediate connector107, protrudedconductive paste111 is spread in the plane direction in heating and pressurizing process. FIG. 8B is a diagram showingintermediate connector107 aftersemiconductor element101 andcircuit substrate113 are affixed. Thus configuration, electric shorting occurs at adjoining connections when the pitch between via hole (connections) is made narrower.
• Consequently, the process for forming[0097]intermediate connector107 in advance oncircuit substrate113 as described above is desirable. According to this process, the opening surface of the via hole for which conductive paste protrusion must be suppressed is in one direction, and can be easily controlled in the scarping process whenconductive paste111 is filled. FIG. 9A is a diagram showingintermediate connector107 withconductive paste111 filled into viahole109 before the intermediate connector is affixed tosemiconductor element101 after it is affixed tocircuit substrate113. It is understood that by controlling the volume ofconductive paste111 in the process to fillconductive paste111, noconductive paste111 is protruded from the surface ofintermediate conductor107. Thus, it is possible to suppress the spread ofconductive paste111 in the plane direction at both end faces of the via hole in the heating and pressurizing process. FIG. 9B is a diagram showingintermediate connector107 aftercircuit substrate113 is affixed tosemiconductor element101. Thus, even when the connections are disposed at a further narrower pitch, electrical shorting can be prevented. In addition,conductive paste111 can be retained without leak as one side of via hole109 (i.e.circuit substrate113 side) closes. Therefore, only one control such as scraping at the time of fillingconductive paste111 is required, and the manufacturing process can be simplified.
• In the present embodiment, for[0098]circuit substrate113, description is made by using the resin multilayer circuit substrate of total-layer IVH construction. However, the construction ofcircuit substrate113 is not restricted to this. The same effects are obtained even by using, for example, glass epoxy substrate and buildup substrate forcircuit substrate113.
• Referring now to FIGS. 10A through 10F, the second manufacturing method of semiconductor device[0099]100 (FIG. 3A) according to embodiment 1 will be described. If the description overlaps the description made referring to FIGS. 4A through 4F, the detailed description will be omitted.
• FIG. 10A is a[0100]diagram showing semiconductor101 and is the same as FIG. 4A. Onsemiconductor element101,electrode103 is formed, further on which 2-levelprotrusion form bump105 is formed.
• FIG. 10B is a diagram showing[0101]conductive paste111 withconductive paste111 transferred to the head end ofbump105. As clear from this,conductive paste111 is not directly filled into viahole109 ofintermediate connector107 as shown in FIG. 4D.
• Then, FIG. 10C is a diagram[0102]showing circuit substrate113 withintermediate connector107 affixed to the surface. Needless to say, whenintermediate connector107 is affixed, same as FIG. 4B,intermediate connector107 is not completely cured.
• FIG. 10D is a diagram showing[0103]intermediate connector107 with a plurality of viaholes109 formed. This is same as FIG. 4C. Note that, in FIG. 10D, there described is an example when cover film106 (FIG. 4B, FIG. 4C) is not formed on the surface ofintermediate connector107. However, ifcover film106 is formed on the surface ofintermediate connector107 and is peeled off after viahole109 is laser-processed, processing chips during laser processing can be prevented from affixing to the surface ofintermediate connector107.
• FIG. 10E is a diagram[0104]showing circuit substrate113 after aligning the position tosemiconductor element101. In order to laminate and disposesemiconductor element101 tointermediate connector107, bump105 withconductive paste111 provided and viahole109 are positioned.
• Lastly, FIG. 10F is a diagram[0105]showing circuit substrate113 withsemiconductor element101 laminated. Bump105 andconductive paste111 are accommodated in viahole109 andpaste111 is cured by heating and pressurizing. Making the best of this heating and pressurizing,conductive paste111 is compressed bybump105 and conductive particles inconductive paste111 may be densified. Thus, electrical connections betweenbump105 andconductive paste111 andelectrode115 oncircuit substrate113 are further stabilized and are desirable. By the above-mentioned second manufacturing method,semiconductor device100 is completed.
• Even in the second manufacturing method, same as the first manufacturing method, when[0106]conductive paste111 is sealed into thoughhole109, a clearance that prevents conductive particles contained inconductive paste111 from flowing out but that allows resin component only to flow out may be formed. The clearance may be formed at the interface betweenintermediate connector107 andsemiconductor element101, or at the interface betweenintermediate connector107 andcircuit substrate113. Thus, the conductive paste can be densified in the heating and pressurizing process and at the same time, electrical shorting with adjoining connections can be suppressed.
• As described above, semiconductor device[0107]100 (FIG. 3A) according to embodiment 1 hasintermediate connector107 equipped with viahole109 located at the positions corresponding to electrode105 ofsemiconductor element101 andelectrode115 ofcircuit substrate113 between thesemiconductor element101 andcircuit substrate113. Electrical connections betweenelectrode103 andelectrode115 are achieved by buryingbump105 formed onelectrode103 intoconductive paste111 filled into viahole109. Becauseconductive paste111 is sealed inside viahole109, it is possible to preventconductive paste111 from being spread to adjoiningelectric connections120 and from causing shorting of adjoiningelectric connections120. Consequently,electric connections120 can be provided at a still narrower pitch.
• In addition, via[0108]hole109 is formed after reflecting the measured value of the position ofelectrode115 incircuit substrate113 and the measured value of the position ofbump105 insemiconductor element101 to the design processing data for processing and correcting the processing data. Consequently, viahole109 can be formed at a higher accuracy and the packaging yield can be improved. Furthermore,electric connections120 can be disposed at a still narrower pitch.
• In addition, because semiconductor device[0109]100 (FIG. 3A) hasbump105 buried inconductive paste111 in viahole109, even when shearing force in the horizontal direction (plane direction) is applied acrosssemiconductor element101 andcircuit substrate113,bump105 does not come off fromconductive paste111 and electrical connections can be stably maintained. In addition, according to the first and the second manufacturing methods of the semiconductor device by embodiment 1, processing of viahole109, filling ofconductive paste111, and heating and pressurizing can be carried out en bloc. Consequently, a plurality of semiconductor elements can be mounted on a large-sized circuit substrate en bloc and excellent productivity can be achieved.
• (Embodiment 2)[0110]
• FIG. 11A is a cross-sectional view showing the construction of[0111]semiconductor device900 according to embodiment 2. FIG. 11B is a partial enlarged view ofsemiconductor device900. In embodiment 1, onelectrode103 of semiconductor element101 (FIG. 3B),bump105 is provided.Semiconductor device900 according to the present embodiment hasbump105 provided onelectrode115 ofcircuit substrate113. Other configurations, for example, thatelectrode103 onsemiconductor element101 andelectrode115 oncircuit substrate113 are electrically connected viabump105 andconductive paste111 and that the wall surface of viahole109 suppresses the flowout ofconductive paste111 and prevents defective shorting across adjoiningelectrical connections120, are same as embodiment 1.
• Referring now to FIGS. 12A through 12F, the manufacturing process of semiconductor device[0112]900 (FIG. 11A) according to embodiment 2 is described. First of all, FIG. 12A is a diagramshowing circuit substrate113. Oncircuit substrate113,electrode115 for electrically connecting tosemiconductor101 is formed. Furthermore, bump105 is formed onelectrode115. In embodiment 2, the two-level protrusion form bump is used forbump115. Same as embodiment 1, thebump105 form is not limited to this.
• Next, FIG. 12B is a diagram showing[0113]semiconductor element101 withintermediate connector107 affixed. On the surface ofintermediate connector107,cover film106 is formed. In the process for affixingintermediate connector107, it is desirable not to completely cure thermosetting resin contained inintermediate connector107.
• Furthermore, FIG. 12C is a diagram showing[0114]intermediate connector107 with viahole109 formed. To be more exact, viahole109 passes throughcover film106 andintermediate connector107. viahole109 passes throughcover film106 andintermediate connector107. It is desirable to form viahole109 using laser. Laser processing is carried out untilelectrode103 onsemiconductor element101 is exposed. When viahole109 is formed using laser processing, the measured value ofbump105 provided oncircuit substrate113 and the measured value ofelectrode103 provided onsemiconductor element101 are reflected to the design processing data and the processing data is corrected. And it is desirable to process viahole109 thereafter.
• FIG. 12D is a diagram showing via[0115]hole109 withconductive paste111 filled. The technique for filling a desired volume ofconductive paste111 is same as that described in embodiment 1.
• Next, FIG. 12E is a diagram[0116]showing circuit substrate113 after aligning the position tosemiconductor element101. The positions ofbump105 withconductive paste111 provided and viahole109 are aligned for laminating and disposingsemiconductor element101 tointermediate connector107. In this process,cover film106 is peeled off fromintermediate connector107.
• FIG. 12F is a diagram[0117]showing circuit substrate113 withsemiconductor element101 laminated.Bump105 is buried inconductive paste111 inside viahole109 by heating and pressurizing and at the same time,intermediate connector107 is affixed tocircuit substrate113. Thus, electrical connections betweenbump105,conductive paste111, andelectrode103 ofsemiconductor element101 are secured. Furthermore, by heating and pressurizing in such event,conductive paste111 may be compressed bybump105. Thus, conductive particles insideconductive paste111 are densified and still more stable electrical connections are achieved betweenbump105,conductive paste111, andelectrode103 ofsemiconductor element101. In this way, by the above-mentioned manufacturing method,semiconductor device900 is completed.
• Semiconductor device[0118]900 (FIG. 11A) of the present embodiment differs from semiconductor100 (FIG. 3A) of embodiment 1 in thatbump105 is formed onelectrode115 ofcircuit substrate113. In general,electrode115 formed incircuit substrate113 is frequently formed by the use of conductive metal layer or copper plating, and the thickness ranges 18 μm to 35 μm. This is frequently thicker thanelectrode103 formed on the side ofsemiconductor element101. Consequently, in the lamination and affixing process by heating and pressurizing shown in FIG. 12F, laminating and disposingintermediate connector107 incircuit substrate113 in such a manner that electrode115 is buried in viahole109 can compress and densifyconductive paste111 further more.
• Note that, in the present embodiment, bump[0119]105 is formed only on the side ofcircuit substrate113. Formingbump105 also on the side ofsemiconductor element101 achieves still higher reliability of electrical connections.
• FIG. 13 is a cross-sectional diagram showing the overall construction of[0120]semiconductor device910 according to a variation of embodiment 2.Semiconductor device910 has electrode115 oncircuit substrate113 formed more thickly and used in place of bump105 (FIG. 11B). Even burying thiselectrode115 inconductive paste111 in viahole109 can produce the advantages same as those obtained from semiconductor devices described by now. Adopting this kind of construction can eliminate thebump105 forming process and achieves better productivity.
• (Embodiment 3)[0121]
• FIG. 14 is a cross-sectional view showing the overall construction of[0122]semiconductor device1200 according to embodiment 3.Semiconductor device1200 is composed withsemiconductor element101 in semiconductor device100 (FIG. 3A) replaced with packagedstructure805 of semiconductor element.
• [0123]Semiconductor device1200 comprises packagedstructure805,intermediate connector107,circuit substrate113, andelectrical connections130.Intermediate connector107 andcircuit substrate113 are same as embodiments 1 and 2 and detailed description will be omitted.
• Packaged[0124]structure805 hascircuit substrate802,semiconductor element801 mounted on it,metal wire803 for electrically connectingcircuit substrate802 andsemiconductor element801, andmold resin806 provided on the surface ofcircuit substrate802 in such a manner to coversemiconductor element801 andmetal wire803.
• In this embodiment, packaged[0125]structure805 forpackaging semiconductor element801 secures electrical connections withsemiconductor element801 andcircuit substrate802 by wire bonding. However, the packaged structure is not limited to this configuration but packagedstructure805 may electrically connectsemiconductor element801 andcircuit substrate802 by the use of flip-chip. Or packagedstructure805 may be of configurations of so-called semiconductor packages such as chip size package (CSP), ball grid array (BGA), etc.
• [0126]Electrical connections130 are external electrodes of packagedstructure805.Electrical connections130 has electrode804 electrically connected to part of the electrodes ofsemiconductor element801, bump105 provided inelectrode804,electrode115 provided incircuit substrate113 and corresponding to each ofelectrodes804, andconductive paste111 for connectingbump105 andelectrode115.Electrode804 andelectrode115 are connected via intermediate electricalconnections comprising bump105 andconductive paste111, and electrically connect packagedstructure805 andcircuit substrate113.
• In general, packaged[0127]structure805 forms a solder ball onelectrode804 and is electrically connected tocircuit substrate113 by solder connection. However, whenelectrode804 is provided at a narrower pitch, there are cases to cause defective shorting across adjoining solder balls. Therefore, insemiconductor device1200 according to embodiment 3, packagedstructure805 is intended to be mounted tocircuit substrate113 at a narrower pitch without generating shorting across adjoiningelectrical connections130.
• [0128]Semiconductor device1200 hasbump105 formed onelectrode804 of packagedstructure805 and bump105 buried inconductive paste111 filled in viahole109 provided inintermediate connector107. Thus,circuit substrate113 and packagedstructure805 are electrically connected. Furthermore, compressingconductive paste111 bybump105 whenbump105 is buried inconductive paste111 can achieve much more stable electrical connection acrosscircuit substrate113 and packagedstructure805. By usingconductive paste111 for electrical connection betweencircuit substrate113 and packagedstructure805 in this way, stress applied to both connection sections ofcircuit substrate113 and packagedstructure805 can be relaxed same as described in embodiment 1, and stable electrical connections can be achieved against dimensional changes caused by thermal shock, etc. In addition, becauseconductive paste111 is confined in viahole109,conductive paste111 does not stick out to adjoiningelectrical connections130 and does not cause shorting in adjoiningelectrical connections130. Consequently,electrical connections130 can be disposed at a still narrower pitch.
• Note that, in the present embodiment, a configuration with[0129]bump105 formed on theelectrode804 side is shown. However, bump105 may be formed on theelectrode115 side ofcircuit substrate113. Furthermore, bump105 may be formed on bothelectrode804 side andelectrode115 side.
• The shape of[0130]bump105 is not restricted to the two-level protrusion form and bumps of other materials or other forms shown in embodiment 1 may be used.
• The electronic parts disposed in[0131]circuit substrate113 viaelectrical connections130 at a narrow pitch are not limited to semiconductor elements and semiconductor packaged structures. The same effects can be obtained even when filters, modules, and other electronic parts are used.
• The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.[0132]

Claims (17)

What is claimed is:

1. A method for manufacturing a semiconductor device with a semiconductor section and a circuit substrate electrically connected, comprising:

a forming process which forms semiconductor electrodes at the semiconductor section,

a forming process which forms substrate electrodes on the circuit substrate,

a first affixing process which affixes one part of the semiconductor section and the circuit substrate to an intermediate connector made of insulating material,

a forming process which forms via hole s in the intermediate connector according to positions of the semiconductor electrodes and positions of the substrate electrodes,

a connecting process which electrically connects each of the semiconductor electrodes and each of the substrate electrodes via each of the via holes, and

a second affixing process which affixes the other part of the semiconductor section and the circuit substrate to the intermediate connector.

2. The method for manufacturing a semiconductor device according toclaim 1, wherein the connecting process comprising:

a forming process which forms bumps on at least one of the semiconductor electrodes and the substrate electrodes;

a filling process which fills conductive paste into the each via hole; and

a connecting process which buries each of the bumps in the conductive paste in the each via hole to electrically connect the each semiconductor electrode and the each substrate electrode via the each bump and the conductive paste.

3. The method for manufacturing a semiconductor device according toclaim 1, wherein the forming process which forms via holes comprises:

a measuring process which measures at least one of positions of the semiconductor electrodes and positions of the substrate electrodes to obtain positional data;

a specifying process which specifies positions on the intermediate connector based on the measured positional data; and

a forming process which forms the each via hole at each of the specified positions on the intermediate connector.

4. The method for manufacturing a semiconductor device according toclaim 2, wherein each of the semiconductor electrodes and each of the substrate electrodes are metal layers with films, each metal layer containing resin formed on the surface, and

wherein the forming process which forms the via holes removes the films to expose the metal layers.

5. The method for manufacturing a semiconductor device according toclaim 4, wherein the forming process which forms the via holes forms each wall surface inclined.

6. The method for manufacturing a semiconductor device according toclaim 2, wherein the filling process comprises:

an injecting process which injects the conductive paste from the bottom to the opening section of the each via hole; and

a scraping process which scraps away a predetermined volume of the conductive paste from the opening section.

7. The method for manufacturing a semiconductor device according toclaim 6, wherein the injecting process applies pressure to the conductive paste to discharge the conductive paste and injects the conductive paste from the bottom to the opening section of the each via hole.

8. The method for manufacturing a semiconductor device according toclaim 1, wherein the first affixing process and the second affixing process bring the intermediate connector in close contact with the semiconductor section and the circuit substrate by pressurizing and include a sealing process which seals the each via hole.

9. The method for manufacturing a semiconductor device according toclaim 8, wherein the conductive paste contains conductive particles and non-conductive resin, and

wherein the sealing process comprises:

a providing process which provides a clearance, through which the nonconductive resin alone to flow, at an interface between the intermediate connector and at least one part of the semiconductor section and the circuit substrate; and

a densifying process which densifies the conductive paste by pressurizing and allowing the nonconductive resin to flow from the each via hole to seal the each via hole with the conductive particles remained.

10. The method for manufacturing a semiconductor device according toclaim 1, wherein the intermediate connector is further made of a material that contracts by pressurizing, and

wherein the first affixing process and the second affixing process contract the intermediate connector by pressurizing to densify the conductive paste.

11. The method for manufacturing a semiconductor device according toclaim 1, wherein the intermediate connector is further made of thermosetting resin, and

wherein the first affixing process hardens part of the intermediate connector containing thermosetting resin by heating to affix the semiconductor section and the circuit substrate to the intermediate connector.

12. The method for manufacturing a semiconductor device according toclaim 11, wherein the second affixing process hardens the intermediate connector by heating to affix the semiconductor section and the circuit substrate to the intermediate connector.

13. The method for manufacturing a semiconductor device according to claim6, wherein the injecting process applies pressure to the conductive paste to discharge with volume smaller than first volume of each via hole and greater than second volume obtained by subtracting volume of each bump from the first volume.

14. A semiconductor device comprising;

a semiconductor section with semiconductor electrodes;

a circuit substrate with substrate electrodes; and

an intermediate connector affixed to the semiconductor section and the circuit substrate therebetween, said intermediate connector made of insulating material, having via holes with conductive paste filled, said intermediate connector electrically connecting each of the semiconductor electrodes and each of the substrate electrodes via the conductive paste in each of the via holes,

wherein the each semiconductor electrode and the each substrate electrode are metal layers with films, each metal layer containing resin formed on the surface and contacting with the conductive paste with the film removed in the each via hole.

15. The semiconductor device according toclaim 14, wherein the each via hole has wall surface inclined.

16. The semiconductor device according toclaim 14, wherein the bumps are formed on at least one part of the semiconductor electrodes and the substrate electrodes.

17. The semiconductor device according toclaim 16, wherein the each bump has a two-level protrusion form.

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