US20020096764A1 - Semiconductor device having bump electrode - Google Patents

Abstract

A semiconductor device having bump electrodes mainly comprises a specialized under bump metallurgy (UBM) applied to a chip with copper contact pads. Typically, the chip comprises a substrate and at least one copper contact pad on the substrate. A passivation layer is formed over the substrate and has an opening positioned over the al least one copper contact pad. The UBM includes a titanium layer, a first copper layer, a nickel-vanadium layer and a second copper layer. The titanium layer forms a closed-loop surrounding the opening of the dielectric layer. The first copper layer is formed over the titanium layer and the opening of the dielectric layer such that the first copper layer directly contacts the copper contact pad. The nickel-vanadium layer is formed on the first copper layer and the second copper layer is formed on the nickel-vanadium layer. A metal bump is provided on the UBM over the copper contact pad thereby forming a bump electrode. The UBM of the present invention is characterized by using the titanium layer with a closed-loop shape as the adhesion layer to significantly increase the adhesion between the UBM and the passivation layer, and using the first copper layer, which is directly contacted with the copper contact pad, to provide a better electrical performance.

Description

BACKGROUND OF THE INVENTION
• 1. Field of the Invention[0001]
• This invention relates to electronic assembly technology and more specifically to solder bump interconnections for mounting chip with copper I/O pads to an interconnection substrate.[0002]
• 2. Description of the Related Art[0003]
• As chips continued to decrease in size, pure copper circuits had undeniable advantages that the traditional aluminum interconnects could not match. Copper wires conduct electricity with about 40 percent less resistance than aluminum. That translates into a speedup of as much as 15 percent in microprocessors that contain copper wires. Furthermore, copper wires are also far less vulnerable than those made of aluminum to electromigration, the movement of individual atoms through a wire, caused by high electric currents, which creates voids and ultimately breaks the wires. Most important, the widths of copper wires can be squeezed down to the 0.2-micron range from the current 0.35-micron widths—a reduction far more difficult for aluminum. Because the conventional aluminum alloys can't conduct electricity well enough, or withstand the higher current densities needed to make these circuits switch faster when wires with very small dimensions is used. Gradually, chip with copper interconnects will substitute for chip with traditional aluminum interconnects.[0004]
• Moreover, as electronic devices have become more smaller and thinner, the velocity and the complexity of IC chip become more and more higher. Accordingly, a need has arisen for higher package efficiency. Demand for miniaturization is the primary catalyst driving the usage of advanced packages such as chip scale packages (CSP) and flip chips. Both of them greatly reduce the amount of board real estate required when compared to the alternative ball grid array (BGA) and quad flat pack (QFP). Typically, a CSP is 20 percent larger than the die itself, while the flip chip has been described as the ultimate package precisely because it has no package. The bare die itself is attached to the substrate by means of solder bumps directly attached to the die.[0005]
• Flip-chip bumping technology typically comprises (a) forming an under bump metallurgy (UBM) on bonding pads of the chip, and (b) forming metal bumps on the UBM. Typically, UBM consists of three metal layers, including: (a) adhesion layer (formed of Al or Cr) for purposes of providing a good adhesion to Al pad and passivation layer; (b) barrier layer (formed of NiV or TiW) for preventing contact pads on the chip and the bump electrode from reacting with each other to generate an intermetallic compound (which is harmful to the reliability of chip); and (c) wetting layer (formed of Ni, Cu, Mo or Pt) wherein that kind of metals provide a higher wetting power to solder thereby allowing for proper wetting of solder during solder-reflow process. Typically, the metal bump is made of conductive material (such as metal high melting point solder alloys, low melting point solder alloys, gold, nickel or copper), depending on the characteristics needed in the to-be-formed flip-chip.[0006]
• FIG. 1 is a cross sectional view of a conventional semiconductor having a bump electrode. An[0007]aluminum contact pad110 is formed on asubstrate120 of a semiconductor integrated circuit. Apassivation film130, serving as an insulation film, is formed on the entire surface of thesubstrate120. A passivation opening section which is formed at a predetermined position, is formed to expose thealuminum contact pad110. Thesemiconductor device100 has aUBM140 consisting of three metal layers, including: (a) aluminum layer140aused as the adhesion layer; (b) nickel-vanadium layer140bused as the barrier layer; and (c)copper layer140cused as the wetting layer.
• However, the UBM[0008]140 is not applicable to chip with copper contact pads because of poor aluminum-to-copper adhesion. Therefore, the semiconductor industry develops a semiconductor device200 (see FIG. 2) wherein the UBM240 consists of two metal layers, including: (a)titanium layer240aused as the adhesion layer and the barrier layer; and (b)copper layer240bused as the wetting layer. Although the titanium layer has a good adhesion to both of thepassivation layer130 and thecopper contact pad210, it has a disadvantage of poor electric conductivity as compared to a copper layer.
• The present invention therefore seeks to provide an under bump metallurgy which overcomes, or at least reduces the above-mentioned problems of the prior art.[0009]
SUMMARY OF THE INVENTION
• It is a primary object of the present invention to provide an under bump metallurgy (UBM) adapted for chip with copper contact pads wherein the UBM is capable of providing a better electrical performance.[0010]
• It is another object of the present invention, by integrating the UBM of the present invention with I/O distribution, to provide a semiconductor device having a structure that permits rearrangement of contact pads and provides a better electrical performance.[0011]
• The UBM of the present invention is applied to a chip with copper contact pads in order to form a semiconductor device having bump electrodes. Typically, the chip comprises a substrate and at least one copper contact pad on the substrate. A passivation layer is formed over the substrate and has an opening positioned over the al least one copper contact pad. The UBM includes a titanium layer, a first copper layer, a nickel-vanadium layer and a second copper layer. The titanium layer forms a closed-loop surrounding the opening of the dielectric layer. The first copper layer is formed over the titanium layer and the opening of the dielectric layer such that the first copper layer directly contacts the copper contact pad. The nickel-vanadium layer is formed on the first copper layer and the second copper layer is formed on the nickel-vanadium layer. A metal bump is provided on the UBM over the copper contact pad thereby forming a bump electrode. Consequently, the semiconductor device of the present invention can be directly mounted to a interconnection substrate by means of bump electrodes directly attached thereon.[0012]
• The UBM of the present invention is characterized by using the titanium layer with a closed-loop shape as the adhesion layer to significantly increase the adhesion between the UBM and the passivation layer, and using the first copper layer, which is directly contacted with the copper contact pad, to provide a better electrical performance.[0013]
• The present invention further provides a semiconductor device having a structure that permits rearrangement of contact pads. The semiconductor device comprises a substrate having a copper contact pad formed thereon; a first dielectric layer formed over the substrate, the first dielectric layer having a first opening positioned over the copper contact pad; a multi-layered lead having a first end portion connected to the copper contact pad through the first opening and a second end portion extending on the first dielectric layer; a second dielectric layer formed over the multi-layered lead and the first dielectric layer, the second dielectric layer having a blind-via formed corresponding to the second end portion of the multi-layered lead; a conductive pad formed over the blind-via; and a metal bump provided on the conductive pad. The multi-layered lead includes a first titanium layer on the first dielectric layer, a copper layer on the first titanium layer and a second titanium layer on the copper layer wherein the first titanium layer has a second opening corresponding to the first opening and the copper layer directly contacts the copper contact pad through the second opening and the first opening.[0014]
BRIEF DESCRIPTION OF THE DRAWINGS
• Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.[0015]
• FIG. 1 is a schematic sectional view of a conventional semiconductor device having a bump electrode;[0016]
• FIG. 2 is a schematic sectional view of another conventional semiconductor device having a bump electrode;[0017]
• FIGS.[0018]3-6 illustrate in cross-section major steps of formation of the UBM in accordance with the present invention;
• FIG. 7 is a schematic sectional view of a portion of a semiconductor device having a bump electrode in accordance with a preferred embodiment of the present invention; and[0019]
• FIG. 8 is a schematic sectional view of a portion of a semiconductor device having a bump electrode in accordance with another preferred embodiment of the present invention.[0020]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
• As shown in FIG. 7, a semiconductor device include a[0021]substrate310, acopper contact pad320, and a dielectric layer such aspassivation layer330. Thesubstrate310 may comprise a layer of a semiconducting material such as silicon, gallium arsenide, silicon carbide, diamond, or other substrate materials known to those having skill in the art. Thepassivation layer330 is preferably a polyimide layer but can alternately be a silicon dioxide layer, a silicon nitride layer, or layers of other passivation materials known to those having skill in the art. As shown, thepassivation layer330 preferably covers the top edge portion of thecopper contact pad320 opposite the substrate, leaving the central surface portion of thecopper contact pad320 exposed from thepassivation layer330. The UBM340 in accordance with the present invention includes atitanium layer340a,afirst copper layer340b,a nickel-vanadium layer340cand asecond copper layer340d.Thetitanium layer340ais provided on thepassivation layer330 to form a closed-loop surrounding the opening330aof thedielectric layer330. Thefirst copper layer340bis formed over thetitanium layer340aand theopening330aof thedielectric layer330 such that thefirst copper layer340bdirectly contacts thecopper contact pad320. The nickel-vanadium layer340cis formed on thefirst copper layer340band thesecond copper layer340dis formed on the nickel-vanadium layer340c.
• The[0022]UBM340 of the present invention chooses thetitanium layer340aas adhesion layer, due to good adhesion of titanium to thepassivation layer330, to obtain a better adhesion between thefirst copper layer340band thepassivation layer330. Since thetitanium layer340ais formed as a closed-loop surrounding theopening330aof thedielectric layer330, thefirst cooper layer340ais allowed to directly contacts the copper pad thereby providing a better electrical performance. Furthermore, theUBM340 utilizing the nickel-vanadium layer340bas the barrier layer and utilizing thesecond copper layer340das the wetting layer.
• The semiconductor device shown in FIG. 7 further comprises a[0023]solder bump350 provided on theUBM340 over thecopper contact pad320 to act as a bump electrode. Consequently, the semiconductor device of the present invention can be directly mounted to a interconnection substrate by means of the bump electrodes directly attached thereon. Typically, there are two kinds of solder compositions used to form thesolder bump350. They includes (a) high melting point solder alloys such as 5Sn/95Pb or 3Sn/97Pb and (b) lower melting point solder alloys such as 63Sn/37Pb or 40Sn/60Pb. Bumping process is typically accomplished by vapor deposition, electroplating or printing. Alternatively, thesolder bump350 may be replaced with a gold bump. Typically, the gold bump comprises at least about 90 weight percentage of Au deposited on theUBM340 by means including electroplating or evaporative lift-off.
• A subtractive process may be used to form the[0024]UBM340 in accordance with the present invention.
• Referring to FIG. 3, a[0025]titanium layer340ais sputtered to deposit across thepassivation layer330 including the exposed surface portions of thecopper contact pad320.
• Referring to FIG. 4, the[0026]titanium layer340ais selectively etched to form a titanium opening corresponding to the passivation layer opening330a.
• Referring to FIG. 5, other metal layers of the UBM[0027]340 (including thefirst copper layer340b,the nickel-vanadium layer340cand thesecond copper layer340d) are sputtered to deposit on thetitanium layer340aand the central surface portion of thecopper contact pad320 exposed from thepassivation layer330 and thetitanium layer340a.
• Referring to FIG. 6, after applying a layer of photoresist and patterning the photoresist layer, solder is electrodeposited on the photoresist opening section to obtain the[0028]solder bump350; thereafter, the remaining photoresist is stripped.
• Referring to FIG. 7, the UBM layers are etched with the[0029]solder bump350 as a mask, and then a reflow step is proceeded.
• FIG. 8 shows a portion of a[0030]semiconductor device400 having a bump electrode in accordance with another embodiment of the present invention. Thesemiconductor device400 is a package with I/O redistribution implemented at the wafer level. Thesemiconductor device400 mainly comprises amulti-layered lead440 having a first end portion connected to thecopper contact pad320 through thepassivation opening330a and a second end portion extending on thepassivation layer330. Themulti-layered lead440 includes afirst titanium layer440aon thepassivation layer330, acopper layer440bon thefirst titanium layer440aand asecond titanium layer440con thecopper layer440b. Thefirst titanium layer440ahas a opening corresponding to thepassivation opening330a.Thecopper layer440bdirectly contacts thecopper contact pad320 through the opening of thefirst titanium layer440aand theopening330athereby providing a better electrical performance. It could be understood that themulti-layered lead440 is a part of a desired trace pattern to redistribute thecopper contact pads320 into a desired format.
• A[0031]dielectric layer450, preferably formed by a polyimide, is formed over themulti-layered lead440 and thepassivation layer330. Thedielectric layer450 has a photo-defined blind-via450aformed corresponding to the second end portion (away from the copper contact pad320) of themulti-layered lead440. Aconductive pad460 is formed over the blind-via450a. Preferably, theconductive pad460 comprises a nickel-vanadium layer460aformed over the blind-via450aand acopper layer460bformed on the nickel-vanadium layer450a. Asolder bump470 is provided on thecopper layer460b. Alternatively, thesolder bump470 may be replaced with a gold bump.
• Although the invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed.[0032]

Claims (9)

What is claimed is:

1. A semiconductor device having a bump electrode comprising:

a substrate having a copper contact pad;

a dielectric layer formed over the substrate, the dielectric layer having an opening positioned over the copper contact pad;

a titanium layer on the dielectric layer wherein the titanium layer forms a closed-loop surrounding the opening of the dielectric layer;

a first copper layer formed over the titanium layer and the opening of the dielectric layer such that the first copper layer directly contacts the copper contact pad;

a nickel-vanadium layer formed on the first copper layer;

a second copper layer formed on the nickel-vanadium layer; and

a metal bump provided on the second copper layer.

2. The semiconductor device as claimed inclaim 1, wherein the dielectric layer is a passivation layer.

3. The semiconductor device as claimed inclaim 1, wherein the metal bump is a gold bump.

4. The semiconductor device as claimed inclaim 1, wherein the metal bump is a solder bump.

5. A semiconductor device having a bump electrode comprising:

a substrate having a copper contact pad;

a first dielectric layer formed over the substrate, the first dielectric layer having a first opening positioned over the copper contact pad;

a multi-layered lead having a first end portion connected to the copper contact pad through the first opening and a second end portion extending on the first dielectric layer;

the multi-layered lead including a first titanium layer on the first dielectric layer, a copper layer on the first titanium layer and a second titanium layer on the copper layer wherein the first titanium layer has a second opening corresponding to the first opening and the copper layer directly contacts the copper contact pad through the second opening and the first opening;

a second dielectric layer formed over the multi-layered lead and the first dielectric layer, the second dielectric layer having a blind-via formed corresponding to the second end portion of the multi-layered lead;

a conductive pad formed over the blind-via; and

a metal bump provided on the conductive pad.

6. The semiconductor device as claimed inclaim 5, wherein the first dielectric layer is a passivation layer.

7. The semiconductor device as claimed inclaim 5, wherein the conductive pad comprises a nickel-vanadium layer formed over the blind-via and a copper layer formed on the nickel-vanadium layer.

8. The semiconductor device as claimed inclaim 5, wherein the metal bump is a gold bump.

9. The semiconductor device as claimed inclaim 5, wherein the metal bump is a solder bump.

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