US20020090180A1 - Wafer scale fiber optic termination - Google Patents

Abstract

An optical fiber terminator package (300) has a chip with a surface with one or more light emitting devices (314) and at least one photoreceptor (312) formed on or in the surface. A cap (302) is bonded to the surface of the chip to encapsulate the devices (312, 314). The cap (302) has one or more regions (316, 318) transparent to light passing to or from the devices (312, 314). The cap (302) has been bonded to the semiconductor chip at the wafer stage prior to separation of the wafer into individual packages.

Description

TECHNICAL FIELD
• This invention relates to the molding and application of protective caps to microelectronic semiconductor chips on a wafer scale as opposed to application on an individual chip basis. More particularly the invention relates to the molding and application of protective caps to semiconductor chips incorporating light emitting devices or receivers or both and the provision of integrated optical fiber connectors.[0001]
BACKGROUND ART
• Semiconductor chips are normally packaged in a protective layer or layers to protect the chip and its wire bonds from atmospheric and mechanical damage. Existing packaging systems typically use epoxy molding and thermal curing to create a solid protective layer around the chip. This is normally carried out on individually diced chips bonded to lead frames and so must be done many times for each wafer. Alternative methods of packaging include hermetically sealed metal or ceramic packages, and array packages such as ball grid array (BGA) and pin grid array (PGA) packages. Recently wafer scale packaging (WSP) has started to be used. This is carried out at the wafer stage before the chips are separated. The use of molding and curing techniques subjects the wafer to both mechanical and thermal stresses. In addition the protective cap so formed is a solid piece of material and so cannot be used for MEMS devices, since the MEMS device would be rendered inoperable by the polymer material. Existing packaging systems for MEMS devices include thematically sealed packages for individual devices , or use silicon or glass wafer scale packaging, both of which are relatively high cost operation.[0002]
• Devices which incorporate optically active devices, such as light emitting devices or photoreceptors, also require a cap with at least a portion of the cap transparent to the relative light. The caps also frequently require a lens to focus light passing through the cap and so the epoxy molding techniques cannot be used. The devices are typically packaged individually or use silicon or glass wafer scale packaging.[0003]
DISCLOSURE OF THE INVENTION
• In one broad form the invention provides an optical fiber terminator package including:[0004]
• a) a semiconductor chip having a top surface and a bottom surface and including at least one first optical device which emits or receives electromagnetic radiation at one or more wavelengths from the top surface;[0005]
• b) a first hollow cap having a central portion and a first perimeter wall extending from the perimeter edge of the central portion with the free edge of the first perimeter wall bonded to the top surface to provide a first cavity which, in plan view, overlays at least part or all of at least one light emitting device, said central portion including:[0006]
• at least one region which is at least substantially transparent or translucent to electromagnetic radiation at said one or more wavelengths; and[0007]
• wherein the first cap has been bonded to the semiconductor chip at the wafer stage prior to separation of the wafer into individual packages.[0008]
• The package may include at least one region which refracts electromagnetic radiation passing therethrough.[0009]
• The package may also include at least one first attachment means for attaching an electromagnetic radiation transmitting cable or fiber to the cap, whereby at least some electromagnetic radiation transmitted between the at least one first optical device and the cable or fiber passes through said at least one region.[0010]
• The package may also include at least one second optical device which emits or receives electromagnetic radiation at one or more wavelengths from the top surface.[0011]
• The package may also include at least one second attachment means for attaching an electromagnetic radiation transmitting cable or fiber to the cap, whereby at least some electromagnetic radiation transmitted between the at least one second optical device and the cable or fiber passes through said at least one region.[0012]
• The first optical device may be a light emitting device and the second optical device may be a photoreceptor.[0013]
• The package may also include a second perimeter wall extending from the periphery of the central portion away from the first perimeter wall.[0014]
• The package may also include at least one recess in the central portion.[0015]
• The package may also include a second cap bonded to the bottom surface of the chip.[0016]
• The second cap bonded to the bottom surface of the chip may, in plan view, overlay at least part or all of at least one first device and, if present, the at least one second device.[0017]
• The package may have a single light emitting device and a single photoreceptor. The two devices may act independently as a receiver and a transmitter for an optical network connection, for example.[0018]
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 shows a prior art method of forming protective caps on semiconductor chips.[0019]
• FIG. 2 shows a cross section of a prior art packaging made according to the FIG. 1 method.[0020]
• FIG. 3 shows a cross section of a prior art packaging of a MEMS device.[0021]
• FIG. 4 shows a cross section through a MEMS device packaged according to the invention.[0022]
• FIG. 5 shows a possible device for forming molded caps;[0023]
• FIG. 6 shows method of applying caps formed using the device of FIG. 5[0024]ato a silicon wafer;
• FIG. 7 shows the wafer and caps of FIG. 6 bonded together[0025]
• FIG. 8 symbolically shows a method for applying molded caps to a silicon wafer according to the invention;[0026]
• FIG. 9 shows the wafer and caps of FIG. 8 bonded together;[0027]
• FIG. 10 shows an exploded cross sectional view of a device for forming the protective caps.[0028]
• FIG. 11 shows an exploded perspective view of the device of FIG. 10.[0029]
• FIG. 12 shows a cross sectional view of the device of FIG. 10 at the commencement of molding.[0030]
• FIG. 13 shows the device of FIG. 10 after molding has finished and just before one side of the mold is released from the other side.[0031]
• FIG. 13[0032]ashows an expanded view of part of FIG. 13.
• FIG. 14 shows a perspective view of the FIG. 10 device corresponding to FIG. 13.[0033]
• FIG. 15 shows a cross sectional side view of the device after one of the molds has been partially removed.[0034]
• FIG. 16 shows a cross sectional side view of the device after one of the molds has been fully removed.[0035]
• FIG. 17 shows a cross sectional side view of the device undergoing an etch.[0036]
• FIG. 18 shows a cross sectional side view of the device after undergoing an etch.[0037]
• FIG. 19 shows a cross sectional side view of the device at the commencement of application to a wafer and removal of the second mold.[0038]
• FIG. 20 shows a cross sectional side view of a wafer after application of the caps.[0039]
• FIG. 21 shows a cross sectional side view of a series of chips after singulation of the wafer.[0040]
• FIG. 22 shows a cross sectional side view of a wafer with caps applied to both sides, before singulation of the wafer.[0041]
• FIG. 23 shows a cross sectional side view of a stage of manufacture of a molding wafer.[0042]
• FIG. 24 shows a cross sectional side view of the wafer of FIG. 23 at a next stage of manufacture.[0043]
• FIG. 25 shows a cross sectional side view of the finished wafer of figure.[0044]
• FIG. 26 shows a cross sectional view of a molding process using the wafer of FIG. 25.[0045]
• FIG. 27 shows a cross sectional view of a semiconductor wafer having optical devices with packaging caps formed by the process of FIG. 26 attached prior to separation of the wafer into separate packages.[0046]
• FIG. 28 shows a cross sectional view of an optical semiconductor chip in its finished packaged form.[0047]
• FIG. 29 shows a perspective view a first finished and packaged optical fiber terminator device packaged according to the invention.[0048]
• FIG. 30 shows a cross sectional side view the optical fiber terminator device of FIG. 29.[0049]
• FIG. 31 shows a cross sectional side view of a molding device for forming the caps of the FIG. 29 package.[0050]
• FIG. 32 shows an exploded perspective sectional view of the device of FIG. 31 after forming of a cap.[0051]
• FIG. 33 shows a perspective view of a part of the device of FIG. 31 after forming of a cap.[0052]
• FIG. 34 shows a cross sectional side view of a wafer having optical devices as the optical lens moldings are attached.[0053]
• FIG. 35 shows a cross sectional side view of the wafer of figure after removal of the mold device.[0054]
• FIG. 36 shows a perspective sectional view of the wafer of FIG. 31 with attached optical lens moldings prior to singulation.[0055]
BEST MODE OF CARRYING OUT THE INVENTION
• Referring to FIGS. 1 and 2 there is show a prior art method of forming protective caps on semiconductor wafers on a wafer scale. A[0056]semiconductor wafer10 is clamped against amold12 havingcavities14 formed therein and aliquid polymer material16 is injected into thecavities14. The polymer material sets to form solidprotective caps18. The wafer is then singulated using a wafer saw. This technique is not applicable to wafers having MEMS devices formed thereon as the liquid polymer material will surround the MEMS devices and stop them from working.
• FIG. 3 shows the present prior art technique for protecting MEMS devices. The[0057]MEMS chip20 including theMEMS devices24, shown symbolically, is bonded to asilicon wafer26. This may be carried out at the individual chip stage or at the wafer stage. Thewafer26 is typically etched using a crystallographic anisotropic etch using an etchant such as KOH to form a series ofrecesses28 which correspond to the locations of the MEMS devices. Thewafers26 are carefully aligned with theMEMS wafer20 and bonded thereto. While this can be an effective means of packaging MEMS devices, it is expensive as it requires an extra silicon (or sometimes glass) wafer, which must be etched to form the cavities.
• FIG. 4 shows a[0058]MEMS wafer30 havingsurface MEMS32 formed thereon. A hollowprotective cap34 of thermoplastic material made and bonded to thewafer30 according to the invention is provided so as to form a mechanical and atmospheric protective barrier for the MEMS devices. Thecap34 forms acavity36 with the wafer to allow the MEMS device(s) to operate.
• The use of molded thermoplastic hollow caps offers the possibility of providing inexpensive packaging. However, conventional techniques do not provide the required accuracy and thermal stability required for micro fabricated devices.[0059]
• FIGS.[0060]5 to7 show a possible technique for packaging asemiconductor wafer40 having a number of groups42 of micro fabricateddevices44, shown symbolically, formed on or in anupper surface46.
• An array of[0061]caps48 is formed using conventional injection molding methods andsteel mold tools50 &52. The caps are supported on a sprule54 at the same nominal spacing as the groups42. Using this method will almost invariably lead to misalignment with resulting destruction of MEMS devices, as shown in FIG. 20. In FIG. 20 thecap48a has been aligned correctly with its group ofMEMS devices42a.However the spacing between the caps is greater than the spacing of the groups so thatcap48bis not aligned correctly, but does not destroy any of the MEMS devices of itsrespective group42b.However, the caps44c&dare sufficiently misaligned that the perimeter walls of the caps overlay one or more of theMEMS devices44, destroying their functionality.
• This misalignment can be the result of a number of actors, including differential thermal expansion of the sprule material compared to the silicon wafer, non rigidity of the molded components and the lack of machinery designed for accurate alignment and bonding of polymers to wafers using these techniques.[0062]
• A solution is to use tools which have the same coefficient of thermal expansion as the wafer, such as silicon and FIGS. 8 & 9 symbolically show a technique using a[0063]silicon tool60 to hold an array of thermoplastics caps60 as the caps are bonded to thesilicon wafer40. Since thetool60 is formed of the same material as thewafer40, changes in temperature will not result in changes in alignment; the spacing of thecaps60 will change by the same amount as the spacing of the groups42 ofMEMS devices44. Thus, when bonded, all of the caps will be correctly aligned, as shown in FIG. 9. Additionally there is much experience in working silicon to the required accuracy.
• FIGS.[0064]10 to16 schematically show a first system for creating and applying hollow protective caps to wafers, preferably semiconductor wafers.
• FIG. 10 shows a[0065]molding system100 for forming the hollow protective caps shown in FIG. 4 which may be used with MEMS devices or any other micro fabricated device. Themolding system100 includes twosilicon wafers102 &104. Theupper wafer102 has been processed using conventional lithography and deep silicon etching techniques to have a series ofrecesses106 in itslower surface108. Thelower wafer104 has been similarly processed so that itsupper surface110 has a series ofgrooves112 which align with edges of therecesses106. Therecesses106 andgrooves112 are sized for the chip size of the wafer to be processed and repeat at centers corresponding to the repeat spacing on the wafer. In the embodiment shown the protective caps are designed for a MEMS inkjet printhead and so are very long relative to their width in plan view. The recesses are rectangular, although the ends of the recesses are not shown. The ends of thegrooves112 are not shown but it is to be understood that thegrooves112 at each side of each recess are in fact one groove which has a rectangular shape in plan view.
• The[0066]grooves112 for adjacent caps define aportion114 of material which has not been etched. Similarlyadjacent recesses106 define aportion116 of material which has not been etched. These portions ofmaterial114 &116 align with each other and when the two wafers are pressed together, the two wafers contact each other at theseportions114 &116.
• The two surfaces have been etched so that the[0067]groove112 for the perimeter of the cap is all in thelower wafer104 and therecess104 for the central portion is all in theupper wafer102.
• It is not essential that the mold wafers only contact on surfaces which have not been etched. Nor is it essential that the central portion is defined by a recess in only one mold or that the perimeter walls be defined by a groove or recess in only one mold. The effective split line between the molds may be located at any position desired and need not be planar. However, planarity of the split line will typically simplify fabrication of the molds.[0068]
• The[0069]assembly100 also includes an upper release or ejectwafer118 and a lower release or ejectwafer120. These upper and lower release wafers are silicon wafers which have been processed utilizing conventional lithography and deep silicon etching techniques to have a series of release pins122 and124 respectively. The upper andlower mold wafers102 &104 are formed withcorresponding holes126 &128 respectively which receive thepins122 &124. Theupper holes126 are located generally toward the center or axis of eachrecess106 whilst thelower holes128 are located in thegrooves112. However the location of theholes126 and128 is not especially critical and they may be placed as required for ejection of the molded caps.
• The release pins[0070]122 &124 have a length greater than the depth of the corresponding holes. When the free ends of thepins122 align with the inner ends of theholes126, there is agap130 between theupper mold wafer102 and theupper release wafer118. In this embodiment the length of thelower pins124 is the same as the thickness of thelower mold wafer104. However the length of thepins124 may be greater than the thickness of the wafer or it may be less. When the length of thepins124 is less than the maximum thickness of thelower wafer104 it needs to be greater than the depth of theholes128, i.e. at least the reduced thickness of thewafer104 at thegrooves112. Thelower wafers104 and120 are positioned with thepins124 part way inserted in theholes128 but not extending beyond theholes128 into thegrooves112 and with agap132 between the two wafers. Thepins124 preferably extend to be flush with the ends of the holes so as to form a substantially planar base to thegroove112.
• The thickness of the mold and release wafers is about 800 microns whilst the[0071]gaps130 and132 are of the order of 10 to 100 microns in thickness. However this is not critical.
• The mold tools are preferably etched using cryogenic deep silicon etching rather than Bosch etching as to produce a smoother etch. Bosch etching produces scalloping of etched side walls, such as the side walls of the pin and cap recesses. The scalloping makes the release of the molds from the molded material more difficult. In comparison, using a cryogenic etch results in much smother etched walls, with easier mold release.[0072]
• A[0073]sheet134 of thermoplastic material of about 200 to 500 microns in thickness is placed between the twowafers102 &104 and the assembly is placed in a conventional wafer bonding machine, such as an EV501, available from Electronic Visions Group of Sharding, Austria.
• The assembly is mechanically pressed together in the machine but it will be appreciated that the mold wafers may be urged toward each other to deform the thermoplastic sheet by applying an above ambient pressure to the[0074]gaps130 &132. Alternatively other means may be used.
• The[0075]sheet134 may be heated by conduction but is preferably heated by radiation and preferably by using infrared radiation, as indicated byarrows136 in FIG. 12. A combination of conductive and radiant heating may be used. The mold and releasewafers102 &104 and118 &120 respectively are formed of silicon, which is substantially transparent to infrared light of a wavelength in the range of about 1000 nm to about 5000 nm. Thematerial134 chosen either intrinsically absorbs light within this wavelength range or is doped so as to absorb light within this wavelength range. If thematerial134 does not intrinsically absorb within this range, a suitable dopant is “carbon black” (amorphous carbon particles) which absorbs light at these wavelengths. Other suitable dopants may be used.
• The[0076]sheet134 is placed between the two mold wafers and exposed to infrared light at a suitable wavelength, as indicated byarrows136. The infrared radiation is preferably supplied from both sides of the wafers and thesheet134 to provide symmetrical heating, but this is not essential and the infrared radiation may be supplied from only one side. Because the silicon wafers are transparent to the infrared radiation, the infrared radiation passes through the wafers and is absorbed by thesheet134. After heating to a suitable temperature the mold wafers may then be urged together to deform thesheet134. The wafers may be pressed together whilst thesheet134 is being heated rather than waiting for thesheet134 to be fully heated, particularly if conductive heating is being used. If a material other then silicon is used heating of thesheet134 may be achieved using electromagnetic radiation at other wavelengths to which the material used is substantially transparent.
• When processed in a wafer bonding machine the[0077]sheet134 is molded to the shape of the cavity defined by therecess106 and thegroove112. The material is also substantially squeezed out of the gap between the twoportions114 &116, as indicated byarrows142 in FIG. 13a,to form a series ofcaps138.
• As previously mentioned, the[0078]molding wafers102 &102 are formed using conventional lithography and deep silicon etching techniques. The accuracy of this process is dependant on the lithography and the resist used. The etch selectivity of silicon versus resist is typically between about 40:1 and about 150:1, requiring a resist thickness for a 500 μm thick etch of between about 15 μm and 4 μm respectively. Using a contact or proximity mask, critical dimensions of around 2 μm can be achieved. Using steppers, electron beam or X-ray lithography the critical dimensions can be reduced to less than a micron. Thus thematerial134 may be squeezed out totally from between theportions114 &116, totally separating theadjacent caps136. Alternatively athin layer140 up to about 2 microns thick may be left between theportions114 &116 betweenadjacent caps136 due to the variation in position of the relative surfaces due to manufacturing tolerances.
• It is not essential that the mold wafers or the release wafers be made of semiconductor materials or that they be processed using conventional lithography and deep silicon etching methods. Other materials and methods may be used if desired. However, the use of similar materials to the semiconductor wafers provides better accuracy since temperature changes have less effect. Also lithography and deep silicon etching methods are well understood and provide the degree of accuracy required. In addition, the one fabrication plant may be used for production of both the semiconductor devices and the molding apparatus.[0079]
• It will be appreciated that the two[0080]mold wafers102 &104 will need to be shaped so that there is space for the material to move into as it is squeezed out from between the two wafers.
• After forming of the[0081]protective caps138 it is preferred to remove the lower mold and releasewafers104 &120 whilst leaving thematerial134 still attached to theupper mold wafer102. A vacuum is applied to thegap132 between the lower mold and release wafers. Therelease wafers118 &120 are mounted in the assembly so as to be immovable whilst themold wafers102 &104 are movable perpendicular to the general plane of the wafers. Accordingly, thelower mold wafer104 is drawn downwards to therelease wafer120. Thepins124 of therelease wafer120 firmly press against thematerial134 and so retain thematerial134 in position and prevent it moving downwards with thelower mold wafer124. The configuration of theassembly100 after this stage is shown in FIG. 15.
• The[0082]lower release wafer120 now only contacts thematerial134 bypins124 and so it is now relatively easy to remove thelower release wafer120 from contact with thematerial134 without dislodging the material from theupper mold wafer102. This is done and the assembly is then in the configuration shown in FIG. 16, with the material134 exposed for further processing and attachment to a wafer.
• Whilst still attached to the upper mold, the[0083]sheet134 is then subject to an etch, preferably an oxygen plasma etch, from below, to remove thethin layer140 of material, as shown in FIG. 17. The etch has little effect on the rest of the material due to the significant greater in thickness of the rest of the material. The etched assembly is shown in FIG. 18.
• The assembly is then placed over a[0084]wafer144 having a number of chips formed on the wafer. Each chip has a plurality ofMEMS devices146. The components are aligned and then placed in a conventional wafer bonding machine, such as an EV501 to bond thecaps138 to the wafer. The array of chips is positioned so that each cap overlays part or all of a chip. The devices are shown symbolically and may be MEMS devices, MOEMS devices, other micro fabricated devices, passive electronic elements or conventional semiconductor devices.
• The assembly is removed from the wafer bonding machine and a vacuum is then applied to the[0085]upper gap130 so as to draw theupper mold wafer102 up toward theupper release wafer118. Similar to the release of the lower mold wafer, thecaps138 are held in place by thepins122 of the upper release wafer. Thus the chance of accidental detachment of any of the caps from the wafer due to the act of removing the upper mold wafer is reduced, if not totally prevented.
• The[0086]wafer144 is now in a state where each chip is protected by adiscrete cap138. The wafer can then be singulated into individual die. If the chips are arranged in a regular array, the conventional methods of wafer singulation—sawing or scribing may be used. However, if the separation lines between chips are not regular or if the chips are too fragile for sawing or scribing, deep reactive ion etching (DRIE) may be used to singulate the wafers. Although DRIE is much more expensive than wafer sawing, this is moot if the wafer already required through wafer deep etching, as is the case with an increasing number of MEMS devices. If etching is used, thewafer144 is next subject to a deep silicon etch in an etching system, such as an Alcatel601 E or a Surface Technology Systems Advanced Silicon Etch machine, to separate thewafer144 into individual packages. This etch is carried out at a rate of about 2 to 5 microns per minute and may be applied from either the cap side of the wafer or the bottom side of the wafer. The etch is highly anisotropic (directional) so there is relatively little etching of silicon sideways of the direction of the etch. If the etch is applied from the caps side, thecaps138 act as masks and only the silicon material between the caps is etched. The etching continues until all the silicon material between individual chips is removed, thereby separating thechips148 for subsequent processing. If the etch is applied from below, a separate mask will need to be applied to the bottom surface of the wafer.
• Any silicon exposed to the direction of the deep etch at the separation stage will be etched away. Thus if the etch is from the top (cap) side any exposed silicon which needs to be retained, such as electrical bond pads, on the upper surface of the chip should be protected, such as by a resist, which must be removed prior to wire bonding. An alternative is to apply a mask to the lower surface of the wafer and to deep silicon etch from the rear. Alternatively second caps may be provided for the lower surface of the wafer, utilizing the same manufacturing methods as for the upper caps and using the lower caps as masks for the etch. By providing both upper and lower caps at the wafer stage, each chip is substantially completely packaged prior to singulation.[0087]
• FIG. 22 shows a technique for providing protective caps for both the upper and lower surfaces. The figure shows a[0088]wafer150 upon which have been formed a series of MEMS device chips153 on anupper surface154. Eachchip153 includes one ormore MEMS devices152 and optionally other micro fabricated elements. A first set ofprotective caps156 have been formed on theupper surface154 as per the techniques of the invention previously described. Thebond pads158 of theindividual chips153 are on theupper surface154 and are not covered by theprotective caps156. A second set ofprotective caps160 have been formed on thelower surface162 of the wafer as per the techniques of the invention previously described. The first and second sets of protective caps may be applied to the wafer sequentially or may be applied to the wafer simultaneously. The order of application is not important. The second set ofcaps160 are located under eachchip153 but are larger than thefirst set156 and extend under and beyond thebond pads158.
• The[0089]wafer150 is then subject to a deep silicon etch from the lower surface of the wafer as indicated byarrows164, rather than from the upper surface, to separate the individual chips. The lower caps160 thus act as a mask to thebond pads158 and because the etching process is very directional, only silicon between thelower caps160 of the individual chips is etched away. Thebond pads158 and other exposed parts on the upper surface within the outline of the lower caps are substantially unaffected by the etch and so thechips152 will not be damaged by the etch.
• It will be appreciated that the provision of the second set of caps is only a necessity where a hollow space is required; if a second set of caps is unnecessary or undesirable, a resist may be coated onto the lower surface with a grid pattern to leave areas between the chips exposed for deep etching.[0090]
• FIG. 28 shows a semiconductor[0091]laser chip package250 incorporating a cap according to the invention. The package includes asemiconductor chip252 on which have been formed a series ofsemiconductor laser devices254. For example these may be Vertical Cavity Surface Emitting Lasers (VCSELs). The VCSELs emit laser light generally perpendicular to the plane of the chip. Thecap256 has been formed and attached to the chip using the inventive techniques described herein. However, the cap is formed of a material substantially transparent to the wavelength(s) of the light emitted by the VCSELs. In addition the cap has been formed so as to have a series ofrefractive lenses258 in thecover portion260. This is relatively easy to accomplish by fabricating the mould wafers with appropriately shaped recesses.
• The steps involved in manufacture of the cap is shown in FIGS.[0092]23 to26. The cap is manufactured using the molding techniques previously described, but modified as below.
• The[0093]lower mold wafer200 used to form the cap needs to have a series of lens forming depressions formed in its molding surface. A resistmask201 is applied to the upper surface having a series ofsmall holes203 in the mask201 (see FIG. 23a). The wafer is then subject to an isotropic etch. The size of the holes is relatively small and so the etching agent etches ahemispherical recess202 behind each hole (see FIG. 23b). After etching themask201 is removed.
• Referring to FIG. 23[0094]c,therecesses204 for the side walls of the cap are formed by applying a second resist206 to theupper surface208 havingapertures210 corresponding to the wall forming recesses. An anisotropic deep silicon etch is applied to the upper surface to form thewall forming recesses204, as seen in FIG. 23. Referring to FIG. 24, a second resist212 is applied to the lower surface with openings for forming ejector pin holes214. An anisotropic deep silicon etch is applied to the lower surface to form the ejector pin holes, as seen in FIG. 24. FIG. 25 shows a side view of the finished lower wafer.
• A[0095]plastic sheet222 is then molded using the molding technique previously described, shown in FIG. 26. Theupper cap220 and upper andlower release wafers224 &226 respectively are as previously described. As with the standard technique, infrared radiation is used to heat the plastic sheet as pressure is applied, as indicated byarrows228. The molding formscaps256 with a series of elongate lenses on the lower surface of the caps. The caps are then bonded to a wafer as shown in figure using the methods previously described. The wafer is singulated and necessary electrical connections made to produce the finished package shown in FIG. 28.
• A fiber optic terminator chip package is shown in FIG. 31. The package includes a[0096]semiconductor chip300, acap302 which is both protective and optically active. The cap has twocylindrical recesses304 &306 into which twooptical fibers308 &310 respectively are affixed.
• The chip has a[0097]photo sensor312 for receiving light transmitted along the firstoptical fiber308 and alaser314 for emitting light for transmission into the secondoptical fiber310. The cap includes twolenses316 &318 for focusing light from the first optical fiber onto the photo sensor and for collecting light from the laser and directing it into the second optical fiber. The chip package includeselectrical bond pads320 outside of the cap to which are affixedwires322 for connection to appropriate control and power circuitry.
• FIG. 31 shows a[0098]molding device350 for forming the caps. Thelower mold352 is formed by etching through pin holes in a resist layer to form hemispherical recesses. Theupper mold354 is formed with twocylindrical posts256, which will form therecesses304 &306 for theoptical fibers308 &310. Thelower mold352 has a lower perimeterwall forming recess358 and the upper mold also has a upper perimeterwall forming recess360. Whilst the drawings show the lowerperimeter wall recess358 being narrower than the upperperimeter wall recess360, this is optional. The two wall recesses may have the same thickness or the lower wall may be thicker than the upper wall. Since in use the optical fibers may apply a bending side loading to the cap, thicker upper walls are preferred to prevent the fibers distorting the fiber receiving recesses and becoming loose or pulling out. As seen in FIG. 32, the upper and lower molds each have fourejection pins362 and364 respectively, located at the comers of the perimeter walls.
• The molding assembly also includes a[0099]spacer wafer366 which is located between the upper andlower mold wafers352 &354.
• After forming an array of caps, the array is detached from the[0100]lower wafer352 as previously described and the array is attached to asemiconductor wafer370 having multiple optical devices, as shown in FIG. 34. The caps are bonded to the wafer and the mold components removed to leave the wafer with each set of optical devices protected by a cap, as seen in FIGS. 30 and 31.
• The[0101]wafer370 is singulated and electrical connections made to the bond pads of each chip. Optical fibers may then be inserted and bonded in the two recesses and the package is then in a usable state.
• Whilst the package described has light emitting device(s) and light receiving device(s), it will be appreciated that the package may only have light emitting device(s) or light receiving device(s). Thus a package similar to that of FIG. 28 may be provided with an upper cap to allow for direct connection of one or more optical fibers. Where the device includes both light emitters and light receivers, the light emitters and light receivers may be operated independently of each other, such as in a connector for a optical network cable. Alternatively the devices may be linked so that the package acts as a repeater.[0102]
• Throughout the specification, reference is made to semiconductors and more particularly silicon semiconductors. It is to be understood that the invention is not limited to use on semiconductors or silicon based semiconductors and has application to non semiconductor devices and to non silicon based semiconductors, such as those based on gallium arsenide semiconductors.[0103]
• Whilst the invention has been described with particular reference to MEMS devices, it is to be understood that the invention is not limited to MEMS or MOEMS devices and has application to any devices which are or may be bulk fabricated on a wafer.[0104]
• It will be apparent to those skilled in the art that many obvious modifications and variations may be made to the embodiments described herein without departing from the spirit or scope of the invention.[0105]

Claims (12)

1. An optical fiber terminator package including:

a) a semiconductor chip having a top surface and a bottom surface and including at least one first optical device which emits or receives electromagnetic radiation at one or more wavelengths from the top surface;

b) a first hollow cap having a central portion and a first perimeter wall extending from the perimeter edge of the central portion with the free edge of the first perimeter wall bonded to the top surface to provide a first cavity which, in plan view, overlays at least part or all of at least one light emitting device, said central portion including:

at least one region which is at least substantially transparent or translucent to electromagnetic radiation at said one or more wavelengths; and

wherein the first cap has been bonded to the semiconductor chip at the wafer stage prior to separation of the wafer into individual packages.

2. The package ofclaim 1 wherein the cap further includes at least one first attachment means for attaching an electromagnetic radiation transmitting cable or fiber to the cap, whereby at least some electromagnetic radiation transmitted between the at least one first optical device and the cable or fiber passes through said at least one region.

3. The package ofclaim 1 wherein the semiconductor chip includes at least one second optical device which emits or receives electromagnetic radiation at one or more wavelengths from the top surface.

4. The package ofclaim 4 wherein the cap further includes at least one second attachment means for attaching an electromagnetic radiation transmitting cable or fiber to the cap, whereby at least some electromagnetic radiation transmitted between the at least one second optical device and the cable or fiber passes through said at least one region.

5. The package ofclaim 1 further including a second perimeter wall extending from the periphery of the central portion away from the first perimeter wall.

6. The package ofclaim 1 further including at least one recess in the central portion.

7. The package ofclaim 1 further including a second cap bonded to the bottom surface of the chip.

8. The package ofclaim 1 wherein the first optical device is a light emitting device.

9. The package ofclaim 1 wherein the first optical device is a photoreceptor.

10. The package ofclaim 1 further including a second cap bonded to the bottom surface of the chip, said second cap, in plan view, overlaying at least part or all of at least one first optical device.

11. The package ofclaim 1 wherein the at least one region refracts said electromagnetic radiation passing therethrough.

12. The package ofclaim 1 wherein the at least second region refracts said electromagnetic radiation passing therethrough.

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