US20020063263A1 - Metal oxide semiconductor transistor with self-aligned channel implant - Google Patents

Abstract

A transistor (50) comprising a gate conductor (68) and a gate insulator (66) separating the gate conductor from a semiconductor material (64) having a first conductivity type. The transistor further comprises a drain region (72₂) having the first conductivity type. The transistor further comprises an angular implanted region (70) having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge (70a) underlying the gate conductor, and the transistor includes a source region (72₁) formed at least in part within the angular implanted region. Finally, a transistor channel (74) is defined between an edge (72a₁) of the source region proximate the gate conductor and the angular implanted region edge (70a) underlying the gate conductor.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS
• Not Applicable.[0001]
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
• Not Applicable.[0002]
BACKGROUND OF THE INVENTION
• The present embodiments relate to metal oxide semiconductor (“MOS”) transistors and are more particularly directed to such a transistor with a self-aligned channel implant.[0003]
• Electronic circuit design is often critically affected by the design of individual transistors used within a circuit. As a result, transistor design has developed for years and continues to be an area of extensive research for various issues, including uniformity of operation between multiple transistors constructed according to a same design as well as device reliability. In this regard, MOS field effect transistor (“MOSFET”) design typically specifies parameters and methods relating to the formation of various components relative to a semiconductor substrate, including the creation of doped regions within the substrate. Consequently, these parameters and methods affect aspects such as operational uniformity and reliability.[0004]
• One aspect of a MOSFET where the above considerations is implicated is in the formation of the transistor channel, which as known in the art is the area in which a current may be induced to flow between the source and drain of the transistor. The locations of the regions that define the channel, as well as the length of the channel, may affect operational uniformity and reliability as well as other aspects relating to the transistor. Channel length may be an issue in various transistors, including one type of known MOSFET referred to in the art as a drain extended MOS (“DEMOS”) transistor. A DEMOS transistor is detailed later but is also introduced here by way of background. A DEMOS transistor is named due to having a drain region formed from two regions, a first region having a doping level comparable to that of the transistor source and a second region having a reduced doping level and which extends under the transistor gate. DEMOS transistors are used in various circuits, where one instance is a circuit that has different operating voltages such as where a first voltage is used at the input/output level while a second and lower voltage is used for the operational core of the circuit. In these cases, transistors suitable for use at the higher input/output voltages are required, and one type of such a transistor is the DEMOS transistor. DEMOS transistors also may be used in applications where the voltage on the drain exceeds the normal voltage rating of the gate oxide.[0005]
• Given the preceding, it has been observed by the present inventors that for the DEMOS transistor, and possibly for other MOSFETs, some approaches in the art form regions that define the transistor channel prior to the formation of the transistor gate. For example, for the DEMOS transistor the channel may be defined relative to an insulating region which generally defines the transistor active region. However, often such designs leave room for variation in the channel length as well as the actual formation of the channel, where both aspects may be affected by the later-formed transistor gate. Consequently, these variations may affect device uniformity and reliability. The preferred embodiments seek to improve upon these drawbacks, as further explored below.[0006]
BRIEF SUMMARY OF THE INVENTION
• In the preferred embodiment, there is a transistor. The transistor comprises a gate conductor and a gate insulator separating the gate conductor from a semiconductor material having a first conductivity type. The transistor further comprises a drain region having the first conductivity type. The transistor further comprises an angular implanted region having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge underlying the gate conductor, and the transistor includes a source region formed within the angular implanted region. Finally, a transistor channel is defined between an edge of the source region proximate the gate conductor and the angular implanted region edge underlying the gate conductor. Other aspects are also disclosed and claimed.[0007]
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
• FIG. 1[0008]aillustrates a cross-sectional view of a priorart DEMOS transistor10.
• FIG. 1[0009]billustrates a cross-sectional view of the priorart DEMOS transistor10 from FIG. 1aafter some preliminary construction steps.
• FIG. 1[0010]cillustrates a cross-sectional view of the priorart DEMOS transistor10 from FIG. 1bafter additional construction steps.
• FIG. 2[0011]aillustrates a cross-sectional view of a preferred embodiment DEMOS transistor after some preliminary construction steps.
• FIG. 2[0012]billustrates a cross-sectional view of the inventive DEMOS transistor from FIG. 2aafter additional construction steps.
• FIG. 2[0013]cillustrates a cross-sectional view of the inventive DEMOS transistor from FIG. 2bafter additional construction steps.
• FIG. 2[0014]dillustrates a cross-sectional view of the inventive DEMOS transistor from FIG. 2cafter additional construction steps.
• FIG. 3 illustrates a cross-sectional view of an alternative preferred embodiment transistor.[0015]
DETAILED DESCRIPTION OF THE INVENTION
• By way of additional introduction to the prior art beyond that discussed in the earlier Background Of The Invention section of this document, FIG. 1[0016]aillustrates a cross-sectional view of a priorart DEMOS transistor10. To present a more thorough appreciation ofDEMOS transistor10, the following discussion first introduces its various components while a later discussion elaborates on the method and order in which various of those components are formed.
• [0017]Transistor10 is formed relative to asubstrate20 which, in the example of FIG. 1a,is formed from a p-type semiconductor material. A shallow trench isolation (“STI”)region22 is formed insubstrate20 and may be various insulating materials such as silicon oxide or silicon nitride. Twowell regions24 and26 of opposite conductivity types are formed insubstrate20 and with aninterface28 between the two. In the example of FIG. 1awell24 is an n-type well and well26 is a p-type well and, thus, are labeled generally with an N and P, respectively. A gate dielectric30 is formed oversubstrate20, and agate conductor32 is formed over gate dielectric30 and extends partially overSTI region22. For the sake of reference,gate conductor32 is also shown by a schematic indication in FIG. 1awith the identifier “G₁.” A lightly dopedregion31 is formed self-aligned toedge32aofgate conductor32, such as by implanting n-type dopants in the area ofedge32aand where those dopants diffuse slightly undergate conductor32 and gate dielectric30. Thereafter, sidewall insulators33₁and33₂are formed alongedges32aand32b, respectively ofgate conductor32. Two doped regions34₁and34₂are formed withinsubstrate20 and are self-aligned to sidewall insulators33₁and33₂(and, hence, also to gate conductor32). In the present example, regions34₁and34₂are n-type regions with relatively high doping concentrations (e.g., relative to n-well24) and are, therefore, labeled in FIG. 1awith an N+ designation. Generally, region34₁combines with the previously-formed lightly dopedregion31 and the combination is considered to provide the source oftransistor10 and is schematically labeled “S₁”, and region34₂is considered to provide in part the drain oftransistor10 and is schematically labeled “D₁.” Note that region34₂as an n-type region functions only as part of the drain oftransistor10 in that the like-conductivity type n-well24 effectively extends the drain region undergate conductor32. Accordingly, atransistor channel36 is defined undergate conductor32 and extending between the left edge of n-well24 and the right edge of the source region S₁which includesregions34₁and31. Lastly, note that other components may be added to transistor10 (e.g., body contact, sidewall insulators, and so forth), although such components are not shown to simplify the Figure and since they are unnecessary to further appreciate the preferred embodiments discussed later.
• Having described the various parts of[0018]transistor10 of FIG. 1a, a further appreciation of some of those parts is facilitated by understanding certain steps of the formation oftransistor10 as is now explored with reference to FIG. 1b.Specifically, FIG. 1billustrates a cross-sectional view of the priorart DEMOS transistor10 from FIG. 1aafter some preliminary construction steps. In FIG. 1b,STI region22 is formed first insubstrate20, and it typically defines an adjacent area generally referred to as the active area, that is, the area in which the transistor source/drain regions will be formed.STI region22 typically is formed by first forming a pit or void within the upper surface ofsubstrate20 and then filling the pit with an insulator and planarizing the insulator to leave the remaining insulator portion shown in FIG. 1basSTI region22. AfterSTI region22 is formed, wellregions24 and26 are formed insubstrate20, typically one immediately after the other, and using dopants of opposite conductivity types. Each well24 and26 typically is formed by masking the surface ofsubstrate20 and then implanting appropriate dopants through any open area of the mask; thus, in the example of FIG. 1a,well24 is formed using n-type dopants while well26 is formed using p-type dopants. Typicallywells24 and26 are formed with a goal that they abut one another and thereby form the generallyvertical interface28 between the two wells. However, note that the alignment ofwells24 and26 is established purely by a photolithographic process relative toSTI region22. In other words, typicallySTI region22 has some type of marker on it that is photographically recognized by the stepper machine that fabricatestransistor10, and in response to this marker the stepper in combination with the masks used to formwells24 and26 thereby determine the physical distance offset of each well boundary relative toSTI region22. As a result of variations in this photolithographic alignment, note thatwells24 and26 may not align in the intended manner.
• FIG. 1[0019]cillustrates a cross-sectional view of the priorart DEMOS transistor10 from FIG. 1bafter additional construction steps.Gate dielectric30 is formed oversubstrate20, and it may be an oxide, a thermally grown silicon dioxide, a nitride, an oxynitride, or a combination of these or other insulators.Gate conductor32 is formed overgate dielectric30 and is patterned to extend partially overSTI region22, such as by forming a layer of conductive material which is patterned and etched to formgate conductor32. Further,gate conductor32 is typically formed from polysilicon, although other materials may be used. In any event, becausegate conductor32 is formed afterwells24 and26, the alignment ofgate conductor32 with respect to those wells, which by way of example may be appreciated from eitheredge32aor32bofgate conductor32 relative to interface28, is also subject to variations of the photolithographic process that is used to formgate conductor32. For example, if in FIG.1cgate conductor32 were shifted to the left, this would increase the distance betweenedge32aandinterface28 while decreasing the distance betweenedge32bandinterface28. As another example, if in FIG.1cgate conductor32 were shifted to the right, this would decrease the distance betweenedge32aandinterface28 while increasing the distance betweenedge32bandinterface28. Aftergate conductor32 is formed, lightly dopedregion31 is formed self-aligned to edge32aofgate conductor32 by implanting n-type dopants in the area ofedge32a. Typically, the n-type dopants are at a lesser concentration than those used for n-type regions34₁and34₂(see FIG. 1a).
• Concluding the details of the formation of[0020]transistor10, attention may be returned to FIG. 1agiven the previous steps illustrated from FIG. 1c. Oncegate conductor32 is formed, doped regions34₁and34₂are formed withinsubstrate20, typically by implanting the appropriate (e.g., n-type) dopants intowells24 and26 and then following with an annealing step. With respect to source region34₁, note that the portion of itadjacent channel36 is self-aligned with respect to edge32aofgate conductor32, meaningedge32acreates a physical mask and, thus, a physical reference point relative to where the edge of region34₁is formed in response to the dopant implant. In addition, the subsequent anneal may cause some lateral encroachment of the dopants of region34₁so that they actually extend undergate conductor32 as shown. In any event, therefore, the edge of source region34₁which defines one end ofchannel36 is defined in response to a physical component self-alignment rather than a photolithographic alignment. The other edge of source region34₁(not shown, but to the left in the Figure), however, may be defined by photolithographic alignment, such as in response to a mask, or in response to another STI or field oxide insulator. With respect to drain region34₂, its edgeproximate STI region22 is self-aligned with the edge ofSTI region22 while its other edge (not shown, but to the right in the Figure) may be defined by photolithographic alignment, such as in response to a mask, or in response to another STI or field oxide insulator.
• The present inventors have observed various drawbacks associated with[0021]prior art transistor10, and those drawbacks should be more readily appreciated in view of the preceding discussion of FIGS. 1athrough1c.Specifically, as introduced above, the prior art transistor is subject to various misalignments, and any of these misalignments may undesirably affect the predictability of the device's operation and its uniformity relative to other like transistors formed at the same time with respect tosubstrate20. Indeed, there are many different possible misalignments. For instance, recalling that p-well26 is aligned by a photolithographic process, then it may be formed such that its right edge as shown in FIG. 1ais shifted to the left, thereby presenting a gap between it and the left edge of n-well24. Similarly, since n-well24 is also aligned by a photolithographic process, then it may be formed such that its left edge as shown in FIG. 1ais shifted to the right, presenting a gap between it and the right edge of p-well26. In either case, the goal of acommon interface28 is not achieved, and this may affect the behavior of operation alongchannel36. As a result, although the edge of source34₁undergate conductor32 is self-aligned and, thus, relatively well-controlled, a shift in the edge of either p-well26 or n-well24 undergate conductor32 may affect the length ofchannel36 and, therefore, may undesirably affect the predicted operation of the device. As a final example,wells24 and26 may overlie one another more extensively than intended alonginterface28 such that the dopants from the second-formed of the two wells are more heavily infused into the first-formed of the two wells. From the preceding, it may be appreciated that the channel length is susceptible to a compound alignment sincegate conductor32 and the well boundaries are all photolithographically aligned. Hence, a minimum channel length, which is often highly desired, is limited by photolithographic process variations.
• FIG. 2[0022]aillustrates a cross-sectional view of a preferredembodiment DEMOS transistor50 after some preliminary construction steps.Transistor50 is constructed relative to asubstrate60 which, in the present example and the preferred embodiment, is a p-type semiconductor substrate and is preferably part of an integrated circuit. AnSTI region62 is formed first insubstrate60, and like the prior art it defines an adjacent area generally referred to as the active area, that is, the area in which the transistor source/drain regions will be formed. However, as further appreciated below, the alignment of various regions in the preferred embodiment are not relative toSTI region62 as they are in the prior art.STI region62 is formed by first forming a pit or void within the upper surface ofsubstrate60 and then filling the pit with an insulator and planarizing the insulator to leave the remaining insulator portion shown in FIG. 2aasSTI region62. AfterSTI region62 is formed, a well64 is formed insubstrate60, and in the preferred embodiment well64 is formed using n-type dopants to thereby create an n-well64. Note that n-well64 extends laterally across the entire span of FIG. 2aand, thus, it is not tightly constrained relative toSTI region22; however, its outer edges (not shown) may by photographically aligned with respect toSTI region22, but those edges are of lesser consequence because they do not lie proximate the gate conductor which is formed later. Alternatively these outer areas may be self-aligned relative to other STI or field oxide regions. In any event, n-well64 preferably is formed by masking the surface ofsubstrate60 and then implanting dopants through any open area of the mask.
• FIG. 2[0023]billustrates a cross-sectional view ofDEMOS transistor50 from FIG. 2aafter additional construction steps. Agate dielectric66 is formed oversubstrate60, and it may be an oxide, a thermally grown silicon dioxide, a nitride, an oxynitride, or a combination of these or other insulators. Agate conductor68 is formed overgate dielectric66 and is patterned to extend partially overSTI region62, such as by forming a layer of conductive material which is patterned and etched to formgate conductor68. Further,gate conductor68 may be formed from polysilicon, although other materials may be used. Aftergate conductor68 is formed, an angular implant is performed in the area shown in FIG. 2bto the left ofgate conductor68 and for the purpose of forming a p-well70, that is, to form a well of opposite conductivity type relative to well64 (which is n-type). Further in this regard, note that such an angular implant has been used in the art of formation of other semiconductor devices, but typically it is used to form a second region of a same conductivity type as the first region within which the second region is formed (e.g., a p-region in a p-well or an n-region in an n-well). In such devices, the angular implant is sometimes referred to as a halo implant or a pocket implant. In any event, due to the angular nature of the implant, part of p-well70 extends laterally underneathgate conductor68 to a greater extent than if a standard vertical implant were used, and in the preferred embodiment a subsequent anneal is performed which may cause the p-type dopants to encroach laterally even more so undergate conductor68. As is important for reasons detailed later, note that the formation of p-well70 defines anedge70aunderneath gate conductor68, and edge70ais self-aligned to edge68aofgate conductor68. In other words, the location ofedge70aoccurs due to the masking effect of a physical device structure, namely,gate conductor68 rather than from a photolithographically imposed edge such as from a photolithographic mask.
• FIG. 2[0024]cillustrates a cross-sectional view ofDEMOS transistor50 from FIG. 2bafter an additional construction step. An n-type region71 is formed preferably using a standard implant followed by an annealing step, withregion71 being formed in p-well70 and preferably using a relatively light doping concentration as compared to higher-doped n-type regions formed below in connection with FIG. 2d.In one embodiment,region71 may be formed using the same mask as is used to form p-well70, but using a lower energy than used for p-well70 and also using a vertical implant, whereby the combination of these factors yields a depth of penetration of the dopants that is less than that of well70 as shown. Additionally, for the formation ofregion71, there may not be a need for a separate mask for that lightly doped region since, like p-well70,region71 also self-aligns to edge68aofgate conductor68. As an alternative embodiment, however, a separate mask may be used. Further, typically the annealing step used in the formation ofregion71 causes it to diffuse slightly undergate conductor68 andgate dielectric66. As further detailed below,region71 forms part of the source fortransistor50, whereas n-well64 acts in part as the drain oftransistor50. As a result, atransistor channel74 is defined undergate conductor68 and extending between the interface betweenedge70aand n-well64 and theright edge71aofregion71.
• FIG. 2[0025]dillustrates a cross-sectional view ofDEMOS transistor50 from FIG. 2cafter additional construction steps. Sidewall insulators76₁and76₂are formed alongedges68aand68b, respectively, ofconductor68, such as by forming an insulator layer over the entire structure and etching it appropriately. Thereafter, two doped regions78₁and78₂are formed at the same time and preferably using a standard implant followed by an annealing step, with region78₁being formed in p-well70 and acting in combination withregion71 as the source S₂while region78₂is formed in n-well64 and acts in part as the drain D₂. In the preferred embodiment, regions78₁and78₂are n-type regions with relatively high doping concentrations (e.g., relative to n-well64 and region71) and are, therefore, labeled in FIG. 2dwith an N+ designation. Region78₁has one edge78a₁proximate and preferably slightly under sidewall insulator76₁, while its other edge extends away from gate conductor68 (and is not shown, but would be to the left in FIG. 2d). Region78₂has one edge78a₂proximate and abuttingSTI region62, while its other edge extends away fromgate conductor68 and STI region62 (and is not shown, but would be to the right in FIG. 2d). Thus, in operation, when a large drain voltage is applied relative togate conductor68, then considerable voltage may be dropped acrossSTI region62 betweengate conductor68 and region78₂, thereby avoiding damage togate dielectric66. Further, n-type region78₂functions only as part of the drain oftransistor50 in that the like conductivity type n-well64 effectively extends the drain region undergate conductor68. Accordingly,transistor channel74 is defined undergate conductor68 and extending between the interface betweenedge70aand n-well64 and theright edge71aof lightly dopedregion71.
• Given the preceding, various observations may be made relative to the preferred embodiment such as with reference to FIG. 2[0026]d.As a first observation and with respect toregions71 and78₁, note that each has an edge that is self-aligned with respect togate conductor68. With respect toregion71, itsedge71a,which isadjacent channel74, is self-aligned with respect to edge68aofgate conductor68, meaningedge68acreates a physical mask and, thus, a physical reference point relative to where edge ofregion71ais formed in response to the dopant implant. With respect to region78₁, its edge78a₁is self-aligned with respect to sidewall insulator76₁. Here, sidewall insulator76₁creates the physical reference point relative to where edge78a₁is formed in response to the dopant implant. Lastly, because sidewall insulator76₁is fixed togate conductor68, then edge78a₁is also therefore self-aligned relative togate conductor68. As a second observation, therefore, note that the lateral length ofchannel74 is defined only by self-aligned features. More particularly, theleft edge74aofchannel74 is defined by the self-alignedright edge71aofregion71, and theright edge74bofchannel74 is defined by the self-alignedright edge70aof p-well70. Accordingly, bothedges74aand74bofchannel74 are self-aligned, and in the preferred embodiment they are self-aligned relative to edge68aofgate conductor68. As a result, the length ofchannel74 is more predictable as compared to a device, such astransistor10 of the prior art, wherein at least one or both edges of the channel are photolithographically defined as opposed to self-aligned. This improvement in channel length predictability gives rise to greater uniformity for various transistors formed in a mutual substrate using the same design astransistor50, and when implemented as a DEMOS transistor there is the added advantage of improved device reliability. As still another benefit, the length ofchannel74 is determined primarily by the angular implant used to form p-well70 and, thus, by controlling the angular implant a considerably small channel may be achieved, and such a small channel may be highly desirable in various instances.
• The preceding has demonstrated various benefits of the preferred embodiment, many of which arise in connection with the formation of p-well[0027]70 using an angular implant. Further in this regard, note that various alternatives are also contemplated within the present inventive teachings as relating to that angular implant. As a first embodiment for the p-well70 formation step, note thattransistor50 may be constructed relative tosubstrate60 at the same time that other devices are being formed relative to that same substrate. Further, some of those other devices may use an angular implant for other reasons, such as forming a second region within a previously-formed region, where both regions have the same conductivity type as mentioned earlier. Given this possibility, in one approach the formation of p-well70 may occur during the same step of using the angular implant for other reasons, that is, the same energy level and dopant concentration used for the other devices may be used to form p-well70. In such an approach, no additional fabrication steps are required to constructtransistor50 that were not already required to construct other devices relative tosubstrate60. As a second embodiment for the p-well70 formation, however, a separate angular implant, with a different energy and/or dopant concentration, may be used solely to create p-well70 (and any other comparable wells for other transistors liketransistor50 then being formed in substrate60). This latter approach increases the number of fabrication steps, but it also gives added flexibility in the formation of p-well70 and likewise in the design flexibility forchannel74.
• Still another benefit of the preferred embodiment arises when[0028]transistor50 is implemented as an input/output transistor on a circuit having different transistor characteristics for its input/output transistors versus its core transistors, as is commonly the case in contemporary circuits where, by way of example, the core transistors may operate at a lesser voltage than the input/output transistors such as discussed in the Background Of The Invention section of this document. In such an embodiment, the core transistors typically include source/drain regions that use two implants, a first for forming an LDD portion extending under the transistor gate, and a second implant forming the remainder of the source/drain region extending away from the transistor channel. In connection withtransistor50 and as introduced above, the same implant step used to form the n-type LDD portions for the core transistors also may be used to form n-type LDD region71 oftransistor50 in the input/output circuit. Thus, there is no need for an additional and different implant step to form n-type LDD region71 beyond that already provided for in constructing the core transistors. In addition, no LDD region need be formed in connection with drain D₂oftransistor50, because the effective lighter doping of drain D₂is achieved in connection with n-well64, and that well may be created at the same time as are other n-wells that will be required to construct p-type devices in a CMOS architecture. As a result, this elimination of additional patterning and related steps may produce a valuable cost savings for a process flow used for dual voltage integrated circuits.
• Yet another alternative in the preferred embodiment is shown in FIG. 3, which illustrates a cross-sectional view of an alternative preferred embodiment transistor designated generally at[0029]80.Transistor80 shares many attributes that are comparable totransistor50 described above and, thus, these attributes are not discussed in significant detail. Looking briefly to these comparable attributes,transistor80 is constructed relative to asubstrate90, which preferably is a p-type semiconductor substrate. An n-well92 is formed insubstrate90, and agate dielectric94 is formed oversubstrate90 and, hence, over n-well92. Next, agate conductor96 is formed overgate dielectric94, preferably from polysilicon or other suitable materials. Aftergate conductor96 is formed, an angular implant is performed in the area shown in FIG. 3 to the left ofgate conductor96 and for the purpose of forming a p-well98, thereby forming a well of opposite conductivity type relative to well92 (which is n-type). Due to the angular nature of the implant, part of p-well98 extends laterally underneathgate conductor96 to a greater extent than if a standard vertical implant were used, and in the preferred embodiment a subsequent anneal is performed which may cause the p-type dopants to encroach laterally even more so undergate conductor96. The formation of p-well98 defines anedge98aunderneath gate conductor96, and edge98ais self-aligned to edge96aofgate conductor96.
• After[0030]gate conductor96 and p-well98 are formed, a lightly doped region100₁is formed self-aligned to edge96aofgate conductor96 and within p-well98. Preferably, region100₁is formed using a standard vertical implant with a relatively light doping concentration and followed by an annealing step which causes both regions to diffuse slightly undergate conductor96 andgate dielectric94. In one embodiment, region100₁may be formed using the same mask as is used to form p-well98, but using a lower energy and vertical implant so that the depth of penetration of the dopants is less than that of well98 as shown. Additionally, for the formation of region100₁, there may not be a need for a separate mask for that lightly doped region since, like p-well98, region100₁also self-aligns to edge96aofgate conductor96. As an alternative embodiment, however, a separate mask may be used. In any event, after the formation of region100₁, sidewall insulators102₁and102₂are formed alongedges96aand96b,respectively, ofgate conductor96. Following that step, two symmetric doped regions104₁and104₂are formed at the same time and preferably using a standard implant followed by an annealing step, with region104₁being formed in p-well98 and acting in combination with region100₁as the source S₃while region104₂is formed in n-well92 and acts in part as the drain D₃. Preferably, regions104₁and104₂are n-type regions with relatively high doping concentrations (e.g., relative to n-well92 and regions100₁and100₂) and are, therefore, labeled in FIG. 3 with an N+ designation.
• Having detailed the various components of[0031]transistor80, note that its source S₃, as comprising region104₁and region100₁, is self-aligned with respect togate conductor96. Specifically, region100₁is adjacent achannel106 and is self-aligned with respect to edge96aofgate conductor96, while region104₁is self-aligned with respect to sidewall insulator102₁and, hence, also with respect togate conductor96. Moreover, edge98aof p-well98 is self-aligned relative togate conductor96 for the same reasons as discussed above relative to p-well70 oftransistor50. Thus, the length ofchannel106 is well-controlled because both of its lateral boundaries, shown vertically in FIG. 3, are self-aligned boundaries. As a result, the length ofchannel106 is more predictable as compared to a prior art device such astransistor10 of the prior art and, hence, device reliability and operability in the preferred embodiment are improved.
• From the above, it may be appreciated that the above embodiments provide an improved transistor with a self-aligned channel implant and gives rise to numerous improvements over the prior art. Further, while various alternatives have been provided above, others are contemplated within the inventive scope. For example, other components may be added to[0032]transistor50 in addition to those shown in FIG. 2dor totransistor80 shown in FIG. 3. As another example, while one preferred transistor is illustrated as a particular configuration of a DEMOS transistor, other DEMOS transistors or indeed, transistors other than DEMOS transistors, also may benefit from the present inventive teachings. As yet another example, when the preferred embodiment is implemented as a DEMOS transistor, it may connected in various circuit configurations. For example, the preferred embodiment may prove quite useful for input/output connections, such as in an open drain/collector configuration. In one instance of such a configuration, the drain oftransistor50 may be physically isolated and connected directly to an integrated circuit bond pad. As still another example, while the preferred embodiment has been illustrated as an n-channel transistor, the present teachings may be used to form a comparable p-channel transistor by complementing various of the material conductivity types described above. Still further, additional alterations may be ascertained by one skilled in the art. Consequently, while the present embodiments have been described in detail, various substitutions, modifications or alterations could be made to the descriptions set forth above without departing from the inventive scope which is defined by the following claims.

Claims (23)

1. A transistor, comprising:

a gate conductor;

a gate insulator separating the gate conductor from a semiconductor material having a first conductivity type;

a drain region having the first conductivity type;

an angular implanted region having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge underlying the gate conductor;

a source region formed within the angular implanted region; and

a transistor channel defined between an edge of the source region proximate the gate conductor and the angular implanted region edge underlying the gate conductor:

2. The transistor ofclaim 1 wherein the edge of the source region proximate the gate conductor is self-aligned with respect to the gate conductor.

3. The transistor ofclaim 2 wherein the angular implanted region edge underlying the gate conductor is self-aligned with respect to the gate conductor.

4. The transistor ofclaim 3 wherein the semiconductor material having a first conductivity type comprises a semiconductor material having an n-type.

5. The transistor of claim4:

and further comprising a p-type semiconductor substrate;

and wherein the semiconductor material comprises an n-well formed in the p-type semiconductor substrate.

6. The transistor ofclaim 5 and further comprising:

a gate insulator separating at least a portion of the gate conductor from the semiconductor material; and

an insulating region proximate one edge of the gate conductor;

and wherein the drain region has a first edge abutting the insulating region and a second edge extending away from the insulating region and the gate conductor.

7. The transistor ofclaim 6 wherein the drain region has a higher dopant concentration than the semiconductor material.

8. The transistor ofclaim 7 wherein the source region has the first conductivity type.

9. The transistor ofclaim 1 wherein the angular implanted region edge underlying the gate conductor is self-aligned with respect to the gate conductor.

10. The transistor ofclaim 1 wherein the semiconductor material having a first conductivity type comprises a semiconductor material having an n-type.

11. The transistor ofclaim 1:

and further comprising a p-type semiconductor substrate;

and wherein the semiconductor material comprises an n-well formed in the p-type semiconductor substrate.

12. The transistor ofclaim 1 and further comprising:

a gate insulator separating at least a portion of the gate conductor from the semiconductor material; and

an insulating region proximate one edge of the gate conductor;

and wherein the drain region has a first edge abutting the insulating region and a second edge extending away from the insulating region and the gate conductor.

13. The transistor ofclaim 1 wherein the drain region has a higher dopant concentration than the semiconductor material.

14. The transistor ofclaim 1 wherein the source region has the first conductivity type.

15. A method of forming an integrated circuit, comprising the steps of:

forming a gate insulator;

forming a gate conductor relative to the gate insulator such that the gate insulator separates the gate conductor from a semiconductor material having a first conductivity type;

forming a drain region having the first conductivity type;

performing an angular implant to form an angular implanted region having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge underlying the gate conductor;

forming a source region formed within the angular implanted region; and

wherein the steps of performing an angular implant and forming a source region define a transistor channel between an edge of the source region proximate the gate conductor and the angular implanted region edge underlying the gate conductor.

16. The method of claim15:

wherein the gate insulator, the gate conductor, the source region, the drain region, and the angular implanted region form a first transistor;

and further comprising forming a second transistor comprising the step of using the angular implant to form at least one region of the second transistor into a previously-formed region of the second transistor.

17. The method ofclaim 16 wherein the at least one region has a conductivity type which is the same as a conductivity type of the previously-formed region.

18. The method ofclaim 15 wherein the edge of the source region proximate the gate conductor is self-aligned with respect to the gate conductor.

19. The method ofclaim 18 wherein the angular implanted region edge underlying the gate conductor is self-aligned with respect to the gate conductor.

20. The method ofclaim 19 wherein the semiconductor material having a first conductivity type comprises a semiconductor material having an n-type.

21. The method ofclaim 20 wherein the semiconductor material comprises an n-well formed in a p-type semiconductor substrate.

22. The method ofclaim 21 and further comprising:

forming a gate insulator separating at least a portion of the gate conductor from the semiconductor material; and

forming an insulating region proximate one edge of the gate conductor;

and wherein the drain region has a first edge abutting the insulating region and a second edge extending away from the insulating region and the gate conductor.

23. The method ofclaim 22 wherein the drain region has a higher dopant concentration than the semiconductor material.

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