US20020030649A1 - Wireless communication device having a color sequential display - Google Patents

Abstract

A color active matrix display system allows random access of pixel electrodes. The control electronics is fabricated with the active matrix circuitry using single crystal silicon technology. The control electronics includes a random access data scanner and random access spec scanners. By selectively actuating pixel electrodes in the active matrix display region, compressed video information can be directly displayed on the active matrix display panel. Color stripes are used to generate sequential color systems to produce a color image from the active matrix display panel.

Description

RELATED APPLICATIONS
• This application is a continuation-in-part of U.S. patent application Ser. No. 08/216,817 entitled “Color Sequential Display Panels” filed Mar. 23, 1994 by Zavracky et al., which is incorporated herein by reference in its entirety.[0001]
BACKGROUND OF THE INVENTION
• Flat-panel displays are being developed which utilize liquid crystals or electroluminescent materials to produce high quality images. These displays are expected to supplant cathode ray tube (CRT) technology and provide a more highly defined television picture or computer monitor image. The most promising route to large scale high quality liquid crystal displays (LCDs), for example, is the active-matrix approach in which thin-film transistors (TFTs) are co-located with LCD pixels. The primary advantage of the active matrix approach using TFTs is the elimination of cross-talk between pixels, and the excellent grey scale that can be attained with TFT-compatible LCDs.[0002]
• Flat panel displays employing LCDs generally include five different layers: a white light source, a first polarizing filter that is mounted on one side of a circuit panel on which the TFTs are arrayed to form pixels, a filter plate containing at least three primary colors arranged into pixels, and finally a second polarizing filter. A volume between the circuit panel and the filter plate is filled with a liquid crystal material. This material will alter the polarization of light in the material when an electric field is applied across the material between the circuit panel and a ground affixed to the filter plate. Thus, when a particular pixel of the display is turned on, the liquid crystal material rotates polarized light being transmitted through the material so that the light will pass through the second polarizing filter.[0003]
• The primary approach to TFT formation over the large areas required for flat panel displays has involved the use of amorphous silicon, which has previously been developed for large-area photovoltaic devices. Although the TFT approach has proven to be feasible, the use of amorphous silicon compromises certain aspects of the panel performance. For example, amorphous silicon TFTs lack the frequency response needed for large area displays due to the low electron mobility inherent in amorphous material. Thus the use of amorphous silicon limits display speed, and is also unsuitable for the fast logic needed to drive the display.[0004]
• As the display resolution increases, the required clock rate to drive the pixels also increases. In addition, the advent of colored displays places additional speed requirements on the display panel. To produce a sequential color display, the display panel is triple scanned, once for each primary color. For example, to produce color frames at 20 Hz, the active matrix must be driven at a frequency of 60 Hz. In brighter ambient light conditions, the active matrix may need to be driven at 180 Hz to produce a 60 Hz color image. At over 60 Hz, visible flicker is reduced.[0005]
• One such color sequential system has been described by Peter Jansen in “A Novel Single Light Valve High Brightness HD Color Projector,” Society For Information Display (SID), Technical Paper, France 1993. In this system, dichroic filters are used to separate light from an arc lamp into three primary colors that are shaped into rectangular stripes which are sequentially scanned across a single light valve using a rotating prism. The control circuitry for this system was fabricated using discrete components for the active matrix, the column drivers and three commercially available random access row drivers mounted separately onto a glass panel with the column drivers and the active matrix. The active matrix was fabricated in poly-silicon and connected to the drivers using pin connections.[0006]
• Owing to the limitations of amorphous silicon, other alternative materials include polycrystalline silicon, or laser recrystallized silicon. These materials are limited as they use silicon that is already on glass, which generally restricts further circuit processing to low temperatures.[0007]
• A continuing need exists for systems and methods of controlling pixels and drive circuits of panel displays having the desired speed, resolution and size and providing for ease, and reduced cost of fabrication.[0008]
SUMMARY OF THE INVENTION
• A preferred embodiment of the invention is an integrated circuit random access video display for displaying an image from a video source. An active matrix drive circuit and an active matrix display region are fabricated in a common integrated circuit module. The integrated circuit module can be formed in a silicon-on-insulator (SOI) structure that is transferred onto an optically transmissive substrate such as glass. A light box module translates a digital video signal into an active matrix drive signal. The active matrix display region has an array of pixel electrodes and an array of pixel transistors registered to the array of pixel electrodes. The pixel transistors actuate the pixel electrodes in response to the active matrix drive signal from the control circuit. The integrated circuit module can then be used to fabricate a liquid crystal display device for use in a projection display system or a head-mounted display system.[0009]
• In particular, the control circuit includes one (or more) random access select scanner and a column driver. The select scanner can enable a row of pixel transistors at random. The column driver can provide actuation signals to the transmission gates that allow video data to flow into the enabled pixel transistors. Timing information for the select scanner and the column driver is provided by a control signal generator, which is also fabricated in the integrated circuit module. The circuit module can also include a video memory, D/A converters, and at least one frame buffer for storing at least one video signal from digital data representing the video image. In a particular preferred embodiment, the display generates color images and there is a frame buffer for the digital data, associated with each primary color (e.g., red, green, blue). In another preferred embodiment, the frame memory is partitioned into channels. The column driver preferably actuates individual pixel electrodes that can be randomly selected by the control circuit.[0010]
• In a preferred embodiment of the invention, the video source is any analog or digital video source including a computer, television receiver, high-definition television (HDTV) receiver or other similar sources. In particular, the active matrix display region is compatible with HDTV formats and is a 1280-by-1024 pixel array. The pixels have a pitch that is preferably in the range of 10-55 microns such that multiple integrated circuit modules can be fabricated on a single five inch wafer.[0011]
• In a particular preferred embodiment, the control circuit generates compressed video data to obtain further bandwidth reductions. As such, only pixels whose data value has changed since the last video frame needs to be updated. Preferably, the control circuit is compatible with standard active matrix drive techniques.[0012]
• As referenced above, a preferred embodiment of the invention includes a process of fabricating an active matrix display in which a circuit is fabricated with an SOI structure and then transferred onto an optically transmissive substrate. The pixel electrodes can be fabricated prior to transfer using processes described in U.S. Pat. No. 5,206,749 entitled “Liquid Crystal Display Having Essentially-Single Crystal Transistors Pixels and Driving Circuits,” the teachings of which are incorporated herein by reference. The pixel electrodes can be made of a transmissive silicon material or a conductive metal oxide such as indium tin oxide. The pixel electrodes can also be formed after transfer of the circuit and connected through the insulator as described by Vu et al. in U.S. Pat. No. 5,256,562 entitled “Method For Manufacturing A Semiconductor Device Using a Circuit Transfer Film,” the teachings of which are incorporated herein by reference. Other methods for fabricating pixel electrodes are described by Zavracky et al. U.S. Ser. No. 08/215,555 filed on Mar. 21, 1994 and entitled “Methods of Fabricating Active Matrix Pixel Electrodes,” the teachings of which are incorporated herein by reference.[0013]
BRIEF DESCRIPTION OF THE DRAWINGS
• The above and other features of the invention, including various novel details of construction and combination of parts, will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular color sequential display panels embodying the invention is shown by way of illustration only and not as a limitation of the invention. The principles and features of this invention may be employed in varied and numerous embodiments without departing from the scope of the invention.[0014]
• FIG. 1 is a block diagram of a control system for a color active matrix display.[0015]
• FIG. 2 is a block diagram of the[0016]light box circuitry7 of FIG. 1.
• FIG. 3 is a schematic block diagram of a display panel drive circuit.[0017]
• FIG. 4 is a schematic diagram illustrating a preferred embodiment of a color sequential display system using a scanning prism.[0018]
• FIGS.[0019]5A-5C are views of the scanning prism120 of FIG. 3 illustrating color scanning.
• FIGS.[0020]6A-6C are views of-theactive matrix display90 of FIG. 3 corresponding to the color scanning of FIGS.5A-5C.
• FIG. 7 is a schematic diagram of a preferred embodiment of a color sequential display system using a rotating cone.[0021]
• FIG. 8 is a schematic block diagram of a color shutter display system.[0022]
• FIG. 9 is a schematic diagram illustrating a preferred embodiment of a ferroelectric liquid crystal color generator as a color filter system.[0023]
• FIG. 10 is a schematic block diagram of a digital falling raster system.[0024]
• FIG. 11 is a schematic diagram of an FLC color filter having an arbitrary number of electrodes.[0025]
• FIGS.[0026]12A-12B are schematic timing diagrams for the color shutter systems of FIG. 8.
• FIG. 13 is a schematic block diagram of a digital drive circuit having wide low-speed RAM.[0027]
• FIG. 14 is a schematic block diagram of a digital drive circuit having narrow high-speed RAM.[0028]
• FIGS.[0029]15A-15B are schematic block diagrams of an analog drive circuit.
• FIG. 16 is a timing diagram of the drive circuit of FIG. 15B.[0030]
• FIG. 17 is a schematic diagram of a preferred color display system utilizing electronically-controlled color shutters.[0031]
• FIGS.[0032]18A-18B are schematic diagram illustrating another preferred embodiment of the invention employing a rotating prism.
• FIG. 19 is a schematic illustration of a color sequential projection system utilizing a binary optic.[0033]
• FIG. 20 is a schematic elevational view of pixel rows in a color sequential LCD display.[0034]
• FIG. 21 is a schematic diagram of a head mounted color sequential LCD display system.[0035]
• FIG. 22 is a perspective view of an optics module and partial broken view of the housing for the module in a head-mounted display system.[0036]
• FIG. 23 is a back view of two modules for a binocular head mounted display.[0037]
• FIG. 24 is a cross-sectional view of an optics module housing for a head mounted display.[0038]
• FIG. 25 is a perspective view of a sliding ramp system for the housing.[0039]
• FIG. 26 is an alternative embodiment for the optical system of a color sequential head mounted display.[0040]
• FIG. 27 is another preferred embodiment of a color sequential head mounted optical system.[0041]
• FIG. 28 is a perspective view of a monocular head mounted color sequential LCD system.[0042]
• FIGS.[0043]29A-29D are perspective and side views of a head mounted computer system having a monocular color sequential display.
• FIG. 30 is a schematic communications network for a head mounted color sequential display system.[0044]
• FIG. 31 is a perspective view of a head mounted color sequential display system.[0045]
• FIG. 32 is a schematic view of the eye-piece module for a color sequential head mounted system.[0046]
• FIG. 33 is a cross-sectional view of a transferred silicon active matrix liquid crystal display.[0047]
• FIG. 34 is a partial cross-sectional view of an active matrix display circuit with a preferred pixel structure for a color sequential system.[0048]
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION
• A preferred embodiment of a control system for a color active matrix display is shown in FIG. 1. A[0049]video signal adaptor2 provides color video signals to alight box module7. Thevideo signal adaptor2 can include any analog or digitalvideo signal source1,4 including a Video Graphics Array (VGA) adaptor, the Apple™ Macintosh™ family of computers, a National Television Systems Committee (NTSC) composite video source, a High-Definition Television (HDTV) receiver, a high-resolution professional display adapter, a Charge-Coupled-Device (CCD), a PAL video source, a SECAM video source, or other similar sources. As illustrated, the work station or computer-generated video signals from agraphics controller1 are processed by amonitor electronics module3 to provide the color video signal, typically a 24-bit RGB signal with Hsync and Vsync information, to thelight box7. Similarly, television broadcasts4 are processed by atelevision electronics module5 to provide the color video signal to thelight box module7. In a particular preferred embodiment, an activematrix display panel9 is adapted as a computer-controlled light valve that displays color images to a viewer. The images can be displayed directly to the viewer or by projection onto a viewing surface. In a particular preferred embodiment, the light valve is part of a head-mounted display (HMD) device.
• Flat panel displays have pixels where the analog RGB signal must contain information on screen position. For the position information to be accurate, each scan line of the analog RGB signal must be divided into discrete values. That task is performed by the[0050]video signal adaptor2, which provides digital color data for each pixel.
• The active[0051]matrix display panel9 operates as a variable multi-frequency display device. Video signals from the video signal source may not be synchronized to a known fixed frequency. A change in the video mode can change the resolution of the data, measured in pixels. For example, aVGA adaptor1 generates synchronization signals that vary depending on the particular video mode in which the adaptor is operating. Astandard VGA adaptor1 can generate a vertical synchronization (Vsync) frequency between about 56 and 70 Hz and a horizontal synchronization (Hsync) frequency between about 15 and 35 Khz. For professional display purposes (e.g., CAD/CAM) the Hsync and Vsync frequencies can be higher than described. To handle current high resolution display applications, the display device can preferably adapt to Vsync frequencies up to about 100 Hz and horizontal synchronization frequencies up to about 66 Khz. In addition, a change in the video mode can also invert the polarities of the synchronization signals. Consequently, a preferred embodiment of the invention adapts to changes in the synchronization signals caused by changes in the video mode.
• FIG. 2 is a block diagram of the[0052]light box module7 of FIG. 1. Thelight box module7 receives the Hsync signal11, theVsync signal13 and acolor data signal15, which is typically operating at 300 MHz from thevideo signal adaptor2. In a preferred embodiment of the invention, the color data signal15 represents the color of each pixel as a 24-bit digital value. The video signals11,13,15 are received by avideo receiver interface10, which formats the color data signal15 for storage in avideo frame memory25. In particular, thevideo receiver interface10 converts the serial colordata input stream15 intoparallel data22 for storage in thevideo frame memory25. The Hsync signal11 and theVsync signal13 are also provided to acontrol signal generator12.
• The[0053]control signal generator12 generates control signals for operating the activematrix display panel9 in response to the Hsync11 andVsync13 signals from thevideo signal source2. In a preferred embodiment, thecontrol signal generator12 permits display of video images at a horizontal resolution of at least 640 pixels and a vertical resolution of at least 480 pixels (640H×480V). In a preferred embodiment of a HMD, the image resolution is at least 1280H×1024V.
• In another preferred embodiment, the aspect ratio of the active[0054]matrix display panel9 is selected to be compatible with High-Definition Television (HDTV) formats, such as 1920H×1080V, 1824H×1026V and 1600H×900V. Furthermore an HDTV-compatible 1280H×720V image can be formed in a 1280H×1024V display or a 1280H×1024V image can be formed in an 1824H×1026V or 1920H×1080V display. It is understood that other video modes having different video rates and resolutions can be supported as well, with minor modifications.
• The[0055]control signal generator12 converts the synchronization signals11,13 into pixel timing information for the pixel columns and select line timing information for the pixel rows of the active matrix. Thecontrol signal generator12 provides control registers to adjust and delay thepixel clock143,pixel data142,select clock147, andselect data146 so the image generated by thevideo source1,4 (e.g. VGA, HDTV) can be precisely mapped to the active matrix pixel resolution (e.g., 640H×480V; 1280H×1024V). Thecontrol signal generator12 provides a pixel data signal142 and apixel clock signal143 to a data scanner42 (FIG. 3). Thevideo signal generator12 also provides a select line data signal146 and a selectline clock signal147 to select scanners46 (FIG. 3).
• Preferred embodiments of the invention supply one or four clocks for each[0056]clock signal143,147. By supplying multiple clocks for eachclock signal143,147, the circuitry of thescanners42,46 can be simplified. This is especially important where thescanners42,46 are monolithically fabricated on an SOI structure with theactive matrix region90 and thelight box module7 is a discrete component.
• Furthermore, the[0057]control signal generator12 provides aframe switch signal121 to thevideo receiver interface10. The data scanner clock and data pulse rate is determined by the number of parallel video input channels. The data scanner can scan sequentially, or alternatively, it can use a random access procedure. Note that in another embodiment, theselect data146 orselect clock147 can be used as a serial address line.
• Because the video data is received in digital form, the[0058]video receiver interface10 can generate normal or inverted video data signals in response to the frame switch signal121 from thevideo signal generator12. Preferably, the polarity of the video signal is switched every video field (every Vsync). The switch can occur more or less often, as might be desirable to inhibit crosstalk or other purposes. Theframe switch signal121 is synchronized to the frame rate.
• In a preferred embodiment, a column inversion technique is used to reduce crosstalk between select lines to reduce or avoid the production of a DC offset voltage. A video switch provides an alternating opposite polarity for the column pixels. The even column pixels are operated at the opposite polarity of the odd column pixels. The polarities of the column pixels are switched on each sequential frame. For example, on one frame even column pixels operate at a positive polarity and odd column pixels operate at a negative polarity relative to the display common electrode. On the next sequential frame, the polarities of the odd and even columns are switched. As a result, the even column pixels operate at a negative polarity and the odd column pixels operate at a positive polarity.[0059]
• Another preferred embodiment of the invention uses a frame inversion technique instead of column inversion. Using frame inversion, each column during any one frame has the same polarity. On alternating frames, as clocked by the[0060]frame switch signal121, the polarity of each column is reversed. In that way, the polarity of the entire active matrix region90 (FIG. 3) is inverted on each successive frame. This frame inversion embodiment does not require the use of distinct odd and even data registers or video drive lines. Other preferred embodiments are row inversion or pixel inversion techniques.
• The[0061]control signal generator12 can also adapt the writing of each line. For example, in a preferred embodiment of the invention the image is written for each select line from the edges of thedisplay panel9 toward the center of thedisplay panel9. Another preferred embodiment writes the video data from the center of thedisplay panel9 outward toward the edges. In yet another preferred embodiment, the video data is scanned left to right across the display panel. Each column of the display can also be randomly accessed. These various video data writing techniques are provided under the control of thecontrol signal generator12.
• In a preferred embodiment of the invention, the[0062]display panel9 is driven at 60 Hz frame rate. During each frame, thedisplay panel9 is overwritten with data for the three primary colors (e.g., RGB). Consequently, there are 180 subframes displayed per second. This produces a pixel data rate of about 300 Mhz. Because the video data must be in digital form to be stored in memory for time compression, it must be converted to analog signal by digital to analog converters (DACS). However, it would require a super-high speed DAC to operate at 300 Mhz. Consequently, a preferred embodiment of the invention separates the video signal into n channels. The number of channels is a design decision where an increase in the number of channels becomes more difficult to manage while the operating speed of the DACs is lowered. Preferably, there are sixteen (n=16) channels of video data and each channel has its own DAC operating at one-sixteenth of the total pixel data rate.
• Accordingly, the[0063]video receiver interface10 partitions the incoming video data signal15 into channels of video data. Each channel carries video data at an offset from the edge of the panel so that the channels stagger the video data for the pixels across the display. For example, with the number of channels being16 (n=16), the first channel can carry data for every 16th pixel starting from the left-most pixel (C₁, C₁₇, C₃₃, . . . ) and the second channel can carry data for every 16th pixel starting form the second left-most pixel (C₂, C₁₈, C₃₄, . . . ), etc. The offset for each channel can be selected by thevideo receiver interface10.
• The video data are fed through an[0064]input bus22 to avideo frame memory25. Thevideo frame memory25 is addressed by an addressingsignal125 from thecontrol signal generator12.
• An[0065]output bus27 delivers the addressed video data from thevideo memory25 to aline memory32 for each channel. ADAC34 for each channel reads the video data from theline memory32, converts the digital video data to an analog video signals input to the panel drive circuit. The analog video signals are amplified by output amplifiers36-1, . . . ,36-n to yield video drive signals35-1, . . . ,35-n which are used to drive the columns44 of thedisplay panel9.
• The data supplied from the[0066]output bus27 at any one time is either red data from a red frame buffer, or green data from a green frame buffer, or blue data from a blue frame buffer. The appropriate data value is provided via theoutput bus27 by the output colorselect signal127 from thecontrol signal generator12.
• In a preferred embodiment where the inputs are red, green, and blue data, the color[0067]select signals127 are two-bit data signals. The chosen data value for each channel is converted back into an analog video signal by thechannel DAC34. Eachoutput amplifier36 amplifies the analog video signal to levels required to drive the LCD circuitry.
• The[0068]video receiver interface10 can also receive control interface signals from a user at17A for adjusting hue, contrast, and brightness and at17B for inversion, gamma correction and liquid crystal voltage offset. Except for hue, these control interface signals can instead be received by the output amplifiers36-1, . . . ,36-n.
• The drive circuitry can incorporate gamma corrections and shading corrections as noted above. Gamma corrections may be required for each primary color if the electro-optical transfer characteristic (transmission vs. pixel voltage) in the liquid crystal varies with wavelength. Shading correction may be required to compensate for the length of time that an image row is displayed on the[0069]panel9. The drive circuitry can also incorporate inversion techniques and offsets.
• FIG. 3 is a schematic block diagram of the active matrix drive circuitry. A[0070]video signal bus35 carries the analog video signals from theDAC amplifiers36 to the column drivers44. Because signal interference and signal loss can occur as the analog video signal crosses each signal line in thesignal bus35, the channels of video signals are arranged to reduce interference. As illustrated, there are four column drivers44a-44d, twocolumn drivers44a,44bat the top of theactive matrix region90 and twocolumn drivers44c,44dat the bottom of theactive matrix region90. Each channel is allocated to one of the column drivers44 such that each column driver44 receives video from four channels. As illustrated, thetop column drivers44a,44breceive video from the channels that drive the odd-numbered columns and thebottom column drivers44c,44dreceive video from the channels that drive the even-numbered columns. As shown, no video signal has to cross the path of more than one other video signal.
• The illustrated arrangement of column drivers is particularly suited for edge-to-center and center-to-edge video writing, although the data can also be written from left-to-right or right-to-left. It should be understood that more or less than four column drivers[0071]44 can be employed in preferred embodiments of the invention.
• The[0072]data scanners42 are responsive to the pixel data signal142 and thepixel clock signal143. Thedata scanners42 can use a shift register array to store data for each scan. An odd shift register array can be used to store data to odd column pixels and an even shift register array can be used to store data to even column pixels. As illustrated, there are left and rightodd data scanners42a,42band left and right evendata scanners42c,42d.
• The column drivers[0073]44 selected by thedata scanner42 will transmit video data to a selected column C in theactive matrix region90. The select scanner46 determines by control lines which pixels accept this column data.
• To reduce signal loss across the[0074]active matrix region90, the select lines are driven from both sides by select scanners46. As viewed in FIG. 3, a leftselect scanner46aand rightselect scanner46bare connected to theselect data line146 and theselect clock line147. A third enablingline148 can also be used after specific applications. The leftselect scanner46aprovides a select line signal at the end of the select line nearest the lowest-valued pixel column (C₁) and rightselect scanner46bprovides a select line signal at the end of the select line nearest the highest-valued pixel column (C_N). Thus, an identical select line signal is supplied at both ends of the select line.
• Although static shift registers can be used, the shift registers of the[0075]data scanner42 and the select scanners46 are implemented as dynamic shift registers. The dynamic shift registers rely on capacitor storage without leakage. However, dynamic shift registers are susceptible to leakage, especially when they are exposed to light. Hence, light shields are needed to protect thescanners42,46 from exposure to light. Similarly, light shields are also used to protect the transmission gates44 and pixels.
• In another preferred embodiment of the invention, the select scanners[0076]46 are random access select scanners. Each random access select scanner can be addressed to drive any row of pixels during any pixel clock period. As such the select scanners46 need not include shift registers. The select line is directly provided by the rowselect signal146, which is implemented as an address bus.
• In another preferred embodiment of the invention, the[0077]data scanner42 is a random access data scanner to select any column of pixels for any clock period. When used in conjunction with random access select scanners, thelight box module7 can actuate any pixel on theactive matrix region90 during any pixel clock period. This embodiment requires the use of double gate pixel transistors for receiving two digital select inputs (row select and column select) to signal pixel actuation with the video signal for the selected pixel. With a fully random accessactive matrix region90, data compression techniques with burst mode refresh of thevideo frame memory25 can be used to write changed pixels to the display.
• In a preferred embodiment of the invention, the panel drive circuitry of FIG. 3 is fabricated as an integrated circuit with the[0078]active matrix region90. The integrated circuitry is preferably fabricated in single crystal silicon having a silicon-on-insulator (SOI) structure using the fabrication and transfer procedures described previously. By fabricating the row andcolumn drive circuitry42,44,46 in single crystal with theactive matrix region90, the size of the display panel is not constrained by the connecting pins for the various discrete components. The integrated fabrication also increases the operating speed of the display over displays constructed from discrete components. Furthermore, the drive circuitry can be optimized to increase display performance. For example, it is easier to construct a 35 mm format-compatible 1280H×1024V display panel with dual select scanners through integrated fabrication than it is using discrete components.
• The pixels in a preferred embodiment are approximately 24 microns square. Consequently, a 1280H×1024V active matrix with the control system can be fabricated such that there are two such integrated circuits on a four inch wafer, four circuits on a five inch wafer and six circuits on a six inch wafer. In another preferred embodiment of the invention, the select scanners[0079]46, thedata scanner42 and the column driver44 are integrated on chip with theactive matrix region90.
• FIG. 4 is a schematic diagram illustrating a preferred color sequential display system according to the invention. As illustrated, a[0080]light source200 having a reflector generates a beam ofwhite light205 that is focused on adichroic mirror assembly210. Thedichroic mirror assembly210 separates thewhite light205 into three parallel strips ofprimary color light211,212,213 separated by unlit black bands214. Preferably, the primary color light isred light211,green light212, andblue light213. The strips of red, green and blue light become incident on aprism220 which is rotatably about a center axis225 under the control of thedrive signal145 from the control system of FIG. 2. Theprism220 is rotated such that the color strips211,212,213 scan vertically downward relative to the figure.
• FIG. 5A-[0081]5C are views of therotating prism220 of FIG. 4. The prism acts as a tilted parallel plate to move the color stripes as it rotates. When the facingsurface221 is perpendicular to the incident light rays (FIG. 6A) the light rays are passed directly through theprism220. As the prism is rotated, the facingsurface221 becomes tilted relative to the incident rays (FIG. 6B). Thebottom color stripe213 is scrolled to the top position and theother color stripes211,212 are scrolled downward. This process is continued in FIG. 5C. Each time a color stripe reaches the bottom, rotating of theprism220 redirects the color stripe to the top from where the stripe repeats its downward motion.
• Returning to FIG. 4, a[0082]field lens230 can be used to align the color stripes exiting from therotating prism220 with theactive matrix display90. Using thescanning prism220, every part of the light valve is exposed equally with rapidly alternating colors and the full spectrum of thelight source200 is utilized at all times. Immediately after a color stripe passes a row of pixels, refresh begins with picture information pertaining to the next color. Theprism220 inherently produces dark bands between the RGB color stripes which accommodate the finite response time of the light valve.
• A[0083]projection lens240 can be used to project the image generated on theactive matrix region90 to a user. Theactive matrix region90 must be addressed and supplied with video information consistent with the scrolling illumination. To this end, theactive matrix region90 is partitioned into three equal height segments as shown in the views of FIGS.6A-6C.
• Each segment is scanned by the[0084]row drivers46a,46b(FIG. 3). Therow drivers46a,46bcan be enabled sequentially in a fixed top-middle-bottom order. However, therow drivers46a,46bcan also implement non-linear scanning. Thecontrol signal generator12 also accommodates non-linear scanning, which is a function of the rotating prism (and liquid crystal speed). The liquid crystal speed can vary due to temperature wavelength. Thecontrol signal generator12 compensates for any liquid crystal speed variations when producing control signals.
• Timing is programmed such that active rows closely track the illumination pattern in each segment. The video data, written to the independent RGB frame buffers[0085]25-xR,25-xG,25-xB is retrieved under control of the colorselect signal127 offset by one-third of the display height. The RGB data are first time compressed and then line-by-line multiplexed into the serial format required by the column driver44. FIGS.6A-6C illustrate thecolor segments91,92,93 corresponding to thered stripe211,green stripe212 andblue stripe213 as scrolled in respective FIGS.5A-5C.
• By using color stripes, the duty cycle of the available light incident on the display can be maximized. Additionally, there is reduced variation in the brightness from the top to the bottom of the display because each line is active with each color for exactly the same amount of time. This is not true with color schemes that change the color of the entire display after writing a frame of data where two of the colors have been removed from light being transmitted through the light valve at any one time.[0086]
• FIG. 7 is a schematic diagram of a preferred color sequential system using a rotating color cone. A[0087]light source200 having a reflector generates awhite light205 focused on acone250. Thecone250 is divided into three equal segments, one red, one green, and one blue. As thewhite light205 becomes incident and passes through thecolor cone250, an expanding beam ofcolor light251 is produced. The color of thecolored light251 is dependent on the color of the cone segment transmitting the light. Thecolor light251 is focused by afield lens260 into parallel rays of light which are transmitted through theactive matrix region90.
• The[0088]color cone250 is rotated by amotor255 coupled to thecone250 by anaxle256. The motor is synchronized to the frequency of thedrive signal145 from thevideo signal generator12 of FIG. 2. The colorselect signal127 is also synchronized to the retention of thecone250 to provide data from the red buffer25-xR, green buffer25-xG and blue buffer25-xB in sequence to the column driver44.
• FIG. 8 is a schematic block diagram of a color shutter display system. Illustrated is a color[0089]sequential drive circuit407, which accepts VGA input in either analog or digital form and other standard or proprietary video inputs. Thedrive circuit407 itself can be either digital or analog as will be described in detail below.
• A[0090]lamp410 projects white or RGB light through afield lens420. Thelamp410 can either be a continuous light source or a flashing light source. The light output from thefield lens420 is collimated on an electroniccolor filter system430.
• The[0091]drive circuit407 controls thecolor filter system430 over acolor signal bus435. Under the control of thedrive circuit407, thecolor filter system430 passes either red, green or blue light. In certain applications, it is advantageous for thecolor filter system430 to also block all light.
• The filtered light from the[0092]color filter system430 is collimated on anactive matrix LCD90. Preferably, thecolor filter system430 is transferred from a substrate and epoxied to theLCD90 to form a single module. Alternatively, thecolor filter system430 can be transferred and epoxied to thefield lens420 or elsewhere in the optical path. Theactive matrix LCD90 is controlled by thedrive circuit407 over adata bus495 to form an image. The image formed on theactive matrix panel90 is projected by anoutput lens440 onto aviewing surface450, which may be a projection screen or rear projection Fresnel lens. Theoutput lens440 can also be a viewing lens for use in direct viewing of the active matrix image.
• FIG. 9 is a schematic diagram of a ferroelectric liquid crystal (FLC) color generator as a[0093]color filter system430 according to a preferred embodiment of the invention. Illustrated is a two-stage multiple wavelength blocking filter, incorporating fast switching ferroelectric liquid crystal surface stabilized SSFLC cells (F1 . . . F5). The stages are defined by polarizers P1 . . . P3 and there are two FLC cells F1, F2 in a first stage bounded by crossed polarizers P1, P2 and three PLC cells F3, F4, F5 in a second stage, bounded by parallel polarizers P2, P3. Thecolor filter system430 is designed to selectively transmit three visible colors (red, green and blue), and is capable of rapid color switching to generate a visual display of a continuous range of visible colors.
• The two-stage blocking filter of FIG. 9 generates a transmission output centered at 465 nm (blue), 530 nm (green) and 653 nm (red). The[0094]color filter system430 consists of three independent two-stage birefringent filter designs which are electronically selectable. For each output, the product of the transmission spectrum of each stage yields a narrow highly transmitted band centered at a chosen wavelength, here a primary color, while effectively blocking all other visible wavelengths. Preferably each stage should have a common maximum centered at a selected color (i.e., primary color). For effective out-of-band rejection, additional maxima for a particular stage must coincide with minima of another stage.
• Each selected band to be transmitted (for example, each primary color band) is produced by switching at least one FLC cell in each stage. Switching more than one FLC cell in a particular stage increases retardation, thus changing the transmission spectrum. The blocking filter consists of two stages, one bounded by crossed polarizers P[0095]1, P2, the other bounded by parallel polarizers P2, P3. The polarization of each polarizer is shown by the arrows. The filter contains the five FLC cells P1 . . . P5, each with a selected thickness of liquid crystal, arranged between the polarizers. The arrows shown on each FLC cell, and the corresponding angles (α₁-α₅) represent the orientation of the optic axes with respect to the input polarizer. These angles can be either 0 or π/4 radians. The transmission of the filter is the product of the transmission spectra of the individual stages. A stage with multiple independently switchable FLC cells can produce multiple transmission spectra.
• The first stage consists of two FLC cells F[0096]1, F2 between the crossed polarizers P1, P2. By switching-the second cell F2 (α₂=π/4), the output is centered in the green (530 nm) and has minima at 446 nm and 715 nm. Switching both cells F1, F2 (α₁α₂=π/4) produces a spectrum that has maxima at 465 nm (blue) and 653 nm (red), with a minima at 530 nm.
• The second stage consists of three cells F[0097]3, F4, F5 between the parallel polarizers P2, P3. With only the fifth cell F5 switched, the output has a maximum at 442 nm (blue) and a minimum at 700 nm. Switching all three cells F3, F4, F5 produces an output having a narrow band centered at 530 nm. The function of the second stage is to narrow the green output (obtained with cell F1 switched), and to select between the blue or red outputs produced when the first stage FLC cells F1, F2 are both switched. Switching the fifth cell F5 blocks the red output of the first stage while transmitting blue output. Switching both the fourth and fifth cells F4, F5 strongly transmits the red at 610 nm, while blocking blue output at 470 nm. Switching all three cells F3, F4, F5 of the second stage narrows the green output (530 nm) from the first stage.
• The source spectrum (i.e., white light) can be transmitted by the filter by switching the first FLC cell F[0098]1 only. The first cell F1 is a zero order half-waveplate over most of the visible. Therefore, when the first cell F1 is switched, the input polarization is rotated by π/2 to align with the optic axis of the second cell F2 and the exit polarizer P2. Because the second stage is between parallel polarizers, none of those cells F3, F4, F5 need be switched. A summary of switching requirements necessary to obtain all outputs is provided below in Table 1.

  TABLE 1
  Summary of Switching Requirements for the FLC
  Blocking Filter of FIG. 7.

  	OUTPUT	α1	α2	α3	α4	α5
  	WHITE	π/4	0	0	0	0
  	BLUE	π/4	π/4	0	0	π/4
  	GREEN	0	π/4	π/4	π/4	π/4
  	RED	π/4	π/4	0	π/4	π/4
  	BLACK	0	0	—	—	—

• The thicknesses of the FLC cells F[0099]1 . . . F5 are; 1.8 μm, 5.2 μm, 2.6 μm, 1.7 μm, and 6.1 μm, respectively. The cell substrates are two λ/10 optical flats, each having one side coated with an ITO transparent electrode. The alignments layer is preferably an oblique vacuum deposited layer of SiO. Typically, the transmission of a single cell without an antireflective (AR) coating is 90%. By using HN42HE dichroic polarizers P1 . . . P3, cementing the cells in each stage together with index matching epoxy and AR coating exterior surfaces, the filter can transmit 50% of incident polarized light.
• The blocking filters have been described specifically for use with an apparently white light source. They have been designed particularly to produce selected wavelength transmission in the visible spectrum. A more detailed description of tunable filters employing FLC cells is provided by Johnson et al. in U.S. Pat. No. 5,132,826, entitled “Ferroelectric Liquid Crystal Tunable Filters and Color Generators,” the teachings of which are incorporated herein by reference. It will be clear to those of ordinary skill in the art that sources other than white light can be employed with FLC blocking filters. The modifications in FLC thickness, choice of materials, source light, etc. required to employ FLC filters for different light sources and in different wavelength region can be readily made by those of ordinary skill in the art.[0100]
• In blocking filters, the thickness of the FLC cells and the relative orientations of the polarizer elements are selected to optimize transmission of desired wavelengths in the blocking filter and minimize transmission of undesired wavelengths. FLC cells with the required thickness and optical transmission properties for a particular color generation application can be readily fabricated using techniques known in the art. The color blocking filters, like those of FIG. 9 can be readily adapted for temporal color mixing such as for Lyot-type filters. Application of an appropriate voltage duty cycle scheme to switch the desired pairs of FLC cells can generate a range of perceived colors (color space).[0101]
• In addition, a blocking filter can be designed to transmit the source light (most often white) with no wavelength effect in one switched configuration state, and transmit no light in another switched state (black). FLC pulsing schemes of such a filter can include switching to white and black to allow more flexible selection of generated colors. Blocking filters switching between two selected wavelengths or more than three selected wavelengths can be implemented by appropriate selection of FLC cells (thickness) and positioning and orientation of polarizers. Additional spectral purity of transmitted color (i.e., narrower band width) can be achieved while retaining blocking of unwanted colors by increasing the number of stages in the filter with appropriately selected FLC cells in the stages.[0102]
• In a preferred embodiment of the invention, chiral smectic liquid crystal (CSLC) cells are used as the FLC cells F[0103]1 . . . F5. Color generators using CSLC cells are available from The University of Colorado Foundation, Inc. as described by Johnson et al. in U.S. Pat. No. 5,243,455 entitled “Chiral Smectic Liquid Crystal Polarization Interference Filters,” the teachings of which are incorporated herein by reference. A unique characteristic of CSLC cells is their fast switching speeds (order of 10's to 100's of μsec). Filters of the present invention are capable of greater than 10 kHz tuning rates, for example between two or more discrete wavelengths. In situations where relatively slow response detectors are used, such as with photographic or movie film, or the human eye, pseudo colors can be generated using the rapidly switching filters described herein. Rapid switching between two primary color stimuli can be used to generate other colors, as perceived by the slow detector, which are mixtures of the primary colors. For example, the two monochromatic stimuli, 540 nm (green) and 630 nm (red) can be mixed in various portions to create the perception of orange (600 nm) and yellow (570 nm).
• Optically, this mixing can be done by varying the quantity of power of the primary stimuli in a transmission. The same result can be achieved by switching between the two stimuli (spatially superimposed or closely adjacent) at rates faster than the response time of the eye (or any detector which averages over many periods). Color can be generated in this way using the filters described herein by varying the time for which the filter is tuned to any particular primary stimulus compared to another primary stimuli. By changing the percentage of a square wave period during which the filter is tuned to one of the primary stimuli with respect to another (i.e., varying the duty cycle of an applied voltage, for example), there is a perceived generation of colors which are mixtures of the primary inputs. In effect, the quantity of optical power transmitted in each primary stimulus is varied by changing the ratio of time which the filter is tuned to each of the primary bands. Because the response time of the human eye is about 50 Hz, the eye will average optical power over many cycles of filter switching, and many colors can be generated for visual detection.[0104]
• FIG. 10 is a schematic block diagram of a digital falling raster system. The digital falling raster system is similar in construction to the FLC[0105]color filter system430 illustrated in FIG. 9. Here, the color filters Fly, F2′, F3′, F4′, F5′ of thecolor filter system430′ are each equally divided into three horizontal sections F1′, F1b′, F1c′, . . . , F5a′, F5b′, F5c′. Each section F1a′, . . . , F5c′ is separately addressed and controlled by theFLC driver270′ so the system produces three color stripes as an output at any one time. Each color strip may be either red, green, blue or black, with black used during data writing to theLCD90. This is accomplished by using three individual electrodes on each color filter, instead of the single electrode described above with respect to FIG. 9.
• As can be seen, the number of electrodes on the FLC filters F[0106]1′, . . . , F5′ can be increased to increase the number of color stripes for displaying color images and thus the duty cycle of the light incident on thecolor filter system430. For example, there can be one color stripe for each line of theLCD90. This would permit more efficient color display techniques.
• FIG. 11 is a schematic diagram of a preferred embodiment of an FLC color filter F[0107]_x″ having an arbitrary number of electrodes E₁. . . E_N. Preferably, there is one electrode E per display line of the LCD. AnFLC Driver270″ is preferably fabricated with the electrodes as a single circuit module, one for each FLC filter F_x″. TheFLC Driver270″ includes acolor decoder276 and aselect line scanner278. TheFLC Driver270″ receives a row address from the selectdata address bus146, theselect clock signal147, and a colorselect signal127 from control circuitry (not shown).
• The[0108]decoder276 of eachFLC Drive270″ is tailored to the specific FLC color filter F_x″ in the resulting color filter system. Consequently, thedecoder276 will either enable operation of theselect scanner278 for a particular color or inhibit such operation, according to the above table in response to thecolor selection signal127. The enablement signal is provided to the select scanner over enableline148.
• The[0109]select scanner278 receives the select line address279 and, if enabled by thedecoder276, energizes the selected electrode E. If thedecoder276 has not enabled theselect scanner278, then no action is taken by-theselect scanner278 for the addressed row.
• As another alternative, each display pixel or block of display pixels (i.e., superpixel) on the[0110]LCD90 can correspond to an individual color filter by forming an active matrix on thecolor filter system430, which are registered to the pixel electrodes on theLCD90. This embodiment permits random color access for each pixel on thedisplay90. Such a random color access in combination with random access select and data scanners of thedisplay panel90 permits full color burst mode refresh of the displayed image.
• Returning to FIG. 8, if the[0111]lamp410 is a flashing light source, then a lamp controller415 (shown in phantom) is used to control the flashing of thelamp410 via aflash synchronization line417. Thelamp controller415 is under the control of thedrive circuit407.
• FIG. 12A is a schematic timing diagram for a flash color shutter system. Illustrated is one frame of standard parallel RGB video. Typically, there are 60 frames of RGB video per second. For each color to be displayed, the[0112]drive circuit407 writes data to theLCD90 over thedata bus495. Thedrive circuit407, while writing the color data, switches thecolor filter system430 to the color corresponding to the color being written to theLCD90. After the color data in the video frame has been written, thedrive controller407 signals thelamp controller415 to flash thelamp410. The steps repeat with the next color. Typically, thecolor filter system430 is switched and thelamp410 flashes at 180 Hz (i.e., three times per video frame, once for each color).
• FIG. 12B is a timing diagram of a continuous light color shutter system. Illustrated is one frame of standard parallel RGB video. The[0113]drive circuit407 of data switches thecolor filter system430 to black and color data is written to theLCD90. After a complete video frame of data has been written to theLCD90, thedrive circuit407 signals oversignal line435 to thecolor filter system430 to switch to the color filter corresponding to the color data written to theLCD90.
• FIG. 13 is a schematic block diagram of a[0114]digital drive circuit407 having a wide bit width low-speed RAM. An analog digital signal is separated into red, green and blue channels. For the red channel, the analog signal is adjusted by aninput circuit510R, which includes avariable gain amplifier512R to adjust contrast and apotentiometer514R to adjust brightness of the video signal. The output from theinput circuit510R is converted to an 8-bit digital signal by an analog-to-digital (A/D)converter515R. The A/D converter515R preferably operates at about 108 MHz for a 1280H×1024V display.
• A series of[0115]parallel latches520R separates the input digital intom channels520R-1, . . . ,520R-m. As illustrated, there are m=16 channels and therefore there are 16 latches. Each latch represents one column of the display. The latched outputs are fed to aframe memory530R, where the digital read data is stored in either aplay frame memory532R or acapture frame memory534R in a 16 column by 8-bit format. Preferably, the latches520 and the frame memory530 operate at about 6.75 MHz for a 1280H×1024V display. Such components are readily available. The total frame memory530 required is about 7.8 Mbytes for this particular embodiment.
• The[0116]appropriate frame memory530R is selected by a digital 2:1multiplexer540R and the 16 column by 8-bit data stream is fed to adigital RGB multiplexer550. The green and blue channels are identical to the above described red channel. The digital 2:1 multiplexer preferably operates at about 21.25 MHz for a 1280H×1024V display.
• The[0117]digital RGB multiplexer550 is a 3:1 8-bit multiplexer for time multiplexing the red, green and blue video data. The output from thedigital RGB multiplexer550 is fed over a 128-bit video bus to m DACs560-1, . . . ,560-m. EachDAC560 represents an input channel to the active matrix drive circuitry. Anoutput network570 is disposed between eachDAC560 for providing amplified analog signals to the drive circuitry. Theoutput network570 can invert the analog signal to implement column or frame inversions on alternate video frames. As illustrated, the even columns are driven by the positive gain amplifiers and the odd columns are driven by the negative gain amplifiers. This reverses on each successive video frame.
• FIG. 14 is a schematic block diagram of a[0118]digital drive circuit407 having a narrow bit width high-speed RAM. The RGB analog signals are separated into separate channels and input torespective input circuits610R,610G,610B, which each include avariable gain amplifier612R,612G,612B to adjust contrast and apotentiometer614R,614G,614B to adjust brightness of the input video signal. The output from the input circuits are fed to respective A/D converters615R,615G,615B to produce respective 8-bit digital color data. As above, the A/D converters615 operate at about 108 MHz for a 1280H×1024V display.
• The 8-bit color data is stored in[0119]respective RAM620R,620G,620B. The RAM is divided into two video frames622,624, one for capture and one for playback. Capture is at 108 MHz (60 frames/sec) while playback is at 324 MHz (180 frames/sec). At present, special multiplexed memory must be used to operate at such high rates. For a 1280H×1024V display, 7.8 Mbytes of RAM is required.
• The selection of the video frame is selected by a 2:1[0120]multiplexer630R,630G,630B under the control of a capture/play signal. The multiplexers630R,630G,630B input 8-bit color data into anRGB multiplexer640.
• The[0121]RGB multiplexer640 is operated under control of a timing signal generated at three times the vertical synchronization signal (VSync). A phase lock loop (PLL)690 generates pixel clocks (PClk) coherent with the horizontal synchronization signal (HSync) at three times the original input rate. The output from thePLL690 is processed by a divide-by-threecircuit695 to generate color data timing signals (PClk) for controlling the sampling at the original input rate and a divide-by-sixteencircuit697 to generate pixel multiplex (i.e., capture/playback) signals (PIXELMUX) for controlling the latch outputs for playback of the video signal.
• The[0122]RGB multiplexer640 separates the 24-bit color data into 16 video input channels to theLCD90. Each channel includes a pair of latches650. A multiplexer660 selects output from one of the latches650 and feeds that output to a DAC670. For a 1280H×1024V display, the latches operate at about 21.25 MHz. An output network680 amplifies the analog voltage for use by the active matrix drive circuitry and provides column inversion.
• FIGS.[0123]15A-15B are schematic block diagrams of ananalog drive circuit407. FIG. 15A is an analog front end circuit. The red, green and blue analog signal are each processed by a respective A/D converter715R,715G,715D to produce an 8-bit digital, data signal. The 8-bit color data is received by aframe memory720R,720G,720B. Each frame memory is divided into even and odd frames722,724. For a 1280H×1024V display, the frame memory720 operates at about 108 MHz.
• A 2:1[0124]multiplexer730R,730G,730B operates under control of an alternate frame signal to select one of either the even or odd frame. The 8-bit output from themultiplexers730R,730G,730B are received by a 3:1RGB multiplexer740. The three colors are time sequenced by theRGB multiplexer740 to yield a 24-bit digital signal. ADAC750 converts the 24-bit digital signal to a sequential RGB analog video signal. For a 1280H×1024V display, the sequential RCB signal is operating at about 324 MHz.
• FIG. 15B illustrates the drive circuitry for processing the sequential RGB analog video signal from FIG. 16A. The sequential RGB video signal is received by an[0125]input circuit760 which includesvariable gain amplifier762 to adjust contrast and apotentiometer764 to adjust brightness. Theinput circuit760 provides both even and odd video signals. Aswitch770 selects between the even and odd video signals to provide for column inversion. Anoutput network780 is also switched to provide two sets of 16 channels—one set holds signals to display while the other set sampling data for display on the next cycle. Theoutput network780 is preferably a sample and hold network. The sample and hold circuitry of theoutput network780 may be too slow to operate for a 1280H×1024V display, but would be suitable for a 640H×480V display.
• FIG. 16 is a timing diagram of the drive circuit of FIG. 15B. There are[0126]32 sample-hold amplifiers in theoutput network780, two for each of the16 output channels. The amplifiers are switched in response to a signal generated every {fraction (1/16)} of the pixel clock period. While one of the amplifiers per output channel is sampling the RGB signal, the other is holding the previously sampled data for the display.
• FIG. 17 is a schematic diagram illustrating a color sequential system using liquid crystal shutters. Liquid crystal cells S[0127]1, S2, S3 are used as a light switch instead of mechanical switches or other types of switches. A beam ofwhite light205′ passes through a first polarizer P1′ and is divided into blue, green and red components by respective mirrors M1a, M2a, M3a. The first mirror M1apasses blue light to the blue shutter S1 and reflects red and green light to a second mirror M2a. The second mirror M2areceives the red and green light reflected from the first mirror M1aand reflects the green light to the green shutter S2 and passes the red light to the third input mirror M3a. The third mirror M3areflects the red light toward the red shutter S3. The shutters S1, S2, S3 are controller by a shutter drive280. The shutter drive280 is tied to the colorselect signal127 from thevideo signal generator12 of FIG. 2. The shutter driver decodes the color select signal and actuates the appropriate shutter S1, S2, S3 to pass the corresponding colored light.
• If the blue shutter S[0128]1 is actuated, the blue light is passed through the first exit mirror M1b. If the green shutter S2 is actuated, the green light is reflected by the second exit mirror M2band the first exit mirror M1b. If the red shutter S3 is actuated, the red light is reflected by the third exit mirror M3b, passed through the second exit mirror M2band reflected by the first exit mirror M1b. The selectedexit light219 is then passed through theactive matrix region90 as previously described herein disposed between parallel polarizers P2′, P3′. Theactive matrix display90 is controlled in conjunction with driver280 to provide color sequential imaging.
• FIGS.[0129]18A-18B are schematic diagrams illustrating another preferred embodiment of the invention employing a rotating prism. In FIG. 18A, alight source200′ generates a strip beam ofwhite light205′, which is focused as a linearhorizontal stripe335 on adeflector330. Thedeflector330 can be tilted relative to the vertical plane by atranslator331. Thetranslator331 is coupled to thedeflector330 via anaxle332. The translator operates under the control of thedrive signal145 from the videocontroller signal generator12 of FIG. 2. As thedeflector330 is rotated, a deflected strip ofwhite light205″ is directed toward acolor shutter340. The optics are aligned such that a strip oflight345 is incident horizontally across thecolor shutter340.
• The resulting strip of colored light[0130]219″ is focused as acolor strip95 on theactive matrix region90. Rotation of thedeflector330 thus results in acolor light beam95 scanning down theactive matrix region90. In the preferred embodiment of the invention, the strip of colored light95 incident on theactive matrix region90 is registered to a line of pixel electrodes registered to the operation of thetranslator331. Although thetranslator331 is shown as a mechanical device, an electronically actuatedbeam deflector330 could be substituted. In another preferred embodiment of the invention, the litpixel row95 can be randomly selected by operation of thedeflector330.
• FIG. 18B is a schematic diagram that illustrates the use of a scanning dot or point to illuminate the[0131]active matrix region90. The system of FIG. 18B differs from that of FIG. 18A in that alight source200 generates a converging beam oflight205, which is focused to be incident at apoint339 on adeflector330. The deflectedwhite light205′″ is deflected to be incident on thecolor shutter340 also at a point349. The colored beam of light209′″ then becomes incident at apixel location99 of theactive matrix region90. Thedeflector330 is controlled by avertical translator331 as in FIG. 10A and ahorizontal translator333. Thevertical translator331 is controlled by thecontrol signal generator12 of FIG. 2 by therow address signal125. Thehorizontal translator333 is controlled by thevideo control generator12 of FIG. 2 via the pixel data signal142.
• The[0132]pixel99 of the activematrix display region90 is registered to the movement of thetranslators331,333 such that the translators can position of thedeflector330 in a plurality of discrete orientations, one discrete orientation for each pixel of theactive matrix region90. As discussed with regard to FIG. 18A, thebeam deflector330 can be electronically actuated. In addition, the beam can be scanned across theactive matrix region90 in a raster scan fashion.
• FIG. 19 is a schematic illustration of one embodiment of a[0133]LCD projection system1300 using color sequencing to produce a full-color image. Thesystem1300 includes three monochromatic LED point orline sources1350,1352,1354, which produce red, green and blue light, respectively. Aparabolic mirror1356 behind the point orline sources1350,1352 and1354 directs light from the sources through a diffractive or binaryoptic element1358. Thebinary optic element1358 splits the incoming light into multiple parallel horizontal bands of monochromatic light which are perpendicular to the page of the drawing. The bands of light are ordered in color along the vertical axis in a repeating pattern. For example, a red band is followed by a green band which is followed by a blue band which is followed by another red band, etc. The colored bands are projected by afield lens1360 onto theLCD panel1362. The colored bands from thebinary optic1358 are spaced such that alternating rows of pixels in the LCD are illuminated by a single colored band. The pixel rows between the illuminated rows remain black, i.e., unilluminated. Light passing through theLCD1362 is projected byprojection lens1364 onto aprojection screen1368.
• A full-color image from the[0134]LCD1362 is produced by color sequencing through the pixels. To perform the color sequencing, thebinary optic1358 is movable along the vertical axis as indicated by the arrow1370. Acontrollable actuator1372 controlled by acontroller1374 is coupled to thebinary optic1358 so as to control the vertical movement of theoptic1358. In one embodiment, theactuator1372 is a stepping actuator controlled by step pulses oncontrol lines1376 from thecontroller1374. In an alternative embodiment, the field lens can be controllably moved along the vertical axis and/or tilted about its normal axis. Thealternative actuator1332 and its associated controller1334 are shown in phantom in FIG. 19 coupled to thefield lens1360.
• In each stationary position of the[0135]binary optic1358, alternating rows of pixels of theLCD1362 receive light of a single color and transmit the light according to pixel data loaded into theLCD1362. At the same time, the unilluminated rows interposed between the illuminated rows are addressed and loaded with pixel data from aLCD controller1378 alonglines1380. When the unilluminated rows are illuminated in a subsequent step, they transmit the light according to the loaded pixel data.
• The pixel data controls whether particular pixels will pass or block the light of a particular color when they are illuminated by that color band. To control the intensity of the color, in an LCD using a ferroelectric LC, the pixel data also includes data which controls the duration of time during which the pixel will transmit light of the color. That is, pixels which require a large amount of blue in their final colors will be set for transmission durations longer than those requiring a small amount of blue. In an LCD using a twisted nematic LC, the pixel data for each pixel encodes an analog voltage level applied to the pixel to control grey scale level and, therefore, the color intensity transmitted by that pixel.[0136]
• The stepping[0137]actuator1372 is pulsed by thecontroller1374 to step thebinary optic element1358 through successive stationary positions. At every other position, each row of pixels transmits light of a particular color. When thebinary optic element1358 steps through six positions, each row of pixels has received all three color bands and has therefore produced a frame of full-color data.
• The[0138]binary optic element1358 can be produced by etching desired shapes directly into the surface of an optical material, such as glass, using photolithographic and microfabrication techniques in order to produce a controlled variation in glass thickness. Thebinary optic element1358 then creates the desired output light pattern by diffraction. The controlled variation in thickness of theelement1358 breaks up the wave front of incoming light at each point on the element's surface and reconstitutes it as a wave traveling in the desired direction. The phase delay introduced by the variation in element thickness causes the controlled redirection of the light emerging from the back surface of theoptical element1358. The surface of theelement1358 is therefore characterized by a custom phase profile dictated by the desired output optical pattern, which, in this embodiment, is a pattern of evenly spaced continuous parallel bands of light.
• The desired phase profile can be translated into a pattern of thickness steps fabricated on the surface of the[0139]element1358. The thickness steps dictated by the desired phase profile are formed by a series of photolithography and microfabrication process steps. For example, theelement1358 is first coated with a photoresist which is then masked, exposed and developed to produce a pattern on the element for the first layer of etching. Theelement1358 is then etched by reactive ion etching or other controllable etching process to remove material as desired for the layer. The next layer of steps is produced by again coating the element with photoresist and masking, exposing and developing the photoresist. The subsequent etching step produces the second layer of steps in the phase profile. The process continues until the entire phase profile of theelement1358 is produced by the varying thickness steps in theelement1358.
• The phase profile for the[0140]binary optic element1358 can be generated using a commercially available optical design tool, such as CODE V for example, a commercially available software package manufactured and sold by Optical Research Associates of Pasadena, Calif. The user of the package provides inputs to CODE V in the form of coordinates which define the configuration of the desired optical output, e.g., the evenly spaced parallel illumination bands. From the phase profile generated by the designer using CODE V, the required thickness step profile and associated masks used to fabricate the steps on theelement1358 are generated.
• In another embodiment, the process described above is used to produce a mold which can then be used to produce the[0141]binary optic element1358 in large quantities. The above steps are performed on a mold material to form a master. The master is then used to stamp a moldable optical material such as plastic into theoptical element1358 having the desired phase profile.
• FIG. 20 is a schematic elevational view of pixel rows in a LCD display[0142]24 used to illustrate the color sequencing process of the invention. The figure illustrates a single stationary position of the colored illumination bands relative to rows24a-24oof pixels. It therefore represents one step, for example, the first step, of the color sequencing process. In the following discussion,row24fof pixels will be referred to by way of example. It will be understood that the description is applicable to all rows of pixels.
• In the position shown,[0143]rows24b,24dand24fare illuminated with red, green and blue illumination bands, respectively. The pixels in these rows transmit the color with which they are illuminated according to the pixel data previously loaded into the pixel rows. That is,row24ftransmits its blue contribution to the final full-color image.Pixel rows24a,24cand24eare not illuminated (“black”) since they fall between the illumination bands. These rows are presently loaded with pixel data for the next step depending upon the next color in the sequence. For example, assuming the illumination bands are to be shifted down in the next step,row24eis presently loaded with green pixel data.
• In the next step,[0144]rows24b,24dand24fbecome black and are loaded with pixel data for the next step. For example,row24fis loaded with green pixel data. In the following step, the green band illuminatesrow24f, and the green light is transmitted according to the loaded pixel data. In the fourth step,row24fis again black while red pixel data is loaded. The binary optic is then stepped once again to move the red illumination band ontorow24f. Red data is transmitted to complete the full-color data for the particular frame forrow24f. Finally, in the sixth step, theoptic1358 is moved down one more step such thatrow24fis not illuminated. During this step,row24fis loaded with blue pixel data for the next frame.
• In a preferred embodiment, to begin the next frame, the[0145]binary optic1358 is moved back in the reverse direction a distance of six pixel line heights such that the first step in the sequence is repeated.Rows24a,24c,24eare once again black, androw24bis illuminated with red light,row24dis illuminated with green light androw24fis illuminated with blue light. Hence, in this embodiment, the color sequencing process is a periodic six-step process in which six stepper pulses are applied to the stepper actuator1372 (FIG. 1) to produce a single complete full-color frame. To ensure a full-color frame rate of 60 Hz, for example, the stepper pulse frequency is 360 Hz.
• It will be seen from FIG. 2 that for a given number of pixel rows in a display, half as many illumination bands are required, one-third of which are dedicated to each single color. That is, in a display having 480 pixel rows, a total of 240 spaced illumination bands are required, 80 of each color. The[0146]binary optic element1358 is fabricated to produce the required quantity and pattern of illuminated lines.
• In another embodiment, the binary optic is configured to produce multiple rows of equal intensity colored spots instead of the multiple continuous illumination bands of the embodiment described above. In this embodiment, the binary optic produces a two-dimensional rectangular array of spots in correspondence with the two-dimensional array of pixels in the LCD. That is, each single-colored illumination band of the embodiment-described above is replaced with a row of separate equal-intensity spots of the single color. The spots are evenly spaced to coincide with pixels along pixel rows in the[0147]LCD1362. This embodiment results in less light from the sources being lost and is therefore more optically efficient. Optical efficiency is further improved by shaping the LCD pixels such that as much as possible of each spot of light impinges on LCD pixels.
• The foregoing description refers to sequentially illuminating rows of pixels with horizontal bands or spots of colored light. It will be understood that the invention can also be implemented by sequentially illuminating columns of pixels with vertical bands of colored light. The binary optic element[0148]20 can be made to produce the vertical illumination bands, and the process described above of stepping vertically through rows of pixels can be altered to step horizontally across vertical columns of pixels.
• FIG. 21 is a schematic diagram of a head-mounted[0149]embodiment1301 of the full-color display of the invention using a diffractive or binaryoptic element1314 to perform the color sequencing operation. Thesystem1301 includes aneyepiece1302 and a control and drive circuit module1304 coupled together by conductive leads. The functional operation of theembodiment1301 shown in FIG. 3 is essentially the same as that for theembodiment1300 shown in FIG. 1, except that it is adapted to be implemented in a head-mounted environment. In the embodiment of FIG. 3, as in the previous embodiment, threeindividual LED sources1306,1308 and1310 provide the illumination for the three separate colors red, green and blue. Theparabolic mirror1312 directs the illumination light onto the diffraction or binaryoptic element1314 which produces the multiple parallel bands of monochromatic light. As in the previous embodiment, astepper actuator1322, operating via step pulses under the control of thestepper controller1324, causes thebinary optic element1314 to move as described above to produce the sequential color illumination as described above. The light passes through theLCD1316 which receives control and data from theLCD controller1326 and then reflects fromfold mirror1318 through theeyepiece lens1320 where the full-color image can be viewed. The stepper control circuitry and the LCD control circuitry are mounted on the frame of the head mounted system as described in greater detail below.
• Color sequential systems in accordance with the invention are well suited for use in head mounted displays due to their compact and light weight structure. They provide a significant improvement over existing head-mounted systems as the resolution provided by a color sequential system is substantively higher than the resolution of color filter based liquid crystal displays presently in use. When combined with the compact structure of the transferred silicon active matrix display which provides a high resolution display having a diameter of less than 1 inch as well as integrated high speed driver circuitry described herein.[0150]
• FIG. 22 is a perspective view of an[0151]optics module sub-assembly1410 with portions of the housing broken away. Two of thesemodules1410 are mounted to a triangulatedrail system1480 havingrods1482a,1482b,1482cand comprise an optics assembly. Eachoptics module1410 consists of the following: Adisplay1420; a backlight andcolor sequential system1490; alens1430; amirror1432; an optic housing1412a; a focus adjustslide1403; an IPD adjust/cover1406; and arail slide1488. The backlight system can be two or three LEDS, or alternatively two or three miniature fluorescent lamps to provide two or three primary colors respectively.
• FIG. 23 is a back-side view of two[0152]modules1410,1410′ mounted on arail system1480. As shown the twomodules1410,1410′ are mounted onrail system1480. In addition to the triangulatedrods1482a,1482b,1482c, therail system1480 includes rod and supports1484. The rods1482 are supported by a central triangulatedsupport member1486. Also illustrated are abacklight cable1492 and adisplay cable1485. Eachdisplay cable1485 is fixed to therail slide1488 by an adhesive or mechanical contact1494. Thedisplay cable1485 includes acable travel bend1483, where thedisplay cable1485 folds and unfolds to permit adjustments to theIPD1407.
• FIG. 24 is a side cross sectional view of the[0153]optics module housing1412 which is mounted onrails1482a,1482b, and1482c. The optical system includeslens1430,mirror1432, thecolor sequential generator1490 anddisplay1420.Generator1490 can be any of the compact color sequential systems described herein including, for example, the embodiments of FIG. 9 or FIG. 10, or that depicted in FIG. 21 or FIG. 32. Focus can be accomplished with a sliding ramp system, shown in FIG. 25 which is incorporated into the focus adjustslide1403 and thegenerator housing1491.Tabs1443 protruding from the generator housing are engaged inslots1445 incorporated in thefocus slide1403. As thefocus slide button1407 is moved horizontally, the backlight housing (along with the attached display) move vertically.Multiple tabs1443 ensure positive alignment throughout the motion range. Thebutton1403aserves as the top of the assembly capturing the top on the focus slide.
• FIG. 26 shows the display placed at the focal length of the[0154]lens1430, thus producing an image of the display at an apparent distance of infinity to the viewer. Generator anddisplay module1420 can include any of the compact color sequential systems described herein. The lens has a small focal length, preferable about 1 inch and can be moved as indicted at1437 to provide a manual focus adjust. The flat optical element is present to correct for lateral color separation in the lens. This element consists of adiffractive optic1434 designed to compensate for the lateral color. The mirror serves to fold the optical path to minimize the depth of the head mounted device while extending its height. The mirror is optional to the system and is present for desired form factor. Two such modules make up a binocular head mounted display system: one for each eye. The distance that the displays appear to the viewer can be adjusted for personal comfort, generally between 15 feet and infinity. Thelens1430 can slide forward and backward1437 usingframe assembly1435. The magnification of the system is about10.
• Other lens systems can be used and are available from Kaiser Electro-Optics, Inc. of Carlsbad, Calif. Such a system is described in U.S. Pat. No. 4,859,031 (issued Aug. 22, 1989), the teachings of which are incorporated herein by reference. Such a[0155]system1500 is shown in FIG.27. Thedisplay system1500 includes anactive matrix display1502, apolarizing filter1504, a semi-reflectiveconcave mirror1506, and a cholesteric liquid crystal element1508. The image that is generated by thedisplay1502 is transmitted through thefilter1504, the semi-reflectiveconcave mirror1506, to the element1508. The element1508 reflects the image back ontomirror1506 which rotates the light so that, upon reflection back to element1508, it is transmitted through element1508 to the viewer'seye1509. A lens can be used with this system depending upon the size, resolution, and distance to the viewer's eye of the optical system components and the particular application. Acolor sequential generator1505 can include the backlight system and any of the compact color sequential systems described herein.
• FIG. 28 is a perspective view of a preferred head-mounted[0156]computer1510. As illustrated, there is a head band1512,stereo headphones1603a,1603b, adisplay arm1516 connecting the headband1512 to adisplay pod1100, which includes a display panel and color sequential generator as described herein. The CPU and video drive circuitry are fabricated as an integral part of the head band1512. Shown on the head band1512 are plurality ofports1557 which accept expansion modules. As shown, there is a Personal Computer Memory Card International Association (PCMCIA) interface module1554 coupled to the head band1512. APCMIA card1558 is inserted into the PCMCIA interface module1554. Also illustrated areexpansion modules1514, such as aninfrared communication sensor1555aand a Charge Coupled Device (CCD)camera1555b.
• FIG. 29A is a partial exploded perspective view of another head-mounted[0157]computer1511 in accordance with the present invention. Thehead band1515 includes a CPU, adisk drive1564 andexpansion modules1525a,1525b,1525call interconnected together by a flexible bus1563. Eachmodule1564,1525a,1525b,1525cconnects to the bus1563 by arespective connector1517a.
• Also shown in FIG. 29A are[0158]earphones1603a,1603bfor providing audio information to the wearer. Attached to one of the earphones is amicrophone arm1690 having amicrophone1559 at its distal end. Theearphones1603a,1603bare hinged to thehead band1515 to provide a comfortable fit for the wearer.
• A[0159]frame assembly1600 is coupled to each end of thehead band1515 by arespective pin1602a,1602b. Thepins1602a,1602ballow theframe assembly1600 to be rotated up and over thehead band1515. In that position, the head-mountedcomputer1511 is compactly stored and easy to carry.
• The[0160]frame assembly1600 includes a pair ofdistal arms1610a,1610bwhich are coupled to the head band1512 by thepins1602a,1602b. Ahorizontal support1630 telescopes out from theproximal arms1610a,1610band around the forehead of the wearer. At least onedisplay pod1100 is mounted to thehorizontal support1630. As illustrated, asingle display pod1100 provides for monocular display. Thedisplay pod1100 is preferably slidable along thehorizontal frame1630 for use with either the left or right eye of the wearer. Thedisplay pod1100 includes aneye cup1102.
• FIG. 29B is a side elevation of the head-mounted[0161]computer1511 of FIG. 29A.
• FIG. 29C is a perspective view of the head-mounted[0162]computer1511 of FIG. 29A with the frame assembly pivoted. The head-mountedcomputer1511 can be worn in this position by a person or it can be stored or carried in this position.
• FIG. 29D is a perspective view of the head-mounted[0163]computer1511 of FIG. 29A worn by a wearer. Thedisplay pod1100 is positioned for viewing before either eye and themicrophone1559 is positioned to receive voice signals.
• FIG. 30 is a functional block diagram of a preferred head-mounted computer architecture according to the invention. The head-mounted[0164]computer1710 includes aCPU1712 having read and write access over the bus to a localdata storage device1714, which can be a floppy disk, a hard disk, a CD-ROM or other suitable mass storage devices. TheCPU1712 also drives a display driver1716 to form images on the display panel1700 for viewing by the wearer.
• Either the head or body mounted platforms can house a memory modem or other expansion card[0165]1741 conforming to the PCMCIA standards. These cards are restricted to fit within a rectangular space of about 55 mm in width, 85 mm in length, and 5 mm in depth.
• A[0166]servo1760 communicates with theCPU1712 to vary the position of the display panel1700 relative to the wearer's eyes. Theservo1760 is controlled by the wearer through an input device1718. Theservo1760 operates a motor1518 to raise or lower the vertical position of the display panel1700. Thus the display panel1700 can be positioned so the wearer can glance up or down at the image without the display panel1700 interfering with normal vision. Additionally, the display panel1700 can be stowed outside the field of view. The CPU or display driver can be used to control color sequential system operation.
• The[0167]CPU1712 also sends and receives data from acommunication module1720 for interfacing with the outside world. Preferably, thecommunication module1720 includes a wireless transducer for transmitting and receiving digital audio, video and data signals. Acommunication module1720 can also include a cellular telephone connection. Thecommunication module1720 can likewise interface directly with the Plain Old Telephone Service (POTS) for normal voice, facsimile or modem communications. Thecommunication module1720 can include a tuner to receive over-the-air radio and television broadcasts.
• The[0168]CPU1712 can also receive and process data from anexternal sensor module1730. Theexternal sensor module1730 receives data signals fromsensors1735, which provide data representing the external environment around the wearer. Such sensors are particularly important where the wearer is encased in protective gear.
• When the wearer is clothed in protective gear, an[0169]internal sensor module1740 can receive sensor data from sensors1745 within the protective gear. The data from the internal sensors1745 provide information regarding the wearer's local environment. In particular, the internal sensors1745 can warn the wearer of a breach or failure of the protective gear.
• In addition, the[0170]CPU1712 can also receive data from alife sign module1750. Thelife sign module1750 receives data fromprobes1755 implanted in or attached to the wearer. The life sign data from theprobes1755 provides theCPU1712 with information regarding the wearer's bodily condition so that corrective actions can be taken.
• The[0171]sensor modules1730,1740,1750 receive data from associated detectors and format the data for transmission over the bus1513 to theCPU1712. The sensor modules can also filter or otherwise preprocess the data before transmitting the preprocessed data to theCPU1712. Thus, each expansion module can contain a microprocessor.
• The wearer can control the operation of the[0172]CPU1712 through the input device1718. The input device1718 can include a keyboard, a mouse, a joystick, a pen, a track ball, a microphone for voice activated commands, a virtual reality data glove, an eyetracker, or other suitable input devices. A preferred eyetracker is described in U.S. Pat. No. 5,331,149 (issued Jul. 19, 1994), the teachings of which are incorporated herein by reference. In a particular preferred embodiment of the invention, the input device1718 is a portable collapsible keyboard. Alternatively, the input device1718 is a wrist-mounted keypad.
• As illustrated, the head-mounted[0173]computer1710 is a node on a distributed computing network. The head-mountedcomputer1710 is in communication with a distributedcommand computer1770 via thecommunication module1720. The distributedcommand computer1770 has access to distributed data storage1775 for providing audio, video and data signals to the head-mounted computer. The distributedcommand computer1770 can also be in communication with acentral operations computer1780 havingcentral data storage1785. Such external networks can be particularly adapted to applications of the head-mounted display or may be general purpose distributed data networks.
• FIG. 31 shows a detailed perspective view of a preferred embodiment of a monocular head mounted display. The display pod[0174]1900 includes an eyecup1902 that is fabricated from a pliable material. The pod can be turned by a wearer to adjust the vertical position of the display pod1900 in the wearer's field of view. The wearer can also adjust the distance of the display pod1900 from the wearer's eye, can swivel the pod relative to the visor at pivotingconnector1920, or can tilt the pod up by the wearer out of the field of view. The visor1930 can also house the video interface circuitry including the color sequential drive circuitry, as well as the circuit harness for the display which can be connected either through thearm1932 suspending the pod athinge1938 or throughoptional cable1934. Amicrophone1940 can be connected to visor1935 or toaudio unit1942 by connector1330 and input cable (not shown) can be connected on the opposite side.
• The display pod can be positioned against a user's glasses, or against the eye, or retracted above the eye, or pressed against the visor.[0175]
• The[0176]display pod1950 can include several different color sequential optical systems. FIG. 32 illustrates another preferred embodiment utilizing threedifferent color lamps1952,1954,1956 areflector1958, a diffuser1960, and active matrixliquid crystal display1955 andlens1962.
• The active matrix and liquid crystal displays fabricated and used in conjunction with the color sequential systems described herein can be made using a transferred silicon process.[0177]
• FIG. 33 illustrates a partial cross-sectional view of a transferred silicon active matrix liquid crystal display which[0178]1968 includes a transistor formed with a thin film singlecrystal silicon layer1970 over an insulatingsubstrate1974. The areas or regions of the circuit in whichpixel electrodes1972 are formed with silicon or can be formed by subjecting the area to a silicon etch to expose the underlying oxide followed by deposition of the transparentconductive pixel electrode1972 on or over the exposed oxide with a portion of the deposited electrode extending up the transistor sidewall to the contact metalization of the transistor sidewall to the contact metalization of the transistor. Apassivation layer1972 is then formed over the entire device, which is then transferred to a opticallytransparent substrate1978. Atransparent adhesive1977 is used to secure the circuit to thesubstrate1978. Thecomposite structure1975 is then attached to acounterelectrode1973 and polarization elements (not shown) and a liquid crystal material1979 is then inserted into the cavity formed between theoxide layer1974 and thecounterelectrode1973.
• A[0179]further embodiment1980 of the display is fabricated in a manner similar to that described in FIG. 33, but which employs a different pixel electrode and insulator structure is shown in FIG. 34. This involves exposing a portion of the single crystal silicon layer in which the transistor circuit is formed by removing the exposed portion throughopenings1984 in theinsulator1974 after transfer (substrate1978 and adhesive1977 not shown) to form the structure shown in FIG. 34. The conductivetransparent electrode1982 is formed as shown that can directly contact the transistor circuit at a contact area or the exposed silicon can be treated prior to contact formation as described previously. A further optional passivation layer (not shown) can also be added to cover thepixel electrode1982 to provide electrical isolation, and planarization of the pixel area. The circuit can then be packaged with the liquid crystal material to form the display. The circuits can also be used to form a active matrix electroluminescent displays as described in U.S. Ser. No. 07/943,896, filed on Sep. 11, 1992, the contents of which are incorporated herein by reference. Instead of color filters, however, a color sequential system such as that described in connection with FIG. 9 and FIG. 10 herein can be mounted onto the circuit and driven by the necessary control circuit for color sequential operation.
• Equivalents[0180]
• Those skilled in the art will know, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments of the invention described herein. These and all other equivalents are intended to be encompassed by the following claims.[0181]

Claims (46)

What is claimed is:

1. A portable communications device comprising:

a wireless telephone transceiver that receives audio and image data;

an audio transducer;

a liquid crystal display panel optically coupled to a light source, the light source having a plurality of light emitting diode devices (LEDs);

a lens that enlarges images on the display panel; and

a sequential color circuit connected to the display panel and the light source such that the light source generates a plurality of colors in sequence.

2. The device ofclaim 1 wherein the LEDs comprise red, green, and blue LEDs.

3. The device ofclaim 1 wherein the device comprises a portable telephone.

4. The device ofclaim 1 further comprising a reflector around the LEDs.

5. The device ofclaim 1 further comprising a diffuser.

6. The device ofclaim 1 further comprising a lens for magnifying an image of the liquid crystal display panel.

7. The device ofclaim 1 wherein the display comprises an active matrix display.

8. The device ofclaim 1 further comprising a camera.

9. The device ofclaim 1 wherein the light source comprises a plurality of red, a plurality of green and a plurality of blue LEDs.

10. The device ofclaim 1 wherein the display and the sequential color circuit are positioned in a display module housing that is attached to a transceiver housing.

11. The device ofclaim 1 wherein the device comprises a head mounted display system.

12. The device ofclaim 1 further comprising a control processor connected to the sequential color circuit.

13. The device ofclaim 12 further comprising a memory connected to the control processor.

14. The device ofclaim 1 wherein the display comprises an active matrix circuit bonded to a transmissive substrate.

15. A method of displaying images with a portable communications device comprising:

receiving audio and image data with a wireless telephone transceiver;

generating a plurality of image with a liquid crystal mix display panel subframes for each color image frame, each subframe having a different color;

a lens that enlarges images on the matrix display panel; and

displaying each subframe in temporal sequence on the liquid crystal matrix display panel illuminated by a plurality of light emitting diode devices (LEDs) to display a color image frame that is enlarged by a lens that is optically couples to the matrix display panel.

16. The method ofclaim 15 further comprising providing a portable telephone housing that contains the transceiver.

17. The method ofclaim 16 further comprising providing a display housing that houses the display, the display housing being pivotably connected to the telephone housing.

18. The method ofclaim 15 further comprising the step of providing an active matrix liquid crystal display panel.

19. The method ofclaim 15 wherein the LEDs for illuminating the display is a backlight.

20. A portable communications device comprising:

a wireless telephone transceiver that receives image data;

an audio transducer;

a liquid crystal display panel optically coupled to a light source, the light source having a plurality of light emitting diode devices (LEDs);

a lens that enlarges images on the display panel; and

a sequential color circuit connected to the display panel and the light source such that the light source generates a plurality of colors in sequence.

21. The device ofclaim 20 wherein the LEDs comprise red, green, and blue LEDs.

22. The device ofclaim 20 wherein the device comprises a portable telephone.

23. The device ofclaim 20 further comprising a reflector around the light emitting devices (LEDs).

24. The device ofclaim 20 further comprising a diffuser.

25. The device ofclaim 20 further comprising a lens for magnifying an image of the liquid crystal display panel.

26. The device ofclaim 20 wherein the display comprises an active matrix display.

27. The device ofclaim 20 further comprising a camera.

28. The device ofclaim 20 wherein the light source comprises a plurality of red, a plurality of green and a plurality of blue LEDs.

29. The device ofclaim 20 wherein the display and the sequential color circuit are positioned in a display module housing that is attached to a transceiver housing.

30. The device ofclaim 20 wherein the device comprises a head mounted display system.

31. The device ofclaim 20 further comprising a control processor connected to the sequential color circuit.

32. The device ofclaim 31 further comprising a memory connected to the control processor.

33. The device ofclaim 23 wherein the display comprises an active matrix circuit bonded to a transmissive substrate.

34. A wireless telephone comprising:

a telephone housing;

a wireless transceiver within the housing that receives audio and image data;

an audio transducer;

a liquid crystal display panel optically coupled to a light source, the light source having a plurality of light emitting diode devices (LEDs);

a lens that enlarges images on the display panel;

the display panel, light source and lens being mounted in a display module housing attached to the telephone housing; and

a sequential color circuit connected to the display panel and the light source such that the light source generates a plurality of colors in sequence.

35. The device ofclaim 34 wherein the LEDs comprise red, green, and blue LEDs.

36. The device ofclaim 34 further comprising a reflector around the LEDs.

37. The device ofclaim 34 further comprising a diffuser.

38. The device ofclaim 34 further comprising a lens for magnifying an image of the liquid crystal display panel.

39. The device ofclaim 34 wherein the display comprises an active matrix display.

40. The device ofclaim 34 further comprising a camera.

41. The device ofclaim 34 wherein the light source comprises a plurality of red, a plurality of green and a plurality of blue LEDs.

42. The device ofclaim 34 wherein the display and the sequential color circuit are positioned in a display module housing that is attached to a transceiver housing.

43. The device ofclaim 34 wherein the device comprises a head mounted display system.

44. The device ofclaim 34 further comprising a control processor connected to the sequential color circuit.

45. The device ofclaim 44 further comprising a memory connected to the control processor.

46. The device ofclaim 34 wherein the display comprises an active matrix circuit bonded to a transmissive substrate.

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