US20020019106A1 - Methods of forming capacitors - Google Patents

Abstract

In one aspect, the invention encompasses a method of forming a capacitor. A mass is formed over an electrical node. An opening is formed within the mass. The opening has a lower portion proximate the node and an upper portion above the lower portion. The lower portion is wider than the upper portion. A first conductive layer is formed within the opening and along a periphery of the opening. After the first conductive layer is formed, a portion of the mass is removed from beside the upper portion of the opening while another portion of the mass is left beside the lower portion of the opening. A dielectric material is formed over the first conductive layer, and a second conductive layer is formed over the dielectric material. The second conductive layer is separated from the first conductive layer by the dielectric material. In another aspect, the invention encompasses a capacitor construction.

Description

TECHNICAL FIELD
• The invention pertains to capacitor constructions and methods of forming capacitors. In a particular aspect, the invention pertains to crown capacitor constructions.[0001]
BACKGROUND OF THE INVENTION
• A method of forming a prior art crown capacitor construction is described with reference to FIGS. 1 and 2. Referring to FIG. 1, a semiconductive[0002]material wafer fragment10 comprises asubstrate12 which supports anelectrical node14.Substrate12 can comprise, for example, lightly doped monocrystalline silicon.Electrical node14 can comprise, for example, a conductively-doped diffusion region provided within amonocrystalline silicon substrate12.
• To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.[0003]
• An[0004]insulative layer16 is formed oversubstrate12.Insulative layer16 can comprise, for example, silicon dioxide, silicon nitride, borophosphosilicate glass (BPSG), or phosphosilicate glass (PSG).Layer16 has anopening18 extending therethrough toelectrical node14. Aconductive plug20 is provided within opening18.Conductive plug20 can comprise, for example, a metal, or conductively doped polysilicon.
• A container-[0005]shaped storage node22 is provided overinsulative layer16, and overconductive plug18.Storage node22 is in electrical connection withelectrical node14 throughconductive plug18. Container-shaped storage node22 can also be referred to as a crown-shaped storage node.Storage node22 comprises upwardly extendingmembers21, and a horizontally extendingmember23.
• Referring to FIG. 2, a[0006]dielectric material24 is provided overstorage node22, and a secondcapacitor electrode layer26 is provided overdielectric material24.Dielectric material24 can comprise, for example, a combination of silicon dioxide and silicon nitride. Alternatively,dielectric material24 can comprise tantalum pentoxide.Second capacitor electrode26 can comprise, for example, a metal, conductively doped polysilicon, or a metal-comprising compound, such as, for example, titanium nitride.Storage node22,dielectric material24, andsecond capacitor electrode26, together define a crown capacitor.
• A problem with the processing described above with reference to FIGS. 1 and 2 is that the upwardly extending[0007]members21 ofstorage node22 can be easily broken during subsequent processing. It would therefore be desirable to develop alternative methods of forming crown capacitors.
SUMMARY OF THE INVENTION
• In one aspect, the invention encompasses a method of forming a capacitor. A mass is formed over an electrical node. An opening is formed within the mass. The opening has a lower portion proximate the node and an upper portion above the lower portion. The lower portion is wider than the upper portion. A first conductive layer is formed within the opening and along a periphery of the opening. After the first conductive layer is formed, a portion of the mass is removed from beside the upper portion of the opening while another portion of the mass is left beside the lower portion of the opening. A dielectric material is formed over the first conductive layer, and a second conductive layer is formed over the dielectric material. The second conductive layer is separated from the first conductive layer by the dielectric material.[0008]
• In another aspect, the invention encompasses a capacitor construction. Such construction includes an insulative mass over an electrical node, and an opening extending through the mass to the electrical node. The construction further includes a storage node layer within the opening. The storage node layer extends around a periphery of the opening and protrudes above the insulative mass. The storage node layer defines a container shape having a void extending therein. The void has a lower portion within the opening and an upper portion above the opening. The upper portion of the void is narrower than the lower portion. Additionally, the construction includes a dielectric material within the void and partially filling the void, and a second capacitor electrode within the void and separated from the first conductive layer by the dielectric material.[0009]
BRIEF DESCRIPTION OF THE DRAWINGS
• Preferred embodiments of the invention are described below with reference to the following accompanying drawings.[0010]
• FIG. 1 is a diagrammatic, cross-sectional view of a semiconductive material wafer fragment shown at a preliminary step of a prior art capacitor-forming process.[0011]
• FIG. 2 is a view of the FIG. 1 wafer fragment shown at a prior art processing step subsequent to that of FIG. 1.[0012]
• FIG. 3 is a diagrammatic, cross-sectional view of a semiconductive material wafer fragment shown at a preliminary step of a capacitor-forming method encompassed by the present invention.[0013]
• FIG. 4 is a view of the FIG. 3 wafer fragment shown at a processing step subsequent to that of FIG. 3.[0014]
• FIG. 5 is a view of the FIG. 3 wafer fragment shown at a processing step subsequent to that of FIG. 4.[0015]
• FIG. 6 is a view of the FIG. 3 wafer fragment shown at a processing step subsequent to that of FIG. 5.[0016]
• FIG. 7 is a view of the FIG. 3 wafer fragment shown at a processing step subsequent to that of FIG. 6.[0017]
• FIG. 8 is a view of the FIG. 3 wafer fragment shown at a processing step subsequent to that of FIG. 7.[0018]
• FIG. 9 is a top view of the FIG. 8 wafer fragment.[0019]
• FIG. 10 is a view of the FIG. 3 wafer fragment shown at a processing step subsequent to that of FIG. 8.[0020]
• FIG. 11 is a view of the FIG. 3 wafer fragment shown at a second embodiment processing step subsequent to that of FIG. 5.[0021]
• FIG. 12 is a view of the FIG. 3 wafer fragment shown at a processing step in accordance with the second embodiment and subsequent to that of FIG. 11.[0022]
• FIG. 13 is a top view of the FIG. 12 wafer fragment.[0023]
• FIG. 14 is a view of the FIG. 3 wafer fragment shown at a processing step in accordance with the second embodiment and subsequent to that of FIG. 12.[0024]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).[0025]
• A first embodiment method of forming a capacitor construction in accordance with the present invention is described with reference to FIGS.[0026]3-10. Referring to FIG. 3, a semiconductivematerial wafer fragment50 is shown at a preliminary process step. Waferfragment50 comprises asubstrate52 supporting anelectrical node54.Substrate52 andnode54 can comprise, for example, the constructions described above forsubstrate12 andnode14, respectively, of the prior art construction of FIG. 1.Substrate52 andnode54 can also, of course, comprise alternate constructions.
• An[0027]insulative material56 is formed oversubstrate52.Insulative material56 can comprise, for example, materials similar to those described above with reference toinsulative layer16 of the prior art construction of FIG. 1. Anopening58 extends throughinsulative material56, and aconductive material60 is formed within the opening.Conductive material60 can comprise, for example, constructions similar to those discussed above with reference toconductive plug20 of the prior art construction of FIG. 1.Plug60 can also comprise alternate constructions. It is noted that although the term “electrical node” was utilized above in describingnode54, plug60 can also be referred to as an “electrical node”.
• A[0028]mass62 is formed overinsulative layer56 andelectrical node60. In the shown embodiment,mass62 comprises the threedistinct layers64,66 and68.Layers64,66 and68 preferably comprise materials selectively etchable relative to one another. For instance, in oneembodiment layer64 consists essentially of PSG,layer66 consists essentially of silicon nitride, andlayer68 consists essentially of BPSG. In another embodiment,layer64 consists essentially of doped silicon dioxide,layer66 consists essentially of silicon nitride, andlayer68 consists essentially of undoped silicon dioxide.Layers64 and66 are preferably electrically insulative.Layers64,66 and68 can be formed to thicknesses of, for example, about 100 nanometers, 10 nanometers and 400 nanometers, respectively.
• Referring to FIG. 4, an[0029]opening70 is etched throughlayers64,66 and68 to exposenode60. Such opening can be formed by, for example, photolithographic processing to form a patterned photoresist mask (not shown) overlayer68, and subsequently utilizing an etchant comprising a halogenated-hydro-carbon and inert gases to etch throughlayers64,66, and68 in the location of opening70.
• Referring to FIG. 5, the material of[0030]layer64 is etched faster than the materials oflayers66 and68. Such faster etching can be accomplished for an etch selective for the material oflayer64 relative to the materials oflayers66 and68. In embodiments wherein the material oflayer64 comprises PSG, and the materials oflayer66 and68 comprise silicon nitride and BPSG, respectively, the selective etching can be accomplished utilizing hydrofluoric acid. Also, in embodiments in whichlayer64 comprises doped silicon dioxide, and layers66 and68 comprise silicon nitride and undoped silicon dioxide, respectively, the selective etching can be accomplished utilizing hydrofluoric acid. It is noted that a hydrofluoric acid etch would typically be done prior to formation of a storage node in contact with electrical node60 (the storage node is described below with reference to FIGS.6-10), to clean exposed portions offragment50 prior to formation of the storage node. Accordingly, the etching with hydrofluoric acid does not add an additional process step beyond the steps generally utilized for capacitor fabrication.
• After the etching of[0031]layer64, opening70 comprises two distinct portions, labeled asportions72 and74 in FIG. 5.Portion72 is a lower portion, andportion74 is an upper portion.Portions72 and74 join at a lower edge oflayer66.Lower portion72 has a width “Y” andupper portion74 has a width “Z”, with “Z” being less than “Y”.
• Referring to FIG. 6, a first[0032]conductive layer80 is formed overmass62 and withinopening70. Firstconductive layer80 can comprise, for example, conductively doped polysilicon and/or a metal. Firstconductive layer80 preferably comprises conductively doped roughened polysilicon, such as, for example, conductively doped hemispherical grain polysilicon. Firstconductive layer80 only partially fills opening70 and defines a void86 therein.
• A masking[0033]material82 is formed overconductive layer80. Maskingmaterial82 is preferably applied whilewafer50 is spinning, and applied at a viscosity such thatmaterial82 flows intoopening70. Further,material82 is preferably applied to a thickness such thatopening70 is predominately filled, but only a very thin amount ofmaterial82 is overmass62.Material82 can comprise, for example, photoresist.
• Referring to FIG. 7,[0034]wafer fragment50 is subjected to etching conditions which remove the thin layer of maskingmaterial82 from overmass62, and subsequently remove firstconductive layer80 from overmass62. During such etching, the portion of maskingmaterial82 withinopening70 protects firstconductive layer80 withinopening70. Accordingly, the etching forms firstconductive layer80 into a container-shape retained withinopening70. The container-shape can also be referred to as a crown-shape.
• The methodologies of FIGS. 6 and 7 are but one exemplary method of removing[0035]conductive material80 from overmass62 while leaving some ofconductive material80 withinopening70, and other methods will be recognized by persons of ordinary skill in the art. For instance, alternative methods of removingconductive material80 from overmass62 include chemical-mechanical polishing and resist etch-back.
• Referring to FIG. 8,[0036]wafer fragment50 is subjected to conditions which remove maskingmaterial82 from withinopening70. In exemplary embodiments where amask material82 comprises photoresist, such conditions can comprise exposure to oxygen and heat sufficient toash photoresist82. Also,wafer fragment50 is subjected to conditions which removelayer68 from overlayer66. In preferred embodiments whereinlayer68 is selectively etchable relative to layer66,layer66 constitutes an etch-stop. In an exemplary embodiment whereinlayer68 comprises undoped silicon oxide andlayer66 comprises silicon nitride, the selective etching oflayer68 relative to layer66 can be accomplished utilizing hydrofluoric acid. The removal oflayer68 reduces a height ofmass62. The removal oflayer68 increases the surface of the conductive material.
• FIG. 9 shows a top view of the[0037]fragment50 of FIG. 8, and shows thatconductive material80 is preferably in a container-shape comprising acircular opening86 extending therein.
• Referring to FIG. 10,[0038]dielectric material90, and a secondconductive layer92 are formed over firstconductive layer80 and withinvoid86.Dielectric material90 and secondconductive material92 can comprise, for example, materials similar to those discussed above regardingdielectric material24 andconductive material26, respectively, of the prior art (FIG. 2). Firstconductive material80,dielectric layer90, and secondconductive layer92 together define a capacitor, with firstconductive material80 corresponding to a storage node of the capacitor and secondconductive material92 corresponding to a second capacitor electrode.Second capacitor electrode92 is separated fromstorage node80 bydielectric layer90.
• In the shown embodiment, a portion of[0039]storage node80 is withinmass62, and a portion extends abovemass62. Accordingly,storage node80 corresponds to a partially buried storage node.Storage node80, like priorart storage node22, comprises upwardly projecting portions (labeled as100 for storage node80), and a horizontal portion (labeled as102 for storage node80). However, the partially buried nature ofcapacitor80 provides structural support for vertically extendingportions100 beyond that provided for vertically extending portions21 (FIG. 2) of a prior art capacitor construction achieving a same capacitance as the capacitor construction of FIG. 10. Such structural support can increase a mechanical stability of vertically projectingportions100 relative to vertically projectingportions21. Also, the partially-buried nature of a storage node of the present invention reduces a non-planarity across an upper surface ofwafer fragment50 in the processing steps of FIGS.8-10 relative to the non-planarity associated with an upper surface ofwafer fragment50 in prior art processing steps associated with FIGS. 1 and 2. Such reduction in non-planarity can alleviate problems associated with photolithographic processing. Specifically, photolithographic processing becomes increasingly more complicated with increasing non-planarity across an upper surface that is to be patterned.
• A second embodiment of the present invention is described with reference to FIGS.[0040]11-14. In referring to FIGS.11-14, similar numbering will be used as was utilized above in describing the first embodiments of FIGS.3-10, with the suffix “a” indicating structures associated with FIGS.11-14.
• Referring to FIG. 11, a semiconductive material wafer fragment[0041]50ais illustrated at a processing step subsequent to the step illustrated in FIG. 5.Wafer fragment50acomprises a firstconductive material80aformed over a mass62aand within an opening70a.Conductive material80aonly partially fills opening70a, and accordingly defines a void86atherein.Mass62acompriseslayers64a,66aand68a.
• A masking[0042]material82ais formed withinvoid86aand overmass62a, and patterned to cover only a portion ofconductive material80aovermass62a. Maskingmaterial82acan comprise, for example, photoresist, and can be patterned by, for example, photolithographic processing.
• Referring to FIG. 12, wafer fragment[0043]50ais subjected to etching conditions which remove exposed portions ofconductive material80afrom overmass62a. Subsequently, maskingmaterial82a(FIG. 11) is removed from withinvoid86a. In the shown embodiment, a portion ofconductive material80aremains over mass62a. Such portion defines aflange150. A top view of the construction of FIG. 12 is shown in FIG. 13. As can be seen in such top view,flange150 extends around an upper periphery of a storage node defined bylayer80a.
• Referring to FIG. 14,[0044]layer68a(FIG. 12) is removed. Subsequently, a dielectric material90aand a secondconductive layer92aare formed overstorage node80aand withinvoid86ato form a capacitor construction analogous to the construction described above with reference to FIG. 10.
• In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.[0045]

Claims (29)

1. A method of forming a capacitor, comprising:

forming a mass over an electrical node;

forming an opening within the mass, the opening having a lower portion proximate the node and an upper portion above the lower portion, the lower portion being wider than the upper portion;

forming a first conductive layer within the opening and along a periphery of the opening;

after forming the first conductive layer, removing a portion of the mass from beside the upper portion of the opening while leaving an other portion of the mass beside the lower portion of the opening;

forming a dielectric material over the first conductive layer; and

forming a second conductive layer over the dielectric material, the second conductive layer being separated from the first conductive layer by the dielectric material.

2. The method ofclaim 1 wherein the first conductive material comprises roughened polysilicon.

3. The method ofclaim 1 wherein the mass comprises at least one electrically insulative material.

4. The method ofclaim 1 wherein the mass comprises at least two materials, a first of the at least two materials being beneath a second of the at least two materials, the removing a portion of the mass comprising removing the second of the materials while leaving the first of the materials.

5. The method ofclaim 1 wherein the mass comprises at least two electrically insulative materials, a first of the at least two electrically insulative materials being beneath a second of the at least two electrically insulative materials, the removing a portion of the mass comprising removing the second of the electrically insulative materials while leaving the first of the electrically insulative materials.

6. The method ofclaim 1 wherein the forming the first conductive material comprises:

depositing polysilicon within the opening and over the mass; and

removing at least some of the polysilicon from over the mass.

7. The method ofclaim 1 wherein the forming the first conductive material comprises:

depositing polysilicon within the opening and over the mass;

forming photoresist within the opening to protect the polysilicon within the opening;

exposing at least some of the polysilicon which is not within the opening to etching conditions to remove said at least some of the polysilicon; and

ashing the photoresist to remove the photoresist from within the opening.

8. A method of forming a capacitor, comprising:

forming a first layer over an electrical node;

forming a second layer over the first layer;

forming an opening through the first and second layers;

after forming the opening, exposing the first and second layers to etching conditions which etch the first layer faster than the second layer, the exposing widening a lower portion of the opening relative to an upper portion of the opening;

forming a first conductive layer within the opening;

after forming the first conductive layer, removing the second layer while leaving the first layer;

forming a dielectric material over the first conductive layer; and

forming a second conductive layer over the dielectric material, the second conductive layer being separated from the first conductive layer by the dielectric material.

9. The method ofclaim 8 wherein the second layer consists essentially of an insulative material.

10. The method ofclaim 8 wherein the first layer consists essentially of a first material, and wherein the second layer consists essentially of a second material, the first material being selectively etchable relative to the second material.

11. The method ofclaim 10 wherein the first material is doped silicon dioxide and the second material is undoped silicon dioxide, and wherein the selectively etching comprises etching with HF.

12. The method ofclaim 10 wherein the first material is PSG and the second material is BPSG, and wherein the selectively etching comprises etching with HF.

13. The method ofclaim 8 wherein the first conductive layer comprises roughened polysilicon.

14. The method ofclaim 8 wherein the forming the first conductive layer comprises:

depositing polysilicon within the opening and over the second layer; and

removing at least some of the polysilicon from over the second layer.

15. The method ofclaim 8 wherein the forming the first conductive layer comprises:

depositing polysilicon within the opening and over the second layer;

forming photoresist within the opening to protect the polysilicon within the opening;

exposing at least some of the polysilicon which is not within the opening to etching conditions to remove said at least some of the polysilicon; and

ashing the photoresist to remove the photoresist from within the opening.

16. A method of forming a capacitor, comprising:

forming a first insulative layer over an electrical node;

forming a second insulative layer over the first insulative layer;

forming a third insulative layer over the second insulative layer;

forming an opening through the first, second and third insulative layers;

after forming the opening, exposing the first, second and third layers to etching conditions which etch the first insulative layer faster than the second and third layers, the exposing widening a lower portion of the opening relative to an upper portion of the opening;

forming a first conductive layer within the opening;

after forming the first conductive layer, removing the third insulative layer while leaving the first and second insulative layers;

forming a dielectric material over the first conductive layer; and

forming a second conductive layer over the dielectric material, the second conductive layer being separated from the first conductive layer by the dielectric material.

17. The method ofclaim 16 wherein the first insulative layer consists essentially of a first material, the second insulative layer consists essentially of a second material, and the third insulative layer consists essentially of a third material, the first material being selectively etchable relative to the second material and third materials, the third material being selectively etchable relative to the second material.

18. The method ofclaim 17 wherein the first material is doped silicon dioxide, the second material is silicon nitride, and the third material is undoped silicon dioxide, wherein the selectively etching the first material relative to the second and third materials comprises etching with HF.

19. The method ofclaim 17 wherein the first material is PSG, the second material is silicon nitride, and the third material is BPSG, wherein the selectively etching the first material relative to the second and third materials comprises etching with HF.

20. The method ofclaim 17 wherein the first conductive layer comprises roughened polysilicon.

21. The method ofclaim 17 wherein the forming the first conductive layer comprises:

depositing polysilicon within the opening and over the third insulative layer; and

removing at least some of the polysilicon from over the third insulative layer.

22. The method ofclaim 17 wherein the forming the first conductive layer comprises:

depositing polysilicon within the opening and over the third insulative layer;

forming photoresist within the opening to protect the polysilicon within the opening;

exposing at least some of the polysilicon which is not within the opening to etching conditions to remove said at least some of the polysilicon; and

ashing the photoresist to remove the photoresist from within the opening.

23. A capacitor construction, comprising:

an insulative mass over an electrical node;

an opening extending through the mass to the electrical node;

a first capacitor electrode within the opening, the first capacitor electrode extending around a periphery of the opening and protruding above the insulative mass, the first capacitor electrode defining a container shape having a void extending therein, the void having a lower portion within the opening and an upper portion above the opening, the upper portion of the void being narrower than the lower portion;

a dielectric material within the void and partially filling the void; and

a second capacitor electrode within the void and separated from the first capacitor electrode by the dielectric material.

24. The capacitor construction ofclaim 23 wherein the first capacitor electrode defines a storage node comprising an uppermost edge and a flange extending around a periphery of the uppermost edge.

25. The capacitor construction ofclaim 23 wherein the first capacitor electrode defines a storage node comprising an uppermost edge and a flange extending around a periphery of the uppermost edge, the flange projecting away from the void.

26. The capacitor construction ofclaim 23 wherein the first capacitor electrode comprises roughened polysilicon.

27. The capacitor construction ofclaim 23 wherein the insulative mass consists essentially of doped silicon dioxide.

28. The capacitor construction ofclaim 23 wherein the insulative mass consists essentially of PSG.

29. The capacitor construction ofclaim 23 wherein the electrical node comprises a polysilicon plug, and wherein the polysilicon plug is within an insulative mass.

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