US20020005562A1 - Semiconductor power integrated circuit and method for fabricating the same - Google Patents

Abstract

A method for fabricating a semiconductor power integrated circuit includes the steps of forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a source and a drift region for forming a drain region, forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure, forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device, forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer, and performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a diode insulating layer pattern and a gate oxide layer pattern, to thereby reduce processing steps and obtain a low on-resistance.

Description

FIELD OF THE INVENTION
• The present invention relates to a semiconductor power integrated circuit; and, more particularly, to a semiconductor power integrated circuit and a method for fabricating the same having a trench isolation, in which a field oxide layer, a gate oxide layer and a diode insulating layer are simultaneously formed together with a trench filling, thereby reducing processing steps and obtaining a low on-resistance.[0001]
DESCRIPTION OF THE PRIOR ART
• Semiconductor power integrated circuits (ICs) for use in a high voltage of 100V to 500V have been used as driver ICs in such as step motors, FED (field emission display) and PDP (plasma display panel). In fabricating the semiconductor power IC having a high breakdown voltage of 30V to 100V, an isolation technology is very important since it directly relates to a packing density and a leakage current.[0002]
• Referring to FIG. 1, a conventional trench filling technology used for isolation in the semiconductor power device will be described below.[0003]
• A buried[0004]oxide layer11 and a P-epi (epitaxial)layer12 are sequentially formed on an N-type silicon substrate10. A deep P-well region13 and deep N-well regions14A and14B are formed on the P-epi layer12. Then, an ion implantation is performed to form a P-well region18, an N-drift region19, N-well regions20A and20B and P-drift regions21A and21B. Thereafter, the deep P-well region13 and the deep N-well regions14A and14B are selectively etched to form atrench15 to thereby expose the buriedoxide layer11.
• A TEOS (tetra-ethyl-ortho-silicate) -[0005]oxide layer16 is formed on a whole surface of the semiconductor structure after forming thetrench15 and thepolysilicon layer17 is then formed on the TEOS-oxide layer16 to thereby fill thetrench15. Then, an etch back or a chemical mechanical polishing (CMP) is performed to planarize a surface of an entire structure after filling thetrench15. Thereafter, a local oxidation of silicon (LOCOS) process is performed at a temperature of about 1000° C. for a long time to form afield oxide layer23, atrench isolation layer22, agate oxide layer24 and adiode insulating layer25.
• [0006]Gate electrodes26 and27 are formed on thefield oxide layer23 and thegate oxide layer24. A n⁺ source regions28A to28C, p⁺ source regions29A to29C, n⁺ drain region30, and p⁺ drain regions31A and31B are formed on the P-well region18, the N-drift region19, the N-well regions20A and20B and the P-drift regions21A and21B by an ion implantation of impurities.
• In semiconductor power IC fabricated by the above-mentioned method, a breakdown voltage and an on-resistance are controlled by the deep N-[0007]well regions14A and14B and the P-drift regions21A and21B, wherein the deep N-well regions14A and14B are formed on the P-epi layer12 having a high resistivity. That is, a breakdown voltage of a vertical direction is determined by a thickness and impurity concentration of the P-epi layer12 and a depth and impurity concentration of the P-drift regions21A and21B. A breakdown voltage of a horizontal direction is determined by a distance between the p⁺ drain regions31A and31B and the p⁺ source regions29B and29C. Additionally, in case where the impurity concentration of the P-drift regions21A and21B are low, the voltage breakdown occurs at a drain edge, and in case where the impurity concentration of the P-drift regions21A and21B is high, the voltage breakdown occurs at a gate edge.
• However, it is difficult to prevent the deep N-[0008]well regions14A and14B and the N-well regions20A and20B from the impurity redistribution since a thermal treatment process is performed at a high temperature for a long time to form thefield oxide layer23, thetrench isolation layer22, thegate oxide layer24 and thediode insulating layer25. Therefore, there may occur a problem that the device characteristic is greatly degraded.
SUMMARY OF THE INVENTION
• It is, therefore, an object of the present invention to provide a semiconductor power integrated circuit and a method for fabricating the same, in which processing steps are reduced and a low on-resistance can be obtained.[0009]
• In accordance with an embodiment of the present invention, there is provided a method for fabricating a semiconductor power integrated circuit, comprising the steps of: a) forming a semiconductor structure having at least one active region, wherein an active region includes a well region for forming a channel and a source, and a drift region for forming a drain region; b) forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure; c) forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor device; d) forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer; and e) performing a selective etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern and a gate oxide layer pattern.[0010]
• In accordance with another embodiment of the present invention, there is provided a semiconductor power integrated circuit, comprising; a) a semiconductor structure having a trench with a predetermined depth from a surface of the semiconductor structure, wherein the semiconductor structure includes an active region having a well region for forming a channel and a source, and a drift region for forming a drain region; b) a trench isolation layer pattern including a first oxide layer and a second oxide layer, wherein the first oxide layer fills inside the trench and has a predetermined thickness from the surface of the semiconductor structure, and wherein the second oxide layer is formed on the first oxide layer and has a predetermined thickness smaller than the second oxide layer; c) a field oxide layer pattern including a third oxide layer and a fourth oxide layer, wherein the third oxide layer is simultaneously formed with the same layer as the first oxide layer of the field oxide layer pattern and has a predetermined thickness from a surface of the semiconductor structure, and wherein the fourth oxide layer is simultaneously formed with the same layer as the second oxide layer of the field oxide layer of the field oxide layer pattern and has a thickness smaller than the third oxide layer; and d) a gate oxide layer pattern including a fifth oxide layer and a sixth oxide layer, wherein the fifth oxide layer is simultaneously formed with the same layer as the first oxide layer of the field oxide layer pattern and has a predetermined thickness from a surface of the semiconductor structure, and wherein the sixth oxide layer is simultaneously formed with the same layer as the second oxide layer of the field oxide layer of the field oxide layer pattern and has a thickness smaller than the third oxide layer.[0011]
BRIEF DESCRIPTION OF THE DRAWINGS
• Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which:[0012]
• FIG. 1 is a cross-sectional diagram illustrating a semiconductor power IC in accordance with the prior art;[0013]
• FIGS. 2A to[0014]2I are cross-sectional diagrams illustrating a semiconductor power IC in accordance with the present invention; and
• FIG. 3 is a graph illustrating a current/voltage characteristic of a semiconductor power IC.[0015]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
• Referring to FIGS. 2A to[0016]2G, a semiconductor power integrated circuit in accordance with the present invention will be described in detail.
• Referring to FIG. 2A, a buried[0017]oxide layer41 and a P-epi layer42 are sequentially formed on an N-type silicon substrate40.
• Referring to FIG. 2B, a deep P-[0018]well region43 and deep N-well regions44A and44B are formed on the P-epi layer42. Thereafter, a drive-in of the deep P-well region43 and the deep N-well regions44A and44B is conducted at a high temperature to form a P-well region45 with a predetermined depth from a surface of the deep P-well region43, and N-well regions47A and47B with a predetermined depth from a surface of the deep N-well regions44A and44B. Sequentially, selectively performing an ion implantation, an N-drift region46 and P-drift regions48A and48B are formed at regions neighboring to the P-well region45 and the N-well regions47A and47B. Here, a region including the P-well region45 and the N-drift region46, and a region including the N-well regions47A and47B and the P-drift regions48A and48B, respectively, are called an active region. Here, channels and source regions are formed in the P-well region and the N-well region47A and47B , and drain regions are formed in the N-drift region46 and the P-drift regions48A and48B. Thereafter, atrench49 for isolation of the active regions is formed by selectively etching the active regions and the deep N-well and deep P-well regions, wherein thetrench49 has a predetermined depth from a surface of a entire structure. At this time, the etching process is performed using a mixed gas of HBr and SiF₄, wherein the mixed gas contains45 percent He and O₂. Then, athermal oxide layer50 is formed on an entire structure after forming thetrench49 to a thickness of approximately 500 Å.
• Referring to FIG. 2C, a first TEOS-[0019]oxide layer51 is formed on thethermal oxide layer50 and above the entire structure. The first TEOS-oxide layer51 fills thetrench49 and has a thickness of 8000 Å to 15000 Å from a surface of the entire structure. Then, a thermal treatment process is performed to the first TEOS-oxide layer51 at a temperature of approximately 850° C. for 30-minutes. Sequentially, an SOG (Spin On Glass)layer52 is formed on the first TEOS-oxide layer51, wherein an etching selectivity of theSOG layer52 is similar to that of the first TEOS-oxide layer51. Thereafter, the first TEOS-oxide layer51 is planarized performing an etch back to the.SOG layer52 and a part of the first TEOS-oxide layer51.
• Referring to FIG. 2D, a second TEOS-[0020]oxide layer52 is formed on the first TEOS-oxide layer51 to a thickness of 2000 Å to 5000 Å.
• Referring to FIG. 2E, a photoresist (not shown in FIG. 2E) is formed on the second TEOS-oxide layer ([0021]52, in FIG. 2D). Then, a taper etching process is performed to the first TEOS-oxide layer (52, FIG. 2D) and the second TEOS-oxide layer (51, FIG. 2D) through a BOE (buffered oxide etchant) to thereby simultaneously form a fieldoxide layer pattern51A and52A, a trenchisolation layer pattern51B and52B, a gateoxide layer pattern51C and52C and adiode insulating layer51D and52D. At this time, an etching rate of the first TEOS-oxide layer (51, FIG. 2D) is different from that of the second TEOS-oxide layer (52, FIG. 2D) because the thermal treatment process is performed only to the first TEOS-oxide layer and not to the second TEOS-oxide layer. Due to the different etching rate between the first TEOS-oxide layer and the second TEOS-oxide layer, the fieldoxide layer pattern51A and52A, the trenchisolation layer pattern51B and52B, the gateoxide layer pattern51C and52C and the diodeinsulating layer pattern51D and52D have tapered side-walls.
• Referring to FIG. 2F,[0022]gate electrodes53A and53B are formed on the fieldoxide layer pattern52A and the gateoxide layer pattern52C. Then, p⁺ source regions54A and n⁺ source region55A, and n⁺ drain region56 are formed on the P-well region45 and the N-drift region46, respectively. Further, n⁺ source regions55B and55C and p⁺ source regions54B and54C, p⁺ drain regions57A and57B are formed on the P-well regions47A and47B and the P-drift regions48A and48B, respectively.
• Referring to FIG. 2G, an insulating layer[0023]63 is formed.
• Referring again to FIG. 2G, a structure of the semiconductor power IC will be described below.[0024]
• The semiconductor power IC in accordance with the present invention includes a semiconductor structure having a[0025]trench49 with a predetermined depth from a surface of the semiconductor structure, a fieldoxide layer pattern51A and52A, a trenchisolation layer pattern51B and52B, a gateoxide layer pattern51C and52C and an gate insulatinglayer pattern51D and52D.
• The semiconductor structure includes a N-[0026]type semiconductor substrate40, a buriedoxide layer41 formed on the N-type semiconductor substrate40, an P-epi layer42 formed on the buriedoxide layer41, a deep P-well region43 and deep N-well regions44A and44B formed on the P-epi layer42. Further, the semiconductor structure includes active regions, which include a P-well region45 and a N-drift region46, N-well regions47A and47B and P-drift regions48A and48B formed on the deep P-well regions43 and the deep N-well regions44A and44B, and athermal oxide layer50 formed on the semiconductor structure having thetrench49. p⁺ source regions54A to54C and n⁺ source regions55A to55C is formed on the P-well region45 and the N-well regions47A and47B. n⁺ drainregion56 and p⁺ drain regions57A and57B are formed on the N-drift region46 and the P-drift regions48A and48B.
• The field oxide layer pattern includes a first TEOS-[0027]oxide layer51A and a second TEOS-oxide layer52A, the trench isolation layer pattern includes a first TEOS-oxide layer51B and52B, wherein the first TEOS-oxide layer51B fills thetrench49, the gate oxide layer includes a first TEOS-oxide layer51C and52C, and the diode insulating layer includes a first TEOS-oxide layer51D and52D. At this time, the first TEOS-oxide layer51A to51D is formed to a thickness of 8000 Å to 15000 Å from a surface of the semiconductor structure, and the second TEOS-oxide layers52A to52D are formed on the first TEOS-oxide layer51A to51D to a thickness of 2000 Å to 5000 Å. Further, the field oxide layer pattern, the trench isolation layer pattern, a gate oxide layer pattern and a diode insulating layer pattern are simultaneously formed.
• FIG. 3 is a graph of a drain current (I[0028]_D) versus a drain voltage (V_D) for various values of gate-source voltage (V_GS). Here, a solid line and a dotted line represent a current/drain characteristic according to the prior art and the present invention, respectively. Compared with the prior art, an on-resistance of the semiconductor power device according to the present invention is relatively reduced, wherein the on-resistance is a value produced by dividing the drain voltage by the drain current.
• Consequently, by forming the field oxide layer, the diode insulating layer, and the gate oxide layer together with the trench filling using the TEOS-oxide layer that is etched taperly, the fabricating steps can be reduced and simplified. Additionally, compared with the LOCOS method, the field oxide layer is formed with the TEOS-oxide layer at a relatively lower temperature, to thereby prevent an out-diffusion of impurities at the P-drift region and the P-epi layer. Accordingly, the impurity concentration and the junction depth can be easily controlled and the on-resistance of the semiconductor power IC can be effectively reduced. In addition, the effective drift length of the semiconductor power IC according to the present invention is shorter than that of the semiconductor power IC according to the prior art because the bird's beak is not generated during the formation of the TEOS tapered field oxide, while the bird's beak is essentially formed during the formation of the field oxide using the conventional LOCOS oxidation technique. Therefore, the on-resistance of the invented power devices is also decreased.[0029]
• While the present invention has been described with respect to certain preferred embodiments only, other modifications and variation may be made without departing from the spirit and scope of the present invention as set forth in the following claims.[0030]

Claims (25)

What is claimed is:

1. A method for fabricating a semiconductor power integrated circuit, comprising the steps of:

a) forming a semiconductor structure having at least one active region, wherein an active region includes a first well region for forming a channel and a source region and a drift region for forming a drain region;

b) forming a trench for isolation of the active regions, wherein the trench has a predetermined depth from a surface of the semiconductor structure;

c) forming a first TEOS-oxide layer inside the trench and above the semiconductor structure, wherein the first TEOS-oxide layer has a predetermined thickness from the surface of the semiconductor structure;

d) forming a second TEOS-oxide layer on the first TEOS-oxide layer, wherein a thickness of the second TEOS-oxide layer is smaller than that of the first TEOS-oxide layer; and

e) performing a selective tapered etching to the first and second TEOS-oxide layers, to thereby simultaneously form a field oxide layer pattern, a trench isolation layer pattern, a gate oxide layer pattern.

2. The method as recited inclaim 1, wherein the step c) includes the step of performing a thermal treatment process to the first TEOS-oxide layer.

3. The method as recited inclaim 2, wherein the field oxide layer pattern, the gate oxide layer pattern and a trench isolation layer pattern have tapered side walls by performing a wet etching through a buffered oxide etchant.

4. The method as recited inclaim 3, wherein the thermal treatment process is performed at a temperature of about 850° C. for 30 minutes.

5. The method as recited inclaim 4, wherein the step b) includes the step of forming a thermal oxide layer on an entire structure after forming the trench.

6. The method as recited inclaim 5, wherein first TEOS-oxide layer is formed to a thickness of 8000 Å to 15000 Å, and the second TEOS-oxide layer is formed to a thickness of 2000 Å to 5000 Å.

7. The method as recited inclaim 6, wherein a thickness of the thermal oxide layer is of about 500 Å.

8. The method as recited inclaim 6, wherein the step c) includes the steps of:

forming a Spin On Glass (SOG) layer on the first TEOS-oxide layer; and

planarizing the first TEOS-oxide layer by performing an etch back to the SOG layer and a part of the first TEOS-oxide layer.

9. The method as recited inclaim 4, wherein the etching process of the step b) is performed using a mixed gas of HBr and SiF₄, the mixed gas containing 45 percent He and O₂.

10. The method as recited inclaim 1, wherein the step a) includes the steps of:

forming a buried insulating layer on a semiconductor substrate of a first conductivity type; and

forming an epitaxial layer of a second type conductivity type on the buried insulating layer.

11. The method as recited inclaim 10, wherein the step e) includes the steps of:

forming a channel and a source region of the second conductivity type on the first well region of the first conductivity type and a drift region and a drain region of the second conductivity type by selectively implanting ions of impurity;

forming a source region of the first conductivity type on the first region of the first conductivity type by selectively implanting ions of impurity; and

forming a gate electrode on the gate oxide layer pattern.

12. The method as recited inclaim 11, wherein the step c) includes the step of performing a thermal treatment process to the first TEOS-oxide layer.

13. The method as recited inclaim 12, wherein the field oxide layer pattern, the trench isolation layer pattern, the gate oxide layer pattern, and the diode insulating layer pattern have tapered side walls by performing a wet etching through a buffered oxide etchant.

14. The method as recited inclaim 12, wherein the thermal treatment process is performed at a temperature of about 850° C. for 30 minutes.

15. The method as recited inclaim 14, wherein the step b) includes the step of forming a thermal oxide layer on an entire structure after forming the trench.

16. The method as recited inclaim 15, wherein the first TEOS-oxide layer is formed to a thickness of 8000 Å to 15000 Å, and the second TEOS-oxide layer is formed to a thickness of 2000 Å to 5000 Å.

17. The method as recited inclaim 16, wherein a thickness of the thermal oxide layer is of about 500 Å.

18. The method as recited inclaim 17, wherein the step c) includes the steps of:

forming a Spin On Glass (SOG) layer on the first TEOS-oxide layer; and

planarizing the first TEOS-oxide layer by performing an etch back to the SOG layer and a part of the first TEOS-oxide layer.

19. The method as recited inclaim 18, wherein the etching process of the step b) is performing using a mixed gas of HBr and SiF₄, the mixed gas containing 45 percent He and O₂.

20. A semiconductor power integrated circuit, comprising;

a) a semiconductor structure having a trench with a predetermined depth from a surface of the semiconductor structure, wherein the semiconductor structure includes an active region having a well region for forming a channel and a source, and a drift region for forming a drain region;

b) a trench isolation layer pattern including a first oxide layer and a second oxide layer, wherein the first oxide layer fills inside the trench and has a predetermined thickness from the surface of the semiconductor structure, and wherein the second oxide layer is formed on the first oxide layer and has a predetermined thickness smaller than the second oxide layer;

c) a field oxide layer pattern including a third oxide layer and a fourth oxide layer, wherein the third oxide layer is simultaneously formed with the same layer as the first oxide layer of the field oxide layer pattern and has a predetermined thickness from a surface of the semiconductor structure, and wherein the fourth oxide layer is simultaneously formed with the same layer as the second oxide layer of the field oxide layer of the field oxide layer pattern and has a thickness smaller than the third oxide layer; and

d) a gate oxide layer pattern including a fifth oxide layer and a sixth oxide layer, wherein the fifth oxide layer is simultaneously formed with the same layer as the first oxide layer of the field oxide layer pattern and has a predetermined thickness from a surface of the semiconductor structure, and wherein the sixth oxide layer is simultaneously formed with the same layer as the second oxide layer of the field oxide layer of the field oxide layer pattern and has a thickness smaller than the third oxide layer.

21. The semiconductor power integrated circuit as recited inclaim 19, wherein the first and second layers are TEOS-oxide layers.

22. The semiconductor power integrated circuit as recited inclaim 21, wherein the predetermined thickness of the first oxide layer is of 8000 Å to 15000 Å and the predetermined thickness of the second oxide layer is of 2000 Å to 5000 Å.

23. The semiconductor power integrated circuit as recited inclaim 22, wherein the semiconductor power device further comprises:

a semiconductor substrate of a first conductivity type;

a buried insulating layer formed on the semiconductor substrate of the first conductivity type; and

an epitaxial layer of a second conductivity type formed on the buried insulating layer.

24. The semiconductor power integrated circuit as recited inclaim 23, wherein the predetermined depth of the trench reaches to the epitaxial layer.

25. The semiconductor power integrated circuit as recited inclaim 24, wherein the semiconductor power integrated circuit further comprises:

a thermal oxide layer entirely formed on the semiconductor structure of the first conductivity type;

a source region of the second conductivity type formed on the first region of the first conductivity type;

a drain region of the second conductivity type formed on the second region of the second conductivity type; and

a source region of the first conductivity type on the first well region of the first conductivity type.

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