US20020005539A1 - Spin coating for maximum fill characteristic yielding a planarized thin film surface - Google Patents

Abstract

A method for spinning a material onto a semiconductor device structure so as to substantially fill recesses formed in a surface of the semiconductor device structure and to impart the material with a substantially planar surface and semiconductor device structures formed thereby. The thickness of the material covering the surface is less than the depth of the recesses. The surface may remain substantially uncovered by the material.

Description

CROSS-REFERENCE TO RELATED APPLICATION
• This application is a divisional of application Ser. No. 09/542,783, filed Apr. 4, 2000, pending.[0001]
BACKGROUND OF THE INVENTION
• 1. Field of the Invention[0002]
• The present invention relates to methods for filling containers, trenches, or other recesses of semiconductor device structures during fabrication thereof. Particularly, the present invention relates to the use of spin coating techniques to fill containers, trenches, and other recesses of semiconductor device structures. As a specific example, the present invention relates to a method for masking hemispherical grain (HSG) silicon-lined containers of a stacked capacitor structure to facilitate removal of HSG silicon from the surface of a semiconductor device structure including the stacked capacitor structure.[0003]
• 2. Background of Related Art[0004]
• Conventionally, spin-on processes have been used to apply substantially planar layers of material to the surfaces of semiconductor device structures being fabricated upon a wafer of semiconductor material (e.g., a silicon, gallium arsenide, or indium phosphide wafer) or other semiconductor substrate (e.g., a silicon on insulator (SOI), silicon on glass (SOG),silicon on ceramic (SOC), silicon on sapphire (SOS), or other similar substrate). Consequently, while the portions of a spun-on layer of material over substantially horizontal structures may be substantially planar, the layer of material may not substantially fill or conform to the numerous, minute recesses formed in the semiconductor device structure.[0005]
• For example, when it is desirable to mask a container, trench, or other recess of a semiconductor device structure without masking the surface of the semiconductor device structure to which the container, trench, or other recess opens, a mask material is typically applied to the surface of the semiconductor device structure, such as by use of known spin-on processes. As an example, FIG. 1 illustrates the fabrication of a stacked[0006]capacitor structure10 with conductively doped HSG silicon 16-linedcontainers14. As it is necessary to removeHSG silicon16 from asurface12 of an electrical insulator layer11 (e.g., borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or borosilicate glass (BSG)) of stackedcapacitor structure10 to prevent electrical shorting betweenadjacent containers14,mask material18′ is introduced intocontainers14 to facilitate removal ofHSG silicon16 fromsurface12.
• While conventional spin-on processes will force some of the mask material into[0007]containers14, trenches, or other recesses, these processes typically result in the formation of a relatively thick, but not necessarily planar layer ofmask material18′ oversurface12. Due to various factors, including the surface tension ofmask material18′ and the centrifugal forces applied tomask material18′ during the spin-on process,mask material18′ tends to migrate out of the small recesses (e.g., containers14) formed insurface12. Thus, the thickness ofmask material18′ within acontainer14, trench, or other recess may not be significantly greater than the thickness ofmask material18′ covering surface12, leavingcontainers14 partially unfilled. Once the layer of material has been dispensed onto the semiconductor device structure, it is solidified or cured, such as by known photographic or soft bake processes.
• In order to reduce the thickness of the layer of mask material covering the surface of the semiconductor device structure without substantially decreasing the thickness of the layer of mask material within the recesses, chemical-mechanical planarization (CMP) processes, such as chemical-mechanical polishing techniques, are typically employed. The use of CMP processes is, however, somewhat undesirable since such processes are known to create defects in the surface of the semiconductor device structure. CMP processes are also known to leave debris, or contaminants, which may be trapped in defects in the surface of the semiconductor device structure and which may subsequently cause electrical shorting of a fabricated semiconductor device. For example, if CMP processes are used to remove mask material and at least part of a conductively doped HSG silicon layer from an insulator at the surface of a stacked capacitor structure, conductive silicon particles may be trapped in defects in the surface of the insulator and subsequently cause electrical shorting between adjacent containers of the stacked capacitor. These potentially damaging contaminants may remain even when a chemical removal process, such as a wet or dry etch, follows the CMP process.[0008]
• Alternatively, a photoresist may be used as the mask material. Patterning of the photoresist requires several steps in which equipment must be precisely aligned with features, such as the containers of a stacked capacitor structure, fabricated on the semiconductor substrate. Additional handling of the semiconductor device structure is also required when a photoresist is used to mask containers, trenches, or other recesses formed in a semiconductor device structure, which is somewhat undesirable.[0009]
• Moreover, when conventional blanket deposition techniques are used to fill the recesses of a semiconductor device structure with a material (e.g., to fill the trenches of a shallow trench isolation structure with an electrical insulator material and to fill dual damascene trenches with a conductive material), the material typically forms a nonplanar layer over the semiconductor device structure. Such material layers typically include valleys located over recesses in the underlying semiconductor device structure and peaks located over other regions of the semiconductor device structure. Chemical-mechanical planarization is an example of a conventional technique for removing such materials from the surface of a semiconductor device structure while leaving these materials within the recesses of the semiconductor device structure. As chemical-mechanical planarization processes typically employ an abrasive pad to mechanically planarize structures, however, the peaks of the material layer may break off in larger than desired pieces and subsequently scratch the surface of the semiconductor device structure, forming defects therein.[0010]
• The art does not teach a semiconductor device structure that includes a nonchemical-mechanical planarized material layer that substantially fills a container, trench, or other recess formed in the semiconductor device structure and which does not substantially cover the remainder of a surface of the semiconductor device structure or which includes only a relatively thin layer of material over the remainder of the surface. The art also fails to teach a method for forming a material layer with these features. In addition, the art lacks teaching of a method for reducing the likelihood that peaks of a nonplanar layer of material will damage a surface of a semiconductor device structure during subsequent planarization of the layer of material.[0011]
SUMMARY OF THE INVENTION
• The present invention includes semiconductor device structures with substantially planar surfaces. The semiconductor device structures also include containers, trenches, or other recesses that are filled with a material. The material may also cover adjacent surfaces of the semiconductor device structures. If the material covers surfaces of the semiconductor device structures, the thickness of the material covering the surface is less than the depth of the containers, trenches, or other recesses that are substantially filled with material. Preferably, the thicknesses of material covering the surfaces of the semiconductor device structures are less than about half the depth of the containers, trenches, or other recesses. The surfaces of the material or materials that fill the recesses and that may cover the surfaces of the semiconductor device structures have not, however, been chemical-mechanical planarized to achieve the reduced depth of material outside of the recesses.[0012]
• In one embodiment of the present invention, the semiconductor device structure includes a stacked capacitor structure with a layer of electrically insulative material, or insulator layer, and at least one container recessed or formed in the insulator layer. The insulator layer includes a substantially planar surface, which is referred to herein as the exposed surface of the insulator layer. A layer of electrically conductive material covers the surface of the insulator layer and lines the at least one container. By way of example, the electrically conductive material may be conductively doped hemispherical grain (HSG) silicon. As the stacked capacitor structure would electrically short if the conductive material remained on the surface of the insulator layer between adjacent containers, for the stacked capacitor to function properly, the conductive material must be removed from the surface of the insulator layer prior to completing fabrication of the stacked capacitor but remain within the containers. Thus, this embodiment of the semiconductor device structure includes a substantially planar surface with a non-chemical-mechanical planarized quantity of mask material substantially filling the at least one container. While the mask material may cover regions of the layer of conductive material overlying the surface of the insulator layer, it is preferred that these regions are substantially uncovered by mask material. If mask material does overlie these regions of the layer of conductive material, the thickness of the mask material overlying these regions is less than the depth of the at least one container. Preferably, the thickness of the mask material over these regions of the layer of conductive material is less than about half the depth of the at least one container.[0013]
• The mask material may be applied to the semiconductor device structure by known processes and is spread across the surface of the stacked capacitor structure so as to substantially fill the at least one container while leaving a thinner, or no, material layer over regions of the layer of conductive material that overlie the surface of the insulator layer. For example, the mask material may be spread across the surface of the stacked capacitor structure by use of spin-on techniques, wherein the mask material is applied at a first speed, the rate of spinning is decreased to a second speed at which the mask material is permitted to at least partially set up, then the rate of spinning is gradually increased, or ramped up, to a third speed at which a desired, reduced thickness of mask material covering the surface may be obtained. The rate at which the stacked capacitor structure is spun may again be decreased to permit the mask material to further set. An edge bead of mask material may then be removed from the stacked capacitor structure and the stacked capacitor structure spun once again to remove solvents from the mask material.[0014]
• In another embodiment of the semiconductor device structure, a mask is disposed over a shallow trench isolation (STI) structure that includes a semiconductor substrate with a substantially planar surface and shallow trenches recessed, or formed, in the semiconductor substrate. The semiconductor device structure has a substantially planar surface, without requiring chemical-mechanical planarization of the surface of the mask. If material of the mask covers the surface of the semiconductor substrate, the thickness of mask material thereover is significantly less than the depths of the shallow trenches. Preferably, the thickness of mask material covering the surface of the semiconductor substrate is less than about half the depths of the trenches. More preferably, the surface of the semiconductor substrate remains substantially uncovered by the mask material. The present embodiment of the semiconductor substrate may also include conductively doped regions continuous with the surface and located between the trenches formed in the semiconductor substrate.[0015]
• The shallow trench isolation structure may be formed by known processes. The mask may be formed by applying a quantity of mask material to the shallow trench isolation structure and spreading the mask material over the surface so as to substantially fill each trench thereof. As an example of the manner in which mask material may be spread across the shallow trench isolation structure, the mask material may be spun across the semiconductor substrate at a first speed, the rate of spinning decreased to a second speed to permit the mask material to at least partially set up while remaining in the trenches, then the rate of spinning gradually increased, or ramped up, to a third speed at which a desired, reduced thickness of mask material covering the surface may be obtained. The rate at which the shallow trench isolation structure is spun may again be decreased to permit the mask material to further set. An edge bead of mask material may then be removed from the shallow trench isolation structure and the shallow trench isolation structure spun once again to remove solvents from the mask material. Conductively doped regions of the semiconductor substrate may be formed by exposing the substrate and mask material to a conductivity dopant. The regions of the semiconductor substrate that remain uncovered or that are covered with thinner layers of the mask material (e.g., the surface of the semiconductor substrate) are implanted with the conductivity dopant while regions of the semiconductor substrate that are covered with thicker layers of the mask material (e.g., regions of the semiconductor substrate beneath the trenches) remain substantially undoped.[0016]
• Another embodiment of a semiconductor device structure according to the present invention includes a surface with one or more recesses formed therein and a layer of a first material substantially filling each recess and at least partially covering the surface. The layer of first material has a nonplanar surface and may include a valley located substantially over each recess in the semiconductor device structure and one or more peaks located substantially over the surface of the semiconductor device structure. A second material disposed over the layer of first material at least partially fills each of the valleys formed in the layer of first material. The second material has a substantially planar surface that is not further planarized following formation thereof.[0017]
• By way of example, the semiconductor device structure may be a shallow trench isolation structure including a semiconductor substrate with a substantially planar surface and trenches recessed, or formed, in the semiconductor substrate. The trenches are filled with a first, electrically insulative material, which is preferably a low dielectric constant, or “low-k”, material, such as a high density plasma (HDP) silicon oxide, or HDP oxide. HDP oxide or another insulative material may be disposed into the trenches by way of known processes, such as chemical vapor deposition (CVD) processes. As the processes that are used to fill the shallow trenches with the first, insulative material are typically blanket deposition processes, the insulative material may also cover the surface of the semiconductor substrate. The surface of a layer of the first, insulative material blanket deposited over a semiconductor substrate with trenches formed therein is nonplanar.[0018]
• As another example of the deposition of a first material over a semiconductor device structure, each recess of the semiconductor device structure may be a dual damascene type trench substantially filled with a first, conductive material. The first, conductive material may be disposed into each dual damascene trench of the semiconductor device structure by known processes, such as physical vapor deposition (PVD) (e.g., sputtering) or chemical vapor deposition techniques. Since these processes typically form a layer of material that blankets substantially the entire semiconductor device structure, the first, conductive material may also cover the surface of the semiconductor device structure. When blanket deposited over a semiconductor device structure with trenches formed therein, such layers typically have nonplanar surfaces.[0019]
• The second material is preferably a stress buffer material that facilitates planarization of the layer of insulative material without causing substantial defects in either the insulative material or in the surface of the underlying semiconductor substrate. Exemplary materials that are useful as the stress buffer include resins and polymers that may be applied by way of spin-on techniques. The stress buffer has a substantially planar surface and preferably fills the valleys in the layer of insulative material without substantially covering the peaks thereof.[0020]
• After the stress buffer material is applied to the semiconductor device structure, it may be spread across the surface of the semiconductor device structure by a spin-on technique that includes spinning the semiconductor device structure at a first speed, decreasing the rate of spinning to a second speed at which the material of the stress buffer within the valleys is permitted to at least partially set, then gradually increasing, or ramping up, the rate of spinning to a third speed at which a desired thickness of stress buffer material covering the surface may be obtained. The rate at which the semiconductor device structure is spun may again be decreased to permit the stress buffer material to further set. An edge bead of stress buffer material may then be removed from the semiconductor device structure and the semiconductor device structure spun once again to remove solvents from the stress buffer material.[0021]
• If portions of the first material layer protrude through the second material, all or part of the first material layer may be removed with selectivity over the second material by known processes, such as by use of wet or dry etchants. The protruding portions of the first material layer may be partially removed until a surface of the first material is in substantially the same plane as a surface of the second material. The first and second materials may then be substantially concurrently removed from over the surface of the semiconductor device structure by known chemical-mechanical planarization or etching processes. Following the removal of the first and second materials, the surface of the first material remaining in each recess is preferably substantially flush with the surface of the semiconductor device structure. Alternatively, the first material can be selectively removed to expose the surface of the semiconductor device structure, then the second material removed therefrom.[0022]
• If the semiconductor device structure has a substantially planar surface after the second material is disposed thereon, the first and second materials may be substantially concurrently removed by known chemical-mechanical planarization or etching processes to provide a semiconductor device structure with the first material substantially filling the recesses thereof and having a substantially planar surface.[0023]
• Other features and advantages of the present invention will become apparent to those of skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims.[0024]
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 (Prior Art) is a cross-sectional representation of a stacked capacitor structure with a surface and containers lined with conductively doped hemispherical grain polysilicon and including a conventionally spun-on layer of mask material thereover;[0025]
• FIG. 2 is a cross-sectional representation of a stacked capacitor structure including a layer of mask material substantially filling the containers thereof and having a substantially planar surface;[0026]
• FIG. 3 is a cross-sectional representation of the stacked capacitor structure of FIG. 2, depicting the mask material and conductively doped hemispherical grain polysilicon removed from over the surface, the containers remaining substantially filled with mask material;[0027]
• FIG. 4 is a cross-sectional representation of the stacked capacitor structure of FIG. 3 with the mask material removed from the containers;[0028]
• FIG. 5 is a cross-sectional representation of a shallow trench isolation structure including a semiconductor substrate with a surface and trenches formed in the surface and a layer of mask material that substantially fills the trenches and has a substantially planar surface;[0029]
• FIG. 6 is a cross-sectional representation of the shallow trench isolation structure of FIG. 5 that schematically illustrates doping of portions of the semiconductor substrate that are continuous with the surface and laterally adjacent the trenches without doping of portions of the semiconductor substrate beneath the trenches;[0030]
• FIG. 7 is a cross-sectional representation of a shallow trench isolation structure including a nonplanar layer of electrically nonconductive material filling the trenches and overlying the surface thereof and a layer of stress buffer material with a substantially planar surface filling recesses in and overlying the layer of electrically nonconductive material;[0031]
• FIG. 8 is a cross-sectional representation of a variation of the shallow trench isolation structure of FIG. 7, which includes stress buffer material with a substantially planar surface partially filling recesses in the layer of electrically nonconductive material;[0032]
• FIG. 9 is a cross-sectional representation of the shallow trench isolation structure of FIG. 8, depicting the layer of electrically nonconductive material partially removed to form a substantially planar surface flush with the surfaces of the stress buffer material in the recesses of the layer;[0033]
• FIG. 10 is a cross-sectional representation of the shallow trench isolation structure of FIG. 9, illustrating stress buffer material disposed at least partially over the electrically nonconductive material remaining in the trenches;[0034]
• FIG. 11 is a cross-sectional representation of the shallow trench isolation structures of FIGS. 7 and 10, depicting the electrically nonconductive material within the trenches as having a substantially planar surface that is substantially flush with the surfaces of the semiconductor substrates of the shallow trench isolation structures;[0035]
• FIG. 12 is a cross-sectional representation of a semiconductor device structure including dual damascene trenches recessed in a surface thereof, a nonplanar layer of conductive material substantially filling the trenches and covering the surface of the semiconductor device structure, and a layer of stress buffer material with a substantially planar surface disposed over and filling recesses in the layer of conductive material;[0036]
• FIG. 13 is a cross-sectional representation of a variation of the semiconductor device structure of FIG. 12, which includes stress buffer material with a substantially planar surface only partially filling recesses formed in the layer of conductive material;[0037]
• FIG. 14 is a cross-sectional representation of the semiconductor device structure of FIG. 13, depicting the layer of conductive material partially removed to form a substantially planar surface flush with the surfaces of the stress buffer material in the recesses of the layer;[0038]
• FIG. 15 is a cross-sectional representation of the semiconductor device structure of FIG. 14, illustrating stress buffer material partially disposed at least partially over the conductive material remaining in the trenches; and[0039]
• FIG. 16 is a cross-sectional representation of the semiconductor structures of FIGS. 12 and 15, depicting the conductive material within the trenches as having a substantially planar surface that is substantially flush with the surfaces of the semiconductor device structures.[0040]
DETAILED DESCRIPTION OF THE INVENTION
• With reference to FIG. 2, a semiconductor device structure, in this case a[0041]stacked capacitor structure10, incorporating teachings of the present invention is illustrated.Stacked capacitor structure10 includes asurface12 withcontainers14 recessed, or formed, insurface12. As illustrated,surface12 andcontainers14 are lined with alayer16 of conductively doped hemispherical grain silicon.Stacked capacitor structure10 also includes amask layer18 of a polymer material (e.g., polyimide or photoresist) disposed overlayer16.Mask layer18 substantially fillscontainers14 and has a substantially planar exposedsurface19. The thickness T of portions ofmask layer18 overlyingsurface12 is less than the depth D ofcontainers14 and, preferably, is less than about half of depth D.
• [0042]Stacked capacitor structure10, including the conductively doped hemisphericalgrain silicon layer16 thereof, may be fabricated by known processes, such as those disclosed in U.S. Pat. No. 5,663,090, issued to Dennison et al. on Sep. 2, 1997, the disclosure of which is hereby incorporated in its entirety by this reference.Mask layer18 is formed on stackedcapacitor structure10 by dispensing a mask material onto stackedcapacitor structure10 while spinning the substrate bearing stackedcapacitor structure10 relative to an axis perpendicular to a plane of the substrate bearing stackedcapacitor structure10 at a first speed, which is preferably an optimum speed for forming a substantially homogeneous film from the mask material. When a substantially homogeneous film of mask material has been formed on stackedcapacitor structure10, the rate at whichstacked capacitor structure10 is spun is decreased to a second speed. The second speed and the duration at whichstacked capacitor structure10 is spun at the second speed permits the mask material to flow into and to begin to set withincontainers14 of stackedcapacitor structure10. The rate of spinning stackedcapacitor structure10 is then gradually increased, or ramped up, to a third speed, which is maintained until a film of maskmaterial covering surface12 reaches a desired, reduced thickness. The rate at whichstacked capacitor structure10 is spun may again be reduced to further permit the mask material to set. A bead of the mask material formed around the periphery of a substrate (e.g., a wafer) including stackedcapacitor structure10 may be removed by known processes to provide a substantially planar surface over stackedcapacitor structure10. The substrate including stackedcapacitor structure10 may also be spun again to begin removing solvents from the mask material.Mask layer18 is then subjected to a soft bake, as known in the art, to substantially remove solvents from the mask material.
• By way of example, when ARCH 895 photoresist is used as the mask material, the substrate bearing stacked[0043]capacitor structure10 is spun at a first speed of about 1,000 rpm until a substantially homogeneous layer is formed (e.g., about one second to about five seconds). The spinning rate is then decreased to about 100 rpm for a period of about five seconds to about ten seconds to allow the photoresist withincontainers14 to begin setting. The rate at whichstacked capacitor structure10 is spun is then gradually increased to a third speed of at least about 1,500 rpm until thephotoresist covering surface12 reaches a desired, reduced thickness or until the photoresist is substantially removed fromsurface12. The spin rate is then decreased again, this time to about 50 rpm, for a duration of about 19 to about 50 seconds to permit additional setting, or casting, of the photoresist. Such additional spinning creates a bead of photoresist near an edge of a substrate of whichstacked capacitor structure10 is a part. Known edge bead removal techniques are employed to remove this bead from the edge of the substrate and to provide a substantially planar surface. Any solvent remaining in the photoresist is then substantially removed therefrom by gradually increasing the rate at whichstacked capacitor structure10 is spun to about 5,000 rpm.Mask layer18 is then subjected to a known soft bake process, preferably at a temperature of about 100° C. to about 150° C. to substantially remove solvents from the photoresist.
• Referring now to FIG. 3, once a[0044]mask layer18 with a substantiallyplanar surface19 is formed, the portions ofmask layer18 and of hemisphericalgrain silicon layer16 that are located above a plane ofsurface12 are removed from stackedcapacitor structure10. In order to reduce or eliminate the creation of potentially contaminating debris and of surface defects that may be caused by mechanical planarization processes, layers18 and16 are removed by known chemical processes, such as dry etch processes or wet etch, or wet dip, processes. For example,mask layer18 may be selectively removed by use of a known resist strip, then layer16 removed fromsurface12 with a wet etchant that removes silicon with selectivity over the portions ofmask layer18 remaining incontainers14 and over anunderlying dielectric layer15. As another example, layers18 and16 may be substantially concurrently removed with an etchant or combination of etchants that will removemask layer18 and hemisphericalgrain silicon layer16 at substantially the same rates. Mask material remaining incontainers14 may then be removed by known processes, such as the use of known wet or dry strip materials (e.g., an ammonium hydroxide (NH₄OH) dry strip known in the art as a “piranha” strip when the mask material is ARCH 895 or a similar photoresist). This process provides astacked capacitor structure10 with conductively doped hemispherical grain silicon 16-linedcontainers14 recessed in a substantially defect-and contaminant-free surface12 ofstructure10 anddielectric layer15, as shown in FIG. 4.Stacked capacitor structure10 shown in FIG. 4 may then be processed as known in the art to fabricate a finished stacked capacitor.
• Turning now to FIGS. 5 and 6, another embodiment of a semiconductor device structure, in this instance a shallow[0045]trench isolation structure20, incorporating teachings of the present invention is illustrated. FIG. 5 depicts a shallowtrench isolation structure20 that includes asemiconductor substrate21 formed from silicon, gallium arsenide, indium phosphide, or another suitable semiconductor material, and which may be in the form of a wafer or another substrate, such as a silicon-on-glass, silicon-on-sapphire, silicon-on-ceramic, or other silicon-on-insulator type substrate.Semiconductor substrate21 includes asurface22 with one ormore trenches24 recessed, or formed, therein.Trenches24 may be formed insemiconductor substrate21 by known techniques, such as mask and etch processes. Shallowtrench isolation structure20 also includes amask layer28 with a substantiallyplanar surface29.Mask layer28 substantially fillstrenches24 and may also coversurface22 ofsemiconductor substrate21. As shown in FIG. 5, the thickness T′ of portions ofmask layer28 overlyingsurface22 is less than the depth D′ oftrenches24. Preferably, thickness T′ is less than about half of depth D′. Alternatively,surface22 may remain substantially uncovered bymask layer28.Mask layer28 may be formed from a photoresist or other polymer by processes the same as or similar to those described previously herein with reference to the fabrication ofmask layer18 illustrated in FIG. 2.
• FIG. 6 illustrates the implantation of a conductivity dopant C, such as a known p-type or n-type conductivity dopant (e.g., phosphorus (P), boron (B), arsenic (As), or antimony (Sb)), into shallow[0046]trench isolation structure20 throughmask layer28. Conductivity dopant C is prevented from passing through the thicker regions ofmask layer28 intoregions25 ofsemiconductor substrate21 located at the bottoms oftrenches24. Conductivity dopant C does, however, pass through thinner areas ofmask layer28 that are located onsurface22 or to exposed areas ofsurface22 so as to conductivelydope regions23 ofsemiconductor substrate21 continuous withsurface22, which regions lie laterallyadjacent trenches24. Onceregions23 have been conductively doped,mask layer28 may be removed fromtrenches24 and surface22 (if necessary) to facilitate completion of shallowtrench isolation structure20, as well as the fabrication of semiconductor devices thereon.
• Referring now to FIGS.[0047]7-11, a second shallowtrench isolation structure30 embodiment of a semiconductor device structure according to the present invention is illustrated. With reference to FIGS. 7 and 8, shallowtrench isolation structure30 includes asemiconductor substrate21 with asurface22 andtrenches24 recessed, or formed in,surface22. A layer of electrically nonconductive material, orinsulator layer36, substantially fillstrenches24 and coverssurface22.Insulator layer36 has a nonplanarupper surface37 and includesvalleys34 located substantially abovetrenches24 andpeaks32 located substantially abovesurface22.
• Shallow[0048]trench isolation structure30 may also have alayer38,38′ of stress buffer material, which is also referred to herein as a stress buffer layer, having a substantiallyplanar surface39,39′ disposed at least partially overinsulator layer36. FIG. 7 illustratesstress buffer layer38, which substantially fillsvalleys34 recessed ininsulator layer36 and substantially completely covers peaks32. The thickness T″ of regions ofstress buffer layer38 located abovepeaks32 is less than the depths D″ ofvalleys34. Thickness T″ is preferably less than about half of depth D″. FIG. 8 depictsstress buffer layer38′, which does not extend overpeaks32 and which may only partially fillvalleys34. Stress buffer layers38,38′ are preferably formed from a photoresist or other polymer by processes the same as or similar to those disclosed previously herein with reference to the fabrication ofmask layer18 illustrated in FIG. 2.
• Once a substantially planar surface is formed over shallow[0049]trench isolation structure30, such as that formed at least partially bysurface39 ofstress buffer layer38 and as illustrated in FIG. 7,stress buffer layer38 and portions ofinsulator layer36 located above the plane ofsurface22 may be substantially concurrently removed. For example, layers38 and36 may be substantially removed by exposure to the same etchant or combination of etchants that will removestress buffer layer38 andinsulator layer36 at substantially the same rates to provide the finished shallowtrench isolation structure30 illustrated in FIG. 11. Either wet etchants or dry etchants may be used. Preferably, the use of etchants eliminates the formation of imperfections or defects insurface22 ofsemiconductor substrate21, as well as the possible introduction of contaminants or other debris thereon. Alternatively, known chemical-mechanical planarization processes may be used to substantially concurrently removestress buffer layer38 and portions ofinsulator layer36 abovesurface22, also providing a finished shallowtrench isolation structure30 such as that illustrated in FIG. 11. Asstress buffer layer38 provides a substantially planar surface over shallowtrench isolation structure30, the likelihood that material ofinsulator layer36 will be broken off during the chemical-mechanical planarization process is reduced, thereby reducing the formation of imperfections or defects insurface22, as well as the creation of contaminants or other debris, which may occur during chemical-mechanical planarization of a nonplanar surface.
• As shown in FIG. 8,[0050]stress buffer layer38′ may not provide shallowtrench isolation structure30 with a substantially planar surface. Rather, peaks32 ofinsulator layer36 protrude abovesurface39′ ofstress buffer layer38′. In order to provide a substantially planar surface over shallowtrench isolation structure30, the portions ofpeaks32 that protrude above the plane ofsurface39′ may be selectively removed, such as by use of selective wet or dry etch processes. The material ofpeaks32 that protrudes above the plane ofsurface39′ is removed at least until a substantiallyplanar surface31 is formed over shallowtrench isolation structure30, as depicted in FIG. 9.
• As illustrated in FIG. 10, the selective removal of material forming[0051]insulator layer36 may continue until portions ofinsulator layer36 located above the plane ofsurface22 are substantially removed. As a result, discontinuous quantities ofstress buffer layer38′ remain abovetrenches24 and the portions ofinsulator layer36 remaining therein.Stress buffer layer38′ may be removed mechanically or by use of a wet or dry etchant that will not substantially remove or react with the materials ofsemiconductor substrate21 or of the portions ofinsulator layer36 remaining withintrenches24. For example, if a photoresist is used to formstress buffer layer38′, known resist strippers may be used to removestress buffer layer38′ to form a finished shallowtrench isolation structure30, such as that illustrated in FIG. 11.
• Alternatively, once a substantially[0052]planar surface31 has been formed over shallowtrench isolation structure30, as shown in FIG. 9,stress buffer layer38′ and the portions ofinsulator layer36 located above the plane ofsurface22 may be substantially concurrently removed from above shallowtrench isolation structure30 by use of one or more dry or wet etchants that remove the materials oflayers38 and36 at substantially the same rates, as known in the art, or by known chemical-mechanical planarization processes to provide the finished shallowtrench isolation structure30 illustrated in FIG. 11.
• Once a finished shallow[0053]trench isolation structure30, such as that depicted in FIG. 11, has been fabricated, one or more semiconductor devices may then be fabricated on shallowtrench isolation structure30, as known in the art.
• FIGS.[0054]12-16 illustrate yet another embodiment of asemiconductor device structure40 that incorporates teachings of the present invention. With reference to FIGS. 12 and 13,semiconductor device structure40 includes dualdamascene trenches44 formed in asurface42 of aninsulator layer41 thereof. Aconductive layer46 overliessurface42 and substantially fillstrenches44.Conductive layer46 has a nonplanarupper surface47 that includesvalleys54 located substantially overtrenches44 andpeaks52 located substantially oversurface42.Insulator layer41,trenches44, andconductive layer46, as well as other structures ofsemiconductor device structure40underlying insulator layer41 andtrenches44 are each fabricated by known processes, such as those disclosed in U.S. Pat. No. 5,980,657 to Farrar et al. on Nov. 9, 1999, the disclosure of which is hereby incorporated in its entirety by this reference.
• [0055]Semiconductor device structure40 also includes a layer of stress buffer material, which is also referred to herein as astress buffer layer48,48′, at least partially coveringconductive layer46 and having a substantiallyplanar surface49,49′. FIG. 12 illustratesstress buffer layer48, which substantially fillsvalleys54 recessed inconductive layer46 and substantially completely covers peaks52. The thickness T″′ of regions ofstress buffer layer48 located abovepeaks52 is less than the depths D″′ ofvalleys54. Thickness T″′ is preferably less than about half of depth D″′. FIG. 13 depictsstress buffer layer48′, which does not extend overpeaks52 and which may only partially fillvalleys54. Stress buffer layers48,48′ are preferably formed from a photoresist or other polymer by processes the same as or similar to those disclosed previously herein with reference to the fabrication ofmask layer18 illustrated in FIG. 2.
• Once a substantially planar surface is formed over[0056]semiconductor device structure40, such as that formed at least partially bysurface49 ofstress buffer layer48 and as illustrated in FIG. 12,stress buffer layer48 and portions ofconductive layer46 located above the plane ofsurface42 may be substantially concurrently removed. For example, layers48 and46 may be substantially concurrently removed with an etchant or combination of etchants that will removestress buffer layer48 andinsulator layer46 at substantially the same rates to provide the finishedsemiconductor device structure40 illustrated in FIG. 16. Either wet etchants or dry etchants may be used. Preferably, the use of etchants eliminates the formation of imperfections or defects insurface42 ofinsulator layer41, as well as the possible introduction of contaminants or other debris thereon. Alternatively, known chemical-mechanical planarization processes may be used to substantially concurrently removestress buffer layer48 and portions ofconductive layer46 abovesurface42, also providing a finishedsemiconductor device structure40 such as that illustrated in FIG. 16. Asstress buffer layer48 provides a substantially planar surface over shallowtrench isolation structure40, the likelihood that material ofconductive layer46 will be broken off during the chemical-mechanical planarization process is reduced, thereby reducing the formation of imperfections or defects insurface42, as well as the creation of contaminants or other debris, which may occur during chemical-mechanical planarization of a nonplanar surface.
• As illustrated in FIG. 13,[0057]stress buffer layer48′ may not providesemiconductor device structure40 with a substantially planar surface. Rather, peaks52 ofconductive layer46 protrude abovesurface49′ ofstress buffer layer48′. In order to provide a substantially planar surface oversemiconductor device structure40, the portions ofpeaks52 that protrude above the plane ofsurface49′ may be selectively removed, such as by use of selective wet or dry etch processes. The material ofpeaks52 that protrudes above the plane ofsurface49′ is removed at least until a substantiallyplanar surface51 is formed oversemiconductor device structure40, as depicted in FIG. 14.
• FIG. 15 illustrates that the selective removal of material forming[0058]conductive layer46 may continue until portions ofconductive layer46 located above the plane ofsurface42 are substantially removed therefrom. As a result, discontinuous quantities ofstress buffer layer48′ remain abovetrenches44 and the portions ofconductive layer46 remaining therein.Stress buffer layer48′ may be removed mechanically or by use of a wet or dry etchant that will not substantially remove or react with the materials ofinsulator layer41 or of the portions ofconductive layer46 remaining withintrenches44. For example, if a photoresist is used to formstress buffer layer48′, known resist strippers may be used to removestress buffer layer48′ to form asemiconductor device structure40 such as that illustrated in FIG. 16.
• Alternatively, once a substantially[0059]planar surface51 has been formed oversemiconductor device structure40, as shown in FIG. 14,stress buffer layer48′ and the portions ofconductive layer46 located above the plane ofsurface42 may be substantially concurrently removed from abovesemiconductor device structure40 by use of one or more wet or dry etchants that remove the materials oflayers48′ and46 at substantially the same rates, as known in the art, or by known chemical mechanical planarization processes to provide thesemiconductor device structure40 illustrated in FIG. 16.
• Once a[0060]semiconductor device structure40 such as that depicted in FIG. 16 has been fabricated, further known fabrication processes may be performed.
• Although the foregoing description contains many specifics, these should not be construed as limiting the scope of the present invention, but merely as providing illustrations of some of the presently preferred embodiments. Similarly, other embodiments of the invention may be devised which do not depart from the spirit or scope of the present invention. Features from different embodiments may be employed in combination. The scope of the invention is, therefore, indicated and limited only by the appended claims and their legal equivalents, rather than by the foregoing description. All additions, deletions and modifications to the invention as disclosed herein which fall within the meaning and scope of the claims are to be embraced thereby.[0061]

Claims (20)

What is claimed is:

1. A semiconductor device structure with a substantially planar surface, comprising:

a substrate including at least one recess formed therein; and

a material layer disposed over said substrate and substantially filling said at least one recess, said material layer having a substantially planar surface free of abrasive planarization-induced defects.

2. The semiconductor device structure ofclaim 1, wherein said substrate comprises a semiconductor substrate with a surface and said at least one recess comprises at least one trench recessed in said surface of said semiconductor substrate.

3. The semiconductor device structure ofclaim 1, wherein said material layer comprises a mask material.

4. The semiconductor device structure ofclaim 3, further comprising at least one conductively doped region continuous with a surface of said semiconductor substrate and laterally adjacent said at least one trench.

5. The semiconductor device structure ofclaim 1, wherein said substrate comprises:

a shallow trench isolation structure including a semiconductor substrate with a surface and at least one trench formed in said surface of said semiconductor device substrate; and

an insulator layer substantially filling said at least one trench and covering said surface of said semiconductor device substrate.

6. The semiconductor device structure ofclaim 5, wherein said insulator layer includes a nonplanar upper surface with at least one peak located substantially above said surface of said semiconductor device substrate and at least one valley located substantially above said at least one trench.

7. The semiconductor device structure ofclaim 6, wherein said material layer comprises a stress buffer layer that substantially fills said at least one valley in said insulator layer.

8. The semiconductor device structure ofclaim 1, wherein said substrate comprises:

a semiconductor device structure including a surface with at least one dual damascene trench formed thereon; and

a conductive layer substantially filling said at least one dual damascene trench and covering said surface of said semiconductor device structure.

9. The semiconductor device structure ofclaim 8, wherein said conductive layer includes a nonplanar upper surface with at least one peak located substantially above said surface of said semiconductor device structure and at least one valley located substantially above said at least one dual damascene trench.

10. The semiconductor device structure ofclaim 9, wherein said material layer comprises a stress buffer layer that substantially fills said at least one valley in said conductive layer.

11. The semiconductor device structure ofclaim 1, wherein said substrate comprises a stacked capacitor structure including an insulator layer with at least one container recessed therein.

12. The semiconductor device structure ofclaim 11, wherein said material layer comprises a mask material, said mask material substantially filling said at least one container.

13. The semiconductor device structure ofclaim 12, wherein mask material covering a surface of said insulator layer has a thickness of less than a height of said at least one container.

14. The semiconductor device structure ofclaim 12, wherein mask material covering a surface of said insulator layer has a thickness of less than about half a depth of said at least one container.

15. A semiconductor device structure with a substantially planar surface, comprising:

a substrate including at least one recess formed therein; and

a material layer disposed at least partially over said substrate so as to at least partially fill said at least one recess, said material layer having a substantially planar surface substantially free of abrasive planarization-induced defects.

16. The semiconductor device structure ofclaim 15, wherein at least one region of said substrate is exposed through said material layer.

17. The semiconductor device structure ofclaim 15, further comprising:

at least one intermediate layer between said substrate and said material layer, at least one portion of said intermediate layer at least partially filling said at least one recess.

18. The semiconductor device structure ofclaim 17, wherein at least one region of said at least one intermediate layer is exposed through said material layer.

19. The semiconductor device structure ofclaim 17, wherein said at least one intermediate layer comprises at least one of a mask material, an insulative material, and a conductive material.

20. The semiconductor device structure ofclaim 15, wherein said material layer has a thickness that is less than a depth of said at least one recess.

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