US20020001965A1 - Technique for producing small islands of silicon on insulator - Google Patents

Abstract

Using sub-micron technology, silicon on insulator (SOI) rows and islands are formed in a silicon substrate. Trenches are directionally-etched in the silicon substrate, leaving rows of silicon between the trenches. Silicon nitride is then deposited over the trenches, extending partly down the sides of the trenches. An isotropic chemical etch is then used to partially undercut narrow rows of silicon in the substrate. A subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas. Devices, such as transistors for CMOS and DRAMs, are then formed in active areas, wherein the active areas are defmed on the silicon rows by LOCal Oxidation of Silicon (LOCOS).

Description

FIELD OF THE INVENTION
• The present invention relates to methods and apparatus for isolating semiconductor devices with silicon on insulator technology, and in particular, for forming isolated silicon islands using sub-micron technology.[0001]
BACKGROUND OF THE INVENTION
• The advantages of silicon on insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are well documented. In general, undesired p-n junction capacitance between a source/drain and a substrate is reduced by approximately twenty-five-percent when using SOI technology. Furthermore, active current consumption is less and device access time is equivalent to that of similar devices formed on bulk-silicon substrates. Other advantages of SOI technology include suppression of the short channel effect, suppression of the body-effect, high punch-through immunity, and freedom from latch-up and soft errors. As the demand increases for battery-operated equipment, SOI technology is becoming increasingly more popular due to its low power requirements and high speeds.[0002]
• There are many different techniques for isolating devices in ICs. A technique is selected according to its different attributes, such as: minimum isolation spacing, surface planarity, process complexity, and density of defects generated during fabrication.[0003]
• SIMOX (Separation by IMplanted OXygen) technology is one method for forming SOI structures. SIMOX entails implanting a high dose of oxygen ions at a sufficiently deep level within a silicon substrate. A subsequent anneal step forms a buried oxide layer in the substrate. After the anneal step, an additional layer of epitaxial silicon is usually deposited to obtain a sufficiently thick silicon layer on which to form a device. Disadvantages of using SIMOX include its high expense and yield loss, which undesirably decreases achievable chip density.[0004]
• Another technique for forming an isolation layer in a substrate is by the wafer bonding method. Using this technique, two oxidized silicon wafers are fused together through a high-temperature furnace step. However, this technique increases the substrate thickness, which is often a critical dimension. Furthermore, wafer bonding techniques are often plagued by low production yield due to particles/voids, which prevent adequate bonding between the two wafers in such areas.[0005]
• Another technique used for forming an isolation layer in a substrate is by forming silicon islands through a series of etch and oxidation steps. For example, U.S. Pat. No. 4,604,162 (hereinafter the '162 patent) uses a series of a pad oxide layer, a silicon nitride layer, and a silicon dioxide layer, which is photolithographically masked and anisotropically etched to define silicon islands capped with a silicon nitride layer. Then, a second anisotropic etch (such as a reactive ion etch (RIE)) removes further substrate material between the silicon islands. The depth of the second anisotropic etch is proportional to the width of the silicon islands. A subsequent oxidation step forms silicon dioxide, undercutting the silicon islands and isolating each of them from surrounding regions. However, this technique has not been used commercially because it is too costly and consumes too much time to oxidize an area having an effective width as great as that of the feature size. Another disadvantage of this technique is that the resulting isolated silicon structure has excess mechanical stress and crystal damage at each of its corners, due to oxidation around the entirety of each individual island, which is necessary for its complete isolation. Furthermore, the method described in the patent application requires an additional planarization step, which adds complexity to the fabrication process.[0006]
• There is a need for an effective isolation technique for sub-micron semiconductor technology that is efficient and simple. A primary concern in the fabrication of ICs is simplicity and minimization of process steps. There is a need for an isolation technique that is inexpensive and compatible with large volume CMOS manufacturing technology. Furthermore, an isolation technique, which allows fabrication of highly dense ICs without increasing the dimensions of the IC is needed.[0007]
SUMMARY OF THE INVENTION
• Silicon on insulator (SOI) rows and islands are formed for subsequent sub-micron device formation. For example, complementary metal-oxide-semiconductor (CMOS) transistors are later formed on such SOI rows, isolated from each other using standard techniques, such as LOCal Oxidation of Silicon (LOCOS). To form the rows, trenches are directionally-etched in a silicon substrate, leaving rows of silicon between the trenches.[0008]
• Silicon nitride is then deposited over the trenches, extending partly down the sides of the trenches. An isotropic chemical etch is then used to partially undercut narrow rows of silicon in the substrate. It is important to use an isotropic etch for this step to compensate for the volume of oxide to be formed. In general, the volume of oxide formed is approximately twice that of the silicon consumed. Furthermore, an isotropic etch is necessary to advantageously minimize the subsequent oxidation time needed to fully undercut the silicon rows. The subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas.[0009]
• One advantage of this invention is that by using narrow, sub-micron rows of silicon and appropriately designed process conditions, generally planar structures are formed in an integrated circuit (IC). The larger volume of oxide fills the trenches between the rows. This avoids complex and expensive planarization techniques, such as employed in older micron dimension technologies. Furthermore, such oxidation minimizes mechanical stress and crystal damage in resulting structures, when used to finish undercutting rows, as compared to undercutting individual silicon islands.[0010]
• This invention enables formation of sub-micron devices, such as CMOS transistors, having a high chip density, without increasing the dimensions of the IC. This method yields isolated active regions, having a high degree of regularity and yield, formed in an inexpensive manner. This method is compatible with CMOS IC manufacturing technology due to its simplicity and minimal number of process steps. Regular array structures, such as dynamic random access memories (DRAMs) particularly benefit from this invention, separated on the silicon rows using LOCOS technology.[0011]
BRIEF DESCRIPTION OF THE DRAWINGS
• FIGS. 1A to[0012]1D are cross-sectional representations of a method for forming isolated silicon rows.
• FIG. 1E is a plan view of isolated silicon islands formed on the isolated silicon rows shown in FIG. 1D.[0013]
• FIG. 1F is a cross-sectional representation of NMOS and PMOS transistors formed on the isolated silicon islands shown in FIG. 1E.[0014]
• FIG. 1G is a plan view of the NMOS and PMOS transistors shown in FIG. 1F.[0015]
DESCRIPTION OF THE EMBODIMENTS
• In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. Numbering in the Figures is usually done with the hundreds and thousands digits corresponding to the figure number, with the exception that the same components may appear in multiple figures.[0016]
• As shown in FIG. 1A, a[0017]silicon substrate101 is directionally-etched to formtrenches102, leavingrows104 of silicon protruding from thesubstrate101. Thesilicon rows104 have widths of one micron or less. Thetrench102 depth and width are approximately equal to the width of thesilicon rows104. The direction of the etch varies with the crystal orientation of thesubstrate101. In one embodiment, the etch direction is orthogonal to the plane of thesubstrate101. For complementary metal-oxide-semiconductor (CMOS) devices,substrates101 having a {100} crystallographic orientation are commonly used due to the ability to achieve small surface state densities on such substrates. Therefore, the direction of the etch is preferably in the <100> direction. To form the trenches, thesubstrate101 is oxidized at a temperature of approximately 900 to 1,100 degrees Celsius, covered with silicon nitride (Si₃N₄), masked and etched to form exposed oxide regions using standard techniques. Then, the exposed oxide regions are etched away with a directional etchant, preferably a reactive ion etch (RIE), formingtrenches102 in thesubstrate101.
• Next, as shown in FIG. 1B, a Si[0018]₃N₄cap106 is formed on thesilicon rows104. The Si₃N₄106 is deposited over the structure, using techniques well known in the art, such as chemical vapor deposition (CVD). Si₃N₄106 forms on the tops of thesilicon rows104 and partly down the sides of thetrenches102. Material overhang at the top of thetrench102 prevents Si₃N₄106 from covering the lower sides of thetrenches102. However, some Si₃N₄106 is deposited onto the bottom of thetrenches102.
• A photoresist mask is used to cover the[0019]silicon rows104 and an etch is then used to remove residual Si₃N₄106 on the bottom of thetrenches102 and then an isotropic chemical etch is used to partially undercut therows104 of silicon, as shown in FIG. 1C. A standard chemical etch using hydrofluoric acid (HF) or a commercial etchant sold under the trade name CP4 (a mixture of approximately 1 part (46% HF): 1 part (CH₂COOH):3 parts (HNO₂)) is used for the isotropic etchant. It is important to use an isotropic etch for this step to compensate for the volume of oxide to be formed in the next step. In general, the volume of oxide formed is approximately twice that of thesilicon101 consumed. Partially undercutting thesilicon rows104, reduces the effective width of therows104 to adistance110 small enough that a relatively short, simple oxidation can fully undercut thesilicon rows104. Fully undercutting therows104 of silicon is possible because thewidth108 of therows104 is one micron or less.
• The[0020]substrate101 is then oxidized using a standard silicon processing furnace at a temperature of approximately 900 to 1,100 degrees Celsius, as shown in FIG.1D. A wet, oxidizing ambient is used in the furnace chamber to oxidize the exposed silicon regions on the lower part of thetrenches102 in a parallel direction to the surface of thesubstrate101. Thesubstrate101 is oxidized for a time period, such thatoxide112 fully undercuts the bottom of thesilicon rows104, leavingisolated silicon rows104. By using narrow,sub-micron rows104 of silicon and appropriately designed process conditions, generally planar structures are formed. The larger volume of oxide fills thetrenches102 between therows104. This avoids the need for complex and expensive planarization techniques, such as employed in older micron dimension technologies. The time period for oxidation depends on thewidth108 of therows104 and theeffective width110 after the partial undercut step. As the desired size of thesilicon rows104 decreases, so does the required oxidation time. For example, for sub-micron technology, oxidation time is approximately 3 to 4 hours. For sub-0.25 micron technology, oxidation time is approximately 1 hour.
• [0021]Active areas114 are then defined on theindividual silicon rows104, using a standard process, such as LOCal Oxidation of Silicon (LOCOS), as shown in FIG. 1E, to formoxide116 between theactive areas114. Depending on the width of thesilicon rows104, the area of theseactive areas114 is approximately one square micron or less for sub-micron technology and approximately 0.0625 square microns or less for sub-0.25 micron technology. The resulting isolatedactive areas114 are not subjected to as much mechanical stress and crystal damage as are active areas formed by prior art techniques of oxidizing to undercut each individual active area, which are excessively stressed and damaged at each corner of the active area.
• Devices are then formed on the resulting[0022]silicon islands114, as shown in FIGS. 1F and 1G, according to methods well known in the art. For example, when forming CMOS transistors, agate oxide layer118, source/drain regions120,122, and agate124 are formed for each transistor on anindividual silicon island114. For PMOS transistors, source/drain regions120 are doped to form (p+) regions. For NMOS transistors, source/drain regions122 are doped to form (n+) regions. Further standard process techniques are then used to connect the devices to form circuits, such as dynamic random access memory (DRAM) devices.
• The process described above is a low cost, simple method for forming sub-micron SOI devices. The method is compatible with existing large volume manufacturing conditions. Resulting devices are able to formed on semiconductor chips in a highly dense, arrayed manner. Thus, the invention enables formation of very high density and very high performance CMOS integrated circuits, DRAMs, as well as other integrated circuits.[0023]
• It should be noted that in CMOS technology, many times certain areas of the semiconductor die described as having a particular doping, could quite easily be of a different doping, promoting a different type of charge carrier. In such instances, if one were to reverse the primary carriers in all areas of the die and adjust for carrier mobility, the invention would operate in the same manner as described herein without departing from the scope and spirit of the present invention.[0024]
• It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.[0025]

Claims (20)

What is claimed is:

1. A method for manufacturing a silicon on insulator substrate, comprising the steps of:

directionally etching a silicon substrate, to form a plurality of trenches between protruding silicon rows;

forming a silicon nitride cap on the silicon rows, extending partway down the sides of the trenches;

isotropically etching the trenches, to partially undercut the silicon rows; and

oxidizing the substrate, to fully undercut the silicon rows.

2. The method ofclaim 1, wherein the silicon substrate has a {100} crystallographic orientation and the directional etch is in the <100> direction.

3. The method ofclaim 1, wherein the directional etchant comprises a reactive ion etch.

4. The method ofclaim 1, wherein the isotropic etchant comprises hydrofluoric acid.

5. The method ofclaim 1, wherein the silicon rows have a width dimension of one micron or less.

6. The method ofclaim 1, wherein the silicon rows have a width dimension of 0.25 microns or less.

7. The method ofclaim 1, wherein the directional etch is approximately as deep as the width of the silicon rows and approximately as wide as the width of the silicon rows.

8. The method ofclaim 1, wherein the oxidizing step comprises oxidizing the substrate in a wet oxidizing ambient at a temperature of approximately 900 to 1,100 degrees Celsius.

9. The method ofclaim 1, and further comprising the step of:

defining a plurality of active areas on the silicon rows by local oxidation of silicon.

10. The method ofclaim 9, and further comprising the step of:

forming a transistor on each of a plurality of the active areas.

11. A silicon on insulator structure, comprising:

a plurality of silicon rows, having a width dimension of one micron or less, embedded in an oxidized substrate; and

a plurality of oxide rows between the silicon rows.

12. The structure ofclaim 11, wherein the oxide rows have a width dimension of one micron or less.

13. The structure ofclaim 11, wherein the silicon rows have a width dimension of 0.25 microns or less.

14. The structure ofclaim 11, wherein the oxide rows have a width dimension of 0.25 microns or less.

15. A plurality of active areas on a semiconductor substrate, comprising:

a plurality of isolated silicon active areas, having an area of one square micron or less, embedded in an oxidized substrate; and

a plurality of oxide rows between the silicon active areas in one direction.

16. The structure ofclaim 15, and further comprising:

a plurality of transistors formed on each of a plurality of the silicon active areas.

17. The structure ofclaim 15, wherein the oxide rows have a width dimension of one micron or less.

18. The structure ofclaim 15, wherein the oxide rows have a width dimension of 0.25 microns or less.

19. The structure ofclaim 15, wherein the area of the silicon active areas is 0.0625 square microns or less.

20. The structure ofclaim 15, wherein the active areas are isolated using local oxidation of silicon.

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