US20020000583A1 - System with meshed power and signal buses on cell array - Google Patents

Abstract

A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Description

CROSS REFERENCE
• This application claims the benefit of U.S. Provisional Application No. 60/005,502, filed Nov. 9, 1995.[0001]
FIELD OF THE INVENTION
• The invention relates generally to semiconductor circuit design and, more particularly, to a method and apparatus for interconnecting power and signal buses in an integrated circuit.[0002]
BACKGROUND OF THE INVENTION
• As semiconductor technology develops, the number of transistors included in a single integrated circuit, or “chip,” is becoming larger and the design rule parameters therefore are becoming smaller. These two developments contribute to increased metal layer resistance and to difficulties associated with this increased resistance. Such difficulties include ground bounce, cross talk noise, and circuit delays. All of these difficulties slow down chip operation and may even corrupt data stored on the chip. Eliminating the impact of increased metal layer resistance is an important design challenge in most semiconductor designs, including designs for dynamic random access memory (DRAM) devices.[0003]
• One solution to this problem has been the development of a meshed power bus system for the chip, as described in Yamada, A 64-Mb[0004]DRAM with Meshed Power Line,26 IEEE Journal of Solid-State Circuits 11 (1991). A meshed power bus system is readily implemented in integrated circuits like DRAMs because of their large arrays of memory cells and the presence of distributed sense amplifier drivers. The meshed system supplies adequate power to the distributed sense amplifier drivers because the system has many power buses running in both horizontal and vertical directions across the arrays.
• The Yamada meshed system may be implemented using a conventional complimentary metal oxide semiconductor (CMOS) technology, including first, second and third metal layers, each electrically isolated from each other, wherein the first metal layer represents the lowest metal layer, the third metal layer represents the upper-most metal layer, and the second metal layer lies between the first and third layers. The Yamada meshed system is constructed in the second and third metal layer and includes a positive supply voltage (V[0005]_DD) mesh and a negative supply voltage (V_SS) mesh, for the V_DDpower buses and the V_SSpower buses, respectively. Conventional designs have these meshes running over the memory array and connecting at the sense amplifiers. Connections are made using through-holes, located in the area of the sense amplifier circuits. However, the presence of V_DDand V_SSpower buses in the sense amplifiers is unnecessary, since these circuits do not require either V_DDor V_SSpower buses, except for well bias.
• As a result, the sense amplifiers, due to their relatively small size and numerous associated signal and power buses, are adversely affected by the Yamada meshed system. The Yamada meshed system overcrowds the sense amplifiers with additional power and signal buses. In addition, the metal line width required for overlapping through-holes is larger than the minimum metal line width and therefore increases the width of the metal layers even further. As a result, the metal layer over the sense amplifiers becomes determinative of the size of the sense amplifier circuits. Accordingly, their size reduction must be realized by tightening the metal width, inevitably resulting in increased resistance and slower operation[0006]
• In addition to the Yamada meshed system, other proposals have been made for conventional DRAM design Recently, a hierarchical word line scheme was proposed in K. Noda et Al.,[0007]a Boosted Dual Word-line Decoding Scheme for256 Mbit DRAM's, 1992 Symp. on VLSI Circuits Dig. of Tech. Papers, pp. 112-113 (1992). The Noda scheme includes main word lines, constructed in the second metal line layer, and subword lines constructed in a poly silicon layer. The Noda scheme describes two main word lines (one true, one bar) for every eight subword lines, and is thereby able to relax the main word line pitch to four times that of the subword line. However, this pitch would not support an improved meshed power and signal bus system.
• Consequently, there is a need for a meshed power and signal bus system on an array-type integrated circuit that does not limit mesh through-hole connections to the area of the sense amplifiers, but provides for such connections at other locations on the array, thereby allowing for a relaxed metal width over the sense amplifiers and a reduction of the overall area of the chip with lower power bus resistance.[0008]
• Furthermore, there is a need for a hierarchical word line scheme that supports an improved meshed power and signal bus system, that has a main word line pitch greater than four times that of the subword line pitch.[0009]
SUMMARY OF THE INVENTION
• The present invention, accordingly, is a method and apparatus for providing a meshed power bus and signal bus system on an array-type integrated circuit that does not limit mesh through-hole connections to the area of the sense amplifiers, but provides for these connections at other locations on the array, thereby allowing for a relaxed metal width over the sense amplifiers, faster sense amplifier operation, and chip size reduction. The through-holes for the mesh system are located in the cell array instead of, or in addition to, being located in the area of the sense amplifier circuits. This utilizes the available space for through-holes in the array, and allows for more efficient use of power and signal buses in the sense amplifiers.[0010]
• The invention includes an array of DRAM memory cells, arranged as a plurality of subarrays and selected by main address decoders. Each subarray is surrounded by a plurality of sense amplifiers circuits, subdecoder circuits, and V[0011]_DD, V_SSand signal buses connecting to and running across the subarray. The V_DDbuses run in both vertical and horizontal directions across the subarray, with all the vertical buses lying in the third metal layer and all the horizontal buses lying in the second metal layer, thereby creating a V_DDmesh. The buses in each layer are connected to each other using through-holes located in the memory cell subarray as well as on the sense amplifier area. Likewise, a V_SSmesh and/or a signal mesh is created using through-holes located on the memory cell subarray. Once connected, the buses extend to the appropriate circuits, such as sense amplifier drive circuits, and the metal layer and through-hole requirement over the sense amplifiers is significantly reduced.
• The invention also includes a hierarchical word line scheme. To facilitate the combination of the above-mentioned meshed system and the hierarchical word line scheme, the Noda hierarchical word line scheme should also be improved to provide a greater pitch of main word lines to subword lines. In the improved hierarchical word line system, an intersection area, created between the sense amplifier and the subdecoder, includes subdecoder drivers as well as sense amplifier drivers. This combination provides high speed word line selection and high speed sense amplifier operation at the same time.[0012]
• Once the sense amplifier size is no longer determined by the metal usage, as provided by the above-mentioned meshed system, an improved layout technique for the sense amplifier circuits may be necessary to match the fine memory cell size. This improved layout technique includes an alternating T-shaped gate region for a bit line equalization circuit and an H-shaped moat region with a metal-to-polysilicon-to-metal change structure for a latch circuit.[0013]
• A technical advantage achieved with the invention is the ability to fully utilize the low resistance design of a meshed power system without having to increase the size of the peripheral circuits, for example, sense amplifiers, that are limited in size by their metal layers.[0014]
• A further technical advantage achieved with the invention is that both signal and power buses may freely run in both horizontal and vertical directions.[0015]
• A further technical advantage achieved with the invention is that the design for through-holes located in the array area or on a step difference compensation area do not have to be made to the minimum design widths like the through-holes located in the peripheral area, and therefore the yield is improved.[0016]
• A further technical advantage achieved with the invention is that the improved hierarchical word line structures are smaller and faster than conventional hierarchical word line structures.[0017]
BRIEF DESCRIPTION OF THE DRAWING
• FIG. 1 is a block diagram of a 256 Mbit DRAM embodying features of the present invention.[0018]
• FIG. 2 is a block diagram of two subarrays and surrounding sense amplifiers and sudecoders of the DRAM of FIG. 1.[0019]
• FIG. 3 is a block diagram of one subarray, two sense amplifiers, and a subdecoder, as shown in FIG. 2, and a meshed power and signal system running across the subarray.[0020]
• FIG. 4 is a schematic diagram of a meshed power and signal system over the subarray of FIG. 3.[0021]
• FIG. 5[0022]ais a cross sectional view of a memory cell of the subarray of FIG. 3 with a through-hole connecting two metal layers used in the meshed power system of FIG. 4.
• FIG. 5[0023]bis a detailed schematic of a memory cell of the subarray of FIG. 3.
• FIGS. 6[0024]a-6care layout diagrams of expanded sections of the meshed system of FIG. 4.
• FIGS. 7[0025]a-bare schematic diagrams of circuits included in the intersection area, sense amplifier, subdecoder and memory array of FIG. 3.
• FIG. 8 is a diagram of the subdecoder circuits of FIG. 7.[0026]
• FIG. 9[0027]ais a schematic diagram of a prior art subdecoder circuit showing the Noda hierarchical word line implementation.
• FIG. 9[0028]bis a schematic diagram of one subdecoder circuit showing a hierarchical word line implementation.
• FIG. 9[0029]cis a schematic diagram of a preferred subdecoder circuit show a hierarchical word line implementation of the present invention.
• FIG. 10[0030]ais a schematic diagram of the two sense amplifier circuits of FIG. 7a.
• FIG. 10[0031]bis a layout diagram of the sense amplifier circuits of FIG. 10a.
• FIG. 11[0032]ais a layout diagram of a circuit used in an equalizer section of a conventional sense amplifier.
• FIG. 11[0033]bis a layout diagram of a circuit ed in the equalizer section of the sense amplifier circuit of FIG. 7a, an alternate T-shaped gate region of the present invention.
• FIG. 12[0034]ais a layout diagram of a circuit used in the latch section of the sense amplifier circuit of FIG. 7a, utilizing the H-shaped moat region of FIG. 10b.
• FIG. 12[0035]bis a simplified diagram of the H-shaped moat region of FIG. 12a.
• FIG. 13[0036]ais a metal layout diagram of a section of a conventional sense amplifier.
• FIGS. 13[0037]b-care metal layout diagrams of an improved section of the sense amplifier of FIG. 7a, implementing a noise decreasing method of the present invention.
• FIG. 14[0038]ais a first cross sectional view of a sense amplifier using a triple well structure.
• FIG. 14[0039]bis a second cross sectional view of the sense amplifier of FIG. 2, using a triple well structure.
• FIG. 14[0040]cis a cross sectional view of the subdecoder of FIG. 2 using a triple well structure.
• FIG. 15[0041]ais a block diagram showing four fuses used for the sense amplifiers of FIG. 2 and two additional sense amplifiers.
• FIG. 15[0042]bis a schematic diagram showing four fuses used for the sense amplifiers of FIG. 2 and two additional sense amplifiers.
DETAILED DESCRIPTION OF THE INVENTION
• In FIG. 1 the[0043]reference numeral10 refers to a memory device embodying features of the present invention. Thedevice10 is fabricated using a conventional CMOS technology, including first, second and third metal layers and a polysilicon layer. Thedevice10 also utilizes metal oxide semiconductor field effect transistors (MOSFETs), but other types of transistors may also be used, such as bipolar, and metal insulator semiconductors. Furthermore, while in a preferred embodiment of the invention, thedevice10 is a 256 Mbit dynamic random access memory (DRAM), it should be understood that the present invention is not limited to use with a 256 Mbit DRAM, but may be used in conjunction with other devices having arrays, including a programmable array logic, a 1 Gbit DRAM and other memory devices.
• The[0044]device10 includes a set of array blocks of memory cells, such as an array block12, a group of pads14a-14f, and a group of main address decoders16a-16l, whereindecoders16b,16e,16hand16kare row decoders anddecoders16a,16c,16d,16f,16g,16i,16jand16lare column decoders. The array block12 is selected by signals from the address pads14a-14d. It should be understood that while more address and signal pads exist, they may be represented by address pads14a-14d, which are decoded by main address decoders16a-16. The main address decoders16a-16lrepresent a plurality of row and column decoders. The row decoders generate signals including main-word signals MWB and subdecoder control signals DXB, and the column decoders generate signals such as column select signals YS. These signals are controlled by different address signals from the address pads14a-14d, as discussed in greater detail below.
• Array block[0045]12, which is representative of the 16 Mbit array blocks, is further divided into 256 subarrays, two of which are shown in FIG. 2, and are respectively designated byreference numerals18aand18b. Each subarray consists of 128K of memory cells (arranged as 512 rows by 256 columns).
• Power is supplied to the[0046]device10 throughpower pads14eand14f.Thepad14eis the positive supply voltage (V_DD) power pad and is connected to an external power supply (not shown). Thepad14fis the negative supply voltage (V_SS) power pad and is connected to an external ground (also not shown).
• Ref to FIG. 2, the memory cells of the subarray[0047]18aare selected by signals from two groups of address subdecoders20aand20b. Likewise, the memory cells of thesubarray18bare selected by signals from two groups ofaddress subdecoders20cand20d. The memory cells ofsubarray18aare read by two groups ofsense amplifiers22aand22b. Likewise, the memory cells ofsubarray18bare read by two groups ofsense amplifiers22band22c. The sense amplifiers22a-22cintersect with the subdecoders20a-20d, at intersection areas24a-24f. In this way, intersection areas24a-24fare created by the extension of sense amplifier areas22a-22cand subdecoder areas20a-20d.
• Referring to FIG. 3, the[0048]pads14eand14fact as electrical ports to supply power to theentire device10 through main V_DDand V_SSpower buses28 and26, respectively. The main V_DDand V_SSpower buses28 and26 supply power to thedevice10 through a plurality of buses, located in different metal layers. The metal layers are layered onto a silicon substrate, in the order of: a first metal layer (M1), a second metal layer (M2), and a third metal layer (M3). Each of the metal layers M1, M2, M3 is electrically isolated from each other, but may be electrically interconnected at intersection points using through-holes. Each metal layer M1, M2, M3 also has associated therewith a thickness such that the thickness for M3 is greater than the thickness for M2, which is greater than the thickness for M1.
• A first V[0049]_DDbus30, comprising a conductor constructed in the third metal layer M3, extends in a vertical path across thesubarray18a. A first V_SSbus32, also a conductor constructed in M3, extends in a vertical path across thememory subarray18a, parallel with thebus30. Similarly, afirst signal bus34 and a first columnselect YS bus35, conductors constructed in M3, run vertically across thesubarray18aparallel withpower buses30 and32. A firstsubdecoder DXB bus36, also a conductor constructed in M3, runs vertically acrossaddress subdecoder20a, outside of the subarray8a.
• A second V[0050]_DDbus37a, a second V_SSbus37band asecond signal bus37c, conductors constructed in M3, run vertically across the subdecoder20aand theintersection areas24aand24b. The second V_DDbus37aand the second V_SSbus37bhave a width that is less than a width of the first V_DDbus30 and the first V_SSbus32, respectively.
• A third V[0051]_DDbus38 and a third V_SSbus40, along with athird signal bus42 and asecond DXB bus44, are also conductors similar to those described above, except that they are constructed in the second metal layer M2, and extend in parallel, horizontal paths across thememory subarray18a. The third V_DDbus38 electrically connects with the second V_DDbus37awithin the subdecoder20aat theirintersection point45 over theperipheral circuit area20aand the first V_DDbus30 at theirintersection point46 within thememory subarray18a. Likewise, the third V_SSbus40 electrically connects with the second V_SSbus37bat theirintersection point47 within the subdecoder20aand the first V_SSbus32 at theirintersection point48 within thememory subarray18a. Furthermore, thethird signal bus42 electrically connects with thesecond signal bus37cat theirintersection point49 within the subdecoder20aand thefirst signal bus34 at theirintersection point50 within thememory subarray18a. Finally, thesecond DXB bus44 electrically connects with thefirst DXB bus36 at theirintersection point52 in thesubdecoder circuit20a. Each of the intersection points is achieved using through-holes, as discussed in greater detail with reference to FIGS. 5a-6c.
• Associated with each bus is a line width, it being understood that a bus with a larger surface area (width and thickness) provides a lower resistance current path. The first V[0052]_DDand V_SSbus30,32 have a line width of 1.8 microns. The second V_DDand V_SSbus37a,37bhave a line width of 0.7 microns. The third V_DDand V_SSbus38,40 have a line width of 1.8 microns. Likewise, the through-holes have associated therewith a diameter, it being understood that a through-hole with a larger surface area (diameter) provides a lower resistance current path. The through-holes located above thememory subarray18ahave a diameter of 0.6 microns, while the through-holes located above thesubdecoder circuit20ahave a diameter of 0.8 microns.
• V[0053]_DDand V_SSpower is supplied through theexternal pads14eand14fthemain power buses28 and26, respectively, as previously described in FIG. 3. The first V_DDbus30 is electrically connected to the main V_DDpower bus28 thereby supplying V_DDpower to the first V_DDbus, the second V_DDbus37a, and the third V_DDbus38. The first V_SSbus32 is electrically connected to the main V_SSpower bus26 thereby supplying V_SSpower to the first V_SSbus, the second V_SSbus37b, and the third V_SSbus40. In this manner, a V_DDmesh54 is created by the V_DDbuses30,37aand38 and a V_SSmesh56 is created by the V_SSbuses32,37band40. As a result, each of the foregoing meshes have power buses running both vertically and horizontally across thesubarray18a, the subdecoder20aand the intersection areas24a-24b. Furthermore, the V_DDand V_SSmeshes54 and56 significantly reduce the total power bus resistance from thepower pads14eand14fto the subdecoder20a, the intersection areas24a-24band other circuits, even when the widths of the V_DDand V_SSbuses37aand37bare narrow.
• A first peripheral circuit (not shown) drives electrical signals to the[0054]first signal bus34 and the column decoder16a(FIG. 1) drives electrical signals to theYS bus35, which is used insen amplifiers22aand22b. Likewise,main address decoder16b(FIG. 1) drives electrical signals to thesecond DXB bus44, in a conventional manner. Thefirst signal bus34 electrically connects with thesecond signal bus37cand thethird signal bus42 thereby creating asignal mesh58 across thesubarray18aand the subdecoder20a. Likewise, thefirst DXB bus36 electrically connects with thesecond DXB bus44 thereby creating asubdecoder mesh60 across the subdecoder20a. In this manner, the signal and subdecoder meshes58 and60 are able to connect the sense amplifiers22a-22b, the subdecoder20a, and the intersection areas24a-24bin many different combinations. Although not shown, there are many additional buses constructed in M2 and extending horizontally across the senseamplifier circuit areas22aand22b. Some of these buses are connected to other signal buses, such as theYS bus35.
• Referring to FIG. 4, the V[0055]_DD, V_SS, signal and subdecoder meshes54,56,58 and60 actually represent many vertical and horizontal lines for each mesh, thereby providing more buses for the surrounding circuits, and decreasing the resistance of each mesh. For example, thesubarray18ahas multiple V_DDbuses38a-38drunning in M2 and multiple V_DDbuses30a-30drunning in M3, all tied to the main V_DDbus28 (FIG. 3), thereby decreasing the overall resistance of the V_DDmesh54. Likewise, thesubarray18ahas multiple V_SSbuses40a-40drunning in M2 and multiple V_SSbuses32a-32drunning in M3, all tied to the main V_SSbus26 (FIG. 3), thereby decreasing the overall resistance of the V_SSmesh56.
• In addition to the V[0056]_DD, V_SS, signal and subdecoder meshes54,56,58 and60, other buses run across thesubarray18a. These other buses include multiple column factor (CF) buses61a-61drunning vertically in M3, for inputs to thecolumn decoders16a,16c,16d,16f,16g,16i,16jand16l(FIG. 2), and multiple subdecoder buses (DXB1, DXB3, DXB5, DXB7)44a-44drunning horizontally in M2, for connection to thesubdecoder circuits20aand20b(FIG. 2) and to thefirst DXB bus36. Furthermore, as shown in FIG. 4,power buses30a-30d,32a-32d,38a-38d,40a-40dare located near an outer edge of the subarray18athan the signal buses61a-61d,44a-44d. As a result, resistance of the power buses is reduced, while the resistance for the signal buses, all grouped toward the interior edge of the subarray18a, are relatively consistent with each other, thereby making signal propagation through the signal buses relatively consistent.
• Referring to FIG. 5[0057]a, the electrical connections between the buses shown in FIG. 4 are made at intersection points located above memory cells. An intersection point48adenotes where the V_SSbus32bcrosses the V_SSbus40b. An electrical connection is made between the V_SSbus32band the V_SSbus40busing a through-hole62, located above amemory cell circuit64.
• Referring to FIGS. 5[0058]a-5b, thememory cell circuit64 of the subarray18acomprises a conventional, one capacitor and one transistor type DRAM cell. For example, acapacitor65 is formed between a plate67 and astorage node68. Likewise, atransistor69 is formed with the source and drain connected to thestorage node68 and a bit line (BL1)bus70, respectively, and the gate connected to a first subword line (SW)bus72a, having awidth74. To avoid any coupling noise caused by the power and signal buses, the cell structure of the preferred embodiment is a capacitor on bit line (COB) structure. This structure facilitates the sensitive nature of theBL1 bus70 and enables operation without any detrimental effect by noise from the power and signal meshes54,56 and58 located over the cell, due to the shielding affect of theplate64.
• Although the intersection point[0059]48aappears to be located directly over thememory cell circuit64, this is not required, and is only for the benefit of explanation. Furthermore, the through-hole62 and V_SSbuses32band40bare not necessary formemory cell64 and not all of the power and signal buses will be connected to other buses.
• Referring to FIGS. 4 and 6[0060]a, afirst section76 gives an expanded view of the subarray18a, showing more signal lines located between the buses shown in FIG. 4.Section76 has several signal and power buses of various widths running both vertically and horizontally across it. These buses includeYS buses35a-35d, having awidth80, theCF bus61a, having awidth82, and the V_SSbus32b, having awidth84, running vertically in M3. Likewise, buses86a-86d, having awidth88, theDXB1 bus44a, having awidth90 and the V_SSbus40b, having awidth92, run horizontally in M2. Thesignal buses YS35a-35d,CF61a, MWB86 and DXB144arun directly to their corresponding circuits, and therefore do not require a through-hole on thesubarray18ato change directions. Only the V_SSbuses32band40bhave a through-hole62 to electrically connect them. With this arrangement, the width of each bus,80,82,84,88,90 and92, is optimized for speed and power resistance effect. For example thewidths84 and92 of the V_SSbuses32band40b, thewidth82 of theCF bus61a, and thewidth90 of theDXB1 bus44aare wider than thewidths80 and88 for high speed and low power resistance, and to accommodate the through-hole62. Meanwhile, thewidth80 of theYS buses35 and thewidth88 of the MWB buses86, are made narrower than thewidths82,84,90,92 to conserve metal space.
• Likewise, referring to FIGS. 6[0061]band6c,sections94 and96 are shown, having two and no through-holes, respectively. As a result, two YS buses and one CF bus (or two YS buses and one power bus) are created with every four sense amplifier circuits, while still meeting acceptable M3 width and space requirements. Likewise, two MWB buses and one DXB bus (or two MWB buses and one power bus) are placed with every sixteen sub-word-line SW buses, while still meeting acceptable M2 width and space requirements. In addition, the widths of all the power and signal buses may be optimized to accommodate the multiple buses used by each mesh for reducing effective resistance and for achieving high speed, keeping the essential advantage of high yield by having the relaxed metal pitch of hierarchical word-line configuration.
• Referring again to FIG. 3, in addition to the power and signal meshes[0062]54,56, and58 being constructed over the subarray18a, they are partially constructed over the subdecoder20a, along with thesubdecoder mesh60. Other circuits are modified to accommodate the metal space needed by the power and signal meshes54,56,58 and60,. The modified circuits are included in the sense amplifiers, the subdecoders and the intersection areas, as described below.
• FIGS. 7[0063]aand7billustrate thesubarray18acomprising 32 representative memory cells including thememory cell64 of FIGS. 5a-b. Furthermore, thesubarray18ais shown in relation to theintersection area24a, the subdecoder20a, and thesense amplifier22aof FIG. 2.
• In the preferred embodiment, the[0064]sense amplifier22aincludes128 sense amplifier circuits, such assense amplifier circuits98aand98b. Both of the sense amplifier circuits98a-98bare connected to asense amplifier driver100a, which is located in theintersection area24a. Thesense amplifier cit98ais connected to a column ofmemory cells102a, through the BL1 bus70 (FIG. 5a) and a bit line (BL1B)bus104a, which are both constructed in M1, and run vertically across thearray18a. Likewise, thesense amplifier circuit98bis connected to a column of memory cells102b, through a bit line (BL2)bus104band a bit line (BL2B)bus104c, which are also constructed in M1, and run vertically across thearray18a. Sense amplifier circuits98a-98bare discussed in greater detail with reference to FIGS. 10a-10b, below.
• In addition to the[0065]sense amplifier driver100a, theintersection area24aincludes a plurality of circuits (excludingsense amplifier driver100aand subdecoder drivers110a-110d) which are referenced generally by the numeral100b. These Fruits100a-100bare designed to employ the advantages of the low resistance of the V_DD, V_SSand signal meshes54,56 and58, as supplied by the buses37a-37c.
• The[0066]subdecoder20aincludes 256 subdecoder circuits, represented generally be subdecoder flit106a-106d. Thesubdecoder circuit106aillustrates a hierarchical word line structure utilized in each of the remaining subdecoder circuits. Thesubdecoder circuit106ais connected to theDXB7 bus44dand theMWB bus86a, which is routed to the four subdecoder circuits106a-106dthrough aconnector bus108, constructed in M1. Thesubdecoder circuit106ais also connected to afirst subdecoder driver110a, located in theintersection area24a, along with the sense amplifier driver100. Likewisesubdecoder circuits106b-106dare connected to subdecoderdrivers110b-110d, located in the intersection areas. Thesubdecoder20ais discussed with more detail below.
• Referring to FIG. 8, two subdecoder drivers[0067]110a-110dare located inintersection area24a, while the other twosubdecoder drivers110b-110care located in theintersection area24b. Thesubdecoder driver110acomprises an inverter, which converts theDXB7 bus44d, to an inverted subdecoder (DX7)bus114d. Likewise, thesubdecoder drivers110b-dconvert the DXB144a,DXB344bandDXB544cto invertedsubdecoder buses DX1114a, DX3114band DX5114c. In the preferred embodiment, each of the subdecoder drivers110a-110ddrive64 subdecoder circuits, thereby driving all 256 of the subdecoder20a. Being located in the intersection areas24a-24b, the subdecoder drivers110a-110dare made of significant size, and are supplied an internally generated boosted voltage (V_PP) so that thebuses DX1114a, DX3114b, DX5114candDX7114dcan be driven to V_PP.
• The[0068]subdecoder circuits106aet seq. employ a hierarchical word line structure. As discussed earlier, the subdecoder circuits formed in thesubdecoder area20aand20bare used to select certain memory cells in thesubarray18a. This is accomplished by utilizing a plurality of subword lines, such as theline72a, constructed in the polysilicon (FG) layer (FIG. 5a). TheMWB bus86adrives four subdecoder circuits106a-106dof subdecoder are20a, which each drive a SW bus72a-72d, extending into thesubarray18a. Likewise, theMWB bus86adrives four additional subdecoder circuits106e-106hof subdecoderarea20b, which each drive a SW bus72e-72h, extending into thesubarray18a.
• Referring to FIGS. 9[0069]a-9b, aconventional subdecoder circuit116 and analternative subdecoder circuit118 implement a hierarchical word line structure. The structures are hierarchical due to the placement of main word line buses, constructed in M2, over a subword line buses, constructed in FG. However, thesubdecoder circuits116,118 do not facilitate the meshed system of the present invention.
• Referring to FIG. 9[0070]a, theconventional subdecoder circuit116, as used in the Noda hierarchical word line structure scheme, consists of three n-type metal oxide semiconductor (NMOS) transistors and produces an SW output. However, thesubdecoder circuit116 requires a non-inverted word line (MW) bus, which must also run across the array (not shown) along with a MWB bus. This effectively doubles the number of main word lines running in M2 across the array. As a result, two main word lines are used to drive eight subword lines, thereby creating a pitch of 4 subword lines to every main word line. This pitch, however, does not allow the extra metal space needed for the meshed system of the present invention.
• Referring to FIG. 9[0071]b, thesubdecoder circuit118 consists of two NMOS transistors and two p-type metal oxide semiconductor (PMOS) transistors. The subdecoder driver does not require a non-inverted word line bus (MW) as in FIG. 9a. As a result, one main word line is used to drive eight subword lines, thereby creating a pitch of 8 subword lines to every main word line. But, since the subdecoder circuit consists of four transistors, it thereby consumes a lot of space, and to speed the circuit up, some of the transistors must be made very large.
• Referring to FIG. 9[0072]c, thesubdecoder circuit106aof the preferred embodiment comprises the advantages of the above two subdecoder drivers. Thesubdecoder circuit106auses theMWB bus86a, theDXB7 bus44d, and theDX7 bus114dto produce the subwordline SW bus72a, thereby allowing the subdecoder cut106ato be constructed with only three transistors120a-120c. Since theDX7 bus114druns only in the subdecoder20a, and does not have to run horizontally across the array, the main word line pitch across thesubarray18aremains at eight subword lines for every main word line. As a result, there is sufficient metal space for the power, signal and subdecoder meshes54,56,58 and60, and the DXB bus44 (FIG. 3) of the present invention.
• In operation, the signals on the[0073]MWB bus86aandDXB7 bus44d, designated as MWB and DXB7, are negative logic signals, i.e. they are high in the standby mode, low in an enable mode. When the signals MWB and DXB7 are both low, an output signal on the subwordline SW bus72ais driven to a selective high level. When only one of the signals MWB or DXB7 is high, the output signal on the subwordline SW bus72ais driven to a non-selective low level. In the standby or precharge mode, i.e., when all of the MWB and DXB signals are high, all subword lines SW are set to low.
• An advantage of the[0074]subdecoder circuit106ais that a subthreshold current in the row decoders and DXB drivers is primarily determined byNMOS transistors120a,120b. As a result, a low standby current is achieved during standby or precharge mode. This is because a gate with for theNMOS transistors120a,120bcan be narrower than that of PMOS transistors, and NMOS transistor cutoff-transition characteristics are sharper than that of PMOS transistors.
• Other advantages of the[0075]subdecoder circuit106aare that thesubdecoder circuit106aprovides eta metal space for the power, signal and subdecoder meshes54,56,58 and60, and thesubdecoder circuit106aimproves in speed performance. The speed of thesubdecoder circuit106ais directly proportional to the ability of theDX7 bus114dto a transition from low to high. Since theDX7 bus114ais driven by thesubdecoder driver110a, and since the subdecoder driver is located in thenon-crowded intersection area24a, it can be made of sufficient size. Furthermore, theDX7 bus114ais constructed in M3, which has the lowest resistance of the three metal layers. Thus, theDX7 bus114aproduces a sharp rising wave form, thereby achieving high speed activation of theSW bus72a. In the preferred embodiment, a gate width (not shown) of theNMOS transistor120bof is narrower than that of a gate width (also not shown) of theNMOS transistor120a, thereby improving speed and layout area optimization. For example, in the preferred embodiment, the gate widths oftransistors120aand102bare 2.2 microns and 1 micron, respectively. The narrow gate width oftransistor120bcontributes to smaller load capacitance and faster fall times for signals on theDXB bus44d. As a result, theDX bus114dachieves faster rise times. In addition, the gate width of120ais set to the sufficient value for falling speed of the subword line SW.
• Referring to FIG. 10[0076]a, thesense amplifier circuit98acomprises alatch section122aand anequalizer section124a. Thelatch section122acomprises two NMOS transistors126a-126b, connected between thebit line buses70 and104aand afirst latch bus128. Thelatch section122aalso comprises two PMOS transistors130a-130bconnected between thebit line buses70 and104aand asecond latch bus132. All fourtransistors126a,126b,130a,130bare cross-coupled in a conventional latching manner for storing signs from thebitline buses70 and104a.
• The[0077]equalizer section124aincludes three NMOS transistors134a-134cfor equaling theBL1 bus70 and theBL1B bus104aduring the standby or pre-charge modes. The three transistors134a-134care controlled by an equalization bus136.
• In a similar manner, the[0078]sense amplifier circuit98bcomprises alatch section122band anequalizer section124bconnected to thebit line buses104b-104c. Thelatch section122band theequalizer section124bare also connected to the twolatch buses128,132 and the equalization bus136, respectively.
• Referring to FIG. 10[0079]b, a further reduction in the size of thesense amplifier22ais achieved by other layout improvements. Theequalizer sections124aand124bare constructed in shapes of alternating “T's” as discussed in greater detail below with reference to FIG. 11a. Thelatch sections122aand122bare constructed utilizing “H” shaped moat regions, as discussed in greater detail below with reference to FIG. 12a-b.
• Referring to FIGS. 11[0080]a-11b, to reduce the size constraints of theequalizer section124acaused by the transistors134a-134c, a T-shapedgate region138a(FIG. 11a) is utilized. The equalizer signal bus136 creates a gate for each of the transistors134a-134c. in a similar manner, theequalizer section124butilizes an inverted T-shapedgate region138b. As a result, thegate regions138a,138bcan be compacted together, while still maintaining a requiredmoat isolation distance137 between thegate regions138a,138b. In so doing, awidth140 of the two gate regions is smaller than aconventional width142 of twosquare gate regions144aand144b, as shown in FIG. 11b, and a smallsense amplifier circuit22acorresponds to the small memory cell circuit64 (FIG. 5a).
• Referring to FIG. 12[0081]a, thesense amplifier22aalso comprises an H-shapedmoat146. TheBL1 bus70, constructed in M1, must cross theBL1B bus104a, also constructed in M1, at the H-shapedmoat146 without electrically intersecting. Furthermore, theBL1 bus70 must drive atransistor gate148aand theBL1B bus104amust drive atransistor gate148b. At acrossing point150, theBL1B bus104ais connected to thetransistor gate148b, constructed in ich runs under the metal layers. Thegate148bnot only serves to allowBL1B bus104ato cross theBL1 bus70, but it is the gate for thetransistor130b. After crossing theBL1 bus70, thegate148bis reconnected to a connectingbus152, also constructed in M1, thereby electrically connecting theBL1B bus104ato the connectingbus152. Similarly, theBL2 bus104band theBL2B104cbus also cross in the H-shapedmoat146.
• Referring to FIG. 12[0082]b, these connections create an M1 to FG to M1 change and construct the two PMOS transistors130a-130b. Not only does this change provide a size reduction, it without using an additional metal layer.
• Furthermore, the H-shaped[0083]moat146 solves another problem associated with the meshed system, that is, noise on thebit line buses70 and104a-104c. Noise at the sense amplifiers22a-22cis often caused by signal buses constructed in M3 overlapping thebit line buses70 and104a-cconstructed in M1. Since thebit line buses70 and104ado a crossing pattern, any noise or capacitive coupling induced from signal buses constructed in M3, such as the CF bus or the YS bus, will be the same for both theBL1 bus70 and theBL1B bus104a, thereby effectively canceling the effect of noise. Likewise, any noise will be the same for theBL2 bus104band theBL2B bus104c.
• Referring to FIG. 13[0084]a, addition noise protection from signal buses constructed in M3 overlapping thebit line buses70 and104a-cconstructed in M1 can be reduced through M2 shielding. For example, in conventional prior art designs having first and second buses154a-154bconstructed in M1 and running in a vertical direction, and having athird bus154cconstructed in M3 which also running in a vertical direction, noise is aggravated. Noise is induced from thethird bus154cto the first andsecond buses154aand154b, since they overlap and run in the same direction, allowing the noise to be strengthened by the large area of overlap. This conventional design can be a problem, especially when thebuses154a,154bare particularly sensitive to noise, such as thebit line buses70 and104aof the present invention. Furthermore, in the conventional design, a group of other buses156a-156dconstructed in M2 and running in a horizontal direction have little to no shielding effect, as shown.
• Referring to FIGS. 13[0085]b-13c, the preferred embodiment reduces the noise between buses running in the same direction by improving the shielding effect of the M2 buses. In the preferred embodiment, theBL1 bus70 and theBL1B bus104aare constructed in M1 and run in the vertical direction. Furthermore, theCF bus61ais constructed in M3 and runs in the vertical direction, just above the twobit line buses70 and104a. Located between theCF bus61aand thebit line buses70 and104aare four buses158a-158dconstructed in M2 and running in the horizontal directions.
• Referring to FIG. 13[0086]b, one technique for reducing noise is used in a situation where theM2 buses158aand158dare noisy, active lines, such as parts of the sense amplifiers, and theM2 buses158b-care inactive, quiet buses, such as a power supply bus, a first technique is used. Instead of having some of the M2 buses158a-158donly extending across one of thebit line buses70 and104a, as shown in FIG. 13a, theMS buses158b-158cnow extend over both bit line buses. In this manner, the M2 buses158a-158dprovide more of a shielding affect from any noise from theCF bus61a.
• Referring to FIG. 13[0087]c, in a situation where two of theM2 buses158aand158dare inactive, quiet buses, such as a power supply bus, and the other two of theM2 buses158b,158care active, noisy buses, a second technique is used. In this case, thebit line buses70 and104aare better shielded from the noise of theCF bus61aby thequiet M2 buses158a,158d. Therefore, thequiet M2 buses158a,158dare drawn as large as possible, thereby maximizing their shielding affect.
• Referring to FIG. 14[0088]a, the well structure of the sense amplifier can also be size determinative, especially in a situation like the preferred invention where power and signal meshes are utilized. In a first design, atriple well structure160 comprising a p well (PW)162a, a deep well (DW)164aand a p-substrate (P-sub)166 is used for noise protection from asense amplifier circuit170 to a subarray168a. Likewise, thetriple well structure160 comprises a p well (PW)162b, a deep n-type well (DW)164band the P-Sub166 for noise protection from asense amplifier circuit170 to asubarray168b. Although thewells162a,162b,164a,164bandsubstrate166 may have various bias arrangements, one such arrangement provides:

  	TABLE 1
  	Well	Bias Name	Bias Voltage

  	PW overDW	VBBA	167a	−1	V
  	NW overDW	VPP	167b	4.0	V
  	DW	VPP
  167b	4.0	V
  	P-Sub	VBB	167c	0	V
  	PW (not over DW)	VBB 167c	0	V
  	NW (not over DW)	VDD 167d	3.3	V

• It is noted that well biasing is well known in the art, and any descriptions of bias voltage are merely illustrative, and should not be limited to such in any manner.[0089]
• The[0090]subarrays168aand168bare isolated from the noisy effects of thesense amplifiers170 by two isolation n wells (NWs)172aand172b, respectively. TheNWs172a,172bcreate separation transistors for sharing one sense amplifier between memory cell arrays located on either side. A negative bias voltage that is suitable for device isolation is supplied to the P-well162sand162b, where the above described separation transistors and the memory cell transistors are both located. TheNWs172a,172bare biased toV_PP167bfor electrical isolation. Furthermore, the NW's172a,172bare located above theDWs164a,164b, respectively, and thereby bias the Dws to V_PP. Thesense amplifier circuit170 has anadditional NW174, which is biased toV_DD167dto provide faster operation of a p-type transistor176. The advantage forDWs164a,164bbeing biased to V_PPis that the subdecoders are CMOS circuits operating at the V_PPvoltage level (FIGS. 7a,7b,14c). On the other hand, because PMOS transistors of thesense amplifier circuit170 operate at or below the V_DDvoltage level, the V_DDvoltage level is suitable as a bias voltage for theNW174, instead of the V_PPvoltage level. Thesense amplifier170 also has twoPWs178a,178b, biased toV_BB167cthrough the P-sub166. ThePW178asupports atransistor180aand thePW178bsupportstransistors180b,180c.
• Referring to FIG. 14[0091]b, the preferred embodiment is able to shrink the well structure of thesense amplifier24b, as compared to FIG. 14a. The preferred embodiment utilizes atriple well structure182 comprising aPW184a, aDW186a, and a P-Sub188, forsubarray18a, and aPW184b, aDW186b, and the P-Sub188, forsubarray18b. The subarrays18a-18bare thereby protected from thesense amplifier circuit22b. Thetriple well structure182 also uses well-biasing similar to the illustrative biases described in Table 1. It is noted, however, that well biasing is well known in the art, and any descriptions of bias voltage are merely illustrative, and should not be limited to such in any manner.
• The subarrays[0092]18a-18bare isolated from the noisy effects of thesense amplifiers24bby twoisolation NWs190a,190b, respectively. Theisolation NWs190a,190bare biased toV_PP167bfor isolation. Furthermore, theisolation NWs190a,190bare located above the DWs186a-186b, respectively, and thereby bias the DWs. The preferred embodiment differs from the conventional system of FIG. 14ain that theisolation NW190aalso supports the transistor130d, which corresponds with thetransistor176 of FIG. 14a. As a result, the transistor130dwill operate slower than thetransistor176 of FIG. 14a. However, the speed of the transistor130dis not critical to the overall timing of the sense amplifier circuit90a. Therefore, although the PMOS transistor130dis using a V_PPbiased well there is no overall speed degradation.
• There is a size advantage, however, to the[0093]isolation NW190aover the conventional technique described in FIG. 14a. Instead of having theNW172afor the sole purpose of isolation, and thesecond NW174 for the transistor176 (FIG. 14a), the two are combined in theNW190aof the preferred embodiment, thereby shrinking the space of thesense amplifier24b. Furthermore, asingle PW192 can be used to support thetransistors134a-134c.
• Referring to FIG. 14[0094]c, a triple well structure193 is implemented for the subdecoder20a. The P-Sub188 and theDW186aextend throughout the subarray18a(FIG. 14b), across the subdecoder20a, and into asubarray196. ThePW184ais separated from aPW198 by anNW200, which is biased toV_PP167bfor isolation. By biasing theNW200 atV_PP167b, theSW bus72acan operate at V_PP.
• Referring to FIGS. 15[0095]aand15b, thesense amplifier22aincludes four fuses202a-202dused for a column redundancy scheme. The two fuses202band202dare used to disable sense amplifier circuits98a-98b, and the twofuses202aand202care used to disable sense amplifier circuits204a-204b. Column redundancy is well known to those skilled in the art; however, conventional designs result in a dramatic area penalty in the sense amplifier design due to the fuse placement. Accordingly, in the preferred embodiment, the fuses202a-202dare lined in parallel with thebit line buses70 and104a, even for the fuses corresponding to sense amplifiers located in a different area. In this way, the vertical runningCF bus61aand theYS buses35c-35dneed to be offset for only one group of fuses, thereby providing the maximum space for the power and signal meshes54,56,58 and60.
• Although the illustrative embodiment of the present invention has been shown and described, a latitude of modification, change and substitution is intended in the foregoing disclosure, and in certain instances, some features of the invention will be employed without a corresponding use of other features. For example, the horizontal and vertical directions were included to make the preferred embodiment simpler to describe, but are not intended to limit the present invention. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.[0096]

Claims (67)

What is claimed is:

1. A semiconductor memory device comprising:

a semiconductor substrate having a main surface;

a memory array portion in said main surface, in which a plurality of memory cells are arranged in row direction and in column direction;

bit lines each extending in said column direction and each of said bit lines connected to said memory cells;

word lines each extending in said row direction and each of said word lines connected to said memory cells;

a first peripheral circuit portion having a plurality of MOSFETs and said first peripheral circuit arranged adjacent to said memory array portion;

an external terminal formed on said main surface of said semiconductor substrate, and a predetermined voltage is supplied to said external terminal from outside of said semiconductor memory device;

a plurality of first voltage supply lines each extending in said column direction and formed over said bit lines and word lines;

a plurality of second voltage supply lines each extending in said row direction and formed over said bit lines and word lines, and said second voltage supply lines formed by a conductive layer which is different from that of said first voltage lines,

wherein said first and second voltage supply lines are connected each other at the intersection of said first and second voltage supply lines,

wherein one of said first and second voltage supply lines is connected to said external terminal, and

wherein said predetermined voltage is supplied to said MOSFETs in said first peripheral circuit portion from said external terminal via said first and second voltage supply lines.

2. A semiconductor memory device according toclaim 1,

wherein said first voltage supply lines are comprised of a first conductive layer and said second voltage supply lines are comprised of a second conductive layer, and said first conductive layer is over said second conductive layer and said first conductive layer has a predetermined thickness which is thicker than that of said second conductive layer.

3. A semiconductor memory device according toclaim 1, further comprising:

a second peripheral circuit portion having a plurality of MOSFETs, said second peripheral circuit portion being adjacent to said memory array region in said row direction and being adjacent to said first peripheral circuit portion in said column direction; and

a third voltage supply line formed in said first peripheral circuit portion and extending in parallel with said bit lines and into said second peripheral circuit portion,

wherein said second voltage supply lines extend into said second peripheral circuit portion and connected to said third voltage supply line at the intersections between said second voltage supply lines and third voltage supply line.

4. A semiconductor memory device according toclaim 3, wherein said third voltage supply line is comprised of said first conductive layer and said third voltage supply line is connected to said MOSFETs in said first peripheral circuit portion.

5. A semiconductor memory device according toclaim 4, wherein said first voltage supply lines each has a predetermined width which is larger than that of said third voltage supply line.

6. A semiconductor memory device according toclaim 5, further comprising:

an insulating layer formed between said first conductive layer and said second conductive layer, said insulating layer has a first through hole through which said first and second voltage supply lines are connected and a second through hole through which said second and third voltage supply lines are connected; wherein said first through hole has a predetermined diameter which is larger than that of said second through hole.

7. A semiconductor memory device according toclaim 6, wherein said memory cell is comprised of a MOSFET and a capacitor element connected in series, and said capacitor element is formed over said MOSFET.

8. A semiconductor memory device according toclaim 4, further comprising:

a sense amplifier circuit portion being adjacent to said memory array portion in said column direction and being adjacent to said first peripheral circuit portion in said row direction, wherein said MOSFETs in said first peripheral circuit portion constitute sense amplifier driver circuit.

9. A semiconductor memory device according toclaim 8, wherein a plurality of signal wirings extending in row direction in said sense amplifier circuit portion, said signal wirings are comprised of said second conductive layer.

10. A semiconductor memory device according toclaim 4, wherein sub-decoder circuit is formed in said second peripheral circuit portion, and said sub-decoder circuit has two input terminals and an output terminal, a main word line and sub-decoder control line are connected to said input terminals and said word line is connected to said output terminal.

11. A semiconductor memory device according toclaim 10, wherein said main word line and said sub-decoder control signal are comprised of said second conductive layer.

12. A semiconductor memory device according toclaim 11, wherein said second voltage supply line has a predetermined width which is larger than that of said main word line.

13. A semiconductor memory device according toclaim 11, further comprising:

a fourth voltage supply line formed in said memory array portion and comprised of said second conductive layer, and said subdecoder control line extending in said row direction arranged in the center of said memory array portion and said fourth voltage supply line extending in said row direction, and said second and fourth voltage supply lines are arranged at the both sides of said sub-decoder control line.

14. A semiconductor memory device according toclaim 13, wherein said fourth voltage supply line is connected to said first voltage supply line at the intersection of said fourth and first voltage supply lines.

15. A semiconductor memory device according toclaim 1, further comprising:

row select lines formed in said memory array portion and comprised of said first conductive layer;

row decoder circuit selecting a predetermined row select line into row select lines, wherein said first voltage supply line has a predetermined width which is larger than that of said row select line.

16. A semiconductor memory device according toclaim 15, further comprising:

signal lines which is different from said row select line, extending in said column direction in said memory array portion, said signal lines comprised of said first conductive layer.

17. A semiconductor memory device according toclaim 16, further comprising:

a fifth voltage supply line comprised of said first conductive layer and being extending in said column direction.

18. A semiconductor memory device according toclaim 17, wherein said signal lines extend at the center of said memory array portion in said column direction, and said first and fifth voltage supply lines are arranged at the both sides of said signal lines.

19. A semiconductor memory device, comprising:

a semiconductor substrate;

a subarray portion including a plurality of memory cells each being arranged at the intersection of bit line extending in a column direction and word line extending in a row direction;

a fit peripheral circuit portion being adjacent to said sub-array in said row direction;

a second peripheral circuit portion being adjacent to said sub-array in said row direction;

a third peripheral circuit portion at the intersection of said first and second peripheral circuit portions;

a plurality of first voltage supply lines each extending in said column direction and formed over said bit lines and word lines;

a plurality of second voltage supply lines each extending in said row direction and formed over said bit lines and word lines, and said second voltage supply lines formed by a conductive layer which is different from that of said first voltage lines, and said second voltage lines formed over said sub-array portion and said second peripheral circuit portion;

a third voltage supply line comprised of said first conductive layer and extending over said second and third peripheral circuit portion,

wherein said first and second voltage supply lines are connected each other at the intersection of said first and second voltage supply lines over said sub-array portion,

wherein said second and third voltage supply lines are connected each other at the intersection of said second and third voltage supply lines over said second peripheral circuit portion, and

wherein said first and second voltage supply lines each has predetermined width which is larger than that of said third voltage supply line.

20. A semiconductor memory device according toclaim 19, wherein a plurality of MOSFETs are arranged in said third peripheral circuit portion, and said MOSFETs are connected to said third voltage supply line.

21. A semiconductor memory device according toclaim 20, further comprising:

a plurality of signal wiring lines extending in said row direction and comprised of said second conductive layer.

22. A semiconductor memory device according toclaim 21, further comprising:

an insulating film formed between said first and second conductive layers, said insulating layer has a first through hole through which said first and second voltage supply lines are connected and a second through hole through which said second and third voltage supply lines are connected, wherein said first through hole has a predetermined diameter which is larger than that of said second through hole.

23. A semiconductor memory device according toclaim 6, wherein said memory cell is comprised of a MOSFET and a capacitor element connected in series, and said capacitor element is formed over said MOSFET.

24. A semiconductor memory device according toclaim 21, wherein said first conductive layer is over said second conductive layer and said first conductive layer has a predetermined thickness which is thicker than that of said second conductive layer.

25. A semiconductor memory device according toclaim 19, wherein sub-decoder circuit is formed n said second peripheral circuit portion, and said sub-decoder circuit has two input terminals and an output terminal, a word line and sub-decoder control line are connected to said input terminals and said word line is connected to said output terminal.

26. A semiconductor memory device according toclaim 25, wherein said main word line and said sub-decoder control signal are comprised of said second conductive layer, and said second voltage supply line has a predetermined width which is larger than that of said main word line.

27. A semiconductor memory device according toclaim 26, wherein said sub-decoder control line extending in said row direction arranged in the center of said sub-array portion and said second voltage supply lines are arranged at the both sides of said of said sub-decoder control line.

28. A semiconductor memory device including a plurality of memory cells formed on a semiconductor substrate, complementary first and second bit lines to which said memory cells are connected, a first and second MOSFET connected in series between said first and second bit lines and third MOSFET connected between said first and second bit lines, comprising:

an active region formed on the main surface of said semiconductor substrate, in order to form said first, second and third MOSFETs;

a first, a second and a third semiconductor region formed in said active region;

an insulating film formed between said first, second and third semiconductor region and said first and second bit lines, said insulating film having a first through hole for connecting said first semiconductor region to said first bit line, a second through hole for connecting said second semiconductor region to said second bit line and a third through hole formed over said third semiconductor region; and

a gate electrode arranged between said first and second semiconductor regions, between second and third semiconductor regions and between said third and first semiconductor regions,

wherein said first, second and third through holes constitute a triangle, and the triangle corresponding complementary bit lines and the triangle corresponding adjacent complementary bit lines are mirror symmetrical relationship.

29. A semiconductor memory device according toclaim 28, wherein said active region has T-shape configuration.

30. A semiconductor memory device according toclaim 29, wherein said gate electrode has T-shape configuration.

31. A semiconductor memory device according toclaim 30, wherein a predetermined fixed voltage is supplied to said third semiconductor region.

32. A semiconductor memory device, comprising:

a first MOSFET and a second MOSFET which constitute a sense amplifier circuit, said first and second MOSFETs each having a first semiconductor region and a second semiconductor region as source and drain;

a first memory array portion and a second memory array portion at both sides of said first and second MOSFETs;

complementary a first and a second bit lines extending in said first memory array portion, and complementary a third and a fourth bit lines extending in said second memory array portion,

wherein said first, second, third and fourth bit lines are comprised of a conductive layer,

wherein said first bit line is connected to said first semiconductor region, and is connected to said third bit line via said gate electrode of said second MOSFET,

wherein said second bit line is connected to said gate electrode of said first MOSFET and said first semiconductor region of said second MOSFET, and said second bit line is integral with said fourth bit line.

33. A semiconductor memory device comprising:

a memory array having a main word line, first and second subword lines corresponding to said main word line, a plurality of data lines and a plurality of memory cells;

a first subdecoder having an output terminal coupled to said first subword line and a first input terminal coupled to said main word line;

a second subdecoder having an output terminal coupled to said second subword line and a first input terminal coupled to said main word line;

a first driver, coupled to a second input terminal of said first subdecoder, outputting selection level voltage to be supplied to said first subword line; and

a second driver, coupled to a second input terminal of said second subdecoder, outputting selection level voltage to be supplied to said second subword line,

wherein said memory array is formed in a first area,

wherein said first and second subdecoders are formed in a second area which is adjacent to said first area, and

wherein said first and second drivers are formed in a third area which is adjacent to said second area.

34. A semiconductor memory device according toclaim 33, further comprising:

a plurality of sense amplifiers coupled to said plurality of data lines,

wherein said plurality of sense amplifiers are formed in a fourth area which is adjacent to said first and third areas.

35. A semiconductor memory device according toclaim 34,

wherein said first and second, third and fourth areas are quadrilateral areas, and

wherein said third area is an intersection area which is indicated by extending said second and fourth areas.

36. A semiconductor memory device according toclaim 35, further comprising,

a first line for delivering a first selection signal to be supplied to an input terminal of said first driver; and

a second line for delivering a second selection signal to be supplied to an input terminal of said second driver,

wherein first and second lines, said main word line and said first and second subword lines are extended to the same direction in said first area.

37. A semiconductor memory device according toclaim 36,

wherein each of said first and second subdecoders has (a) a first MOSFET having a gate coupled to said first input terminal and a source-drain path provided between said second input terminal and said output terminal, (b) a second MOSFET having a gate coupled to said first input terminal and a source-drain path provided between said output terminal and a ground potential and (c) a third MOSFET having a source-drain path coupled to said source-drain path of said second MOSFET in parallel.

38. A semiconductor memory device according toclaim 37,

wherein said first and second drivers are invertor circuits.

39. A semiconductor memory device according toclaim 37,

wherein said first MOSFET is an p-type, and

wherein said second and third MOSFETs are n-type.

40. A semiconductor memory device according toclaim 39, wherein a gate width of said third MOSFET is narrower than that of said second MOSFET.

41. A semiconductor memory device according toclaim 40,

wherein a voltage level of a selected subword line is higher than a high level voltage of said data lines.

42. A semiconductor memory device comprising:

a memory array having a main word line, a plurality of subword lines corresponding to said main word line, a plurality of data lines and a plurality of memory cells each of which is arranged to correspond to an intersection of one of said data lines and one of said subword lines;

a plurality of subdecoder circuits each of which includes (a) p-type first MOSFET having a drain coupled to corresponding one of said subword lines and a gate coupled to said main word line, (b) an n-type second MOSFET having a source receiving a ground potential, a drain coupled to said drain of said first MOSFET and a gate coupled to said main word line and (c) a third MOSFET having a source-drain path coupled between said drain and source of said second MOSFET;

a plurality of signal lines each of which is coupled to a gate of corresponding said third MOSFET, wherein one of said signal lines is set to a selection level; and

a plurality of drivers each of which has an input terminal coupled to corresponding one of said signal lines and an output terminal coupled to a source of corresponding said first MOSFET,

wherein said memo array is formed in a first quadrilateral region,

wherein said decoder circuits are formed in a second quadrilateral region which is adjacent to said first quadrilateral region, and

wherein said drivers are formed in a third quadrilateral region which is adjacent to said second quadrilateral region.

43. A semiconductor memory deice according toclaim 42,

wherein said third MOSFET is an n-type,

wherein said selection level is low level, and

wherein said drive circuits are invertor circuits.

44. A semiconductor memory device according toclaim 43,

wherein a voltage level of a selected subword line is higher than a high level voltage of said data lines.

45. A semiconductor memory device according toclaim 44, further comprising:

a plurality of sense amplifiers coupled to said data lines,

wherein said sense amplifiers are formed in a fourth quadrilateral region which is adjacent to said first and third quadrilateral regions.

46. A semiconductor memory device according toclaim 45,

wherein a gate width of said third MOSFET is narrower than that of said second MOSFET.

47. A semiconductor device comprising:

an array of electronic circuits;

an electrical port located outside said array;

a first conductor electrically connected to said electrical port and disposed over said array;

a second conductor disposed over said array, wherein said second conductor crosses said first conductor at a cross point in said array;

a peripheral circuit located outside of said array, wherein said peripheral circuit is electrically connected to said second conductor, and;

means for electrically connecting said first and second conductors at said cross point,

wherein said peripheral circuit is electrically connected to said electrical port via said first and second conductor.

48. The apparatus ofclaim 47 further comprising:

a third conductor disposed outside of said array, wherein said third conductor crosses said second conductor at a second cross point outside of said array and,

means for electrically connecting said second and third conductors at said second cross point,

wherein said peripheral circuit is electrically connected to said second conductor via said third conductor.

49. The apparatus ofclaim 47 wherein said second conductor is formed in a separate layer from said first conductor.

50. The apparatus ofclaim 48 wherein said second conductor is formed in a separate layer from said third conductor.

51. The apparatus ofclaim 47 wherein said array is a memory array and said electronic circuits are memory cells.

52. The apparatus ofclaim 47 wherein said peripheral circuit is a sense amplifier driver.

53. The apparatus ofclaim 47 wherein said means for electrically connecting comprises a through-hole.

54. The apparatus ofclaim 47 wherein said electrical port is a power pad, said first and second conductors are power buses.

55. The apparatus ofclaim 52 further comprising:

a first signal bus disposed over said array;

a second signal bus disposed over said array, wherein said second signal bus crosses said first signal bus at a second cross point in said array; and

means for electrically connecting said first and second signal buses at said second cross point.

56. The apparatus ofclaim 51 wherein each of said memory cells comprises:

a memory storage circuit;

a subword line; and

a main word line;

wherein said main word line is arranged in a hierarchical structure with said subword line.

57. The apparatus of claims56 further comprising a subdecoder circuit comprising three transistors.

58. The apparatus ofclaim 57 wherein said subdecoder circuit is connected to said peripheral circuit.

59. A method for supplying power and signals on an array-type semiconductor device comprising:

supplying power to a power source located outside said array;

forming a first power bus connected to said power source and disposed over said array;

forming a second power bus over said array, such that said second power bus crosses said first power bus at a cross point in said array;

electrically connecting a peripheral circuit located outside of said array to said second power bus; and

electrically connecting said first and second power buses at said cross point.

60. The method ofclaim 59 further comprising:

forming a third power bus outside said array such that said third power bus crosses said second power bus at a second cross point outside said array,

electrically connecting said third power bus to said second power bus outside said array; and

electrically connecting said peripheral circuit to said second power bus via said third power bus.

61. The method ofclaim 59 wherein said first power bus is formed in a third metal layer and said second power bus is formed in a second metal layer.

62. The apparatus ofclaim 59 wherein said first power bus is formed in a separate layer from said second power bus.

63. The method ofclaim 59 wherein said array is a memory array.

64. The method ofclaim 63 wherein said peripheral circuit is a sense amplifier driver.

65. The method ofclaim 59 wherein said electrically connecting said first and second power buses is accomplished using a through-hole.

66. The method ofclaim 59 further comprising:

forming a first signal bus over said array;

forming a second signal bus over said array, such that said second power bus crosses said first signal bus at a second cross point in said array; and

electrically connecting said first and second signal buses at said second cross point.

67. The method ofclaim 66 wherein said electrically connecting said first and second signal buses is accomplished using a through-hole.

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