US20010053573A1 - Semiconductor device manufacturing method for preventing electrical shorts between lower and upper interconnection layers - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided which suppresses migration of lower interconnectors formed on a borophosphosilicate glass (BPSG) layer toward upper interconnectors as a result of secondary reflowing of the BPSG layer during subsequent thermal processing, thereby preventing the formation of electrical shorts. The semiconductor device manufacturing method includes: forming a transistor; depositing a first interlevel dielectric film (ILD) to cover the transistor; depositing a BPSG layer as a planarization layer on the first interlevel dielectric film; reflowing the BPSG layer; etching the BPSG layer using Ar ion sputtering until a portion of the film is exposed, thereby planarizing the surfaces of the first ILD and the BPSG layers forming an interconnector on the exposed portion of the first interlevel dielectric film; depositing a second interlevel dielectric film to cover the interconnector and the BPSG layer; and forming metal electrodes on the second interlevel dielectric film, the metal electrodes being in contact with predetermined regions of the transistor.

Description

BACKGROUND OF THE INVENTION
• 1. Field of the Invention[0001]
• The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a semiconductor device in which electrical shorts between lower and upper interconnection layers, caused by the flow of an intermediate borophosphosilicate glass (BPSG) layer, can be reduced or prevented.[0002]
• 2. Description of the Related Art[0003]
• In manufacturing a stacked semiconductor device, planarization of interlevel dielectric films (ILDs) must be performed to ensure a sufficient processing margin for subsequent photolithography and etch steps to provide increased reliability of the resulting semiconductor devices. As the integration density of semiconductor devices continues to increase, even greater interest has been focused on the planarization of ILDs.[0004]
• A typical ILD planarization technique is to use a high-fluidity or reflowable layer such as a borophosphosilicate glass (BPSG) layer. In planarizing ILDs with a BPSG layer, deposition of the BPSG layer is followed by a thermal process for reflowing the BPSG layer.[0005]
• FIG. 1 is a sectional view of a conventional semiconductor device with a BPSG layer as a planarization layer.[0006]
• As shown in FIG. 1, isolation layers[0007]2 are appropriately located in asemiconductor substrate1 to define an active area. A gate electrode4 on agate oxide layer3 is formed in the active area of thesemiconductor substrate1 by conventional processes using a hardmask oxide layer5 as an etching mask. A pair ofspacers7 is then formed on the sidewalls of the hardmask oxide layer5 and the gate electrode4. Source anddrain regions6aand6bare formed at both sides of the gate electrode4 in the active area, to produce the basic transistor structure.
• A first[0008]insulating layer8 is then deposited on thesemiconductor substrate1 such that the transistor is fully covered. ABPSG layer9 provided as a planarization layer is deposited on the firstinsulating layer8 and then flowed at a temperature of 820° C. or more, so that the surface of theBPSG layer9 is planarized. A secondinsulating layer10 is deposited on theplanarized BPSG layer9. This secondinsulating layer10 serves to prevent out diffusion of boron or phosphorous from theBPSG layer9.
• An interconnection layer is formed on a portion of the second[0009]insulating layer10. The interconnection layer is then patterned and etched to form aninterconnector structure11 that is aligned above the gate electrode4. It is preferable that the interconnection layer is formed of polysilicon. The interconnection layer can also comprise other conductors such as tungsten silicide (WSi_x), cobalt silicide (CoSi_x), or titanium silicide (TiSi_x). A thirdinsulating layer12 is deposited on the secondinsulating layer10 such that theinterconnection layer11 is fully covered. The third and secondinsulating layers12 and10, theBPSG layer9, and the first insulatinglayer8 are then etched to formcontact holes13 through which the source anddrain regions6aand6bare exposed. A metal layer is then deposited on the third insulatinglayer12, filling thecontact holes13, and patterned and etched to formmetal electrodes14, which contact the source and drainregions6aand6b.
• In the conventional semiconductor device described above, an electrical short between the[0010]interconnection layer11 and themetal electrodes14 may form as the result of undesirable flowing of the BPSG layer during subsequent thermal processes. In other words, if the initial post-deposition reflow of theBPSG layer9 is not sufficient, a secondary flowing of theBPSG layer9 can occur during thermal processes subsequent to the formation of theinterconnection structure11. As a result, theinterconnection structure11 formed on theBPSG layer9 can migrate or shift closer to one of themetal interconnection layers14, thereby causing an electrical short.
• It is therefore preferable that the initial reflow of the[0011]BPSG layer9 occurs at a high temperature of 820° C. or more to ensure that the flowing of theBPSG layer9 is substantially complete and not likely to subject to secondary flowing during subsequent processes. Unfortunately, when temperatures of 820° C. or more are utilized to reflow theBPSG layer9, the high levels of impurities contained in theBPSG layer9, particularly boron and phosphorous, can diffuse into the gate electrode4. The presence of these dopants in the gate electrode will degrade the electrical characteristics of the resulting semiconductor device, for example, by rendering the transistor threshold voltage unstable or variable.
• To prevent this degradation in the electrical characteristics of the resulting semiconductor devices, the[0012]BPSG layer9 is typically reflowed at a temperature of 820° C. or less even though at this temperature theBPSG layer9 will not fully flow. Accordingly, the incompletely reflowedBPSG layer9 will tend to undergo additional flow during subsequent thermal processes, particularly after the formation of theinterconnection structure11. As a result of this additional flow in theBPSG layer9, theinterconnector11 on theBPSG layer9 will tend to migrate in a direction (alternative directions of movement indicated by arrows) towards ametal electrode14, thereby causing an electrical short between theinterconnector11 and themetal electrodes14. This migration of theinterconnector11 is more prevalent in peripheral areas that have a low pattern density than in cell areas that have a high pattern density.
• The conventional semiconductor device having the configuration described above in which an electrical short occurs between the interconnector and the metal electrodes due to the incomplete reflow of the BPSG layer at the initial manufacturing stage, is undesirable in terms of the reliability and yield of the semiconductor device. In addition, it is known that electrical shorts between the interconnector and the metal electrodes caused by flowing of the BPSG layer, cannot be completely prevented even when the BPSG layer is reflowed at a temperature of 820° C. or more during the initial manufacturing stage.[0013]
• One solution to the creation of electrical short between the interconnector layer and the metal electrodes is the formation of insulating spacers on the sidewalls of contact holes. This method, however, is inefficient in terms of the manufacturing time and cost because it requires the performance of additional process steps to form the insulating spacers.[0014]
SUMMARY OF THE INVENTION
• It is an objective of the present invention to provide a method for forming semiconductor devices in which occurrence of an electrical short between interconnectors and metal electrodes, due to flowing of a BPSG layer, can be prevented or significantly suppressed.[0015]
• The objective of the present invention is achieved by a semiconductor device manufacturing method including: forming a transistor in a semiconductor substrate; depositing a first interlevel dielectric film to cover the transistor on the semiconductor substrate; depositing a BPSG layer as a planarization layer on the first interlevel dielectric film; reflowing the BPSG layer; etching the BPSG layer by using Ar ion sputtering until a portion of the first interlevel dielectric film is exposed, wherein the surfaces of the first interlevel dielectric film including the BPSG layer are planarized; forming an interconnector on the exposed portion of the first interlevel dielectric film; depositing a second interlevel dielectric film to cover the interconnection layer on the first interlevel dielectric film and the BPSG layer; and forming metal electrodes on the second interlevel dielectric film, the metal electrodes extending through the dielectric layers to contact predetermined regions of the transistor.[0016]
BRIEF DESCRIPTION OF THE DRAWINGS
• The above objective and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached figures.[0017]
• FIG. 1 is a sectional view of a semiconductor device manufactured by a conventional method;[0018]
• FIGS. 2A to[0019]2D are sectional views illustrating successive stages of a semiconductor device manufacturing method according to a preferred embodiment of the present invention; and
• FIG. 3 is a sectional view of a semiconductor device manufactured by another preferred embodiment of the semiconductor device manufacturing method according to the present invention.[0020]
DETAILED DESCRIPTION OF THE INVENTION
• The present invention will now be described more fully with reference to the accompanying figures, in which preferred embodiments of a semiconductor device manufacturing method according to the present invention are shown.[0021]
• Referring to FIG. 2,[0022]isolation layers22 are formed at a predetermined region of asemiconductor substrate21 to define an active area. A gate oxide layer, a gate conductive layer, a hard mask oxide layer are deposited on thesemiconductor substrate21 in succession, and then patterned and etched by a known photolithography and etch processes, such that agate electrode24 with agate oxide layer23 are formed in the active area of thesemiconductor substrate21.Spacers27 are formed on the sidewalls of ahard mask layer25 and thegate electrode24. Source anddrain regions26aand26bare formed at both sides of thegate electrode24 in the active area, thereby forming a transistor. The source anddrain regions26aand26bare formed to have a lightly doped drain (LDD) structure by low concentration implanting impurities such as boron or phosphorous into the active area of thesemiconductor substrate21.
• Referring to FIG. 2B, a first interlevel dielectric (ILD)[0023]film28 is deposited on thesemiconductor substrate21 such that the transistor is fully covered. The first ILDfilm28 is preferably a tetraethylorthosilicate (TEOS) film and is deposited to have a thickness of at least 1,200 Å, preferably, 1,200-2,000 Å. If desired, borophosphosilicate glass (BPSG) layer that will act as a planarization layer is then deposited on thefirst ILD film28, and then reflowed at a temperature of 700-820° C., such that the surface of theBPSG layer29 is nearly planarized. A borosilicate glass (BSG) layer, or a phosphosilicate glass (PSG) layer, can be used as the planarization layer instead of the BPSG layer.
• Referring to FIG. 2C, the[0024]BPSG layer29 is etched by sputtering using argon (Ar)ions40 until a portion of thefirst ILD film28 is exposed. As a result, the exposed surface of the first ILDfilm28 and the BPSGlayer29 become substantially planar. The sputtering withAr ions40 is carried out with application of a power of 400 Watts or less at a pressure of not more than 10 torr. In addition, the conditions for the Ar ion sputtering are adjusted to maintain a BPSG-to-TEOS selectivity of at least 2:1. Furthermore, the Ar ion sputtering is carried out such that the borders of the BPSG layer are rounded off by the isotropic etching of theBPSG layer29. The exposed portion of thefirst ILD film28 above thegate electrode24 is also partially etched by the Ar ion sputtering. Preferably, the duration of the Ar ion sputtering is controlled to ensure that thefirst ILD film28 remains at least 1,000 Å thick in the exposed areas.
• Referring to FIG. 2D, an interconnection layer that will serve as a lower interconnection layer is formed on the exposed portion of the[0025]first ILD film28 above thegate electrode24. It is preferable that this interconnection layer comprises a polysilicon layer. The interconnection layer may, however, be formed of a metal-silicide layer or a stacked layer of polysilicon and metal-silicide layers. This interconnection layer is then patterned and etched to form aninterconnector30, positioned abovegate24. Asecond ILD film31 is deposited on thefirst ILD film28 and theBPSG layer29 such that theinterconnector30 is fully covered. It is preferable that thesecond ILD film31 be a TEOS layer. Thesecond ILD film31, theBPSG layer29 and thefirst ILD film28 are then etched to form contact holes32 through which selected portions of the source and drain regions of the transistor are exposed. A metal layer (not shown) is deposited on thesecond ILD film31 to fill the contact holes32, and then the metal is patterned and etched, thereby formingmetal electrodes33 in contact with the source and drainregions26aand26b,respectively. As a result, a semiconductor device is obtained.
• In semiconductor devices manufactured according to the present method, the[0026]interconnector30 does not migrate closer to themetal electrodes33 during subsequent thermal processes and thus does not tend to form electrical shorts between the interconnector30 and themetal electrodes33. In particular, the TEOS film used as thefirst ILD film28 is denser than theBPSG layer29, and thus undergoes almost no deformation, such as shrinkage or expansion, during subsequent thermal processes. Because the layer underlying theinterconnector30 is formed from such dense TEOS film, it does not migrate toward themetal electrodes33 during subsequent thermal processing, thereby preventing the electrical shorts between the interconnector30 and themetal electrodes33.
• FIG. 3 is a sectional view of a semiconductor device manufactured by another embodiment of the method according to the present invention. Unlike the previous embodiment, after the Ar ion sputtering step, a[0027]dummy insulating layer50 is deposited on the exposedfirst ILD film28 andBPSG layer29 in the present embodiment. Thedummy insulating layer50 is formed of a material layer that is thermally stable, i.e., undergoes no substantial expansion or contraction during subsequent thermal processes. For example, thedummy insulating layer50 is preferably formed from a material selected from the group consisting of low pressure (LP)-TEOS, plasma enhanced (PE)-TEOS, high temperature oxide (HTO), middle temperature oxide (MTO), undoped silicate glass (USG) and silicon oxynitride SiON, and is deposited to a thickness of up to 3,000 Å, preferably, 1,000-3,000 Å. In the present embodiment, because theinterconnector30 is formed on thedummy insulating layer50, a layer which exhibits almost no thermal shrinkage or expansion, the migration of theinterconnector30 toward themetal electrodes33 can be effectively suppressed.
• As previously described, in the semiconductor device manufacturing method according to the present invention, the BPSG layer can be planarized by the Ar ion sputtering. In addition, portions of the first ILD film, a thermally stable TEOS layer are exposed by the Ar ion sputtering. The lower interconnectors are then formed on the exposed portions of the first ILD film. As a result, the migration of the lower interconnector toward the upper interconnection layer during subsequent thermal processing can be suppressed. For this reason, although the BPSG layer is initially reflowed at a temperature of 820° C. or less, the subsequent migration of the lower interconnection layer due to the incomplete reflowing of the BPSG layer is suppressed so that no electrical shorts form between the lower interconnector and the metal electrodes, thereby improving the reliability and yield of the semiconductor device.[0028]
• While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made to the described embodiments without departing from the spirit and scope of the invention as defined by the appended claims.[0029]

Claims (10)

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:

forming a transistor in a semiconductor substrate;

depositing a first interlevel dielectric film to cover the transistor on the semiconductor substrate;

depositing a BPSG layer as a planarization layer on the first interlevel dielectric film;

reflowing the BPSG layer;

etching the BPSG layer by using Ar ion sputtering until a portion of the first interlevel dielectric film is exposed, wherein the surfaces of the first interlevel dielectric film including the BPSG layer are substantially planarized;

forming an interconnector on the exposed portion of the first interlevel dielectric film;

depositing a second interlevel dielectric film to cover the interconnector on the first interlevel dielectric film and the BPSG layer; and

forming metal electrodes on the second interlevel dielectric film, the metal electrodes being in contact with predetermined regions of the transistor.

2. The method of

claim 1

, wherein the first interlevel dielectric film comprises a TEOS film.

3. The method of

claim 2

, wherein the TEOS film is 1,200-2000 Å thick as deposited.

4. The method of

claim 1

, wherein the BPSG layer is reflowed at a temperature of 700-820° C.

5. The method of

claim 1

, wherein the Ar ion sputtering is carried out with application of a power of not more than 400 W and at a pressure of not more than 10 torr.

6. The method of

claim 2

, wherein the Ar ion sputtering is carried out such that the etching selectivity of the BPSG layer with respect to the TEOS film is at least 2:1.

7. The method of

claim 3

, wherein the Ar ion sputtering is terminated with the thickness of the remaining TEOS film in the exposed portions of the first interlevel dielectric film being at least 1,000 Å.

8. The method of

claim 1

, after the Ar ion sputtering, further comprising depositing a dummy insulating layer on the planarized BPSG layer and first interlevel dielectric film before forming the interconnection layer.

9. The method of

claim 8

, wherein the dummy insulating layer comprises a material selected from the group consisting of LP-TEOS, PE-TEOS, HTO, MTO, USG and SiON.

10. The method of

claim 8

, wherein the dummy insulating layer is deposited to a thickness of 1,000-3,000 Å.

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