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US20010049757A1 - Programmable task scheduler for use with multiport xDSL processing system - Google Patents

Programmable task scheduler for use with multiport xDSL processing systemDownload PDF

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Publication number
US20010049757A1
US20010049757A1US09/797,648US79764801AUS2001049757A1US 20010049757 A1US20010049757 A1US 20010049757A1US 79764801 AUS79764801 AUS 79764801AUS 2001049757 A1US2001049757 A1US 2001049757A1
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data
data object
memory
transfer
processing circuitry
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US09/797,648
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Ming-Kang Liu
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Realtek Semiconductor Corp
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Assigned to REAL COMMUNICATIONS, INCreassignmentREAL COMMUNICATIONS, INCASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).Assignors: INTEGRATED TELECOM EXPRESS, INC
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Assigned to REAL COMMUNICATIONS, INC.reassignmentREAL COMMUNICATIONS, INC.ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).Assignors: INTEGRATED TELECOM EXPRESS, INC.
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Assigned to REAL COMMUNICATIONS, INC.reassignmentREAL COMMUNICATIONS, INC.ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).Assignors: INTEGRATED TELECOM EXPRESS, INC.
Assigned to REAL COMMUNICATIONS, INC.reassignmentREAL COMMUNICATIONS, INC.ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).Assignors: INTEGRATED TELECOM EXPRESS, INC.
Assigned to REAL COMMUNICATIONS, INC.reassignmentREAL COMMUNICATIONS, INC.ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).Assignors: INTEGRATED TELECOM EXPRESS, INC.
Assigned to REAL COMMUNICATIONS, INC.reassignmentREAL COMMUNICATIONS, INC.ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).Assignors: INTEGRATED TELECOM EXPRESS, INC.
Assigned to REAL COMMUNICATIONS, INC.reassignmentREAL COMMUNICATIONS, INC.ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).Assignors: INTEGRATED TELECOM EXPRESS, INC.
Assigned to REAL COMMUNICATIONS, INC.reassignmentREAL COMMUNICATIONS, INC.ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).Assignors: INTEGRATED TELECON EXPRESS, INC.
Assigned to REAL COMMUNICATIONS, INC.reassignmentREAL COMMUNICATIONS, INC.ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).Assignors: INTEGRATED TELECOM EXPRESS, INC.
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Priority to US11/299,953prioritypatent/US7818748B2/en
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Abstract

A task scheduler for a TC subsystem is disclosed. The task scheduler is responsible for responding to computation block requests from the TC subsystem, and retrieving/storing data objects for such computation blocks. The task scheduler thus facilitates a type of logical pipeline by exchanging such data objects with a common TC memory used by each computation block. The task scheduler generally includes a queue, a state machine and a bus master for satisfying the data object requests.

Description

Claims (58)

What is claimed is:
1. Scheduling apparatus for scheduling the transfer of machine readable data objects associated with a logical pipeline involving a plurality of processing circuitry blocks, said scheduling apparatus comprising:
means for handling a first transfer request for a machine readable data object, said first transfer request including a first field containing data associated with a function sharing parameter and a second field containing id data associated with the identification of one of said processing circuitry blocks that is to use said machine readable data object;
a state machine means capable of accessing one or more offset address tables in an address table memory to obtain address information associated with the machine readable data objects, said address information being generated based on said first field and/or said second field;
a bus interface means capable of processing said address information from said state machine block and initiating a transfer of a machine readable data object in connection with said address information.
2. The apparatus of
claim 1
 wherein said state machine means is capable of obtaining address information in connection with a second transfer request during a clock period in which said machine readable data object is being transferred.
3. The apparatus of
claim 1
 further comprising:
a transfer request queue storing a plurality of transfer requests.
4. The apparatus of
claim 3
 wherein said one or more of said transfer requests are handled with a programmable priority.
5. The apparatus of
claim 1
 wherein at least one of said one or more offset address tables is stored in a memory means located within said scheduling apparatus.
6. The apparatus of
claim 1
 wherein said second field contains data associated with the identification of a subset of functionality of one of said processing circuitry blocks.
7. Data object retrieval apparatus for use in a communications system in connection with the movement of data objects among a plurality of processing circuitry blocks, said movement being dynamic and configurable, said data object retrieval apparatus comprising:
a movement request lookup means for accessing a table in connection with a first movement request, said table providing address information associated with a data object based on parameters specified by said first movement request;
a movement request enacting means for processing said address data in machine readable form relating to said address information, said movement request enacting means further being configured for performing an access to a memory block in connection with said address data,
wherein said movement request enacting means is capable of performing some part of said access while said movement request lookup means is available to access said table in connection with a second movement request.
8. The apparatus of
claim 7
 wherein said movement of data objects may be associated with priority information in machine readable form.
9. The apparatus of
claim 7
 wherein said each of said processing circuitry blocks is hardware-based or software-based.
10. The apparatus of
claim 7
 wherein said movement request enacting means is capable of performing an access to an external memory block.
11. The apparatus of
claim 7
 wherein said movement request enacting means is capable of performing an access to an internal memory block.
12. The apparatus of
claim 7
 wherein said communications system process a stream of xDSL data, and wherein a processing circuitry block processes Discrete Multi Tone DMT) symbols.
13. Transfer request queue circuitry for storing a plurality of transfer requests in machine readable form, said transfer requests being used in a communications system in connection with the movement of data objects among a plurality of processing circuitry blocks, said movement associated with a logical pipeline processing operation involving the processing of a stream of communications data, said transfer request queue circuitry comprising:
an upload transfer memory for temporarily storing an upload transfer request in machine readable form received from a first processing circuitry block, said upload transfer request being receivable over a bus;
a download transfer memory for temporarily storing a download transfer request in machine readable form received from a second processing circuitry block, said download transfer request being receivable over said bus;
a transfer request priority means associated with said transfer requests.
14. The circuitry of
claim 13
 wherein said transfer request priority means is a circuitry block providing a relative priority between said upload transfer memory and said download transfer memory.
15. The circuitry of
claim 13
 wherein said transfer request priority means provides a relative priority among said transfer requests.
16. The circuitry of
claim 13
 wherein said relative priority is associated with information in machine readable form relating to fields contained in said data objects.
17. The circuitry of
claim 13
 wherein said first processing circuitry block and said second processing circuitry block each process Discrete Multi Tone (DMT) symbols.
18. A data object memory in machine readable form for use in a communications system in connection with the movement of data objects in machine readable form, said movement occurring among a plurality of processing circuitry blocks, said movement associated with a logical pipeline processing operation involving the processing of a stream of communications data, said data object memory comprising:
a first memory for storing a plurality of fields containing data associated with data object address information usable in connection with said movement of data objects;
a second memory for storing a plurality of records, each of said records being comprised of said plurality of fields, said each of said fields corresponding to one of said data objects;
wherein one of said records is useable in connection with said logical pipeline processing operation to enable in part the transfer of said one of said data objects in connection with at least one processing circuitry block.
19. The data object memory of
claim 18
 wherein said plurality of fields and said plurality of records are configurable by said communications system.
20. The data object memory of
claim 18
 wherein said transfer of said one of said data objects is enabled in part by a second data object memory in machine readable form, said second data object memory associated with data object sequence information.
21. The data object memory of
claim 18
 wherein said transfer of said one of said data objects is enabled in part by a second data object memory in machine readable form, said second data object memory associated with processing circuitry block sequence information.
22. The data object memory of
claim 18
 wherein said data object memory and said second data object memory are contained in a memory circuitry block located externally to a scheduling apparatus, said scheduling apparatus for scheduling said transfer.
23. The data object memory of
claim 18
 wherein said each of processing circuitry blocks is hardware-based or software-based.
24. The data object memory of
claim 18
 wherein said at least one processing circuitry block processes Discrete Multi Tone (DMT) symbols.
25. Data object retrieval apparatus for use in an communications system in connection with the movement of data objects in machine readable form among a plurality of processing circuitry blocks, said data objects containing retrieval apparatus comprising:
a movement request lookup means configured for accessing a first table in connection with a movement request from a processing circuitry block, said first table being configured to provide a first address information based on parameters specified by said movement request;
said movement request lookup means further being configured for accessing a second table in connection with said movement request, said second table being configured to provide a second address information based in part on a computation parameter specified by said movement request;
a movement request enacting means configured for performing an access to a memory block in connection with said first address information and said second address information.
26. The apparatus of
claim 25
 wherein each of a plurality of processing circuitry blocks is hardware-based or software-based.
27. The apparatus of
claim 25
 wherein said processing circuitry block processes Discrete Multi Tone (DMT) symbols.
28. The apparatus of
claim 25
 wherein said computation parameter is associated with the computation function performed by said processing circuitry block.
29. The apparatus of
claim 25
 wherein said computation parameter is associated with the computation sequence of a data object in connection with said processing circuitry block.
30. Method of operating a scheduling apparatus for scheduling the transfer of machine readable data objects associated with a logical pipeline involving a plurality of processing circuitry blocks, said method comprising:
handling a first transfer request for a machine readable data object, said first transfer request including a first field containing data associated with a function sharing parameter and a second field containing id data associated with the identification of one of said processing circuitry blocks that is to use said machine readable data object;
accessing one or more offset address tables in an address table memory to obtain address information associated with the machine readable data objects, said address information being generated based on said first field and/or said second field;
initiating a transfer of a machine readable data object in connection with said address information.
31. The method of
claim 30
 wherein said address information is obtained in connection with a second transfer request during a clock period in which said machine readable data object is being transferred.
32. The method of
claim 30
 further comprising:
providing a transfer request queue storing a plurality of transfer requests.
33. The method of
claim 32
 wherein said one or more of said transfer requests are handled with a programmable priority.
34. The method of
claim 32
 wherein at least one of said one or more offset address tables is stored in a memory means located within said scheduling apparatus.
35. The method of
claim 32
 wherein said second field contains data associated with the identification of a subset of functionality of one of said processing circuitry blocks.
36. A method for operating a data object retrieval for use in a communications system in connection with the movement of data objects among a plurality of processing circuitry blocks, said movement being dynamic and configurable, said method comprising:
providing a movement request lookup means for accessing a table in connection with a first movement request, said table providing address information associated with a data object based on parameters specified by said first movement request;
providing a movement request enacting means for processing said address data in machine readable form relating to said address information, said movement request enacting means further being configured for performing an access to a memory block in connection with said address data,
wherein said movement request enacting means is capable of performing some part of said access while said movement request lookup means is available to access said table in connection with a second movement request.
37. The method of
claim 36
 wherein said movement of data objects may be associated with priority information in machine readable form.
38. The method of
claim 36
 wherein said each of said processing circuitry blocks is hardware-based or software-based.
39. The method of
claim 36
 wherein said movement request enacting means is capable of performing an access to an external memory block.
40. The method of
claim 39
 wherein said movement request enacting means is capable of performing an access to an internal memory block.
41. The method of
claim 39
 wherein the communications system process a stream of xDSL data, and wherein a processing circuitry block processes Discrete Multi Tone (DMT) symbols.
42. Method of operating a transfer request queue for storing a plurality of transfer requests in machine readable form, said transfer requests being used in a communications system in connection with the movement of data objects among a plurality of processing circuitry blocks, said movement associated with a logical pipeline processing operation involving the processing of a stream of communications data, said method comprising:
providing an upload transfer memory for temporarily storing an upload transfer request in machine readable form received from a first processing circuitry block, said upload transfer request being receivable over a bus;
providing a download transfer memory for temporarily storing a download transfer to request in machine readable form received from a second processing circuitry block, said download transfer request being receivable over said bus;
providing a transfer request priority means associated with said transfer requests.
43. The method of
claim 42
 wherein said transfer request priority means is a circuitry block providing a relative priority between said upload transfer memory and said download transfer memory.
44. The method of
claim 42
 wherein said transfer request priority means provides a relative priority among said transfer requests.
45. The method of
claim 42
 wherein said relative priority is associated with information in machine readable form relating to fields contained in said data objects.
46. The method of
claim 42
 wherein said first processing circuitry block and said second processing circuitry block each process Discrete Multi Tone (DMT) symbols.
47. A method for operating a data object memory in machine readable form for use in a communications system in connection with the movement of data objects in machine readable form, said movement occurring among a plurality of processing circuitry blocks, said movement associated with a logical pipeline processing operation involving the processing of a stream of communications data, said method comprising:
storing a plurality of fields containing data associated with data object address information usable in connection with said movement of data objects;
for storing a plurality of records, each of said records being comprised of said plurality of fields, said each of said fields corresponding to one of said data objects;
wherein one of said records is useable in connection with said logical pipeline processing operation to enable in part the transfer of said one of said data objects in connection with at least one processing circuitry block.
48. The method of
claim 47
 wherein said plurality of fields and said plurality of records are configurable by said communications system.
49. The method of
claim 47
 wherein said transfer of said one of said data objects is enabled in part by a second data object memory in machine readable form, said second data object memory associated with data object sequence information.
50. The method of
claim 47
 wherein said transfer of said one of said data objects is enabled in part by a second data object memory in machine readable form, said second data object memory associated with processing circuitry block sequence information.
51. The method of
claim 47
 wherein said data object memory and said second data object memory are contained in a memory circuitry block located externally to a scheduling apparatus, said scheduling apparatus for scheduling said transfer.
52. The method of
claim 47
 wherein said each of processing circuitry blocks is hardware-based or software-based.
53. The method of
claim 47
 wherein said at least one processing circuitry block processes Discrete Multi Tone (DMT) symbols.
54. A method for retrieving a data object in an communications system in connection with the movement of data objects in machine readable form among a plurality of processing circuitry blocks, said method comprising:
accessing a first table in connection with a movement request from a processing circuitry block, said first table providing a first address information based on parameters specified by said movement request;
accessing a second table in connection with said movement request, said second table providing a second address information based in part on a computation parameter specified by said movement request;
performing an access to a memory block in connection with said first address information and said second address information.
55. The method of
claim 54
 wherein each of a plurality of processing circuitry blocks is hardware-based or software-based.
56. The method of
claim 54
 wherein said processing circuitry block processes Discrete Multi Tone (DMT) symbols.
57. The method of
claim 54
 wherein said computation parameter is associated with the computation function performed by said processing circuitry block.
58. The method of
claim 54
 wherein said computation parameter is associated with the computation sequence of a data object in connection with said processing circuitry block.
US09/797,6482000-03-012001-03-01Programmable task scheduler for use with multiport xDSL processing systemAbandonedUS20010049757A1 (en)

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US11/299,953US7818748B2 (en)2000-03-012005-12-12Programmable task scheduler

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US09/797,648US20010049757A1 (en)2000-03-012001-03-01Programmable task scheduler for use with multiport xDSL processing system

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US09/797,648AbandonedUS20010049757A1 (en)2000-03-012001-03-01Programmable task scheduler for use with multiport xDSL processing system
US09/798,113Expired - LifetimeUS7200138B2 (en)2000-03-012001-03-01Physical medium dependent sub-system with shared resources for multiport xDSL system
US09/797,778Expired - LifetimeUS7085285B2 (en)2000-03-012001-03-01xDSL communications systems using shared/multi-function task blocks
US09/797,755Expired - LifetimeUS6988188B2 (en)2000-03-012001-03-01Data object architecture and method for xDSL ASIC processor
US09/797,633Expired - LifetimeUS7075941B2 (en)2000-03-012001-03-01Scaleable architecture for multiple-port, system-on-chip ADSL communications systems
US09/798,054Expired - LifetimeUS6839830B2 (en)2000-03-012001-03-01Logical pipeline for data communications system
US09/797,634Expired - LifetimeUS7032223B2 (en)2000-03-012001-03-01Transport convergence sub-system with shared resources for multiport xDSL system
US09/797,789Expired - LifetimeUS6986073B2 (en)2000-03-012001-03-01System and method for a family of digital subscriber line (XDSL) signal processing circuit operating with an internal clock rate that is higher than all communications ports operating with a plurality of port sampling clock rates
US09/797,782Expired - LifetimeUS6965960B2 (en)2000-03-012001-03-01xDSL symbol processor and method of operating same
US09/798,133AbandonedUS20020010810A1 (en)2000-03-012001-03-01xDSL function ASIC processor & method of operation
US09/797,793Expired - LifetimeUS6839889B2 (en)2000-03-012001-03-01Mixed hardware/software architecture and method for processing xDSL communications
US10/986,502Expired - LifetimeUS8325751B2 (en)2000-03-012004-11-10Mixed hardware/software architecture and method for processing communications
US11/299,953Expired - LifetimeUS7818748B2 (en)2000-03-012005-12-12Programmable task scheduler
US11/330,610Expired - LifetimeUS7295571B2 (en)2000-03-012006-01-12xDSL function ASIC processor and method of operation

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US09/798,113Expired - LifetimeUS7200138B2 (en)2000-03-012001-03-01Physical medium dependent sub-system with shared resources for multiport xDSL system
US09/797,778Expired - LifetimeUS7085285B2 (en)2000-03-012001-03-01xDSL communications systems using shared/multi-function task blocks
US09/797,755Expired - LifetimeUS6988188B2 (en)2000-03-012001-03-01Data object architecture and method for xDSL ASIC processor
US09/797,633Expired - LifetimeUS7075941B2 (en)2000-03-012001-03-01Scaleable architecture for multiple-port, system-on-chip ADSL communications systems
US09/798,054Expired - LifetimeUS6839830B2 (en)2000-03-012001-03-01Logical pipeline for data communications system
US09/797,634Expired - LifetimeUS7032223B2 (en)2000-03-012001-03-01Transport convergence sub-system with shared resources for multiport xDSL system
US09/797,789Expired - LifetimeUS6986073B2 (en)2000-03-012001-03-01System and method for a family of digital subscriber line (XDSL) signal processing circuit operating with an internal clock rate that is higher than all communications ports operating with a plurality of port sampling clock rates
US09/797,782Expired - LifetimeUS6965960B2 (en)2000-03-012001-03-01xDSL symbol processor and method of operating same
US09/798,133AbandonedUS20020010810A1 (en)2000-03-012001-03-01xDSL function ASIC processor & method of operation
US09/797,793Expired - LifetimeUS6839889B2 (en)2000-03-012001-03-01Mixed hardware/software architecture and method for processing xDSL communications
US10/986,502Expired - LifetimeUS8325751B2 (en)2000-03-012004-11-10Mixed hardware/software architecture and method for processing communications
US11/299,953Expired - LifetimeUS7818748B2 (en)2000-03-012005-12-12Programmable task scheduler
US11/330,610Expired - LifetimeUS7295571B2 (en)2000-03-012006-01-12xDSL function ASIC processor and method of operation

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US8325751B2 (en)2012-12-04
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US20050071800A1 (en)2005-03-31
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US6839830B2 (en)2005-01-04
US6965960B2 (en)2005-11-15

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