US20010045652A1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device capable of preventing diffusion of a particle of copper or the like which forms a conductive layer is provided without any increase in the number of manufacturing the steps. Further, a semiconductor device preventing diffusion of a particle forming a conductive layer into an insulating layer even when a width of the conductive layer is increased is provided. The semiconductor device includes: an insulating layer2; a barrier layer4; a conductive layer5; a barrier layer6having an opening11; an insulating layer7having a through hole8exposing a surface of conductive layer5and a part of a surface of barrier layer6; a barrier layer9formed on a surface of said through hole8and insulating layer7which is in contact with an upper surface6aof barrier layer6; and a conductive layer10filling opening11and through hole8.

Description

BACKGROUND OF THE INVENTION
• 1. Field of the Invention[0001]
• The present invention relates to semiconductor devices and manufacturing methods thereof and, more particularly to a semiconductor device having a conductive layer including copper and a manufacturing method thereof.[0002]
• 2. Description of the Background Art[0003]
• With recent increase in demand for higher integration degree and speed of the semiconductor device, various considerations are given to the material of a conductive layer. If a width of the conductive layer becomes smaller than about 0.15 μm, the selection of materials which can be used for the conductive layer would extremely be limited. Recently, the use of copper for the conductive layer has been described for example in “Damascene Cu interconnection capped by TiWN layer”[0004]TECHNICAL REPORT OF IEICE., SDM96-169 (1996-12).
• FIG. 29 is a cross sectional view showing a structure of the conductive layer which is described in the aforementioned article. Referring to FIG. 29, a[0005]trench92 is formed in an insulatinglayer91 including silicon dioxide and formed on a silicon substrate. Aconductive layer94 including copper is formed intrench92 with abarrier layer93 including titanium nitride, tantalum or tantalum nitride in the interposed. Acap layer96 including titanium tungsten nitride (TiWN) is formed to cover an upper surface ofconductive layer94.Barrier layer93 andcap layer96 effectively prevent oxidation ofconductive layer94 and diffusion of copper inconductive layer94 into insulatinglayer91, so that degradation of characteristic such as increase in electrical resistance ofconductive layer94 is effectively prevented.
• Conventionally, a so-called dual damascene structure as shown in FIG. 29 in which a multiple of conductive layers including copper are formed is described, for example, in 1997[0006]Symposium on VLSI Technology Digest of Technical Paperspp. 59-60. FIGS.30 to38 are cross sectional views showing a method of manufacturing the dual damascene structure described in the above mentioned document. Referring to FIG. 30, an insulatinglayer101 including silicon dioxide is formed on a silicon substrate, and atrench102 is formed in insulatinglayer101. A first layer including titanium nitride, tantalum or tantalum nitride is formed to cover a surface oftrench102, and a copper layer is formed on the first layer to filltrench102. The copper and first layers are planarized by CMP (Chemical Mechanical Polishing), so that abarrier layer103 including titanium nitride, tantalum or tantalum nitride and aconductive layer104 including copper are formed.
• Formed on insulating[0007]layer101 are abarrier layer105 including silicon nitride, an insulatinglayer106 including silicon dioxide, abarrier layer107 including silicon nitride, an insulatinglayer108 including silicon dioxide and abarrier layer109 including titanium nitride, tantalum or tantalum nitride. By sequentially etching these layers, holes111 and110 are formed.
• As shown in FIG. 31, when the etching is finished, a[0008]particle112 of carbon fluoride (CF_x), aparticle113 of cupric oxide (CuO), aparticle116 of copper fluoride (CuF_x) or the like adhere to a sidewall ofhole110. Acupric oxide layer114 is formed on a surface ofconductive layer104, and a cuprous oxide (Cu₂O)layer115 is formed therebelow. It is noted that barrier layers103,105,107 and109 as well as insulatinglayer108 are not shown in FIGS.31 to34.
• Referring to FIG. 32, oxygen plasma allows[0009]particles112 and116 of carbon and copper fluoride to be oxidized and disappeared.
• Referring to FIG. 33, an oxide is reduced by hydrofluoric acid (HF). Thus,[0010]particle113 of cupric oxide disappears and,cupric oxide layer114 inconductive layer104 is also reduced to formcuprous oxide layer115.
• Referring to FIG. 34,[0011]cuprous oxide layer115 is reduced by gaseous hydrogen to copper.
• Referring to FIG. 35, a[0012]barrier layer121 including titanium nitride, tantalum or tantalum nitride is formed to cover side surfaces ofholes110 and111 and the surface ofconductive layer104.
• Referring to FIG. 36, an entire surface of[0013]barrier layer121 is etched back to expose the surface ofconductive layer104.
• Referring to FIG. 37, a[0014]copper layer123 is formed by CVD (Chemical Vapor Deposition).
• Referring to FIG. 38, an entire surface of the copper layer is etched back by CMP to form a[0015]conductive layer124 including copper. Thus, a dual damascene structure in whichconductive layers104 and124 are connected is completed.
• In the above described method, however, a step of[0016]cleaning hole110 as shown in conjunction with FIGS.32 to34 is required afterholes110 and111 are formed, whereby the number of steps for manufacturing the semiconductor device disadvantageously increases.
• Further, if[0017]hole110 is formed with a diameter larger than a width oftrench102 in the step shown in FIG. 30 such that a width ofconductive layer124filling hole110 is increased, a surface ofinsulating layer101 is exposed byhole110. Ifhole110 is filled withcopper layer123, the copper is oxidized as it is in contact with silicon dioxide, so that electrical resistance ofconductive layer124 increases. In addition, as copper is diffused intoinsulating layer101, insulating characteristic ofinsulating layer101 is impaired.
SUMMARY OF THE INVENTION
• The present invention is made to solve the aforementioned problem. An object of the present invention is to provide a semiconductor device having a conductive layer capable of effectively preventing diffusion of particles of copper or the like which form the conductive layer without any increase in the number of manufacturing steps.[0018]
• Another object of the present invention is to provide a semiconductor device in which particles of copper or the like forming a conductive layer are not diffused to an insulating layer even when a width of the conductive layer is increased.[0019]
• A semiconductor device according to the present invention includes a first insulating layer, first diffusion preventing layer, first conductive layer, second diffusion preventing layer, second insulating layer, third diffusion preventing layer and second conductive layer.[0020]
• The first insulating layer is formed on a semiconductor substrate and has a recess. The first diffusion preventing layer is formed on a surface of the recess. The first conductive layer is formed on a surface of the first diffusion preventing layer to fill the recess. The second diffusion preventing layer is formed on a surface of the first insulating layer and provided with an opening which exposes a surface of the first conductive layer. The second insulating layer is formed on a surface of the second diffusion preventing layer to expose the surface of the first conductive layer and a part of the surface of the second diffusion preventing layer, and has a first hole communicating with the opening. The third diffusion preventing layer is formed on a side surface of the first hole and on the second insulating layer in contact with an upper surface of the second diffusion preventing layer. The second conductive layer fills the opening and the first hole such that it is in contact with the first conductive layer.[0021]
• In the semiconductor device having the above described structure, a side surface of the opening is formed by the part of the surface of the second diffusion preventing layer, the side surface of the first hole is formed by the third diffusion preventing layer, and the third diffusion preventing layer is in contact with the upper surface of the second diffusion preventing layer. Thus, the portion of the second conductive layer which fills the opening and the first hole is in contact with the second and third diffusion preventing layers, so that the second conductive layer would not be in contact with the insulating layer even if a diameter of the first hole and a width of the first conductive layer are increased. As a result, atoms of the second conductive layer would not be diffused into the insulating layer. In addition, increase in electrical resistance of the second conductive layer is prevented.[0022]
• Preferably, the diameter of the first hole is larger than that of the opening.[0023]
• Further, the third diffusion preventing layer preferably includes fourth and fifth diffusion preventing layers which are respectively formed on the side surface of the first hole and on the second insulating layer.[0024]
• Preferably, the semiconductor device further includes a fourth diffusion preventing layer formed on a portion of the third diffusion preventing layer which is formed on the side surface of the first hole. In this case, as two diffusion preventing layers are formed on the side surface of the first hole, the diffusion of atoms forming the second conductive layer is more effectively be prevented.[0025]
• More preferably, the semiconductor device further includes a third insulating layer formed on the second insulating layer, where the third insulating layer has a second hole communicating with the first hole and the third diffusion preventing layer is formed on the side surfaces of the first and second holes and on the third insulating layer. In this case, if the second hole is filled with a conductive layer, another conductive layer can be formed.[0026]
• Preferably, the first and second conductive layers include copper, and the first and second insulating layers include silicon dioxide.[0027]
• Preferably, the first and third diffusion preventing layers include at least one material selected from a group of titanium nitride, tantalum or tantalum nitride, and the second diffusion preventing layer includes silicon nitride. In this case, as the first and third diffusion preventing layers which are respectively in contact with the first and second conductive layers in a large area include at least one material selected from the group of titanium nitride, tantalum or tantalum nitride, which are all conductors. Thus, electrical resistance of the first and second conductive layers is not increased. Further, as the second diffusion preventing layer formed between the first and second insulating layers includes silicon nitride, which is an insulator, the problem associated with short-circuit is avoided even when the silicon nitride is brought into contact with another conductive layer.[0028]
• A method of manufacturing a semiconductor device according to the present invention includes the steps of:[0029]
• forming a first insulating layer having a recess on a semiconductor substrate;[0030]
• forming a first diffusion preventing layer on a surface of the recess;[0031]
• forming a first conductive layer on a surface of the first diffusion preventing layer to fill the recess;[0032]
• forming a second diffusion preventing layer on surfaces of the first conductive and insulating layers;[0033]
• forming a second insulating layer on a surface of the second diffusion preventing layer;[0034]
• selectively removing the second insulating layer to form a first hole which exposes a portion of the second diffusion preventing layer;[0035]
• forming a third diffusion preventing layer on a side surface of the first hole in contact with an upper surface of the second diffusion preventing layer;[0036]
• removing the exposed portion of second diffusion preventing layer using the second insulating layer and the third diffusion preventing layer as masks to form an opening which communicates with the first hole and exposes a portion of the first conductive layer; and[0037]
• filling the opening and the first hole to form a second conductive layer in contact with the first conductive layer.[0038]
• In the method of manufacturing the semiconductor device having the above described steps, the third diffusion preventing layer is formed on the sidewall of the first hole when the exposed portion of the second diffusion preventing layer is removed. Thus, for removing the first diffusion preventing layer, even when a particle comes from the first conductive layer therebelow, contact between the particle and the second insulating layer is prevented by the third diffusion preventing layer. As a result, the semiconductor device is provided which has a connection structure capable of effectively preventing diffusion of the particle or the like forming the conductive layer without any step of cleaning the hole which has conventionally been used.[0039]
• Preferably, the step of forming the third diffusion preventing layer includes forming a third diffusion preventing layer on a surface of the exposed portion of the second diffusion preventing layer, side surface of the first hole and the second insulating layer. The method of manufacturing the semiconductor further includes a step of removing a portion of the third diffusion preventing layer on the surface of the portion of the second diffusion preventing layer to expose the portion of the second diffusion preventing layer.[0040]
• Preferably, the step of forming the first hole includes forming the first hole having a diameter which is larger than a width of the first conductive layer, and the step of forming the opening includes forming a resist pattern with a hole pattern having a diameter which is equal to or smaller than the width of the first conductive layer on the surface of the second diffusion preventing layer such that a portion of the second diffusion preventing layer on the first conductive layer is exposed and removing the exposed portion of the second diffusion preventing layer using the resist pattern as a mask. In this case, as the first hole having a large diameter is formed, electrical resistance of the second conductive layer which fills the first hole can be reduced. Further, as the portion of the second diffusion preventing layer is removed in accordance with the resist pattern with the hole pattern having a width which is equal to or smaller than the width of the first conductive layer, the diameter of the opening formed in the second diffusion preventing layer would be equal to or smaller than the diameter of the first conductive layer. Thus, the first insulating layer is not exposed and contact between the first and second insulating layers is prevented.[0041]
• Preferably, the method further includes a step of forming a fourth diffusion preventing layer on a surface of the second insulating layer, and the step of forming the first hole includes forming the first hole by selectively removing the fourth diffusion preventing layer and the second insulating layer.[0042]
• Preferably, the method further includes a step of forming the fourth diffusion preventing layer on surfaces of the portion of the first conductive layer, third diffusion preventing layer and second insulating layer which have been exposed by removing the second diffusion preventing layer, and the step of forming the second conductive layer includes filling the opening and the first hole to form the second conductive layer which is in contact with the fourth diffusion preventing layer.[0043]
• In this case, two diffusion preventing layers, that is, the third and fourth diffusion preventing layers, are formed on a sidewall of the first hole.[0044]
• Preferably, the method further includes a step of forming a third insulating layer on the surface of the second insulating layer and a step of selectively removing the third insulating layer to form a second hole in the third insulating layer. In such manufacturing method, another conductive layer can be formed in the second hole.[0045]
• The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.[0046]
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a cross sectional view showing a semiconductor device according to a first embodiment of the present invention.[0047]
• FIGS.[0048]2 to7 are cross sectional views showing first to sixth steps of a method of manufacturing the semiconductor device shown in FIG. 1.
• FIG. 8 is a cross sectional view showing a semiconductor device according to a second embodiment of the present invention.[0049]
• FIGS.[0050]9 to12 are cross sectional views showing first to fourth steps of a method of manufacturing the semiconductor device shown in FIG. 8.
• FIG. 13 is a cross sectional view showing a semiconductor device according to a third embodiment of the present invention.[0051]
• FIGS.[0052]14 to17 are cross sectional views showing first to fourth steps of a method of manufacturing the semiconductor device shown in FIG. 13.
• FIG. 18 is a cross sectional view showing a semiconductor device according to a fourth embodiment of the present invention.[0053]
• FIGS.[0054]19 to22 are cross sectional views showing first to fourth steps of a method of manufacturing the semiconductor device shown in FIG. 18.
• FIG. 23 is a cross sectional view showing a semiconductor device according to a fifth embodiment of the present invention.[0055]
• FIGS.[0056]24 to28 are cross sectional views showing first to fifth steps of a method of manufacturing the semiconductor device shown in FIG. 23.
• FIG. 29 is a cross sectional view showing a conductive layer in accordance with a conventional damascene structure.[0057]
• FIGS.[0058]30 to38 are cross sectional views showing first to ninth steps of a method of manufacturing a conventional semiconductor device having conductive layers which are mutually connected.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
• Now, embodiments of the present invention will be described with reference to the drawings.[0059]
• First Embodiment[0060]
• Referring to FIG. 1, in a semiconductor device according to a first embodiment of the present invention, an insulating[0061]layer2 including silicon dioxide (SiO₂) is formed as a first insulating layer on asilicon substrate1 as a semiconductor substrate. Atrench3 having a width of about 0.2 μm and a depth of about 0.2 μm is formed in insulatinglayer2. Abarrier layer4 having a thickness of about 20 nm and including tantalum nitride is formed as a first diffusion preventing layer to cover a surface oftrench3. Aconductive layer5 including copper is formed to filltrench3 in contact withbarrier layer4.
• A[0062]barrier layer6 having a thickness of 40 nm and including silicon nitride is formed on insulatinglayer2 as a second diffusion preventing layer.Barrier layer6 prevents diffusion of copper into insulatinglayer2 and serves as an etching stopper.Barrier layer6 is provided with anopening11, which exposesconductive layer5. A second insulatinglayer7 including silicon dioxide is formed on anupper surface6aofbarrier layer6. Insulatinglayer7 is provided with a throughhole8 having a diameter of about 0.2 μm, which exposes a surface ofconductive layer5 and a side surface ofbarrier layer6. Abarrier layer9 is formed on a side surface of throughhole8 as a third diffusion preventing layer.Barrier layer9 includes tantalum nitride.
• A[0063]conductive layer10 is formed as a second conductive layer which fillsopening11 and throughhole8 and is in contact withconductive layer5 andbarrier layer6.Conductive layer10 includes copper. Anend surface9aofbarrier layer9 is in contact withupper surface6aofbarrier layer6.
• In the semiconductor device having the above described structure, as the entire portion of[0064]conductive layers5 and10 are in contact withbarrier layers4,6 and9, diffusion of copper ofconductive layers5 and10 into silicon dioxide of insulatinglayers2 and7 is prevented. Thus, insulating characteristic of insulatinglayers2 and7 would not be impaired. Further, asconductive layers5 and10 are not oxidized, electrical resistance ofconductive layers5 and10 is not increased.
• A method of manufacturing the semiconductor device shown in FIG. 1 will now be described. Referring to FIG. 2, an insulating[0065]layer2 including silicon dioxide is formed by CVD on asilicon substrate1. A resistpattern21 having a prescribed pattern is formed on insulating layer. Etching insulatinglayer2 in accordance with resistpattern21 forms atrench3.
• Referring to FIG. 3, a tantalum nitride layer is formed to cover surfaces of[0066]trench3 and insulatinglayer2 by CVD. A copper layer is formed on the tantalum nitride layer by CVD. By etching the copper and tantalum nitride layers by CMP, barrier andconductive layers4 and5 respectively including tantalum nitride and copper are formed intrench3. Abarrier layer6 including silicon nitride and having a thickness of about 40 nm is formed by CVD to cover insulatinglayer2,barrier layer4 andconductive layer5.
• Referring to FIG. 4, an insulating[0067]layer7 including silicon dioxide having a thickness of about 500 nm is formed onbarrier layer6 by CVD. A resistpattern22 having a prescribed pattern is formed on insulatinglayer7. Etching insulatinglayer7 in accordance with resistpattern22 forms a throughhole8.
• Referring to FIG. 5, a[0068]barrier layer9 including tantalum nitride is formed by sputtering to cover a side surface of throughhole8,barrier layer6 and anupper surface7aof insulatinglayer7. A thickness of the portions ofbarrier layer9 which are in contact with the side surface of throughhole8 andbarrier layer6 is about 20 nm, and the portion ofbarrier layer9 which is in contact withupper surface7ais about 40 nm.
• Referring to FIG. 6, an entire surface of[0069]barrier layer9 is etched back by sputter etching using argon. Thus, a portion ofbarrier layer6 is exposed. In addition, a thickness of the entire portion ofbarrier layer9 becomes about 20 nm.
• Referring to FIG. 7,[0070]barrier layer6 is etched using CF gas (CFx). Thus, anopening11 is formed inbarrier layer6, and a surface ofconductive layer5 and a part of a surface ofbarrier layer6 are exposed.
• Referring to FIG. 1, a[0071]conductive layer10 including copper is formed by CVD to fillopening11 and throughhole8, so that the semiconductor device shown in FIG. 1 is obtained.
• In the above described manufacturing method,[0072]barrier layer9 is formed on a sidewall of throughhole8 when etchingbarrier layer6 in the step shown in FIG. 7. Thus, even if copper ofconductive layer5 adheres tobarrier layer9 during etching, the copper would not be diffused into silicon dioxide of insulatinglayer10 because of the barrier layer. As a result, the problem associated with insulating characteristic of insulatinglayer7 is avoided. In addition, as a conventional step of cleaning the sidewall of throughhole8 is not necessary, the number of steps required for manufacturing the semiconductor device is reduced.
• Second Embodiment[0073]
• A semiconductor device according to a second embodiment of the present invention shown in FIG. 8 includes a through[0074]hole18 having a diameter of about 0.4 μm. In this respect, it is different from the semiconductor device shown in FIG. 1 which includes throughhole8 having a diameter of about 0.2 μm. Further, aconductive layer19 including copper is formed to fill throughhole18 in contact withconductive layer5 as a second conductive layer. Other parts of the structure of the semiconductor device shown in FIG. 8 are similar to those shown in FIG. 1.
• The semiconductor device having the above mentioned structure provides a similar effect as the semiconductor device shown in FIG. 1. Further, electrical resistance can be reduced as a width of[0075]conductive layer19 is large. Even if the width ofconductive layer19 is increased, the conductive layer is in contact withbarrier layers6 and9, but not withinsulating layer7. Thus, diffusion of copper ofconductive layer19 into silicon dioxide of insulatinglayer7 is prevented. In addition,conductive layer19 is not oxidized and electrical resistance ofconductive layer19 is not increased.
• A method of manufacturing the semiconductor device shown in FIG. 8 will now be described. Referring to FIG. 9, an insulating layer is formed on a[0076]silicon substrate1, and a trench is formed in insulatinglayer2, as in the first embodiment. Barrier andconductive layers4 and5 are formed in a trench, and abarrier layer6 is formed to cover insulatinglayer2,barrier layer4 andconductive layer5. An insulatinglayer7 is formed onbarrier layer6. A resistpattern23 having a prescribed pattern is formed on insulatinglayer7. Etching insulatinglayer7 in accordance with resistpattern23 forms a throughhole18 leading tobarrier layer6. A diameter of throughhole18 is about 0.4 μm.
• Referring to FIG. 10, a[0077]barrier layer9 including tantalum nitride is formed by sputtering to cover anupper surface7aof insulatinglayer7, a side surface of throughhole18 andbarrier layer6. A thickness of the portions ofbarrier layer9 which are in contact withbarrier layer6 and the side surface of throughhole18 is about 20 nm, and the thickness of the portion in contact withupper surface7aof insulatinglayer7 is about 40 nm.
• Referring to FIG. 11, an entire surface of[0078]barrier layer9 is etched back by sputter etching using argon to expose a portion ofbarrier layer6. A thickness of the entire portion ofbarrier layer9 is about 20 nm.
• Referring to FIG. 12, a resist[0079]pattern24 having ahole pattern24awith a width of about 0.2 μm is formed to coverbarrier layers6 and9.Hole pattern24ais aboveconductive layer5.Etching barrier layer6 in accordance with resistpattern24 by CF gas forms anopening11 inbarrier layer6.
• Referring to FIG. 8, a[0080]conductive layer19 including copper is formed by CVD to fill throughhole18 andopening11, so that the semiconductor device shown in FIG. 8 is obtained.
• In such manufacturing method, even if a particle of copper comes from[0081]conductive layer5 when etchingbarrier layer6 in the step shown in FIG. 12, the particle of copper adheres to a side surface ofhole pattern24a. Thus, diffusion of copper into silicon dioxide forming insulatinglayer7 is prevented, and insulating characteristic of insulatinglayer7 is not impaired.
• Third Embodiment[0082]
• In a semiconductor device according to a third embodiment of the present invention shown in FIG. 13, barrier layers[0083]31 and32 are formed as fourth and fifth diffusion preventing layers including tantalum nitride having a thickness of about 20 nm in contact with a side surface of a throughhole8 and anupper surface7aof an insulatinglayer7, respectively. In this respect, the semiconductor device shown in FIG. 13 is different from that shown in FIG. 1. Other parts of the structure of the semiconductor device in FIG. 13 are similar to those in FIG. 1.
• The semiconductor device having the above mentioned structure provides a similar effect as that shown in FIG. 1. A method of manufacturing the semiconductor device shown in FIG. 13 will now be described. Referring to FIG. 14, an insulating[0084]layer2 is formed on asilicon substrate1 as in the first embodiment. Atrench3 is formed in insulatinglayer2, and barrier andconductive layers4 and5 are formed intrench3. Abarrier layer6 is formed to cover insulatinglayer2,barrier layer4 andconductive layer5. An insulatinglayer7 is formed onbarrier layer6.Barrier layer32 including tantalum nitride and having a thickness of about 20 nm is formed on insulatinglayer7 by sputtering. A resistpattern33 having a prescribed pattern is formed onbarrier layer32. Etching barrier and insulatinglayers32 and7 in accordance with resistpattern33 forms a throughhole8 leading tobarrier layer6.
• Referring to FIG. 15, a[0085]barrier layer31 including tantalum nitride and having a thickness of about 20 nm is formed by CVD to coverbarrier layer32, a side surface of throughhole8 andbarrier layer6.
• Referring to FIG. 16, sputter[0086]etching barrier layer31 using argon leavesbarrier layer31 only on the side surface of throughhole8, so thatbarrier layer6 is exposed andbarrier layer31 onbarrier layer32 is removed.
• Referring to FIG. 17, barrier layer[0087]61 is etched using CF gas. Thus, anopening11 is formed inbarrier layer6 and a surface ofconductive layer5 is exposed.
• Referring to FIG. 13, a[0088]conductive layer10 including copper is formed by CVD to fill throughhole8. Thus, the semiconductor device shown in FIG. 13 is obtained.
• According to the above described manufacturing method, as in the manufacturing method shown in the first embodiment, diffusion of a particle of copper into insulating[0089]layer7 when etchingbarrier layer6 is prevented, and insulating characteristic of insulatinglayer7 is not impaired.
• Fourth Embodiment[0090]
• In a semiconductor device according to a fourth embodiment of the present invention shown in FIG. 18, two barrier layers, that is, barrier layers[0091]41 and42, are formed in a throughhole8. In this respect, it is different from the semiconductor device shown in FIG. 1 in which only onebarrier layer9 is formed in throughhole8. Further, in the semiconductor device shown in FIG. 18, abarrier layer42 including tantalum nitride is formed betweenconductive layers10 and5. In this respect also, it is different from the semiconductor device shown in FIG. 1 in whichconductive layers5 and10 are directly in contact with each other. Other parts of the structure of the semiconductor device shown in FIG. 18 are similar to those of the semiconductor device shown in FIG. 1.
• The semiconductor device having the above mentioned structure provides a similar effect as that of the semiconductor device in FIG. 1. As two barrier layers are formed on the side surface of through[0092]hole8, diffusion of copper ofconductive layer10 filled in throughhole8 into an insulatinglayer7 is more effectively prevented.
• A method of manufacturing the semiconductor device shown in FIG. 18 will now be described. Referring to FIG. 19, an insulating[0093]layer2 is formed on asilicon substrate1 as in the first embodiment. Atrench3 is formed in insulatinglayer2, and barrier andconductive layers4 and5 are formed to cover a surface oftrench3. Abarrier layer6 is formed to cover insulatinglayer2,barrier layer4 andconductive layer5, and an insulatinglayer7 is formed onbarrier layer6. A resist pattern having a prescribed pattern is formed on insulatinglayer7. Etching insulatinglayer7 in accordance with the resist pattern forms a throughhole8 leading tobarrier layer6. Abarrier layer41 including tantalum nitride having a thickness of about 20 nm is formed by CVD to cover the side surface of throughhole8, anupper surface7aof insulatinglayer7 andbarrier layer6.
• Referring to FIG. 20, an entire surface of[0094]barrier layer41 is etched back by sputter etching using argon. Thus,barrier layer41 is left only on the side surface of throughhole8,barrier layer6 is exposed, andbarrier layer41 formed onupper surface7aof insulatinglayer7 is removed.
• Referring to FIG. 21,[0095]barrier layer6 is etched using CF gas. Thus, anopening11 is formed andconductive layer5 is exposed.
• Referring to FIG. 22, a[0096]barrier layer42 including tantalum nitride having a thickness of about 20 nm is formed by CVD to coverbarrier layer41, andupper surface7aof insulatinglayer7.
• Referring to FIG. 18, a[0097]conductive layer10 including copper is formed by CVD, so that the semiconductor device shown in FIG. 18 is obtained.
• As in the first embodiment, in the above described manufacturing method of the semiconductor device, even if a particle of copper comes from[0098]conductive layer5 when etchingbarrier layer6 in the step shown in FIG. 21, diffusion of the particle of copper into insulatinglayer7 is prevented bybarrier layer41. Thus, insulating characteristic of insulatinglayer7 is not impaired.
• Fifth Embodiment[0099]
• In a semiconductor device according to a fifth embodiment of the present invention shown in FIG. 23, an insulating[0100]layer52 is formed on an insulatinglayer7 with abarrier layer51 interposed, and ahole54 is formed in insulatinglayer52. In this respect, the semiconductor device shown in FIG. 23 is different from that shown in FIG. 1. In addition, a throughhole56 is formed to communicate withhole54, and abarrier layer53 having a thickness of about 20 nm and including tantalum nitride is formed on side surfaces ofhole54 and throughhole56. Aconductive layer55 including copper is formed to cover throughhole56 andhole54.
• The semiconductor device having the above described structure provides a similar effect as that of the semiconductor device according to the first embodiment. In addition, another conductive layer can be formed in[0101]hole54.
• A method of manufacturing the semiconductor device shown in FIG. 23 will now be described. Referring to FIG. 24, an insulating[0102]layer2 is formed on asilicon substrate1. Atrench3 is formed in insulatinglayer2, and barrier andconductive layers4 and5 are formed to cover a surface oftrench3. Abarrier layer6 is formed to cover insulatinglayer2,barrier layer4 andconductive layer5, on which an insulatinglayer7 is further formed. Abarrier layer51 including silicon nitride having a thickness of about 20 nm is formed on insulatinglayer7 by CVD. An insulatinglayer52 including silicon dioxide having a thickness of about 0.1 μm is formed onbarrier layer51 by CVD. A resist pattern58 having a prescribed pattern is formed on insulatinglayer52. Insulatinglayer52,barrier layer51 and insulatinglayer7 are etched in accordance with resist pattern58. Thus, a throughhole56 is formed which exposesbarrier layer6.
• Referring to FIG. 25, a resist[0103]pattern59 having a prescribed pattern is formed on insulatinglayer52. Insulatinglayer52 is etched in accordance with resistpattern59. Thus, ahole54 is formed.
• Referring to FIG. 26, a[0104]barrier layer53 including tantalum nitride is formed by sputtering. Thicknesses ofbarrier layer53 are about 20 nm, 40 nm, 60 nm and 20 nm onbarrier layer6,barrier layer51, insulatinglayer52 and side surfaces ofhole54 and throughhole56, respectively.
• Referring to FIG. 27, an entire surface of[0105]barrier layer53 is etched back by sputter etching using argon. Thus,barrier layer6 is exposed, and a thickness of the other portion ofbarrier layer53 would be about 20 nm.
• Referring to FIG. 28,[0106]barrier layer6 is etched by CF gas. Thus, anopening11 is formed, so that a surface ofconductive layer5 is exposed.
• Referring to FIG. 23, a[0107]conductive layer55 including copper is formed by CVD to fill throughhole56 andhole54. Thus, the semiconductor device shown in FIG. 23 is obtained.
• In the manufacturing method of the semiconductor device having the above described structure, as in the first embodiment, even if a particle of copper comes from[0108]conductive layer5 when etchingbarrier layer6 in the step shown in FIG. 28, diffusion of the particle into insulatinglayer7 is prevented bybarrier layer53. Thus, conductivity of insulatinglayer7 is not reduced.
• Although the embodiments of the present invention have been described, various modifications can be made to be embodiments. For example, although[0109]hole54 is formed after formation of throughhole56 in the fifth embodiment,hole54 may first be formed, followed by throughhole56. In addition, barrier layers4,9,31,32,41,42 and53 may include tantalum or titanium nitride. Further, a thickness, material or the like can suitably be changed as desired.
• Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.[0110]

Claims (13)

What is claimed is:

1. A semiconductor device, comprising:

a first insulating layer having a recess and formed on a surface of a semiconductor substrate;

a first diffusion preventing layer formed on a surface of said recess;

a first conductive layer formed on a surface of said first diffusion preventing layer to fill said recess;

a second diffusion preventing layer formed on a surface of said first insulating layer and having an opening exposing a surface of said first conductive layer;

a second insulating layer formed on a surface of said second diffusion preventing layer to expose said surface of said first conductive layer and a part of the surface of said second diffusion preventing layer and having a first hole communicating with said opening;

a third diffusion preventing layer formed on a side surface of said first hole and on said second insulating layer in contact with an upper surface of said second diffusion preventing layer; and

a second conductive layer filling said opening and said first hole in contact with said first conductive layer.

2. The semiconductor device according to

claim 1

, wherein a diameter of said first hole is larger than a diameter of said opening.

3. The semiconductor device according to

claim 1

, wherein said third diffusion preventing layer includes a fourth diffusion preventing layer formed on said side surface of said first hole and a fifth diffusion preventing layer formed on said second insulating layer.

4. The semiconductor device according to

claim 1

, further comprising a fourth diffusion preventing layer formed on a portion of said third diffusion preventing layer on said side surface of said first hole.

5. The semiconductor device according to

claim 1

, further comprising a third insulating layer formed on said second insulating layer and including a second hole communicating with said first hole,

said third diffusion preventing layer being formed on side surfaces of said first and second holes and on said third insulating layer.

6. The semiconductor device according to

claim 1

, wherein said first and second conductive layers include copper, and said first and second insulating layers include silicon dioxide.

7. The semiconductor device according to

claim 1

, wherein said first and third diffusion preventing layers include at least one material selected from a group of titanium nitride, tantalum and tantalum nitride, and said second diffusion preventing layer includes silicon nitride.

8. A method of manufacturing a semiconductor device, comprising the steps of:

forming a first insulating layer having a recess on a semiconductor substrate;

forming a first diffusion preventing layer on a surface of said recess;

forming a first conductive layer on a surface of said first diffusion preventing layer to fill said recess;

forming a second diffusion preventing layer on surfaces of said first conductive layer and said first insulating layer;

forming a second insulating layer on a surface of said second diffusion preventing layer;

selectively removing said second insulating layer to form a first hole exposing a portion of said second diffusion preventing layer;

forming a third diffusion preventing layer on a side surface of said first hole in contact with an upper surface of said second diffusion preventing layer;

removing said exposed portion of said second diffusion preventing layer using said second insulating layer and said third diffusion preventing layer as masks to form an opening communicating with said first hole and exposing a portion of said first conductive layer; and

filling said opening and said first hole to form a second conductive layer in contact with said first conductive layer.

9. The method of manufacturing the semiconductor device according to

claim 8

, wherein said step of forming said third diffusion preventing layer includes forming a third diffusion preventing layer on a surface of said exposed portion of said second diffusion preventing layer, on said side surface of said first hole and on said second insulating layer, and said method further comprises the step of removing a portion of said third diffusion preventing layer on the surface of the portion of said second diffusion preventing layer to expose the portion of said second diffusion preventing layer.

10. The method of manufacturing the semiconductor device according to

claim 8

, wherein said step of forming said first hole includes forming a first hole having a diameter larger than a width of said first conductive layer, and

said step of forming said opening includes forming a resist pattern with a hole pattern having a diameter equal to or smaller than said width of said first conductive layer on a surface of said second diffusion preventing layer to expose a portion of said second diffusion preventing layer on said first conductive layer and removing said exposed portion of said second diffusion preventing layer using said resist pattern as a mask.

11. The method of manufacturing the semiconductor device according to

claim 8

, further comprising the step of forming a fourth diffusion preventing layer on a surface of said second insulating layer, and wherein

said step of forming said first hole includes selectively removing said fourth diffusion preventing layer and said second insulating layer to form said first hole.

12. The method of manufacturing the semiconductor device according to

claim 8

, further comprising the step of forming a fourth diffusion preventing layer on the surface of the portion of said first conductive layer exposed by removing said second diffusion preventing layer, on a surface of said third diffusion preventing layer and on the surface of said second insulating layer, and wherein

said step of forming said second conductive layer includes filling said opening and said first holes to form said second conductive layer in contact with said diffusion preventing layer.

13. The method of manufacturing the semiconductor device according to

claim 8

, further comprising the steps of:

forming a third insulating layer on a surface of said second insulating layer; and

selectively removing said third insulating layer to form a second hole in said third insulating layer.

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