US20010045579A1 - Semiconductor device with reduced current consumption in standby state - Google Patents

Abstract

A logic portion outputs to a DRAM portion a start address and an end address indicating a memory region where data to be stored is present prior to transition to power down mode having reduced current consumption. In the power down mode, a refresh control unit holds the start address and the end address and controls refresh to be carried out for data only in a region requiring refresh. The power supply of the logic portion is set in off state in the power down mode and accordingly a semiconductor device can consume reduced current while holding data.

Description

BACKGROUND OF THE INVENTION
• 1. Field of the Invention[0001]
• The present invention generally relates to semiconductor devices, and particularly to reduction of current consumption in standby state of a semiconductor device having therein a dynamic semiconductor memory device requiring refresh.[0002]
• 2. Description of the Background Art[0003]
• Recently, as personal digital assistants have widely been used, a semiconductor memory device is required to have smaller size and lower power consumption. The semiconductor memory device is often employed being integrated on one chip with a microcomputer and a large-sized logic circuit. An integrated circuit on which various circuits of such large size are mounted to implement system-on-chip is herein referred to as system LSI.[0004]
• A conventional structure of a semiconductor memory device is first described before discussion on reduction in supply current consumption of the system LSI.[0005]
• FIG. 35 is a schematic block diagram showing a structure of a conventional[0006]semiconductor memory device1000.
• Referring to FIG. 35,[0007]semiconductor memory device1000 includes an external clocksignal input terminal1116 receiving externally supplied complementary clock signals ext.CLK and ext./CLK,clock input buffers1084 and1085 buffering the clock signals supplied to external clocksignal input terminal1116, an internal control clock signal generatingcircuit1118 receiving respective outputs ofclock input buffers1084 and1085 to generate internal clock signal int.CLK, and amode decoder1120 receiving an external control signal supplied to an external controlsignal input terminal1110 via input buffers1012-1020 which operate according to internal clock signal int.CLK.
• External control[0008]signal input terminal1110 receives clock enable signal CKE, chip select signal /CS, row address strobe signal /RAS, column address strobe signal /CAS and write control signal /WE.
• Clock enable signal CKE is used to allow a control signal to be input to the chip. If this signal is not activated, input of the control signal is not permitted and[0009]semiconductor memory device1000 does not accept signal input from the outside.
• Chip select signal /CS is used for determining whether a command signal is input or not. When this signal is activated (at L level), a command is identified according to a combination of levels of other control signals at the rising edge of the clock signal.[0010]
• [0011]Mode decoder1120 outputs an internal control signal for controlling an operation of an internal circuit ofsemiconductor memory device1000 according to these external control signals.Mode decoder1120 outputs, as internal control signals, signal ROWA, signal COLA, signal ACT, signal PC, signal READ, signal WRITE, signal APC and signal SR.
• Signal ROWA indicates that row-related access is made, signal COLA indicates that column-related access is made, and signal ACT is used to instruct that a word line is activated.[0012]
• Signal PC specifies precharge operation to end a row-related circuit operation. Signal READ instructs a column-related circuit to perform reading operation, and signal WRITE instructs the column-related circuit to perform writing operation.[0013]
• Signal APC specifies auto precharge operation. When the auto precharging operation is designated, precharge operation is automatically started simultaneously with the end of a burst cycle. Signal SR designates self refresh operation. When the self refresh operation starts, a self refresh timer operates. After a certain time passes, a word line is activated and the refresh operation starts.[0014]
• [0015]Semiconductor memory device1000 further includes aself refresh timer1054 which starts its operation when self refresh mode is designated by signal SR and then designates activation of a word line, i.e., start of the refresh operation when a certain time passes, and arefresh address counter1056 for generating a refresh address according to an instruction fromself refresh timer1054.
• [0016]Semiconductor memory device1000 further includes a referencepotential input terminal1022 receiving signal VREF which is to be used as a reference for determining whether an input signal is H or L level, amode register1046 holding an address signal supplied via an addresssignal input terminal1112 as well as information regarding a predetermined operation mode, for example, information regarding burst length according to a combination of external control signals described above, arow address latch1250 receiving address signals via address input buffers1032-1038 operating according to internal clock signal int.CLK2 to hold, when a row address is input, the input row address, acolumn address latch1550 receiving address signals A0-A12 to hold, when a column address is input, this column address, amultiplexer1058 receiving respective outputs fromrefresh address counter1056 androw address latch1250 to select the output fromrow address latch1250 in the normal operation and select the output fromrefresh address counter1056 in self refresh operation and accordingly output the selected one, and arow predecoder1136 receiving an output frommultiplexer1058 to predecode a row address.
• [0017]Semiconductor memory device1000 further includes aburst address counter1060 generating an internal column address according to burst length data frommode register1046 based on the column address held incolumn address latch1550, acolumn predecoder1134 receiving an output ofburst address counter1060 to predecode a corresponding column address, abank address latch1052 receiving bank addresses BA0-BA2 supplied to an address input terminal via input buffers1040-1044 which operate according to internal clock signal int.CLK, and abank decoder1122 receiving an output ofbank address latch1052 to decode a bank address.
• The address signal supplied to address[0018]signal input terminal1112 is also used for writing data in the mode register by a combination of any bits when operation mode information is written into the mode register. For example, burst length BL, value of CAS latency CL and the like are designated by a combination of a predetermined number of bits of an address signal.
• Bank address signals BA[0019]0-BA2 designate an access bank in each of the row-related access and the column-related access. Specifically, in the row-related access and the column-related access each, bank address signals BA0-BA2 supplied to address signal input buffers1040-1044 are taken bybank address latch1052 and then decoded bybank decoder1122 to be transmitted to each memory array block (bank).
• In addition,[0020]semiconductor memory device1000 includes memory array blocks100a-100grespectively serving as banks0-7 each for independent reading/writing operation, arow decoder1244 for selecting a row (word line) in a corresponding bank according to respective outputs frombank decoder1122 androw predecoder1136, acolumn decoder1242 for selecting a column (bit line pair) in a corresponding bank according to an output fromcolumn predecoder1134, an I/O port1266 supplying data read from a selected memory cell in a selected bank to a global I/O bus G-I/O in reading operation and supplying write data transmitted by bus G-I/O to a corresponding bank in writing operation, a data input/output circuit1086 holding externally supplied write data and supplying it to bus G-I/O in writing operation and holding read data transmitted by bus G-I/O in reading operation, and bidirectional input/output buffers1072-1082 for transmitting input/output data DQ0-DQ31 between data input/output circuit1086 and data input/output terminal1070.
• Bidirectional input/output buffers[0021]1072-1082 operate in synchronization with the internal clock signal according to operation mode data held inmode register1046.
• FIG. 36 illustrates power supply potential applied from the outside to a conventional system LSI.[0022]
• Referring to FIG. 36, the system LSI includes a chip CH on which a logic portion LG and a DRAM portion MEM are mounted. The DRAM portion includes a power supply generating circuit VGEN[0023]1 generating boosted potential VPP and a power supply generating circuit VGEN2 generating substrate potential VBB.
• The logic portion LG receives supply potential LVDDH of 3.3V applied from the outside via a terminal T[0024]50 and potential LVDDL of 1.5V applied via a terminal T51. The DRAM portion MEM receives supply potential DVDDH of 3.3V applied from the outside via a terminal T52 and supply potential DVDDL of 1.5V applied via a terminal T53.
• In such a system LSI, in order to cut supply current consumption in the standby state while data stored in a memory cell of the DRAM portion MEM is maintained, supply potentials LVDDH and LVDDL applied to the logic portion LG are set at 0V to stop power supply current from being applied. In this way, current consumption in the logic portion LG in the standby state is reduced.[0025]
• Preferably personal digital assistants and the like can be operated by a battery as long as possible. In order to achieve this, power consumption of the system LSI should be reduced as much as possible.[0026]
• The DRAM portion included in the system LSI requires refresh operation even in the standby state in order to preserve data stored in a memory cell. The refresh operation is carried out in every one cycle at regular intervals, or all of memory cells are successively refreshed and this successive refresh is carried out at regular intervals. In any case, during the period in which the refresh operation is performed, any circuit operation is carried out in the DRAM portion, which accompanies leakage current upon activation of a transistor. The leakage current in operation and in standby state increases as threshold voltage of an employed MOS transistor is decreased in order to accelerate the speed of operation and to lower the power supply potential. As a result, current consumption of the entire device increases.[0027]
• FIG. 37 illustrates power supply potential applied to peripheral circuitry of the DRAM portion MEM shown in FIG. 36.[0028]
• Referring to FIGS. 36 and 37, power supply potential DVDDL applied to the DRAM portion MEM is provided to a[0029]clock control unit1402, a row-relatedcommand control unit1404, a column-relatedcommand control unit1406, a row-relatedaddress control unit1408, a bankaddress control unit1410, a column-relatedaddress control unit1412, an input/output data-related control unit1414 and a self refresh-related control unit1416. Supply potential DVDDL is also applied from the outside to the peripheral circuitry except for the memory array portion shown in FIG. 36 in the conventional device. For this reason, a considerable leakage current is generated in the standby state in any circuit which is unnecessary in the refresh operation, for example, input/output data-related control unit1414 and the like.
SUMMARY OF THE INVENTION
• One object of the present invention is to provide a semiconductor device having a power down mode which enables power supply current to be consumed less while information stored in a DRAM portion is preserved in standby state.[0030]
• The present invention, in brief, is a semiconductor device transmitting/receiving data in a normal mode and performing refresh of stored data with reduced current consumption in the power down mode. The semiconductor device includes a memory array, a first peripheral circuit and a second peripheral circuit.[0031]
• The memory array includes a plurality of memory cells arranged in a matrix of rows and columns. The first peripheral circuit inputs/outputs data to be stored in a memory cell in the normal mode. The first peripheral circuit stops its operation for reducing current consumption in the power down mode. The second peripheral circuit controls refreshing of data held in a memory cell in the power down mode.[0032]
• Accordingly, a major advantage of the present invention is that reduction of current consumption is possible by stopping the first peripheral circuit from operating in the power down mode.[0033]
• The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.[0034]
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a schematic block diagram showing a structure of a[0035]semiconductor device1 according to a first embodiment of the invention.
• FIG. 2 is a block diagram showing a structure of a[0036]refresh control unit132 in FIG. 1.
• FIG. 3 is a circuit diagram illustrating a hierarchical power supply structure.[0037]
• FIG. 4 is a waveform chart illustrating an operation of a circuit having the hierarchical power supply structure shown in FIG. 3.[0038]
• FIG. 5 is a block diagram showing a first example of an[0039]address counter312 in FIG. 2.
• FIG. 6 is an operation waveform chart illustrating an operation of[0040]address counter312 shown in FIG. 5.
• FIG. 7 is a block diagram showing a structure of an[0041]address counter312awhich is a modification ofaddress counter312.
• FIG. 8 is an operation waveform chart illustrating an operation of[0042]address counter312ain FIG. 7.
• FIG. 9 illustrates that power supply is externally provided to a semiconductor device according to a second embodiment.[0043]
• FIG. 10 shows a structure in which power supply potential is applied to an internal circuit of a DRAM portion shown in FIG. 9.[0044]
• FIG. 11 illustrates a first example of grouping peripheral circuits PCKT[0045]1 and PCKT2 shown in FIG. 10.
• FIG. 12 illustrates a second example of grouping peripheral circuits.[0046]
• FIG. 13 illustrates a third example of grouping peripheral circuits.[0047]
• FIG. 14 is a schematic showing a structure of a memory array.[0048]
• FIG. 15 illustrates a structure of a boundary portion inactivating an I/O line used for writing operation by stopping power supply.[0049]
• FIG. 16 is a circuit diagram showing a structure of a flip-[0050]flop1172ain FIG. 15.
• FIG. 17 illustrates that power supply is applied preceding and following a[0051]read amplifier1154 in FIG. 14.
• FIG. 18 is a circuit diagram showing a structure of[0052]read amplifier1154 and an equalizecircuit528 in FIG. 17.
• FIG. 19 is a block diagram illustrating that a transistor having a high threshold is used for a part of a block for the purpose of reducing power consumption of a refresh control-related portion.[0053]
• FIG. 20 is a circuit diagram showing a circuit structure for multiplexing an address in a normal operation and an address in a self refresh.[0054]
• FIG. 21 is a circuit diagram showing a second structure for multiplexing addresses.[0055]
• FIG. 22 is a circuit diagram showing a structure of a level converting circuit.[0056]
• FIG. 23 is a circuit diagram showing a structure of a[0057]selection circuit620 in FIG. 21.
• FIG. 24 is a circuit diagram showing a structure of a first[0058]level converting circuit660 for level converting from 1.5V to 3.3V.
• FIG. 25 is a circuit diagram showing a structure of a[0059]level converting circuit680 as a second example of level conversion.
• FIG. 26 is a circuit diagram showing a structure of a[0060]level converting circuit710 as a third example of level conversion.
• FIG. 27 is a circuit diagram showing a structure of a column selection[0061]line fixing circuit730.
• FIG. 28 is a circuit diagram showing a structure of a column selection[0062]line fixing circuit740 as a second example for fixing a column selection line.
• FIG. 29 is a circuit diagram showing a structure of a column selection[0063]line fixing circuit757 as a third example for fixing a column selection line.
• FIG. 30 is a block diagram showing a structure of a[0064]semiconductor device800 according to a third embodiment.
• FIG. 31 is a circuit diagram showing a structure of a DRAM[0065]power supply circuit810 in FIG. 30.
• FIG. 32 is a circuit diagram showing a structure of a clock/[0066]reset control circuit806 in FIG. 30.
• FIG. 33 is an operation waveform chart illustrating a power down mode of the DRAM portion of the semiconductor device in FIG. 30.[0067]
• FIG. 34 is a waveform chart illustrating an operation of returning from the power down mode in FIG. 33 to an operation mode.[0068]
• FIG. 35 is a schematic block diagram showing a structure of a conventional[0069]semiconductor memory device1000.
• FIG. 36 illustrates supply potential applied from the outside to the conventional system LSI.[0070]
• FIG. 37 illustrates power supply potential applied to a peripheral circuit of the DRAM portion MEM in FIG. 36.[0071]
DESCRIPTION OF THE PREFERRED EMBODIMENTS
• Embodiments of the present invention are hereinafter described in conjunction with the drawings.[0072]
• First Embodiment[0073]
• FIG. 1 is a schematic block diagram showing a structure of a[0074]semiconductor device1 according to the first embodiment of the invention.
• Referring to FIG. 1,[0075]semiconductor device1 includes a large-sized logic portion2 coupled to a group of external pin terminals PG to carry out designated processing, and aDRAM portion4 coupled tologic portion2 via internal interconnection to store data required bylogic portion2.Logic portion2 outputs toDRAM portion4, clock signals CLK and /CLK, control signals CKE, /CS, /RAS, /CAS, and /WE, reference potential Vref for taking data in, row address signals RA0-RA12, column address signals CA0-CA10, and bank address signals BA0-BA2.Logic portion2 andDRAM portion4 transmit and receive data signals DQ0-DQ31.
• If[0076]logic portion2 andDRAM portion4 are integrated on one chip, it is easier to increase the number of signal lines for data transmission compared with a logic portion and a DRAM portion mounted on separate chips. Therefore, the structure in FIG. 1 does not have so-called address pin multiplexing and has separate lines for column address and row address transmitted from the logic portion to the DRAM portion.
• [0077]DRAM portion4 includes clock input buffers50 and52 buffering complementary clock signals CLK and /CLK supplied fromlogic portion2, an internal control clocksignal generating circuit118 receiving respective outputs of clock input buffers50 and52 to output internal clock signal int.CLK, input buffers12-20 receiving control signals CKE, /CS, /RAS, /CAS and /WE according to internal clock signal int.CLK, and amode decoder120 receiving control signals via input buffers12-20 to output an internal control signal for controlling an operation of an internal circuit.
• Clock enable signal CKE is used for permitting input of a control signal to the chip. If the clock enable signal is not activated, input of the control signal is not allowed and[0078]DRAM portion4 does not transmit and receive data to and from the logic portion.
• Chip select signal /CS is used for determining if a command signal is supplied or not. During the period in which this signal is activated (L level), a command is identified according to a combination of levels of other control signals at the rising edge of the clock signal.[0079]
• [0080]Mode decoder120 outputs as internal control signals, for example, signal ROWA, signal COLA, signal ACT, signal PC, signal READ, signal WRITE, signal APC and signal SR.
• Signal ROWA indicates that row-related access is made, signal COLA indicates that column-related access is made, and signal ACT is a signal for designating activation of a word line.[0081]
• Signal PC specifies precharge operation to instruct that row-related circuit operation is completed. Signal READ instructs a column-related circuit to perform reading operation, and signal WRITE instructs a column-related circuit to perform writing operation.[0082]
• Signal APC designates auto precharge operation. When the auto precharge operation is designated, precharge operation is automatically started simultaneously with the end of a burst cycle. Signal SR specifies self refresh operation. For example, when a combination of control signals designating a self refresh mode is supplied from the logic portion in a standby mode, the self refresh signal SR is generated. Accordingly, the self refresh operation is started, a self refresh timer operates, and a word line is activated after a certain time passes and accordingly the refresh operation is started.[0083]
• [0084]DRAM portion4 further receives reference potential VREF used as a reference for determining whether an input signal is H level or L level.
• [0085]DRAM portion4 further includes amode register122 holding information regarding a predetermined operation mode according to a combination of an address signal and a control signal supplied from the logic portion, for example, information regarding burst length, arow address latch124 receiving and holding row address signals RA0-RA12 from the logic portion, acolumn address latch126 receiving and holding column address signals CA0-CA10 supplied from the logic portion, arow predecoder140 receiving an output fromrow address latch124 to predecode a row address, a burst address counter134 generating an internal column address according to data on the burst length frommode register122 using as a reference the column address held incolumn address latch126, acolumn predecoder142 receiving an output from burst address counter134 to predecode a corresponding column address, abank address latch128 receiving bank addresses BA0-BA2 supplied from the logic portion via input buffers40-44 operating according to internal clock signal int.CLK to hold a designated bank address value, and abank decoder136 receiving an output ofbank address latch128 to decode a bank address.
• Address signals supplied from the logic portion are used for writing data into the mode register according to a combination of several bits. For example, values of burst length BL, CAS latency CL and the like are designated according to a combination of a predetermined number of bits of an address signal.[0086]
• Bank address signals BA[0087]0-BA2 designate respective access banks in row-related access and column-related access. Specifically, in each of the row-related access and the column-related access, bank address signals BA0-BA2 supplied from thelogic portion2 are taken bybank address latch128, decoded bybank decoder136 and thereafter transmitted to each memory array block (bank).
• [0088]DRAM portion4 further includes arefresh control unit132 receiving an address signal from the logic portion and signal SR designating the self refresh mode to control the refresh, and amultiplexer144 for switching between a row-related control signal and a bank designation signal output fromrefresh control unit132 and respective outputs ofrow predecoder140 andbank decoder136 according to signal SR.
• [0089]DRAM portion4 further includes memory array blocks100a-100gserving as respective banks0-7 where reading/writing operation can be performed separately, arow decoder244 for selecting a row (word line) in a corresponding bank according to an output ofmultiplexer144, acolumn predecoder242 for selecting a column (bit line pair) in a corresponding bank according to an output ofcolumn predecoder142, an I/O port266 supplying data read from a selected memory cell in a selected bank to a global I/O bus G-I/O in reading operation and supplying write data transmitted by bus GI/O to a corresponding bank in writing operation, a data input/output circuit130 holding write data supplied from the outside to supply it to bus G-I/O in writing operation and holding read data transmitted by bus G-I/O in reading operation, and data input/output buffers72-78 for transmitting and receiving input/output data DQ0-DQ31 between data input/output circuit130 andlogic portion2.
• [0090]DRAM portion4 further includes aVDC circuit138 receiving supply potential VDDH of 3.3V from the outside to output supply potential VDD2 of 2.0V for example.
• FIG. 2 is a block diagram showing a structure of[0091]refresh control unit132 shown in FIG. 1.
• Referring to FIG. 2, refresh[0092]control unit132 includes atimer302 receiving self refresh signal SR frommode decoder120 in FIG. 1 to measure a standby period of refresh when the mode is changed to self refresh mode, a triggerpulse generating circuit304 outputting trigger pulse TRIG according to an output oftimer302, acyclic timer306 outputting cycle signal CYCLE determining a cycle of word line activation in refresh according to trigger pulse TRIG, an RASclock generating circuit308 outputting row-related operation reference clock signal RASCK according to cycle signal CYCLE, and adelay circuit310 for control outputting signals EQ, MWL, SO and PC at predetermined timing using clock signal RASCK as a reference.Control delay circuit310 outputs signals EQ, MWL, SO and PC when internal enable signal IEN is activated.
• Signal EQ indicates an equalize period of a bit line, signal MWL indicates an activation period of a main word line, signal SO indicates an activation period of a sense amplifier, and signal PC indicates a precharge period.[0093]
• [0094]Refresh control unit132 further includes anaddress counter312 which is reset according to reset signal PON and self refresh reset signal SRRST when the power is made on, receives start address SADR and end address EADR from the logic portion, and increments an address according to clock signal RASCK.Address counter312 outputs refresh address ReADR to the memory array and outputs timer reset signal TRST totimer302 when one cycle of address count is completed.
• [0095]Timer302 inrefresh control unit132 is not required to operate speedily. Therefore,timer302 is constituted of a transistor having a high threshold and has small leakage current even in operation. When the timer circuit portion detects time, trigger pulse TRIG is generated and address counter312 starts its operation according to trigger signal TRIG.Address counter312 is constituted of a transistor operating with a low threshold. However, in order to cut leakage current prior to detection of time bytimer302, standby state is started by a reset signal.Address counter312 employs hierarchical power supply structure described below and can reduce the leakage current in the standby state.
• FIG. 3 is a circuit diagram illustrating the hierarchical power supply structure.[0096]
• Referring to FIG. 3, five stages of inverters IV[0097]1-IV5 connected in series are shown as internal circuits. Input signal IN supplied to the first stage inverter IV1 is at L level in standby cycle. Inverters IV1-IV5 have the same structure and each include a P channel MOS transistor PT and an N channel MOS transistor NT. These MOS transistors PT and NT are low-threshold voltage (L-Vth) MOS transistors having a small absolute value of threshold voltage.
• For these inverters IV[0098]1-IV5, there are provided amain supply line321 receiving supply potential Vcc, asub supply line323 coupled tomain supply line321 via a P channel MOS transistor PQ for leakage cut, amain ground line322 transmitting ground potential Vss, and asub ground line324 connected tomain ground line322 via an N channel MOS transistor NQ for leakage cut. Leakage cut MOS transistors PQ and NQ are constituted of respective MOS transistors each having an absolute value of the threshold voltage (M-Vth) greater than the absolute value of the threshold voltage of MOS transistors PT and NT.
• MOS transistor PQ has its gate receiving control signal /φ, and MOS transistor NQ has its gate receiving control signal φ. Control signal φ is at H level in an active cycle in which an internal circuit operates. Control signal φ is at L level in a standby cycle in which the internal circuit is on standby. On the other hand, control signal /φ is at L level in the active cycle and at H level in the standby cycle.[0099]
• In each of inverters IV[0100]1, IV3, IV5 . . . in the stages of odd numbers in the internal circuits, the source of P channel MOS transistor PT is connected tomain supply line321 and the source of N channel MOS transistor NT is connected to subground line324. In inverters IV2, IV4 . . . of the even number stages, the source of P channel MOS transistor PT is connected to subsupply line323 and the source of N channel MOS transistor NT is connected tomain ground line322.
• FIG. 4 is a waveform chart illustrating an operation of a circuit having the hierarchical power supply structure shown in FIG. 3.[0101]
• Referring to FIGS. 3 and 4, in the standby cycle, control signal φ is at L level and control signal /φ is at H level. Input signal IN is at L level. In this state, leakage cut MOS transistors PQ and NQ are in off state.[0102]
• Inverters IV[0103]1, IV3 and IV5 of the odd number stages each have input signal IN at L level. Therefore, P channel MOS transistor PT is in on state while N channel MOS transistor NT is in off state. P channel MOS transistor PT has its source connected tomain supply line321 and N channel MOS transistor NT has its source connected to subground line324.
• When P channel MOS transistor PT is turned on and accordingly voltage of supply potential Vcc level on[0104]main supply line321 is transmitted to a corresponding output node (drain), the drain potential becomes equal to the source potential and no current flows.
• On the other hand, N channel MOS transistor NT receives a signal of L level at its gate and accordingly is turned off. In this state, when there is a potential difference of at least a certain value between the source coupled to the sub ground line and the drain, off-leakage current is generated.[0105]Sub ground line324 is connected tomain ground line322 via leakage cut MOS transistor NQ having a relatively high threshold voltage M-Vth. Therefore, even if the off-leakage current flows from inverters IV1, IV3 and IV5 . . . to subground line324, leakage cut MOS transistor NQ cannot discharge all of this off-leakage current. Consequently, voltage level SVss onsub ground line324 becomes higher than ground potential Vss.
• Potential SVss on[0106]sub ground line324 is finally determined by a relation between the amount of leakage current discharged by leakage cut MOS transistor NQ and off-leakage current from inverter stage included in the internal circuit. When potential SVss onsub ground line324 becomes higher than ground potential Vss, the portion between the gate and source of N channel MOS transistor NT in each of inverters IV1, IV3, IV5 . . . of odd number stages is set into an inverse-bias state. In this case, the off-leakage current is further reduced.
• In inverters IV[0107]2, IV4 . . . of even number stages, input signal has H level. In these inverters IV2, IV4 . . . of even number stages, the source of P channel MOS transistor PT is connected to subpower supply line323 and the source of N channel MOS transistor NT is connected tomain ground line322. In inverters IV2, IV4 . . . of even number stages, the N channel MOS transistor has the same source and drain corresponding to ground potential Vss level. In the P channel MOS transistor PT, off-leakage current is generated even in the non-conducting state.
• Between[0108]main supply line321 andsub supply line323, leakage cut MOS transistor PQ having a relatively large absolute value (M-Vth) of threshold voltage is provided. The amount of leakage current frommain supply line321 to subsupply line323 is determined by leakage cut MOS transistor PQ and voltage SVcc onsub supply line323 drops lower than the level of supply potential Vcc level. The voltage level of SVcc onsub supply line323 is finally determined by a relation between leakage current supplied from leakage cut MOS transistor PQ and the total of off-leakage current in inverters IV2, IV4 . . . of even number stages. When voltage SVcc becomes lower than supply potential Vcc, in inverters IV2, IV4 . . . of even number stages, the portion between the gate and source of P channel MOS transistor PT is set into reverse-bias state and the off-leakage current is further reduced.
• In the active cycle, control signal φ has H level and control signal /φ has L level, leakage cut MOS transistors PQ and NQ are turned on,[0109]main supply line321 is connected to subsupply line323, andmain ground line322 is connected to subground line324.
• Accordingly, voltage SVcc on[0110]sub supply line323 has supply potential Vcc and potential SVss onsub ground line324 has ground potential Vss level. In this active cycle, input signal IN appropriately changes according to operation state. MOS transistors of inverters IV1-IV5 . . . constituting internal circuits are each a MOS transistor having low threshold voltage and operate at a high speed. Current supply capability of leakage cut MOS transistors PQ and NQ is set at a large value for ensuring the operation of this internal circuit.
• The hierarchical structure described above is thus realized by providing a main supply line and a sub supply line as supply lines and a main ground line and a sub ground line as ground lines. In this way, the impedance of supply line/ground line is increased to reduce the leakage current in the standby cycle, and the impedance of the supply line/ground line is reduced in the active cycle in order to achieve a high speed operation by MOS transistors having low threshold voltage in the internal circuits.[0111]Address counter312 in FIG. 2 can have such a hierarchical power supply structure so as to implement a semiconductor device having reduced current consumption in the standby period in which no refresh is performed in the power down mode and operates at a high speed in the refresh.
• In the standby period in which self refresh is carried out, MOS transistors PQ and NQ are turned off, substrate potential is made lower than the source potential of the transistor to further reduce the leakage current so that further reduction of the leakage current is realized. The leakage current can further be reduced by decreasing current supplied to a common source line of a sense amplifier in the memory array.[0112]
• FIG. 5 is a block diagram showing a first example of[0113]address counter312 in FIG. 2.
• Referring to FIG. 5,[0114]address counter312 includes alatch circuit332 receiving and holding start address SADR from the logic portion, alatch circuit334 receiving and holding end address EADR supplied from the logic portion, and acounter336 performing count-up operation according to clock signal RASCK from RASclock generating circuit308 in FIG. 2, outputs refresh address ReADR0, and outputs timer reset signal TRST at the end of one cycle of refresh addresses.
• [0115]Address counter312 further includes acomparison circuit338 comparing refresh address ReADR0 output fromcounter336 with start address SADR held bylatch circuit332 to activate an output when refresh address ReADR0 is equal to or greater than start address SADR, acomparison circuit340 comparing refresh address ReADR0 with end address EADR held bylatch circuit334 to activate an output when refresh address ReADR0 is equal to or smaller than end address EADR, an ANDcircuit342 receiving respective outputs ofcomparison circuits338 and340 to output internal enable signal IEN, and abuffer circuit344 receiving refresh address ReADR0 to output refresh address ReADR to the row decoder of the memory array when enable signal IEN is activated.
• FIG. 6 is an operation waveform chart illustrating an operation of[0116]address counter312 shown in FIG. 5.
• Referring to FIGS. 5 and 6, preceding input of a command at time t[0117]1, the DRAM portion is instructed by the logic portion to perform refresh before transition to power down mode. After time t1, internal clock signal CLK is fixed at L level according to decreasing of supply voltage of the logic portion and clock signal supplied to the DRAM portion is inactivated.
• At time t[0118]1, a command determined by a combination of control signals /CS, /RAS, /CAS and /WE specifies a power down mode.
• In the system LSI including therein the DRAM, input of an address from the outside is unnecessary. Therefore, even if the number of bits of an address signal supplied to the DRAM portion from the logic portion increases, the number of external terminals is not increased. Therefore, there is no need to employ so-called address pin multiplexing and a row address and a column address are transmitted by separate lines.[0119]
• A start address and an end address for designating a region to be refreshed are supplied from the logic circuit. In refresh, designation of a column address is unnecessary. The logic circuit thus supplies a refresh start address as row address signals RADD[0120]0-RADDn and supplies a refresh end address as column address signals CADD0-CADDn. Refresh is performed between the start address and the end address and no refresh operation is carried out for other addresses and they are skipped. These addresses may be specified by a bank address for example.
• The refresh start address SADR and refresh end address EADR are supplied from the logic portion to the DRAM portion when the logic portion uses the DRAM portion, prior to the power down mode, by recognizing a memory region where information should be held in transition to the power down mode. At time t[0121]1, when the refresh start address and the refresh end address are held inlatch circuits332 and334 inaddress counter312 of the DRAM portion, supply of the power supply voltage to the logic portion is stopped to reduce power consumption.
• When self refresh signal SR is input from[0122]mode decoder120 in FIG. 1 to refreshcontrol unit132, a reference clock is generated by a ring oscillator contained intimer302 in FIG. 2, transition to power down mode occurs after refresh in the normal operation and the standby period from the transition to the following refresh operation is measured.
• At time t[0123]2,timer302 supplies a predetermined output because that it is a predetermined time and accordingly triggerpulse generating circuit302 outputs trigger pulse TRIG.Cyclic timer306 then outputs cycle signal CYCLE in a period corresponding to the refresh cycle and accordingly clock signal RASCK is input to addresscounter312. Clock signal RASCK is input to counter336 ofaddress counter312 and counter336 successively outputs refresh address signal ReADR0. However, refresh operation is unnecessary for a memory region which holds no necessary information. For the purpose of reducing power consumption,comparison circuit338 andcomparison circuit340 determine whether refresh address signal ReADR0 generated currently bycounter336 is present between a start address and an end address and accordingly internal enable signal IEN is output.
• From time t[0124]2 to time t3, the refresh address signal is smaller than the start address. Therefore, an output ofbuffer circuit344 is inactivated and internal enable signal IEN is also inactivated.
• No refresh address is transmitted to the memory array and no control signal is transmitted from[0125]control delay circuit310. These signals have their levels fixed and current consumption is accordingly reduced by the amount of current for driving a signal line by these signals.
• At time t[0126]3, when refresh address ReADR0 output fromcounter336 and start address held bylatch circuit332 matches, an output ofcomparison circuit338 changes and internal enable signal IEN is accordingly activated so that execution of refresh is started.
• At time t[0127]4, when end address EADR held bylatch circuit334 and refresh address ReADR0 counted up bycounter336 according to clock signal RASCK match, an output ofcomparison circuit340 changes and accordingly internal enable signal IEN is inactivated. Then, refresh of a necessary region is completed and no refresh is carried out for subsequent addresses. At time t5, when addresses generated bycounter336 are all used, counter336 outputs timer reset signal TRST and the standby period is measured again bytimer302. In this standby period,address counter312 is set in a standby state in the hierarchical power supply structure described above.
• At time t[0128]6, whentimer302 indicates that the standby period has passed, trigger pulse TRIG is accordingly activated, and address counter312 changes to the active mode to start counting of a refresh address. At time t7, when the refresh address matches start address, refresh is carried out for a memory cell which stores information to be preserved.
• At time t[0129]8, clock enable signal CKE is activated to H level, power is applied to the logic circuit and clock signal CLK is input to the DRAM portion. Then, all memory areas are first refreshed by inserting a dummy cycle considering the case in which refresh is completed in the way in the power down mode. After this, data is transmitted and received again between the logic circuit portion and the DRAM portion.
• FIG. 7 is a block diagram showing a structure of an[0130]address counter312aas a modification ofaddress counter312.
• Referring to FIG. 7, address counter[0131]312ais different in the structure fromaddress counter312 in that anaddress detecting circuit352 and acomparison circuit354 are included instead ofcomparison circuits338 and340, ANDcircuit342 andbuffer circuit344. Other components are similar to those ofaddress counter312 and description thereof is not repeated here.
• When[0132]address detecting circuit352 receives start address SADR and end address EADR fromlatch circuits332 and334, it detects the ratio of an address region to be refreshed to the entire address region and outputs tocyclic timer306 in FIG. 2 cycle selection signal SELC for selecting a refresh cycle.
• In[0133]cyclic timer306, the number of stages of counter circuits included is changed according to cycle selection signal SELC so as to change the refresh cycle. According to this cycle, clock signal RASCK is input to counter336 and the cycle for counting up refresh address ReADR is changed. For example, if 4012 word line addresses are self-refreshed in32 ms, the period of clock signal RASCK can be made four times provided that the start address and end address are selected in the range of one-fourth of addresses of 4012 word lines. Refresh can be carried out at dispersed times and accordingly, the peak current can be reduced which is advantageous for reducing power consumption in the standby state.
• When refresh address ReADR output from counter[0134]336 matches end address EADR held bylatch circuit334,comparison circuit354 outputs timer reset signal TRST totimer302 in FIG. 3.
• FIG. 8 is an operation waveform chart illustrating an operation of[0135]address counter312ain FIG. 7.
• Referring to FIGS. 7 and 8, at time t[0136]1, a self refresh command as well as a refresh start and end addresses are input andtimer302 measures a standby period until time t2 as described in conjunction with FIG. 6.
• At time t[0137]2, trigger pulse TRIG is activated according to change of an output oftimer302. Then,cyclic timer306 generates cyclic pulse CYCLE according to refresh cycle selected byaddress detecting circuit352. Counter336 starts count up of refresh address ReADR from start address SADR received fromlatch circuit332. Different from the operation shown in FIG. 6, the period is extended by the ratio of the memory region skipped in the FIG. 6 and refresh is continued to the end address.
• At time t[0138]5, when the refresh address output from counter336 matches the end address, timer reset signal TRST is output fromcomparison circuit354, andtimer302 starts measuring the standby period again. In this period, the address counter is set in the standby mode.
• This structure is advantageous in that refresh period is extended to reduce the peak value of current consumption as long as the refresh interval of a memory cell is allowed, and accordingly power consumption can be reduced.[0139]
• Second Embodiment[0140]
• The first embodiment has been described according to which power consumption is reduced by decreasing the refresh region. It is also possible to cut the power consumption by employing a structure in which power is made off for a certain portion of the internal circuit of the DRAM portion in the power down mode, for example.[0141]
• FIG. 9 illustrates that power is externally supplied to a semiconductor device according to the second embodiment.[0142]
• Referring to FIG. 9, a semiconductor device CH has a logic portion LG and a DRAM portion MEM. In the DRAM portion, a voltage generating circuit VGEN[0143]1 for generating boosted potential VPP and a voltage generating circuit VGEN2 for generating substrate potential VBB are provided.
• Logic portion LG receives supply potential LVDDH of 3.3V via a terminal T[0144]1 and receives supply potential VDD of 1.5V via a terminal T2. Supply potential VDD is also applied to DRAM portion MEM. Supply potential DVDDH of 3.3V is applied to DRAM portion MEM via a terminal T3.
• In this semiconductor device, supply potentials LVDDH and VDD provided to logic portion LG are set in off state in the power down mode. DRAM portion MEM operates to refresh information held by a memory cell only by supply potential DVDDH in the power down mode.[0145]
• FIG. 10 shows a structure for providing supply potential to an internal circuit of the DRAM portion in FIG. 9.[0146]
• Referring to FIG. 10, for memory arrays ARY[0147]1 and ARY2 including memory cells for holding data arranged in a matrix of rows and columns in the DRAM portion, peripheral circuits PCKT1 and PCKT2 are provided for controlling their operations.
• The memory cell arrays operate with a high voltage and the peripheral circuit portions operate with 1.5V in the normal operation. Especially the peripheral circuit portions are often supplied with the same power source. Further, in order to operate them with a low voltage external power source, the threshold voltage or the like of a transistor constituting the peripheral circuit is reduced. In this case, a problem occurs that leakage current increases due to reduction of the threshold voltage. The leakage current also leads to power loss when power is being applied in non-operating state of the peripheral circuits.[0148]
• In order to reduce the leakage current, peripheral circuit PCKT[0149]1 operates by receiving from the outside supply potential VDD of 1.5V via supply lines L1 and L4. The power supply is made off in the power down mode and accordingly the leakage current is reduced.
• To the peripheral circuit PCKT[0150]2, supply potential VDD3 is continuously supplied in order to perform refresh operation or the like for memory arrays ARY1 and ARY2 even in the power down mode. Only the supply potential DVDDH of 3.3V is applied to the DRAM portion in the power down mode as shown in FIG. 9. Therefore, the DRAM portion generates supply potential VDD3 for operating peripheral circuit PCKT2 from supply potential DVDDH in the power down mode.
• Specifically, there are provided a voltage down converter circuit VDC receiving supply potential DVDDH of 3.3V to decrease it to approximately 2.0V, and power supply selection circuits SE[0151]1 and SE2 selectively applying supply potential VDD and an output of voltage down converter circuit VDC to respective supply lines L1 and L4.
• Power supply selection circuit SE[0152]1 includes an N channel MOS transistor Tr2 activated by self refresh signal SR to transmit an output of voltage down converter circuit VDC to supply line L2, and an N channel MOS transistor Tr1 turned on according to signal /SR which is an inverted version of the self refresh signal to supply power supply potential VDD to supply line L2 in the normal operation.
• Power supply selection circuit SE[0153]2 is activated according to self refresh signal SR to reduce an output of voltage down converter circuit VDC by the threshold voltage to supply it to supply line L3, and an N channel MOS transistor Tr4 turned on according to signal /SR to supply externally provided power supply potential VDD to supply line L3 in the normal operation.
• A switch SW[0154]1 for connecting supply lines L1 and L2 and a switch SW2 for connecting supply lines L3 and L4 are provided for any user requiring no power down mode. For example, switches SW1 and SW2 may be implemented by an aluminum mask option (using an optional photomask for aluminum line to change interconnections) employed in a manufacturing process of a semiconductor device.
• FIG. 11 illustrates a first example of grouping in peripheral circuits PCKT[0155]1 and PCKT2 in FIG. 10.
• Referring to FIG. 11, the DRAM portion generally includes as the peripheral circuit a[0156]clock control unit402, a row-relatedcommand control unit404, a column-relatedcommand control unit406, a row-relatedaddress control unit408, a bankaddress control unit410, a column-relatedaddress control unit412, an input/output data-relatedcontrol unit414 and a self refresh-relatedcontrol unit416.
• [0157]Clock control unit402 includes for example clock input buffers50 and52 and internal control clocksignal generating circuit118 illustrated in FIG. 1.
• Row-related[0158]command control unit404 includes for example input buffers12-20 and a portion ofmode decoder120 that generates a row-related command. Column-relatedcommand control unit406 includes input buffers12-20 and a portion ofmode decoder120 that generates a column-related command.
• Row-related[0159]address control unit408 includes for examplerow address latch124 androw predecoder140. Bankaddress control unit410 includes for example input buffers40-44,bank address latch128 andbank decoder136. Column-relatedaddress control unit412 includes for examplecolumn address latch126, burst address counter134 andcolumn predecoder142. Input/output data-relatedcontrol unit414 includes data input/output buffers72-78 and data input/output circuit130. Self refresh-relatedcontrol unit416 includesrefresh control unit132 andmultiplexer144.
• According to the first grouping shown in FIG. 11, input/output data-related[0160]control unit414 operates with supply potential VDD applied from the outside and other components operate with supply potential VDD3 generated in the power down mode based on supply potential DVDDH described above in conjunction with FIG. 10. Specifically, in FIG. 11, input/output data-relatedcontrol unit414 is included in peripheral circuit PCKT1, and peripheral circuit PCKT2 includesclock control unit402, row-relatedcommand control unit404, column-relatedcommand control unit406, row-relatedaddress control unit408, bankaddress control unit410, column-relatedaddress control unit412 and self refresh-relatedcontrol unit416.
• FIG. 12 illustrates a second example of grouping in the peripheral circuit.[0161]
• Referring to FIG. 12, external supply potential VDD is supplied to input/output data-related[0162]control unit414, column-relatedaddress control unit412, column-relatedcommand control unit406 andclock control unit402 via asupply line424. Supply potential VDD3 is supplied to self refresh-relatedcontrol unit416, row-relatedcommand control unit404, row-relatedaddress control unit408, and bankaddress control unit410 via asupply line422.
• In the structure shown in FIG. 12, peripheral circuit PCKT[0163]1 in FIG. 10 includesclock control unit402, column-relatedcommand control unit406, column-relatedaddress control unit412 and input/output data-relatedcontrol unit414. Peripheral circuit PCKT2 includes row-relatedcommand control unit404, row-relatedaddress control unit408 and bankaddress control unit410.
• FIG. 13 illustrates a third example of grouping in the peripheral circuit.[0164]
• Referring to FIG. 13, external supply potential VDD is supplied via a[0165]supply line428 toclock control unit402, column-relatedcommand control unit406, row-relatedaddress control unit408, bankaddress control unit410, column-relatedaddress control unit412 and input/output data-relatedcontrol unit414. Supply potential VDD3 is applied to self refresh-relatedcontrol unit416 and row-relatedcontrol unit404 via asupply line426.
• In the grouping illustrated in FIG. 13, peripheral circuit PCKT[0166]1 in FIG. 10 includesclock control unit402, column-relatedcommand control unit406, row-relatedaddress control unit408, bankaddress control unit410, column-relatedaddress control unit412 and input/output data-relatedcontrol unit414. Peripheral circuit PCKT2 includes row-relatedcommand control unit404 and self refresh-relatedcontrol unit416.
• The portion described below is a main concern when the power supply of any block is partially made off.[0167]
• FIG. 14 is a schematic diagram showing a structure of a memory array.[0168]
• Referring to FIG. 14, the memory array has memory mats arranged in a matrix of four rows and four columns. A group of[0169]main word drivers1142 is provided correspondingly to each row and an I/O selector1152 is provided correspondingly to each column. Each memory mat has acorresponding sense amplifier1148 and a correspondingsub word driver1150.
• In a column-related selecting operation, a[0170]driver1160 activates main column line selection signal MYS and anSDYS driver1146 activates segment decode YS selection signal SDYS. These signals cause activation of subYS signal SYS and accordingly, a corresponding I/O gate1162 activates an I/O line1164.
• In a row-related selecting operation, a[0171]main word driver1156 first activates a main word line MWL. AnSD driver1144 activates a segment decode line SD. Main word line MWL and segment decode line SD activate a corresponding sub word driver1168 and then asub word line1170 is activated and an access transistor connected to a memory cell is turned on. Accordingly, abit line pair1158 outputs data and the data amplified by asense amplifier1166 is read via I/O line1164. Aread amplifier1154 and awrite amplifier1153 are connected to I/O line1164 and readamplifier1154 and writeamplifier1153 are connected to an input/output latch1172. Input/output latch1172 is connected to aninput buffer1174 and anoutput buffer1176 for transmitting and receiving data to and from the logic portion.
• In respective examples shown in FIGS. 11, 12 and[0172]13, input/output data-relatedcontrol unit414 is supplied with operation supply potential from supply potential VDD which is made off in the power down mode. Therefore, in self refresh in the power down mode, power supply of input/output latch1172,input buffer1174 andoutput buffer1176 is made off. In this case, if I/O line1164 has an unstable potential, any negative influence may be exerted on the refresh operation.
• FIG. 15 shows a structure of a boundary portion inactivating an I/O line used for writing operation, by stopping power supply.[0173]
• Referring to FIG. 15, supply potential VDD is applied to latch[0174]circuit1172.Latch circuit1172 includes flip-flops1172aand1172breceiving write data signals WDATa and WDATb respectively transmitted via the input/output control unit from the logic portion.
• Respective outputs of flip-[0175]flops1172aand1172bare input to agate circuit504 to which operation supply potential is applied by supply potential VDD3.Gate circuit504 includes an ANDcircuit505areceiving signal /SR which is set at L level when self refresh is carried out and an output of flip-flop1172a,and an ANDcircuit505breceiving signal /SR and an output of flip-flop1172b.An output of ANDcircuit505ais supplied to an input ofinverter1153afor driving a write I/O line WIOa and an output of ANDcircuit505bis supplied to an input ofinverter1153bfor driving a write I/O line WIOb. Such agate circuit504 is provided in addition to conventional components in order to set signal /SR at L level in the power down mode, and accordingly, respective outputs of ANDcircuits505aand505bare fixed at H level and then the write I/O line is fixed at H level.
• FIG. 16 is a circuit diagram showing a structure of flip-[0176]flop1172ain FIG. 15.
• Referring to FIG. 16, flip-[0177]flop1172aincludes a clockedinverter506 activated according to clock signal /CK which is inverted when input signal D is supplied, aninverter508 receiving and inverting an output ofinverter506, a clockedinverter510 receiving and inverting an output ofinverter508 and activated according to clock signal CK supplied to an input portion ofinverter508, atransmission gate512 which becomes conductive according to clock signal CK to transmit an output ofinverter508 to the next stage, aninverter514 receiving and inverting data transmitted bytransmission gate512, a clockedinverter516 receiving and inverting an output ofinverter514 and activated according to clock signal /CK supplied to an input portion ofinverter514, and aninverter518 receiving and inverting an output ofinverter514 to provide output signal Q. Flip-flop1172bhas the same structure as that of flip-flop1172aand description thereof is not repeated here.
• Referring again to FIG. 15, supply potential VDD applied to latch[0178]circuit1172 is set in off state in power down refresh mode. Even if respective outputs of flip-flops1172aand1172bbecome unstable, the write I/O line is fixed by providinggate circuit504 and using signal /SR. Therefore, when supply potential VDD is made on again to make transition to the normal operation, the write I/O line never becomes unstable. In this way, the operation can be stabilized.
• FIG. 17 illustrates that power supply is applied preceding and following[0179]read amplifier1154 shown in FIG. 14.
• Referring to FIG. 17, an equalize[0180]circuit528 is connected to read I/O lines RIO and /RIO and the read I/O lines are precharged to H level before reading operation. This equalizecircuit528 is supplied with operation potential from supply potential VDD3. Data read onto read I/O lines RIO and /RIO is supplied to readamplifier1154. Readamplifier1154 amplifies the read data and supplies it to a latch1172c.Latch1172csupplies the read data RDAT to the logic portion via the input/output control unit. Readamplifier1154 and latch1172care supplied with operation supply potential from supply potential VDD which is made off in power down refresh mode.
• FIG. 18 is a circuit diagram showing a structure of[0181]read amplifier1154 and equalizecircuit528 shown in FIG. 17.
• Referring to FIG. 18, equalize[0182]circuit528 includes Pchannel MOS transistors538 and540 for coupling respective read I/O lines RIO and /RIO to supply potential VDD3. The gates of Pchannel MOS transistors538 and540 receive precharge signal /PC.
• [0183]Read amplifier1154 includes an Nchannel MOS transistor534 connected between a ground node and an output node NOUT1 and having its gate connected to read I/O line /RIO, an Nchannel MOS transistor536 connected between an output node NOUT2 and the ground node and having its gate connected to read I/O line RIO, a Pchannel MOS transistor532 connected between a node receiving supply potential VDD and node NOUT2 and having its gate connected to node NOUT1, and a Pchannel MOS transistor530 connected between the node receiving supply potential VDD and node NOUT1 and having its gate connected to node NOUT2.
• Supply potential is thus applied to the read amplifier and the equalize circuit so as to prevent any influence on data in the array even if supply potential VDD is made off in the power down refresh mode.[0184]
• FIG. 19 is a block diagram illustrating that a transistor having a high threshold is employed in some blocks for the purpose of reducing power consumption in the refresh control-related portion.[0185]
• Referring to FIG. 19, when the self refresh mode is set by the mode decoder, a[0186]buffer626 activates self refresh signal SR. Accordingly, anaddress control circuit614, anSR timer616 and anSR control circuit618 start respective operations. Usually address signal Add is supplied to abuffer606 and an output ofbuffer606 and a refresh address Ref/Add output fromaddress control circuit614 are supplied to amultiplexer608.Multiplexer608 outputs a refresh address signal when self refresh signal SR is activated. An output ofmultiplexer608 is supplied to anaddress comparison circuit604 and a replace instruction circuit andpredecoder610.Address comparison circuit604 compares a replace address signal set by afuse602 with an input address signal and issues a replace instruction to replace instruction circuit andpredecoder610 when these addresses match each other. Replace instruction circuit andpredecoder610 outputs result of decoding to abuffer612 and buffer612 outputs array select information to the memory array.
• A path through which a command signal is transmitted is now described. A[0187]selection circuit620 receives command signal CMD from the mode decoder via abuffer622 in the normal operation.Selection circuit620 receives a command signal fromSR control circuit618 at the other input in the self refresh.Selection circuit620 outputs any of the command signals to abuffer624 according to self refresh signal SR, and buffer624 transmits the command signal to the array. Abuffer628 is further provided for transmitting a reset signal from the logic portion.
• In the example of the structure shown in FIG. 19, the circuit portion which should operate at a high speed needs a transistor having a low threshold voltage. In the self refresh, another circuit constituted of a transistor having a high threshold voltage different from the normal circuit is activated. The reason is that no high speed reading operation like that in the normal operation is required in the self refresh. Signals required for refresh may be only those for inactivation of an equalize signal, activation of a word line and activation of a sense amplifier. For example, in FIG. 19,[0188]address control circuit614,SR timer616 andSR control circuit618 are constituted by using transistors having a high threshold voltage. Similarly, fuse602 andaddress comparison circuit604 are constituted by transistors having a high threshold voltage operating with supply voltage of 3.3 V and having a thick gate oxide film.
• It is noted that[0189]multiplexers608 and620 andbuffers626 and628 are constituted of transistors having a thick gate oxide film and operate with supply voltage of 1.5 V.
• FIG. 20 is a circuit diagram showing a first example of a circuit structure for multiplexing an address in the normal operation and an address in the self refresh.[0190]
• Referring to FIG. 20, address signal Add supplied in the normal operation and refresh address signal Ref-Add supplied in the self refresh mode are input to[0191]multiplexer608 in FIG. 19.Multiplexer608 includesmultiplexers608a-608cfor multiplexing bits of address signal Add and refresh address signal Ref-Add. These multiplexers select an address signal according to self refresh signal SR and output the selected address signal to adecode unit550.Decode unit550 includes N channel MOS transistors552-556 connected in series between a node N1 and a ground node. Respective outputs ofmultiplexers608a-608care supplied to respective gates of N channel MOS transistors552-556. Node N1 is coupled to supply potential VDD3 by a Pchannel MOS transistor566 according to precharge signal /PC. The potential on node N1 is inverted by aninverter558 to be output as output signal OUT. Signal OUT is supplied to the gate of a Pchannel MOS transistor564 connected between node N1 and a node to which supply potential VDD3 is applied.
• [0192]Inverter558 includes a Pchannel MOS transistor560 and an Nchannel MOS transistor562 connected in series between the node to which supply potential VDD3 is supplied and the ground node. The gates of Pchannel MOS transistor560 and Nchannel MOS transistor562 are both connected to node N1 and output signal OUT is supplied from a connection node between Pchannel MOS transistor560 and Nchannel MOS transistor562.
• FIG. 21 is a circuit diagram showing a second example of a structure for address multiplexing.[0193]
• Referring to FIG. 21, a[0194]circuit609 in the second example includesdecode units568 and570 instead ofmultiplexer608 anddecode unit550 instructure549 of the first example. Other components are similar to those in the example ofcircuit549 and description thereof is not repeated here.Decode unit568 includes N channel MOS transistors572-576 having respective gates receiving address signal Add in the normal operation and connected in series between node N1 and the ground node.
• [0195]Decode unit570 includes N channel MOS transistors578-582 having respective gates receiving refresh address Ref-Add in the refresh and connected in series between node N1 and the ground node. In the normal operation, each bit of refresh address Ref-Add is set at L level. In the self refresh mode, each bit of normal address signal Add is fixed at L level. In this structure, an N channel MOS transistor having a high threshold voltage Vth is employed indecode unit570 so as to reduce leakage current in the power down mode.
• For operational switching from[0196]decode unit568 to decodeunit570,decode unit568 should be set in a non-operating state. In this case, it is not necessarily required to set all address bits of address signals Add at L level. Any address which always fixed at L level in the self refresh may be supplied to one of transistors572-576. Similarly, in order not to operatedecode unit570 in the normal operation, any address which is always fixed at L level in the normal operation may be supplied to any of transistors578-582.
• A circuit structure employed for transmitting a command signal to a memory array when a plurality of supply potentials are present as shown in FIG. 19 is described.[0197]
• FIG. 22 is a circuit diagram showing a structure of a level conversion circuit.[0198]
• Referring to FIG. 22, the level conversion circuit includes an N[0199]channel MOS transistor638 connected between a node N3 and a ground node and having its gate receiving command signal CMD, an Nchannel MOS transistor636 connected between a node N2 and the gate of Nchannel MOS transistor638 and having its gate receiving supply potential VDD, a Pchannel MOS transistor632 connected between node N2 and a node receiving supply potential VDD and having its gate connected to node N3, and a Pchannel MOS transistor634 connected between the node receiving supply potential VDD and node N3 and having its gate connected to node N2. From node N3, output signal OUT is supplied.
• By such a structure, an output amplitude of command signal CMD is converted to an amplitude between ground potential and supply potential VDD.[0200]
• FIG. 23 is a circuit diagram showing a structure of[0201]selection circuit620 in FIG. 21.
• Referring to FIG. 23,[0202]selection circuit620 includes an Nchannel MOS transistor648 connected between a node N6 and the ground node and having its gate receiving command signal CMD, an Nchannel MOS transistor646 connected between a node N4 and the gate of Nchannel MOS transistor648 and having its gate receiving inversion signal /SR of a self refresh signal, a Pchannel MOS transistor642 connected between node N4 and a node receiving supply potential VDD3 and having its gate connected to node N6, and a Pchannel MOS transistor644 connected between the node receiving supply potential VDD3 and node N6 and having its gate connected to node N4. Output signal OUT is supplied from node N6 and output signal /OUT is supplied from node N4.
• [0203]Selection circuit620 further includes an Nchannel MOS transistor652 connected between the ground node and node N6 and having its gate receiving command signal Ref-CMD in the refresh, and an Nchannel MOS transistor650 connected between node N4 and the gate of Nchannel MOS transistor652 and having its gate receiving self refresh signal SR. Since Nchannel MOS transistors650 and652 operate only in the self refresh mode, higher speed than that in the normal operation is unnecessary. Therefore, an N channel MOS transistor having a high threshold voltage and low leakage current is employed. By such a structure, leakage current in the self refresh can be reduced and power consumption of the chip can further be decreased.
• A structure for converting the level of a signal to transmit it between circuits having a plurality of supply potentials is now described.[0204]
• FIG. 24 is a circuit diagram showing a structure of a first[0205]level conversion circuit660 for converting the level from 1.5V to 3.3V.
• Referring to FIG. 24,[0206]level conversion circuit660 includes aninverter666 receiving and inverting a mode signal, atransmission gate662 which becomes conductive according to an output ofinverter666 to transmit signal Sig supplied in the normal operation to a node N10, a clockedinverter668 activated by mode signal Mode, receiving signal Ref in the refresh and inverting it, aninverter670 having its input connected to node N10, a Pchannel MOS transistor672 and an Nchannel MOS transistor676 connected in series between a node receiving supply potential of 3.3V and the ground node, and a Pchannel MOS transistor674 and an Nchannel MOS transistor678 connected in series between the node receiving supply potential of 3.3V and the ground node. The gate of Nchannel MOS transistor676 is connected to node N10. The gate of Nchannel MOS transistor678 receives an output ofinverter670. An output of Pchannel MOS transistor672 is connected to a connection node between Pchannel MOS transistor674 and Nchannel MOS transistor678. The gate of Pchannel MOS transistor674 is connected to a connection node between Pchannel MOS transistor672 and Nchannel MOS transistor676. An output signal Sout is supplied from the connection node between Pchannel MOS transistor674 and Nchannel MOS transistor678.
• [0207]Level conversion circuit660 employs as transistors672-678 MOS transistors having a high threshold voltage. Therefore, leakage current in the refresh mode is set small in this portion. MOS transistors having a low threshold voltage are employed as other transistors and inverters. Such a structure uses the minimum number of transistors to carry out the conversion.
• FIG. 25 is a circuit diagram showing a structure of a[0208]level conversion circuit680 as a second example.
• Referring to FIG. 25,[0209]level conversion circuit680 includes aninverter686 receiving and inverting signal Sig, aninverter692 receiving and inverting mode signal Mode, and clockedinverters694 and696 connected in series, activated according to mode signal Mode and receiving signal Ref. An output of clockedinverter694 is connected to a node N12 and an output of clockedinverter696 is connected to a node N13.
• [0210]Level conversion circuit680 further includes atransmission gate682 which becomes conductive when mode signal Mode is at L level to transmit signal Sig to node N12, and atransmission gate688 which becomes conductive when mode signal Mode is at L level to transmit an output ofinverter686 to node N13.
• [0211]Level conversion circuit680 further includes an Nchannel MOS transistor702 connected between a node N14 and the ground node and having its gate connected to node N12, an Nchannel MOS transistor704 connected between a node N15 and the ground node and having its gate connected to node N13, a Pchannel MOS transistor698 connected between a supply node receiving 3.3V and node N14 and having its gate connected to node N15, and a Pchannel MOS transistor700 connected between the node receiving supply potential of 3.3V and node N15 and having its gate connected to node N14.
• In the structure of[0212]level conversion circuit680, input-related circuits associated with the transmission gate and signal Ref are constituted by transistors having a high threshold voltage controlled by 3.3V. Compared withlevel conversion circuit660 shown in FIG. 24, the number of transistors increases and the speed becomes a little lower. However, the gate potential oftransmission gates682 and688 is controlled by 3.3V. Therefore, it is not necessary to supply a signal having an amplitude of 1.5V and power source of any circuitry operating with supply potential of 1.5V may be made off.
• FIG. 26 is a circuit diagram showing a structure of a[0213]level conversion circuit710 as a third example of the level conversion circuit.
• Referring to FIG. 26,[0214]level conversion circuit710 includes aninverter722 receiving and inverting signal Sig, an Nchannel MOS transistor720 connected between a node N23 and the ground node and having its gate receiving mode signal Mode, an Nchannel MOS transistor716 connected between a node N20 and node N23 and having its gate receiving signal Sig, an Nchannel MOS transistor718 connected between nodes N21 and N23 and having its gate receiving an output ofinverter722, a Pchannel MOS transistor712 connected between node N20 and a supply node receiving 3.3V and having its gate connected to node N21, and a Pchannel MOS transistor714 connected between the supply node receiving 3.3V and node N21 and having its gate connected to node N20.
• [0215]Level conversion circuit710 further includes aninverter728 receiving and inverting mode signal Mode, a clockedinverter730 activated according to mode signal Mode and receiving and inverting signal Ref, and atransmission gate724 for coupling nodes N21 and N24 according to the mode signal and an output ofinverter728.
• [0216]Level conversion circuit710 is constituted of transistors having a high threshold voltage except forinverter722.Level conversion circuit710 is different fromlevel conversion circuit680 in FIG. 25 in that signal Sig applied with the amplitude of 1.5V is level-converted and thereafter the resultant signal is multiplexed with signal Ref supplied in the refresh.
• [0217]Level conversion circuit710 can be constituted with a reduced number of transistors compared withlevel conversion circuit680.
• A structure concerning control of a column selection line is now described. The column selection line becomes a floating state when 1.5V-related power supply is made off. Therefore, the potential should be fixed.[0218]
• FIG. 27 is a circuit diagram showing a structure of a column selection[0219]line fixing circuit730.
• Referring to FIG. 27, column selection[0220]line fixing circuit730 includes aNAND circuit732 receiving write enable signal WE and address signal Yadd, aninverter736 receiving and inverting signal Self set at H level in the self refresh mode, aNAND circuit734 receiving respective outputs ofNAND circuit732 andinverter736, aninverter738 receiving and inverting an output ofNAND circuit734 and having its output connected to a write column selection line CSLWL, and aninverter740 receiving an output ofNAND circuit734 and having its output connected to a write column selection line CSLWR.
• Column selection[0221]line fixing circuit730 is constituted of transistors all having a low threshold voltage and operating with 1.5V. In the self refresh, signal Self is at H level. Therefore, an output ofNAND circuit734 is fixed at H level and accordingly both of write column selection lines CSLWL and CSLWR are fixed at L level.
• FIG. 28 is a circuit diagram showing a structure of a column selection[0222]line fixing circuit740 as the second example of a structure for fixing a column selection line.
• Referring to FIG. 28, column selection[0223]line fixing circuit740 includes aNAND circuit742 receiving write enable signal WE and address signal Yadd, alevel shifter744 converting an output ofNAND circuit742 from the amplitude of 1.5V to the amplitude of 2.5V or 3.3V, aninverter746 receiving and inverting signal Self, atransmission gate748 which becomes conductive according toinverter746 and signal Self to transmit an output oflevel shifter744 to a node N30, a Pchannel MOS transistor752 receiving an output ofinverter746 at its gate for coupling node N30 to supply potential of 2.5V or 3.3V, aninverter754 having its input connected to node N30 and its output connected to write column selection line CSLWL, and aninverter756 having its input connected to node N30 and its output connected to column selection line CSLWR.
• Column selection[0224]line fixing circuit740 is employed when the column selection line operates with 2.5V or 3.3V. As a transmission gate, a transistor having a high threshold voltage is employed. Precharge operation of 2.5V/3.3V is carried out by Pchannel MOS transistor752 having a high threshold voltage. In the self refresh mode, signal Self is activated to H level and accordingly Pchannel MOS transistor752 is turned on andtransmission gate748 becomes nonconductive. Node N30 is then fixed at H level and accordingly both of column selection lines CSLWL and CSLWR are fixed at H level. In such a structure,NAND circuit742 with its power source set in the off state and thelevel shifter744 are separated by node N30 andtransmission gate748. Then noise of the column selection line can be reduced.
• FIG. 29 is a circuit diagram showing a structure of a column selection[0225]line fixing circuit757 as a third example of the structure for fixing the column selection line.
• Referring to FIG. 29, column selection[0226]line fixing circuit757 includes aNAND circuit758 receiving write enable signal WE and address signal Yadd, aninverter760 receiving and inverting an output ofNAND circuit758, aninverter762 receiving and inverting an output ofinverter760, aninverter768 receiving and inverting an output ofinverter760, aninverter770 receiving and inverting signal Self which is at H level in the self refresh, atransmission gate764 which becomes conductive according toinverter770 and signal Self to transmit an output ofinverter762 to write column selection line CSLWL, atransmission gate772 which becomes conductive according to an output ofinverter770 and signal Self to transmit an output ofinverter768 to write column selection line CSLWR, and Nchannel MOS transistors766 and778 having the gate receiving signal SELF for fixing respective write column selection lines CSLWL and CSLWR at ground potential in the self refresh mode.
• Compared with column selection[0227]line fixing circuit740 shown in FIG. 28, column selectionline fixing circuit757 enables further reduction of a slight amount of through current or leakage current of driver circuits orinverters754 and756 for driving the column selection line. In other words, the power supply ofinverters762 and768 as the driver circuits can be made off andtransmission gates764 and772 separate respective outputs ofinverters762 and768 from column selection lines CSLWL and CSLWR. In this way, leakage current of the driver circuit can be eliminated when the column selection line is fixed at L level.
• In order to reduce the leakage current, various structures are employed as described above. In this way, power supply of the peripheral circuit of the DRAM portion in the system LSI can be made off. Further, in the circuit having its power source in the on state, the leakage current can be decreased.[0228]
• Third Embodiment[0229]
• FIG. 30 is a block diagram showing a structure of a[0230]semiconductor device800 according to the third embodiment.
• Referring to FIG. 30,[0231]semiconductor device800 includes alogic portion802 transmitting and receiving data to and from the outside and performing various arithmetic operations and the like, and aDRAM portion804 receiving from logic portion802 a command signal and an address signal and transmitting and receiving data to and fromlogic portion802.DRAM portion804 includes a clock/reset control circuit806 receiving signal NPDSR from the logic portion and outputting power down mode signal PDSR and making various reset controls, aperipheral circuit812 receiving a command signal and an address signal fromlogic portion802, aperipheral circuit814 receiving an internal command signal and an internal address signal and the like fromperipheral circuit812 to perform row-related processing, a selfrefresh control circuit808 outputting clock signal CLKS to peripheral circuit314 in the self refresh mode, a DRAMpower supply circuit810 receiving externally provided supply potential of 3.3V and supply potential VDD of 1.5V to output 1.5V supply potential VDD3 and 2.0V supply potential VDD2 to a memory array, andmemory array860 in which reading of data is controlled byperipheral circuits814 and812.
• [0232]Peripheral circuit812 includes acommand decoder822 receiving command signal CMD from the logic portion with the amplitude of 1.5V, anaddress buffer824 receiving row address signal RAD [14:0] fromlogic portion802 with an amplitude of 1.5V, anaddress buffer826 receiving column address signal CAD [7:0] fromlogic portion802 with an amplitude of 1.5V, acolumn predecoder828 predecoding an output ofaddress buffer826, and aclock buffer834 receiving 1.5V amplitude clock signal CLK fromlogic portion802 to supply it to any circuit ofDRAM portion804.
• [0233]Peripheral circuit812 further includes a preamplifier/write driver858 reading data frommemory array860 or writing data intomemory array860, and an I/O selector830 transmitting and receiving data to and from preamplifier/write driver858 and selectively connecting it with a data input/output buffer according to an output ofcolumn decoder828. Data input/output buffer832 transmits and receives data input signal DI and data output signal DO to and fromlogic portion802 with an amplitude of 1.5V.
• [0234]Peripheral circuit814 includes aselection circuit833 receiving self refresh command REFS fromcommand decoder822 and receiving power down self refresh signal PDSR from clock/reset control circuit806 and activate signal REFSD according to any of them, anACT generating circuit838 receiving signal REFSD and refresh command REFA and row active command ACT fromcommand decoder822 and outputting row-related activation signal NACT, a flip-flop840 receiving signal NACT synchronously with clock signal CLKR after reset according to reset signal NRSTR to latch the received signal, and atiming generating circuit844 outputting a timing signal for activating a word line and a sense amplifier according to an output of flip-flop840.
• [0235]Peripheral circuit814 further includes anaddress counter835 outputting a refresh address according to refresh command REFA, signal REFSD, and row-related activation signal NANCT, aselection circuit836 transmitting an output ofaddress counter835 to the inside as an address signal in the refresh and transmitting an output ofaddress buffer824 to the inside in the normal operation, a row-relatedfuse848 where a redundancy replace address is set, aredundancy determination circuit846 comparing the redundancy replace address with an address supplied fromselection circuit836 to make judgement of redundancy replace, arow predecoder850 predecoding an output ofredundancy determination circuit846, and a flip-flop852 taking an output ofrow predecoder850 synchronously with clock signal CLKR to supply it to rowdecoder846 after reset by reset signal NRSTR.
• [0236]Peripheral circuit814 further includes arow decoder854 for performing row-related decode processing for selecting a memory cell ofmemory array860, and acolumn decoder856 receiving an output ofcolumn predecoder828 to make column-related selection. In the power down mode,column decoder856 is structured to fix potentials of read and write selection lines CSLR/W by signal PDSR.
• [0237]Refresh control circuit808 includes alevel shift circuit818 receiving signal REFSD and performing level shift, aself timer816 activated according to an output oflevel shift circuit818, generating a clock signal by a ring oscillator included inside, and outputting a reference clock for self refresh using the generated clock signal as a reference, and adown converter820 receiving an output ofself timer816 to convert it to the one having a low level amplitude. An output ofdown converter820 is supplied as clock signal CLKS toACT generating circuit838 which outputs row-related activation pulse.
• Power supply provided to[0238]semiconductor device800 is now described. VDDH is supply potential of 3.3V supplied from the outside. Supply potential VDD is an externally applied supply potential of 1.5V. The logic portion receives supply potentials VDDH and VDD to carry out internal operation. A clock reset control circuit andperipheral circuit814 receive as operation supply potential, 1.5V supply potential VDD3 from DRAMpower supply circuit810.
• [0239]Peripheral circuit812 receives supply potential VDD as its operational supply potential.
• FIG. 31 is a circuit diagram showing a structure of DRAM[0240]power supply circuit810 in FIG. 30.
• Referring to FIG. 31, DRAM[0241]power supply circuit810 includes alevel shifter862 converting the level of the power down self refresh signal to 3.3V, abuffer circuit864 driven by power supply of 3.3V and buffering an output oflevel shifter862, adown converter866 converting the voltage of an output oflevel shifter862 to 2V, a voltage downconverter circuit868 receiving 3.3V supply potential VDDH and outputting 2.0V supply potential VDD2, an N channel MOS transistor872 turned on in the normal operation mode to transmit externally provided 1.5V supply potential VDD to an output node NVO, and an Nchannel MOS transistor870 turned on in the power down mode to transmit an output of voltage downconverter circuit868 to output node NVO. From output node NVO, supply potential VDD3 is output as an output ofDRAM supply circuit810. Supply potential VDD2 is an output of voltage downconverter circuit868 and applied to a memory array.
• The gate potential of N[0242]channel MOS transistor870 is set at 2V in the power down mode. Voltage drop corresponding to almost threshold voltage is generated by Nchannel MOS transistor870 and supply potential VDD3 is set at approximately 1.5V in the power down mode.
• A[0243]switch874 is provided for allowing coupling between the node receiving external supply potential VDD and output node NVO when the power down mode is unnecessary.Switch874 may be set selectively in the conductive state by changing a metal mask in a manufacturing process of a semiconductor device.
• FIG. 32 is a circuit diagram showing a structure of clock/[0244]reset control circuit806 in FIG. 30.
• Referring to FIG. 32, clock/[0245]reset control circuit806 includes abuffer circuit898 receiving reset signal NRESET from the logic portion to supply reset signal NRST to the inside, abuffer circuit900 receiving signal NPDSR from the logic portion, and an ORcircuit902 receiving signal NRESET and an output ofbuffer circuit900 and outputting signal NRSTR.
• Clock[0246]reset control circuit806 further includes apulse generating circuit882 receiving signal NPDSR from the logic portion and generating a low-active pulse signal on the fall of the received signal, acounter886 receiving refresh command signal REFA from a command decoder after reset by reset signal NRESET to carry out counting up and change an output when eight inputs are received, an ORcircuit904 receiving an output ofcounter886 and an output ofbuffer900 and outputting signal NRSTS, apulse generating circuit888 generating a low-active pulse according to an output ofcounter886, and alatch circuit896 set by an output ofpulse generating circuit888 and reset by reset signal NRESET.
• Clock/[0247]reset control circuit806 further includes apulse generating circuit883 receiving signal LAT which is a /Q output signal oflatch circuit890 and generating a low-active pulse signal on the falling of the received signal, and alatch circuit884 set by an output ofpulse generating circuit882 and reset by an output ofpulse generating circuit883. Power down self refresh signal PDSR is supplied from the Q output oflatch circuit884.
• Clock/[0248]reset control circuit860 further includes aselector896 receiving clock signal CLK having 1.5V amplitude supplied from the logic portion and clock signal CLKS generated byself timer816 in FIG. 30, and selecting any of clock signals according to signal REFSD to output it as clock signal CLKR.
• FIG. 33 is an operation waveform chart illustrating power down mode of the DRAM portion of the semiconductor device shown in FIG. 30.[0249]
• Referring to FIGS. 30 and 33, at time t[0250]1, power is applied tosemiconductor device800. Then reset signal NRESET is supplied fromlogic portion802 to the DRAM portion and subsequently a power-on-sequence is carried out in which refresh command REFA is supplied several times. At time t2, the power on sequence is completed and the normal operation can be carried out accordingly.
• Preceding transition to the power down mode at time t[0251]3, an auto refresh command is supplied from the logic portion to the DRAM portion at time t3 to refresh the entire memory space. Then at the time t4, the logic portion sets signal NPDSR at L level to cause the DRAM portion to start a self refresh operation. From time t4, the DRAM portion is in the power down mode.
• At time t[0252]5, supply potential LVDDH and 1.5V supply potential VCC1.5 applied to the logic portion are set in the off state and accordingly the power down mode is started. Specifically, supply potential applied for self refresh is 3.3V supply potential DVDDH only. When the mode returns from the power down mode to the operation mode at time t6, 1.5V supply potential VCC1.5 is applied and successively a stable clock signal is applied.
• At time t[0253]7, reset signal NRESET is fixed at L level for 200μ minutes, and thereafter reset signal NRESET is set at H level to cancel reset and refresh command REFA is input eight times to initialize the internal circuit. After this, self refresh exit command SREX for terminating the self refresh is input and signal NPDSR is raised from L level to H level. Then after the time period represented by tSRX, the logic portion supplies an auto refresh command to the DRAM portion and the DRAM portion refreshes the entire memory space. After the last refresh command REFA is issued, all banks are inactivated and command can be input after the minimum read cycle time tRC+1 clock passes.
• FIG. 34 is a waveform chart illustrating an operation when the mode returns from the power down mode to the operation mode in FIG. 33.[0254]
• Referring to FIGS. 32 and 34, at time t[0255]4, signal NPDSR falls to L level and accordingly pulse generatingcircuit882 generates low-active pulse signal FS. Accordingly latchcircuit884 is set and signal PDSR is set at H level.
• At time t[0256]7, reset signal NRESET after cancellation of power down is input and then latchcircuit890 is reset. Refresh command REFA is input eight times and then at time t8, an output ofcounter886 generates a pulse signal to setlatch circuit890. Signal LAT as the /Q output oflatch circuit890 then falls from H level to L level andlatch circuit884 is reset according to an output ofpulse generating circuit883. Signal PDSR is then at L level and thereafter the normal operation can be carried out.
• The return sequence from the power down mode is the same as the normal power supply sequence. After reset by reset signal NRESET, refresh command REFA is input eight times to reset all special modes set in a mode register and the like.[0257]
• After this, at time t[0258]9, signal NPDSR rises to H level. Signal NPDSR is used for transition to the power down mode and having no influence on an operation when it rises to H level any time after the mode returns to the normal mode.
• As heretofore described, current consumption in the standby state is reduced in the power down mode of the semiconductor device according to the third embodiment. After the mode returning, a normal high speed operation is possible by predetermined input.[0259]
• Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.[0260]

Claims (17)

What is claimed is:

1. A semiconductor device transmitting/receiving data in a normal mode and refreshing stored data with reduced current consumption in a power down mode, comprising:

a memory array including a plurality of memory cells arranged in a matrix of rows and columns;

a first peripheral circuit inputting/outputting storage data in said memory cells in said normal mode and stopping operation in said power down mode for reducing current consumption; and

a second peripheral circuit controlling refresh of data stored in said memory cells in said power down mode.

2. The semiconductor device according to

claim 1

, wherein

said second peripheral circuit includes a refresh control unit controlling refresh of a partial region of said memory array by holding a start address indicating an address where the refresh is started and an end address indicating an address where the refresh is ended.

3. The semiconductor device according to

claim 2

, wherein

said refresh control unit includes:

a timer circuit generating a reference clock for activating a row of said memory array in the refresh; and

an address counter outputting an address for refresh between said start address and said end address,

said address counter includes

a first latch circuit holding said start address,

a second latch circuit holding said end address,

a counter taking count according to said reference clock,

a first comparison circuit comparing an output of said counter with an output of said first latch circuit,

a second comparison circuit comparing the output of said counter with an output of said second latch circuit, and

a gate circuit receiving respective outputs of said first and second comparison circuits to detect that the output of said counter is at least said start address and at most said end address, and

said refresh control unit further includes a delay circuit for control activated according to an output of said gate circuit to output a timing signal for controlling row selection of said memory array according to said reference clock.

4. The semiconductor device according to

claim 2

, wherein

said refresh control unit includes:

a timer circuit generating a reference clock for activating a row of said memory array in the refresh; and

an address counter outputting an address for refresh between said start address and said end address,

said address counter includes

a first latch circuit holding said start address,

a second latch circuit holding said end address,

a detecting circuit receiving respective outputs of said first and second latch circuits to designate a cycle of said reference clock to said timer circuit according to ratio of a region designated by said start address and said end address to region of said memory array,

a counter receiving the output of said first latch circuit, taking count according to said reference clock using said start address as an initial count, and outputting a refresh address, and

a comparison circuit comparing an output of said counter with the output of said second latch circuit to detect that the refresh is completed.

5. The semiconductor device according to

claim 1

, further comprising:

a first power supply terminal receiving a first supply potential;

a second power supply terminal receiving a second supply potential higher than said first supply potential;

a first power supply line connecting said first supply terminal and said first peripheral circuit;

a voltage down converter circuit connected to said second power supply terminal and outputting a third supply potential lower than said second supply potential;

a power supply selection circuit receiving said first power supply potential and said third power supply potential to selectively output one of the received power supply potentials; and

a second power supply line supplying output of said power supply selection circuit to said second peripheral circuit.

6. The semiconductor device according to

claim 5

, wherein

said power supply selection circuit includes:

a first MOS transistor connected between said first power supply line and said second power supply line and activated in said normal mode; and

a second MOS transistor connected between said voltage down converter circuit and said second power supply line and activated in said power down mode.

7. The semiconductor device according to

claim 6

, wherein

said power supply selection circuit further includes a voltage converter circuit supplying an activation potential equal to an output potential of said voltage down converter circuit to gate of said second MOS transistor in said power down mode.

8. The semiconductor device according to

claim 5

, further comprising a logic portion receiving supply potential from said first power supply line and performing a predetermined processing according to an externally supplied instruction, wherein

said first peripheral circuit includes a data input/output control unit for transmitting and receiving data between said logic portion and said memory array,

said second peripheral circuit includes a self refresh control unit controlling self refresh for said memory array in said power down mode, and

said first power supply terminal receives an inactive potential in said power down mode.

9. The semiconductor device according to

claim 8

, wherein

said first peripheral circuit further includes:

a clock control unit receiving a clock signal from said logic portion to generate an internal clock signal for transmitting and receiving data to and from said memory array;

a column-related command control unit receiving an instruction from said logic portion to generate a column-related command; and

a column address control unit receiving a column address from said logic portion to select a column of said memory array.

10. The semiconductor device according to

claim 9

, wherein

said memory array includes a plurality of banks capable of operating independently of each other, and said first peripheral circuit further includes:

a row address control unit receiving a row address from said logic portion to select a row of said memory array; and

a bank address control unit receiving a bank address from said logic portion to select any of said plurality of banks.

11. The semiconductor device according to

claim 8

, wherein

said memory array includes:

a write data line transmitting write data to said memory cells;

a latch circuit receiving power supply potential from said first power supply line, and receiving and holding data from said data input/output control unit in said normal mode; and

a gate circuit receiving power supply potential from said second power supply line, transmitting an output of said latch circuit to said write data line in said normal mode, and fixing potential of said write data line in said power down mode.

12. The semiconductor device according to

claim 8

, wherein

said memory array includes:

a read data line for reading data from said memory cells;

a read amplifier circuit receiving power supply potential from said first power supply line, amplifying potential change of said read data line and transmitting the amplified potential change to said input/output control unit in said normal mode; and

a switch circuit coupling said read data line to said second power supply line in said power down mode.

13. The semiconductor device according to

claim 8

, wherein

said self refresh control unit outputs a refresh address in said power down mode,

said second peripheral circuit further includes an address synthesizing unit receiving a normal address from said logic portion in the normal mode and said refresh address, and

said address synthesizing unit includes:

a first group of MOS transistors connected in series between an internal node and a ground node and each having its gate receiving any of address bits of said normal address;

a second group of MOS transistors connected in series between said internal node and said ground node and each having its gate receiving any of address bits of said refresh address; and

a switch circuit connected between said second power supply line and said internal node and precharging said internal node.

14. The semiconductor device according to

claim 13

, wherein

said second group of MOS transistors has a greater threshold voltage than that of said first group of MOS transistors.

15. The semiconductor device according to

claim 8

, wherein

said self refresh control unit outputs a first command signal in the self refresh,

said second peripheral circuit further includes a command synthesizing unit receiving a second command signal supplied from said logic portion in the normal mode and said first command signal, and

said command synthesizing unit includes:

a first P channel MOS transistor connected between said second power supply line and a first internal node and having its gate connected to a second internal node;

a second P channel MOS transistor connected between said second power supply line and said second internal node and having its gate connected to said first internal node;

a first N channel MOS transistor having its gate receiving said first command signal and connected between said second internal node and a ground node;

a second N channel MOS transistor rendered conductive in said self refresh to transmit said first command signal to said first internal node;

a third N channel MOS transistor having its gate receiving said second command signal and connected between said second internal node and said ground node; and

a fourth N channel MOS transistor rendered conductive in said normal mode to transmit said second command signal to said first internal node.

16. The semiconductor device according to

claim 15

, wherein

said first and second N channel MOS transistors have a greater threshold voltage than that of said third and fourth N channel MOS transistors.

17. The semiconductor device according to

claim 8

, wherein

said logic portion outputs a mode switch signal indicating transition to said power down mode,

said second peripheral circuit further includes a holding circuit holding mode information indicating said power down mode according to said mode switch signal, and

said holding circuit receives a reset signal from said logic portion when mode returns from said power down mode to said normal mode, and resets said mode information when said holding circuit receives a command signal a predetermined number of times from said logic portion.

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