Movatterモバイル変換


[0]ホーム

URL:


US20010040907A1 - Optical device including carbon-doped contact layers - Google Patents

Optical device including carbon-doped contact layers
Download PDF

Info

Publication number
US20010040907A1
US20010040907A1US09/097,205US9720598DUS2001040907A1US 20010040907 A1US20010040907 A1US 20010040907A1US 9720598 DUS9720598 DUS 9720598DUS 2001040907 A1US2001040907 A1US 2001040907A1
Authority
US
United States
Prior art keywords
region
contact
dopant
waveguide
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/097,205
Other versions
US6317444B1 (en
Inventor
Utpal Kumar Chakrabarti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avago Technologies International Sales Pte Ltd
Nokia of America Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IndividualfiledCriticalIndividual
Assigned to LUCENT TECHNOLOGIES INC.reassignmentLUCENT TECHNOLOGIES INC.ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).Assignors: HAMM, ROBERT ALAN, SMITH, LAWRENCE EDWIN, SEILER, JOSEPH BRIAN, CHAKRABARTI, UTPAL KUMAR, SHTENGEL, GLEB E.
Publication of US20010040907A1publicationCriticalpatent/US20010040907A1/en
Assigned to DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENTreassignmentDEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENTPATENT SECURITY AGREEMENTAssignors: AGERE SYSTEMS LLC, LSI CORPORATION
Assigned to AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.reassignmentAVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).Assignors: AGERE SYSTEMS LLC
Assigned to LSI CORPORATION, AGERE SYSTEMS LLCreassignmentLSI CORPORATIONTERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031)Assignors: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Assigned to BANK OF AMERICA, N.A., AS COLLATERAL AGENTreassignmentBANK OF AMERICA, N.A., AS COLLATERAL AGENTPATENT SECURITY AGREEMENTAssignors: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Assigned to AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.reassignmentAVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTSAssignors: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Assigned to AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDreassignmentAVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDMERGER (SEE DOCUMENT FOR DETAILS).Assignors: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Assigned to AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDreassignmentAVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITEDCORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0026. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER.Assignors: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Grantedlegal-statusCriticalCurrent

Links

Images

Classifications

Definitions

Landscapes

Abstract

The invention is an optical device and method of fabrication which mitigates the problem of Zn migration in the cladding and waveguide regions. The contact region includes carbon, which acts as a p-type dopant in ternary semiconductor material.

Description

Claims (7)

What is claimed is:
1. An optical device comprising:
a semiconductor waveguide region;
a cladding region including a dopant comprising Zn formed adjacent to the waveguide region; and
a semiconductor contact region selected from InGaAs and InGaAsP formed over the waveguide region, the contact region including a p-type dopant comprising carbon to provide sufficient conductivity to make low resistance contact the waveguide region.
2. The device according to
claim 1
wherein the concentration of the dopant is within the range 1×1018-3×1019cm−3.
3. The device according to
claim 1
wherein the device is an electroabsorption modulated laser.
4. The device according to
claim 1
wherein the device is a Capped Mesa buried heterostructure laser.
5. A method for fabricating an optical device comprising the steps of:
epitaxially forming, a semiconductor waveguide region over a substrate;
forming a cladding region adjacent to said waveguide region, the cladding region including a dopant comprising Zn; and
epitaxially forming a contact region selected from InGaAs and InGaAsP over the waveguide region, the contact layer including a p-type dopant comprising carbon to provide a sufficient conductivity to make low resistance contact to the waveguide region.
6. The method according to
claim 5
wherein the concentration of the dopant is within the range 1×1018-3×1019cm−3.
7. The method according to
claim 5
wherein the contact region is formed by metallorganic chemical vapor deposition.
US09/097,2051998-06-121998-06-12Optical device including carbon-doped contact layersGrantedUS20010040907A1 (en)

Applications Claiming Priority (1)

Application NumberPriority DateFiling DateTitle
US09/097,205US6317444B1 (en)1998-06-121998-06-12Optical device including carbon-doped contact layers

Publications (1)

Publication NumberPublication Date
US20010040907A1true US20010040907A1 (en)2001-11-15

Family

ID=22262037

Family Applications (2)

Application NumberTitlePriority DateFiling Date
US09/097,205GrantedUS20010040907A1 (en)1998-06-121998-06-12Optical device including carbon-doped contact layers
US09/097,205Expired - LifetimeUS6317444B1 (en)1998-06-121998-06-12Optical device including carbon-doped contact layers

Family Applications After (1)

Application NumberTitlePriority DateFiling Date
US09/097,205Expired - LifetimeUS6317444B1 (en)1998-06-121998-06-12Optical device including carbon-doped contact layers

Country Status (4)

CountryLink
US (2)US20010040907A1 (en)
EP (1)EP0964489A1 (en)
JP (1)JP2000031580A (en)
CN (1)CN1239342A (en)

Cited By (26)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US7479421B2 (en)2005-09-282009-01-20Intel CorporationProcess for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US7518196B2 (en)*2005-02-232009-04-14Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US7547637B2 (en)2005-06-212009-06-16Intel CorporationMethods for patterning a semiconductor film
US7550333B2 (en)2004-10-252009-06-23Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US7579280B2 (en)2004-06-012009-08-25Intel CorporationMethod of patterning a film
US7736956B2 (en)2005-08-172010-06-15Intel CorporationLateral undercut of metal gate in SOI device
US7781771B2 (en)2004-03-312010-08-24Intel CorporationBulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7820513B2 (en)2003-06-272010-10-26Intel CorporationNonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7879675B2 (en)2005-03-142011-02-01Intel CorporationField effect transistor with metal source/drain regions
US7898041B2 (en)2005-06-302011-03-01Intel CorporationBlock contact architectures for nanoscale channel transistors
US7902014B2 (en)2005-09-282011-03-08Intel CorporationCMOS devices with a single work function gate electrode and method of fabrication
US7960794B2 (en)2004-08-102011-06-14Intel CorporationNon-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7989280B2 (en)2005-11-302011-08-02Intel CorporationDielectric interface for group III-V semiconductor device
US8084818B2 (en)2004-06-302011-12-27Intel CorporationHigh mobility tri-gate devices and methods of fabrication
US8268709B2 (en)2004-09-292012-09-18Intel CorporationIndependently accessed double-gate and tri-gate transistors in same process flow
US8362566B2 (en)2008-06-232013-01-29Intel CorporationStress in trigate devices using complimentary gate fill materials
US8405164B2 (en)2003-06-272013-03-26Intel CorporationTri-gate transistor device with stress incorporation layer and method of fabrication
US8617945B2 (en)2006-08-022013-12-31Intel CorporationStacking fault and twin blocking barrier for integrating III-V on Si
US9337307B2 (en)2005-06-152016-05-10Intel CorporationMethod for fabricating transistor with thinned channel
CN106461987A (en)*2014-02-242017-02-22洛克利光子有限公司Detector remodulator
US10401656B2 (en)2017-07-052019-09-03Rockley Photonics LimitedOptoelectronic device
US10928659B2 (en)2014-02-242021-02-23Rockley Photonics LimitedOptoelectronic device
US11036006B2 (en)2016-12-022021-06-15Rockley Photonics LimitedWaveguide device and method of doping a waveguide device
US11101256B2 (en)2016-11-232021-08-24Rockley Photonics LimitedOptical modulators
US11105975B2 (en)2016-12-022021-08-31Rockley Photonics LimitedWaveguide optoelectronic device
US11150494B2 (en)2015-03-052021-10-19Rockley Photonics LimitedWaveguide modulator structures

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US7160746B2 (en)2001-07-272007-01-09Lightwave Microsystems CorporationGeBPSG top clad for a planar lightwave circuit
US6553170B2 (en)2001-08-312003-04-22Lightwave Microsystems CorporationMethod and system for a combination of high boron and low boron BPSG top clad fabrication process for a planar lightwave circuit
JP4500516B2 (en)*2002-12-132010-07-14三菱電機株式会社 Semiconductor laser device and manufacturing method thereof
US7142342B2 (en)*2003-06-022006-11-28Avago Technologies Fiber Ip (Singapore) Pte. Ltd.Electroabsorption modulator
DE102004006648B4 (en)*2004-02-112008-11-13Pfw Aerospace Ag Cargo hold floor for aircraft
US7332439B2 (en)2004-09-292008-02-19Intel CorporationMetal gate transistors with epitaxial source and drain regions
JP5243901B2 (en)*2008-09-192013-07-24日本オクラロ株式会社 Coaxial type semiconductor optical module
CN111682400B (en)*2020-06-222021-07-20苏州长光华芯光电技术股份有限公司Method for manufacturing contact layer, semiconductor laser and manufacturing method thereof
EP4568030A1 (en)*2022-08-042025-06-11Sumitomo Electric Industries, Ltd.Semiconductor laminate, semiconductor element, and method for producing semiconductor laminate

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
JPS61258487A (en)1985-05-111986-11-15Fujitsu Ltd Manufacturing method of quantum well laser
JPH01214190A (en)1988-02-231989-08-28Toshiba CorpSemiconductor laser device
JPH05198895A (en)1991-10-311993-08-06Fujitsu Ltd Semiconductor light emitting device and method of manufacturing the same
US5212703A (en)*1992-02-181993-05-18Eastman Kodak CompanySurface emitting lasers with low resistance bragg reflectors
JP2809124B2 (en)1995-02-091998-10-08日本電気株式会社 Optical semiconductor integrated device and method of manufacturing the same
US5706306A (en)*1996-03-151998-01-06MotorolaVCSEL with distributed Bragg reflectors for visible light
US5719893A (en)1996-07-171998-02-17Motorola, Inc.Passivated vertical cavity surface emitting laser
US5818861A (en)*1996-07-191998-10-06Hewlett-Packard CompanyVertical cavity surface emitting laser with low band gap highly doped contact layer
JPH10135567A (en)1996-11-011998-05-22Sharp Corp Semiconductor laser device

Cited By (61)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US20110020987A1 (en)*2003-06-272011-01-27Hareland Scott ANonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US8273626B2 (en)2003-06-272012-09-25Intel CorporationnNonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US8405164B2 (en)2003-06-272013-03-26Intel CorporationTri-gate transistor device with stress incorporation layer and method of fabrication
US7820513B2 (en)2003-06-272010-10-26Intel CorporationNonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7781771B2 (en)2004-03-312010-08-24Intel CorporationBulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7579280B2 (en)2004-06-012009-08-25Intel CorporationMethod of patterning a film
US8084818B2 (en)2004-06-302011-12-27Intel CorporationHigh mobility tri-gate devices and methods of fabrication
US7960794B2 (en)2004-08-102011-06-14Intel CorporationNon-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US8399922B2 (en)2004-09-292013-03-19Intel CorporationIndependently accessed double-gate and tri-gate transistors
US8268709B2 (en)2004-09-292012-09-18Intel CorporationIndependently accessed double-gate and tri-gate transistors in same process flow
US8749026B2 (en)2004-10-252014-06-10Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US8502351B2 (en)2004-10-252013-08-06Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US9190518B2 (en)2004-10-252015-11-17Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US7550333B2 (en)2004-10-252009-06-23Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US9741809B2 (en)2004-10-252017-08-22Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US10236356B2 (en)2004-10-252019-03-19Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US8067818B2 (en)2004-10-252011-11-29Intel CorporationNonplanar device with thinned lower body portion and method of fabrication
US9614083B2 (en)*2005-02-232017-04-04Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US8664694B2 (en)2005-02-232014-03-04Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US8183646B2 (en)*2005-02-232012-05-22Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US7518196B2 (en)*2005-02-232009-04-14Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US10121897B2 (en)2005-02-232018-11-06Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US9748391B2 (en)2005-02-232017-08-29Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US9368583B2 (en)2005-02-232016-06-14Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US9048314B2 (en)2005-02-232015-06-02Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US8368135B2 (en)2005-02-232013-02-05Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US8816394B2 (en)2005-02-232014-08-26Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US7893506B2 (en)2005-02-232011-02-22Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US7825481B2 (en)2005-02-232010-11-02Intel CorporationField effect transistor with narrow bandgap source and drain regions and method of fabrication
US7879675B2 (en)2005-03-142011-02-01Intel CorporationField effect transistor with metal source/drain regions
US9806195B2 (en)2005-06-152017-10-31Intel CorporationMethod for fabricating transistor with thinned channel
US9337307B2 (en)2005-06-152016-05-10Intel CorporationMethod for fabricating transistor with thinned channel
US11978799B2 (en)2005-06-152024-05-07Tahoe Research, Ltd.Method for fabricating transistor with thinned channel
US10937907B2 (en)2005-06-152021-03-02Intel CorporationMethod for fabricating transistor with thinned channel
US10367093B2 (en)2005-06-152019-07-30Intel CorporationMethod for fabricating transistor with thinned channel
US7547637B2 (en)2005-06-212009-06-16Intel CorporationMethods for patterning a semiconductor film
US9385180B2 (en)2005-06-212016-07-05Intel CorporationSemiconductor device structures and methods of forming semiconductor structures
US8071983B2 (en)2005-06-212011-12-06Intel CorporationSemiconductor device structures and methods of forming semiconductor structures
US8581258B2 (en)2005-06-212013-11-12Intel CorporationSemiconductor device structures and methods of forming semiconductor structures
US8933458B2 (en)2005-06-212015-01-13Intel CorporationSemiconductor device structures and methods of forming semiconductor structures
US9761724B2 (en)2005-06-212017-09-12Intel CorporationSemiconductor device structures and methods of forming semiconductor structures
US7898041B2 (en)2005-06-302011-03-01Intel CorporationBlock contact architectures for nanoscale channel transistors
US7736956B2 (en)2005-08-172010-06-15Intel CorporationLateral undercut of metal gate in SOI device
US8193567B2 (en)2005-09-282012-06-05Intel CorporationProcess for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US7479421B2 (en)2005-09-282009-01-20Intel CorporationProcess for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US7902014B2 (en)2005-09-282011-03-08Intel CorporationCMOS devices with a single work function gate electrode and method of fabrication
US8294180B2 (en)2005-09-282012-10-23Intel CorporationCMOS devices with a single work function gate electrode and method of fabrication
US7989280B2 (en)2005-11-302011-08-02Intel CorporationDielectric interface for group III-V semiconductor device
US8617945B2 (en)2006-08-022013-12-31Intel CorporationStacking fault and twin blocking barrier for integrating III-V on Si
US9450092B2 (en)2008-06-232016-09-20Intel CorporationStress in trigate devices using complimentary gate fill materials
US9806193B2 (en)2008-06-232017-10-31Intel CorporationStress in trigate devices using complimentary gate fill materials
US8362566B2 (en)2008-06-232013-01-29Intel CorporationStress in trigate devices using complimentary gate fill materials
US9224754B2 (en)2008-06-232015-12-29Intel CorporationStress in trigate devices using complimentary gate fill materials
US8741733B2 (en)2008-06-232014-06-03Intel CorporationStress in trigate devices using complimentary gate fill materials
CN106461987A (en)*2014-02-242017-02-22洛克利光子有限公司Detector remodulator
US10928659B2 (en)2014-02-242021-02-23Rockley Photonics LimitedOptoelectronic device
US11150494B2 (en)2015-03-052021-10-19Rockley Photonics LimitedWaveguide modulator structures
US11101256B2 (en)2016-11-232021-08-24Rockley Photonics LimitedOptical modulators
US11036006B2 (en)2016-12-022021-06-15Rockley Photonics LimitedWaveguide device and method of doping a waveguide device
US11105975B2 (en)2016-12-022021-08-31Rockley Photonics LimitedWaveguide optoelectronic device
US10401656B2 (en)2017-07-052019-09-03Rockley Photonics LimitedOptoelectronic device

Also Published As

Publication numberPublication date
EP0964489A1 (en)1999-12-15
CN1239342A (en)1999-12-22
JP2000031580A (en)2000-01-28
US6317444B1 (en)2001-11-13

Similar Documents

PublicationPublication DateTitle
US6317444B1 (en)Optical device including carbon-doped contact layers
US6437372B1 (en)Diffusion barrier spikes for III-V structures
US4864581A (en)Semiconductor structures and a method of manufacturing semiconductor structures
EP0132081B1 (en)Semiconductor laser device
EP0103415A2 (en)Light-emitting semiconductor devices and methods of producing the same
US6911713B2 (en)Optical device having a carrier-depleted layer
US5661743A (en)Semiconductor laser
US5020068A (en)Semiconductor laser device
EP0083697A1 (en)Double channel planar buried heterostructure laser
US6391671B2 (en)Method of producing an optical semiconductor device having a waveguide layer buried in an InP current blocking layer
US6706542B1 (en)Application of InAIAs double-layer to block dopant out-diffusion in III-V device Fabrication
US4766472A (en)Monolithic semiconductor structure of a laser and a field effect transistor
US5335241A (en)Buried stripe type semiconductor laser device
EP0293000B1 (en)Light emitting device
US5309465A (en)Ridge waveguide semiconductor laser with thin active region
EP0915542B1 (en)Semiconductor laser having improved current blocking layers and method of forming the same
US6819695B1 (en)Dopant diffusion barrier layer for use in III-V structures
US5770471A (en)Method of making semiconductor laser with aluminum-free etch stopping layer
US5518954A (en)Method for fabricating a semiconductor laser
JPH09214045A (en) Semiconductor laser and manufacturing method thereof
EP1271722A1 (en)Semiconductor laser structure and method of manufacturing same
US5572539A (en)II-VI semiconductor laser with different guide layers
US20030112841A1 (en)Means of controlling dopant diffusion in a semiconductor heterostructure
US4517674A (en)Zinc-diffused narrow stripe AlGaAs/GaAs double heterostructure laser
US20030062517A1 (en)Semiconductor device with current confinement structure

Legal Events

DateCodeTitleDescription
ASAssignment

Owner name:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG

Free format text:PATENT SECURITY AGREEMENT;ASSIGNORS:LSI CORPORATION;AGERE SYSTEMS LLC;REEL/FRAME:032856/0031

Effective date:20140506

ASAssignment

Owner name:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD

Free format text:ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AGERE SYSTEMS LLC;REEL/FRAME:035365/0634

Effective date:20140804

ASAssignment

Owner name:LSI CORPORATION, CALIFORNIA

Free format text:TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039

Effective date:20160201

Owner name:AGERE SYSTEMS LLC, PENNSYLVANIA

Free format text:TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031);ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:037684/0039

Effective date:20160201

ASAssignment

Owner name:BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH CAROLINA

Free format text:PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001

Effective date:20160201

Owner name:BANK OF AMERICA, N.A., AS COLLATERAL AGENT, NORTH

Free format text:PATENT SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:037808/0001

Effective date:20160201

ASAssignment

Owner name:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., SINGAPORE

Free format text:TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001

Effective date:20170119

Owner name:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD

Free format text:TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS;ASSIGNOR:BANK OF AMERICA, N.A., AS COLLATERAL AGENT;REEL/FRAME:041710/0001

Effective date:20170119

ASAssignment

Owner name:AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITE

Free format text:MERGER;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:047195/0026

Effective date:20180509

ASAssignment

Owner name:AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITE

Free format text:CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0026. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:047477/0423

Effective date:20180905


[8]ページ先頭

©2009-2025 Movatter.jp