Movatterモバイル変換


[0]ホーム

URL:


US20010023956A1 - Process of manufacturing a dram cell capacitor having increased trench capacitance - Google Patents

Process of manufacturing a dram cell capacitor having increased trench capacitance
Download PDF

Info

Publication number
US20010023956A1
US20010023956A1US09/767,634US76763401AUS2001023956A1US 20010023956 A1US20010023956 A1US 20010023956A1US 76763401 AUS76763401 AUS 76763401AUS 2001023956 A1US2001023956 A1US 2001023956A1
Authority
US
United States
Prior art keywords
substrate
trench
side walls
trenches
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/767,634
Other versions
US6440813B2 (en
Inventor
Christopher Collins
Harris Jones
James Norum
Stefan Schmitz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IndividualfiledCriticalIndividual
Priority to US09/767,634priorityCriticalpatent/US6440813B2/en
Publication of US20010023956A1publicationCriticalpatent/US20010023956A1/en
Application grantedgrantedCritical
Publication of US6440813B2publicationCriticalpatent/US6440813B2/en
Anticipated expirationlegal-statusCritical
Expired - Fee Relatedlegal-statusCriticalCurrent

Links

Images

Classifications

Definitions

Landscapes

Abstract

A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches electrically connect. The invention also includes a single trench capacitor wherein the trench is curved around an axis substantially perpendicular to a substrate surface.

Description

Claims (45)

What is claimed:
1. A trench capacitor comprising a first trench adjacent a second trench in a substrate, said substrate having a surface, each of said trenches having a top on said surface, a bottom in said substrate, and opposing inner and outer side walls extending from said top to said bottom, wherein the inner wall of said first trench electrically contacts the inner wall of said second trench.
2. The trench capacitor of
claim 1
wherein the inner wall of said first trench electrically contacts the inner wall of said second trench through a contact bridge adjacent to the substrate surface.
3. The trench capacitor of
claim 1
wherein the inner wall of said first trench physically contacts the inner wall of said second trench.
4. The trench capacitor of
claim 1
wherein said opposing side walls in at least one of said trenches curve away from each other from top to bottom.
5. The trench capacitor of
claim 1
wherein said opposing side walls in at least one of said trenches curve in opposite directions and reach a maximum distance from each other at a point intermediate the top and bottom of said trench.
6. The trench capacitor of
claim 1
wherein at least one of said trenches is curved around an axis substantially perpendicular to the substrate surface.
7. The trench capacitor of
claim 1
wherein the substrate is silicon.
8. The capacitor of
claim 1
wherein said trenches have a dielectric layer on the trench side walls and an electrode deposited in said trenches.
9. The capacitor of
claim 8
wherein said dielectric layer is silicon oxide.
10. The capacitor of
claim 8
wherein said dielectric layer comprises a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.
11. The capacitor of
claim 8
wherein said electrode is heavily doped polysilicon.
12. A process of fabricating a trench capacitor having two trenches extending in a substrate, said process comprising the steps of:
(i) forming said trenches extending in the substrate such that a substrate portion extends between said trenches, said trenches having side walls; and
(ii) removing a surface portion of said substrate portion such that said trenches physically connect.
13. The process of
claim 12
wherein the step of forming said trenches comprises:
forming a mask on said substrate, said mask having openings extending to the substrate, wherein a mask island is formed between said openings; and
etching said substrate through said openings to form said trenches.
14. The process of
claim 12
wherein said step of removing a surface portion of said substrate comprises etching the mask island and the surface portion of said substrate underlying said mask island.
15. The process of
claim 12
wherein steps (i) and (ii) occur simultaneously.
16. The process of
claim 12
wherein said steps of forming said trenches and removing a surface portion of said substrate portion are completed by reactive ion etching said substrate.
17. The process of
claim 14
wherein said step of etching the mask island is completed by reactive ion etching.
18. The process of
claim 12
wherein the trenches are formed such that said trenches are curved around an axis substantially perpendicular to the substrate surface.
19. The process of
claim 12
wherein said side walls are radially expanded.
20. The process of
claim 19
wherein said radially expanded side walls are formed by reactive ion etching the substrate in an etching chamber having a cathode, and increasing a temperature of the cathode to radially expand said side walls.
21. The process of
claim 19
wherein said radially expanded side walls are formed by etching the substrate with a plasma comprising NF3, HBr, and HeO2.
22. The process of
claim 19
wherein said radially expanded side walls are formed by etching the side walls with a gas selected from the group consisting of SF6, CF4, Cl2, and a combination thereof.
23. A process of fabricating a trench capacitor having two trenches extending in a substrate, said process comprising the steps of:
forming two trenches in the substrate, said trenches having facing inner side walls; and
radially expanding the side walls below a surface of said substrate such that the trench inner side walls electrically contact.
24. The process of
claim 23
wherein the step of forming said trenches comprises:
forming a mask on said substrate, said mask having openings extending to said substrate; and
etching said substrate through said openings to form said trenches.
25. The process of
claim 24
wherein said etching is reactive ion etching.
26. The process of
claim 23
wherein the trenches are formed such that said trenches are curved around an axis substantially perpendicular to the substrate surface.
27. The process of
claim 23
wherein the step of radially expanding the side walls includes reactive ion etching the substrate in an etching chamber having a cathode and increasing the temperature of the cathode to radially expand said side walls.
28. The process of
claim 23
wherein the step of radially expanding the side walls comprises etching the substrate with a plasma comprising NF3, HBr, and HeO2.
29. The process of
claim 23
wherein the step of radially expanding the side walls comprises etching the side walls with a gas selected from the group consisting of SF6, CF4, Cl2, and a combination thereof.
30. A trench capacitor comprising a trench in a substrate, said substrate having a surface, wherein the trench is curved around an axis substantially perpendicular to the substrate surface, said trench having a top on said surface, a bottom in said substrate and opposing inner and outer side walls extending from said top to said bottom.
31. The trench capacitor of
claim 30
wherein said curved trench completely surrounds said axis.
32. The trench capacitor of
claim 30
wherein said opposing side walls curve in opposite directions and reach a maximum distance from each other at a point intermediate the top and bottom of said trench.
33. The trench capacitor of
claim 30
wherein said inner side walls physically contact.
34. The trench capacitor of
claim 30
wherein the substrate is silicon.
35. The trench capacitor of
claim 30
wherein the trench has a dielectric layer on the trench side walls and an electrode deposited in said trench.
36. The capacitor of
claim 30
wherein said dielectric layer is silicon oxide.
37. The capacitor of
claim 30
wherein said dielectric layer comprises a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.
38. The capacitor of
claim 30
wherein said electrode is heavily doped polysilicon.
39. A process of fabricating a trench capacitor having a trench extending in a substrate, said trench having side walls, wherein the trench is curved around an axis substantially perpendicular to a substrate surface, said process comprising the steps of:
forming a mask on a substrate, said mask having a mask island and having an opening curved around an axis substantially perpendicular to a substrate surface, said opening extending to the substrate;
etching said substrate through said opening to form said trench.
40. The process of
claim 39
wherein said step of etching said substrate further comprises etching the mask island and the surface portion of said substrate underlying said mask island.
41. The process of
claim 39
wherein said curved trench completely surrounds said axis.
42. The process of
claim 39
wherein said side walls are radially expanded.
43. The process of
claim 39
wherein said radially expanded side walls are formed by reactive ion etching the substrate in an etching chamber having a cathode, and increasing the temperature of the cathode to radially expand said side walls.
44. The process of
claim 39
wherein said radially expanded side walls are formed by etching the substrate with a plasma comprising NF3, HBr, and HeO2.
45. The process of
claim 39
wherein said radially expanded side walls are formed by etching the side walls with a gas selected from the group consisting of SF6, CF4, Cl2, and a combination thereof.
US09/767,6341999-06-092001-01-23Process of manufacturing a DRAM cell capacitor having increased trench capacitanceExpired - Fee RelatedUS6440813B2 (en)

Priority Applications (1)

Application NumberPriority DateFiling DateTitle
US09/767,634US6440813B2 (en)1999-06-092001-01-23Process of manufacturing a DRAM cell capacitor having increased trench capacitance

Applications Claiming Priority (2)

Application NumberPriority DateFiling DateTitle
US09/328,961US6188096B1 (en)1999-06-091999-06-09DRAM cell capacitor having increased trench capacitance
US09/767,634US6440813B2 (en)1999-06-092001-01-23Process of manufacturing a DRAM cell capacitor having increased trench capacitance

Related Parent Applications (1)

Application NumberTitlePriority DateFiling Date
US09/328,961DivisionUS6188096B1 (en)1999-06-091999-06-09DRAM cell capacitor having increased trench capacitance

Publications (2)

Publication NumberPublication Date
US20010023956A1true US20010023956A1 (en)2001-09-27
US6440813B2 US6440813B2 (en)2002-08-27

Family

ID=23283235

Family Applications (2)

Application NumberTitlePriority DateFiling Date
US09/328,961Expired - Fee RelatedUS6188096B1 (en)1999-06-091999-06-09DRAM cell capacitor having increased trench capacitance
US09/767,634Expired - Fee RelatedUS6440813B2 (en)1999-06-092001-01-23Process of manufacturing a DRAM cell capacitor having increased trench capacitance

Family Applications Before (1)

Application NumberTitlePriority DateFiling Date
US09/328,961Expired - Fee RelatedUS6188096B1 (en)1999-06-091999-06-09DRAM cell capacitor having increased trench capacitance

Country Status (1)

CountryLink
US (2)US6188096B1 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US6544838B2 (en)*2001-03-132003-04-08Infineon Technologies AgMethod of deep trench formation with improved profile control and surface area
US20040266098A1 (en)*2003-06-272004-12-30Tse-Yao HuangMethod of forming geometric deep trench capacitors
US20070189057A1 (en)*2006-01-102007-08-16International Business Machines CorporationMultiple port memory having a plurality of parallel connected trench capacitors in a cell
US20080102639A1 (en)*2006-10-302008-05-01Hynix Semiconductor Inc.Method for fabricating semiconductor device with recess gate
US20100117132A1 (en)*2008-11-132010-05-13Inotera Memories, Inc.Memory device and fabrication method thereof
US10079277B2 (en)*2016-11-282018-09-18United Microelectronics Corp.Method of fabricating metal-insulator-metal capacitor
US20210343881A1 (en)*2019-12-272021-11-04Taiwan Semiconductor Manufacturing Company, Ltd.Trench capacitor profile to decrease substrate warpage

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
WO2001082075A2 (en)2000-04-252001-11-01Icplanet Acquisition CorporationSystem and method for scheduling execution of cross-platform computer processes
DE50107496D1 (en)*2001-07-202006-02-02Infineon Technologies Ag Method for producing self-aligning mask layers
US6781184B2 (en)*2001-11-292004-08-24Symetrix CorporationBarrier layers for protecting metal oxides from hydrogen degradation
US6894336B2 (en)*2002-06-122005-05-17Infineon Technologies AgVertical access transistor with curved channel
US6989561B2 (en)*2003-12-022006-01-24Nanya Technology Corp.Trench capacitor structure
JP4446202B2 (en)*2006-09-222010-04-07エルピーダメモリ株式会社 Semiconductor device and manufacturing method of semiconductor device
TWI358818B (en)2008-03-272012-02-21Inotera Memories IncMemory device and fabrication thereof
US9349789B1 (en)2014-12-092016-05-24International Business Machines CorporationCoaxial carbon nanotube capacitor for eDRAM
CN115425006B (en)*2022-09-292025-02-07武汉新芯集成电路股份有限公司 Deep trench capacitor and method of manufacturing the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US4688063A (en)1984-06-291987-08-18International Business Machines CorporationDynamic ram cell with MOS trench capacitor in CMOS
US4939104A (en)*1984-10-311990-07-03Texas Instruments, IncorporatedMethod for forming a buried lateral contact
US5190889A (en)*1991-12-091993-03-02Motorola, Inc.Method of forming trench isolation structure with germanium silicate filling
JP3069468B2 (en)*1993-06-142000-07-24株式会社東芝 Method for manufacturing semiconductor device
US5731941A (en)*1995-09-081998-03-24International Business Machines CorporationElectrostatic discharge suppression circuit employing trench capacitor
US5656532A (en)*1996-01-111997-08-12Vanguard International Semiconductor CorporationMethod for fabricating a coaxial capacitor of a semiconductor device
US6015985A (en)*1997-01-212000-01-18International Business Machines CorporationDeep trench with enhanced sidewall surface area
TW356601B (en)*1997-08-281999-04-21Tsmc Acer Semiconductor Mfg CorpMethod for making memory cell of self-aligning field plate and structure of the same
TW429613B (en)*1999-10-212001-04-11Mosel Vitelic IncDynamic random access memory with trench type capacitor

Cited By (17)

* Cited by examiner, † Cited by third party
Publication numberPriority datePublication dateAssigneeTitle
US6544838B2 (en)*2001-03-132003-04-08Infineon Technologies AgMethod of deep trench formation with improved profile control and surface area
US20040266098A1 (en)*2003-06-272004-12-30Tse-Yao HuangMethod of forming geometric deep trench capacitors
US6964926B2 (en)*2003-06-272005-11-15Nanya Technology CorporationMethod of forming geometric deep trench capacitors
US7785959B2 (en)*2006-01-102010-08-31International Business Machines CorporationMethod of multi-port memory fabrication with parallel connected trench capacitors in a cell
US20070189057A1 (en)*2006-01-102007-08-16International Business Machines CorporationMultiple port memory having a plurality of parallel connected trench capacitors in a cell
WO2007082227A3 (en)*2006-01-102008-09-25IbmMultiple port memory having a plurality of parallel connected trench capacitors in a cell
US7485525B2 (en)*2006-01-102009-02-03International Business Machines CorporationMethod of manufacturing a multiple port memory having a plurality of parallel connected trench capacitors in a cell
EP1977425A4 (en)*2006-01-102009-04-29Ibm MEMORY WITH MULTIPLE PORTS HAVING MULTIPLE TRENCH CAPACITORS CONNECTED IN PARALLEL IN A CELL
US20090176339A1 (en)*2006-01-102009-07-09Kangguo ChengMethod of multi-port memory fabrication with parallel connected trench capacitors in a cell
US20080102639A1 (en)*2006-10-302008-05-01Hynix Semiconductor Inc.Method for fabricating semiconductor device with recess gate
US7858476B2 (en)*2006-10-302010-12-28Hynix Semiconductor Inc.Method for fabricating semiconductor device with recess gate
US20100117132A1 (en)*2008-11-132010-05-13Inotera Memories, Inc.Memory device and fabrication method thereof
US8294189B2 (en)*2008-11-132012-10-23Inotera Memories, Inc.Memory device and fabrication method thereof
US10079277B2 (en)*2016-11-282018-09-18United Microelectronics Corp.Method of fabricating metal-insulator-metal capacitor
US20210343881A1 (en)*2019-12-272021-11-04Taiwan Semiconductor Manufacturing Company, Ltd.Trench capacitor profile to decrease substrate warpage
US11769792B2 (en)*2019-12-272023-09-26Taiwan Semiconductor Manufacturing Company, Ltd.Trench capacitor profile to decrease substrate warpage
US12176387B2 (en)2019-12-272024-12-24Taiwan Semiconductor Manufacturing Company, Ltd.Trench capacitor profile to decrease substrate warpage

Also Published As

Publication numberPublication date
US6440813B2 (en)2002-08-27
US6188096B1 (en)2001-02-13

Similar Documents

PublicationPublication DateTitle
US6905944B2 (en)Sacrificial collar method for improved deep trench processing
KR100598301B1 (en) Trench Capacitor with Insulation Collar
KR100609545B1 (en)A trench capacitor with isolation collar and corresponding manufacturing method
US6188096B1 (en)DRAM cell capacitor having increased trench capacitance
US5821139A (en)Method for manufacturing a DRAM with increased electrode surface area
JP3222944B2 (en) Method for manufacturing capacitor of DRAM cell
US5913118A (en)Method of manufacturing trench DRAM cells with self-aligned field plate
US6294436B1 (en)Method for fabrication of enlarged stacked capacitors using isotropic etching
US5966612A (en)Method of making a multiple mushroom shape capacitor for high density DRAMs
US6020609A (en)DRAM cell with a rugged stacked trench (RST) capacitor
US6150213A (en)Method of forming a cob dram by using self-aligned node and bit line contact plug
US5933742A (en)Multi-crown capacitor for high density DRAMS
US5539230A (en)Chimney capacitor
US5759895A (en)Method of fabricating a capacitor storage node having a rugged-fin surface
US5770510A (en)Method for manufacturing a capacitor using non-conformal dielectric
US5913129A (en)Method of fabricating a capacitor structure for a dynamic random access memory
US20030060005A1 (en)Increased capacitance trench capacitor
KR100227176B1 (en)Method for fabricating semiconductor memory device
US5512768A (en)Capacitor for use in DRAM cell using surface oxidized silicon nodules
US5814549A (en)Method of making porous-si capacitor dram cell
US20030045119A1 (en)Method for forming a bottle-shaped trench
US5701264A (en)Dynamic random access memory cell having increased capacitance
US7018893B1 (en)Method for fabricating bottom electrodes of stacked capacitor memory cells
US7504299B2 (en)Folded node trench capacitor
US6184078B1 (en)Method for fabricating a capacitor for a dynamic random access memory cell

Legal Events

DateCodeTitleDescription
FPAYFee payment

Year of fee payment:4

REMIMaintenance fee reminder mailed
LAPSLapse for failure to pay maintenance fees
STCHInformation on status: patent discontinuation

Free format text:PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FPLapsed due to failure to pay maintenance fee

Effective date:20100827


[8]ページ先頭

©2009-2025 Movatter.jp