US20010015499A1 - Semiconductor device and method for fabricating the same - Google Patents

Abstract

An insulating film is formed of a carbon-containing silicon dioxide film on a semiconductor substrate. In the insulating film, an interconnect groove is formed. A silicon dioxide layer with a density high enough to allow almost no oxygen to pass therethrough is formed on the bottom and side faces of the interconnect groove. And a metal interconnect is formed on the silicon dioxide layer inside the interconnect groove.

Description

BACKGROUND OF THE INVENTION
• The present invention relates to a semiconductor device, including metal interconnects laid in an insulating film with a low dielectric constant (which will be herein called a low-dielectric-constant film), and also relates to a method for fabricating the same.[0001]
• Hereinafter, the structure of a semiconductor device, including inlaid metal interconnects in a low-dielectric-constant film, will be described with reference to FIG. 6.[0002]
• As shown in FIG. 6, a second[0003]insulating film102 is formed of a silicon dioxide film, for example, on a firstinsulating film101 deposited on asemiconductor substrate100. In the secondinsulating film102,metal interconnects105 have been formed. Specifically, each of themetal interconnects105 consists of abarrier metal layer105aof tantalum nitride, for example, and amain interconnect layer105bof copper, for instance.
• In this semiconductor device, the second[0004]insulting film102, which exists between themetal interconnects105, is made of silicon dioxide with a dielectric constant between about 3.9 and about 4.2. Therefore, a parasitic capacitance, generated between themetal interconnects105, increases, thereby interfering with high-speed operation of the semiconductor device.
• To solve this problem, a carbon-containing silicon dioxide film with a low dielectric constant of about 2.5 may be used as the second[0005]insulating film102.
• Hereinafter, a method for fabricating a semiconductor device, including inlaid metal interconnects formed in an insulating film of carbon-containing silicon dioxide, will be described with reference to FIGS.[0006]7A through FIGS. 7E.
• First, as shown in FIG. 7A, a second[0007]insulating film110 of carbon-containing silicon dioxide, is deposited on a firstinsulating film101 formed on asemiconductor substrate100. Then, aresist pattern111 with openings for forming interconnect grooves is defined on the secondinsulating film110 as shown in FIG. 7B.
• Next, as shown in FIG. 7C, the second[0008]insulating film110 is plasma-etched using an etching gas, consisting essentially of fluorine and carbon, and being masked with theresist pattern111. In this manner,interconnect grooves112 are formed in the secondinsulating film110. As a result, the upper part of theresist pattern111 changes into a curedlayer111a. Specifically, the bonding states of atoms in the curedlayer111aare different from those of atoms in the original material of theresist pattern111 that has not yet been plasma-etched. And the curedlayer111ais made of a polymer consisting essentially of fluorine and carbon and has a thickness of about 50 nm. The curedlayer111acannot be removed by a wet etching process but can be removed by a plasma etching process using oxygen gas.
• Accordingly, the[0009]resist pattern111 is ashed away with oxygen plasma as shown in FIG. 7D. In this case, the ashing process is performed by a down flow technique (in which no bias voltage is applied to the substrate) in a vacuum between about 267 Pa and about 400 Pa, for example, and with the substrate heated to a relatively high temperature between about 150° C. and about 250° C., for instance. In this manner, theresist pattern111 with thecured layer111ain its upper part can be stripped just as intended. Also, asilicon dioxide film113 with a thickness of 200 nm, for example, is formed in the upper part of the secondinsulating film110 of carbon-containing silicon dioxide.
• In the ashing process using oxygen plasma, carbon is removed from the carbon-containing silicon dioxide for the second[0010]insulating film110, thereby producing silicon dioxide. Hereinafter, this mechanism will be described with reference to FIGS. 8 and 9.
• FIG. 8 illustrates an example of a chemical formula representing a carbon-containing silicon dioxide. If the carbon-containing silicon dioxide represented by this chemical formula and oxygen are bonded together, the following chemical reaction[0011]
• 2CH₃+7O→2CO₂↑+3H₂O↑
• occurs. Then, CH[0012]₃, which has been bonded to Si, disappears. That CH₃disappeared is replaced with O to form SiO₂bonds. Therefore, a silicon dioxide as represented by the chemical formula shown in FIG. 9 is produced.
• Next, a tantalum nitride film is deposited over the second[0013]insulating film110, or on thesilicon dioxide film113 more exactly, by a sputtering process. And then, a copper film is deposited on the tantalum nitride film by an electroplating process. Thereafter, excessive parts of the copper and tantalum nitride films, existing over the secondinsulating film110, are removed by a CMP process, thereby definingmetal interconnects114 as shown in FIG. 7E. Themetal interconnects114 are made up of abarrier metal layer114aof tantalum nitride and amain interconnect layer114bof copper.
• However, the semiconductor device formed in this manner has the following problems.[0014]
• First of all, in the step of ashing away the[0015]resist pattern111 using oxygen plasma, thesilicon dioxide film113 is adversely formed in the upper part of the secondinsulating film110 of carbon-containing silicon dioxide. Specifically, thesilicon dioxide film113 exhibits a high dielectric constant and has a thickness of 200 nm, for example. Therefore, although the carbon-containing silicon dioxide film is used as the secondinsulating film110, a parasitic capacitance generated between themetal interconnects114 cannot be reduced sufficiently.
• Also, the[0016]silicon dioxide film113 has a density between 1.7 g/cm³and 1.8 g/cm³, which is lower than that of a silicon dioxide film formed by a plasma CVD process, for instance. Therefore, when oxygen plasma is supplied in a subsequent process step, oxygen ions go through thesilicon dioxide film113 to reach and oxidize the carbon-containing silicon dioxide film under thefilm113. As a result, thesilicon dioxide film113 has its film thickness increased undesirably. This phenomenon is observed, for example, in the subsequent process step of ashing away a resist pattern for forming via holes over themetal interconnects114. The phenomenon is also observed, for instance, in the subsequent process step of ashing away a resist pattern for forming interconnect grooves for upper-level metal interconnects to be formed over the via holes.
• As described above, in the known semiconductor device including inlaid metal interconnects in an insulating film of carbon-containing silicon dioxide, a thick silicon dioxide film is unintentionally formed in upper parts of the insulting film that surround the metal interconnects. As a result, a parasitic capacitance generated between the metal interconnects increases disadvantageously.[0017]
SUMMARY OF THE INVENTION
• It is therefore an object of the present invention to enhance the performance of a semiconductor device, including inlaid metal interconnects in an insulating film of carbon-containing silicon dioxide, by reducing a parasitic capacitance produced between the metal interconnects.[0018]
• To achieve this object, a first inventive semiconductor device includes: an insulating film formed of a carbon-containing silicon dioxide film on a substrate; an interconnect groove formed in the insulating film; a silicon dioxide layer, which is formed on the bottom and side faces of the interconnect groove and has a density high enough to allow almost no oxygen to pass therethrough; and a metal interconnect formed on the silicon dioxide layer inside the interconnect groove.[0019]
• In the first inventive device, the silicon dioxide layer with a density high enough to allow almost no oxygen to pass therethrough is formed on the bottom and side faces of the interconnect groove. Therefore, even if oxygen plasma is supplied in a subsequent process step, oxygen ions cannot pass through the silicon dioxide layer, and the carbon-containing silicon dioxide film surrounding the silicon dioxide layer is not oxidized. Accordingly, the thickness of the silicon dioxide layer, existing on the bottom and side faces of the interconnect groove, does not increase. As a result, a parasitic capacitance produced between the metal interconnects can be reduced just as intended.[0020]
• In one embodiment of the first device, the silicon dioxide layer preferably has a density of 2.0 g/cm[0021]³or more.
• In such an embodiment, the silicon dioxide layer prevents the oxygen ions from passing therethrough with much more certainty. As a result, it is possible to suppress the increase in thickness of the silicon dioxide layer existing on the bottom and side faces of the interconnect groove.[0022]
• A second inventive semiconductor device includes: an insulating film formed of a carbon-containing silicon dioxide film on a substrate; an interconnect groove formed in the insulating film; a silicon dioxide layer, which is formed on the bottom and side faces of the interconnect groove and has a small and uniform thickness; and a metal interconnect formed on the silicon dioxide layer inside the interconnect groove.[0023]
• In the second inventive device, the silicon dioxide layer with a small and uniform thickness is formed on the bottom and side faces of the interconnect groove. In other words, the silicon dioxide layer, existing between the metal interconnects, has a high dielectric constant and a small and uniform thickness. As a result, a parasitic capacitance produced between the metal interconnects can be reduced just as intended.[0024]
• In one embodiment of the second device, the silicon dioxide layer preferably has a thickness of 20 nm or less.[0025]
• In such an embodiment, the parasitic capacitance produced between the metal interconnects can be further reduced.[0026]
• A first inventive method for fabricating a semiconductor device includes the steps of: a) forming an insulating film of a carbon-containing silicon dioxide film on a substrate; b) etching the insulating film using a resist pattern as a mask, thereby forming an interconnect groove in the insulating film; c) performing a dry etching process using an etching gas containing oxygen, thereby removing a cured layer and forming a silicon dioxide layer on the bottom and side faces of the interconnect groove; d) removing the resist pattern by a wet etching process; and e) filling the interconnect groove with a metal film to form a metal interconnect. The cured layer has been formed in an upper part of the resist pattern as a result of the step b).[0027]
• According to the first inventive method, by performing a dry etching process using an etching gas containing oxygen, a cured layer, formed in an upper part of a resist pattern as a result of the step b), is removed and a silicon dioxide layer is formed on the bottom and side faces of an interconnect groove. Therefore, the bottom and side faces of the interconnect groove are exposed to the etching gas containing oxygen for just a short time. Accordingly, a silicon dioxide layer with a small and uniform thickness is formed on the bottom and side faces of the interconnect groove. Also, the resist pattern having the cured layer removed is stripped by a wet etching process. Therefore, in the step d), the bottom and side faces of the interconnect groove are not exposed to the oxygen plasma, and the thickness of the silicon dioxide layer does not increase. Consequently, it is possible to reduce a parasitic capacitance produced between the metal interconnects just as intended.[0028]
• In one embodiment of the first method, the dry etching process is preferably performed within a plasma ambient at a pressure of 13.3 Pa or less.[0029]
• Then, a silicon dioxide layer with a thickness of about 20 nm or less can be formed on the bottom and side faces of the interconnect groove. As a result, the parasitic capacitance produced between the metal interconnects can be further reduced.[0030]
• In this particular embodiment, the dry etching process is preferably an anisotropic RIE process.[0031]
• In such an embodiment, a silicon dioxide layer with a thickness of about 20 nm or less and a density high enough to allow almost no oxygen to pass therethrough can be formed on the bottom and side faces of the interconnect groove. Therefore, even if oxygen plasma is supplied in a subsequent process step, oxygen ions cannot pass through the silicon dioxide layer, and a carbon-containing silicon dioxide film surrounding the silicon dioxide layer is not oxidized. Accordingly, the thickness of the silicon dioxide layer, existing on the bottom and side faces of the interconnect groove, does not increase. As a result, the parasitic capacitance produced between the metal interconnects can be reduced just as intended.[0032]
• In another embodiment, the first inventive method preferably further includes the step of removing the silicon dioxide layer, existing on the bottom and side faces of the interconnect groove, by a wet etching process.[0033]
• In such an embodiment, the silicon dioxide layer with a high dielectric constant no longer exists between the metal interconnects. As a result, the parasitic capacitance produced between the metal interconnects can be further reduced.[0034]
• A second inventive method for fabricating a semiconductor device includes the steps of: a) forming an insulating film of a carbon-containing silicon dioxide film on a substrate; b) etching the insulating film using a resist pattern as a mask, thereby forming an interconnect groove in the insulating film; c) filling the interconnect groove with a resist film; d) removing a part of the resist film, existing over the interconnect groove, and the resist pattern with a cured layer by a dry etching process using an etching gas containing oxygen; e) removing the other part of the resist film, still existing inside the interconnect groove, by a wet etching process; and f) filling the interconnect groove with a metal film to form a metal interconnect. The cured layer has been formed in an upper part of the resist pattern as a result of the step b).[0035]
• In the second inventive method, an interconnect groove is filled with a resist film and then a cured layer, existing in an upper part of a resist pattern, is removed by a dry etching process using an etching gas containing oxygen. Therefore, the bottom and side faces of the interconnect groove are not exposed to the etching gas containing oxygen, and no silicon dioxide layer is formed thereon. The other part of the resist film, still existing in the interconnect groove, is removed by a wet etching process. Accordingly, the bottom and side faces of the interconnect groove are not exposed to the oxygen plasma, and no silicon dioxide layer is formed thereon in the step e). As a result, a parasitic capacitance produced between the metal interconnects can be reduced just as intended.[0036]
• In one embodiment, the second inventive method preferably further includes the step of performing an anisotropic RIE process between the steps e) and f) within a plasma ambient containing oxygen at a pressure of 13.3 Pa or less to form a silicon dioxide layer on the bottom and side faces of the interconnect groove.[0037]
• In such an embodiment, it is possible to form a silicon dioxide layer with a thickness of about 20 nm or less and a density high enough to allow almost no oxygen to pass therethrough on the bottom and side faces of the interconnect groove. Therefore, even if oxygen plasma is supplied in a subsequent process step, oxygen ions cannot pass through the silicon dioxide layer, and a carbon-containing silicon dioxide film surrounding the silicon dioxide layer is not oxidized. As a result, the parasitic capacitance produced between the metal interconnects can be reduced just as intended.[0038]
BRIEF DESCRIPTION OF THE DRAWINGS
• FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.[0039]
• FIGS. 2A through 2F are cross-sectional views illustrating respective process steps for fabricating a semiconductor device according to a second embodiment of the present invention.[0040]
• FIGS. 3A through 3F are cross-sectional views illustrating respective process steps for fabricating a semiconductor device according to a third embodiment of the present invention.[0041]
• FIGS. 4A through 4G are cross-sectional views illustrating respective process steps for fabricating a semiconductor device according to a fourth embodiment of the present invention.[0042]
• FIGS. 5A through 5D are cross-sectional views illustrating respective process steps for fabricating a semiconductor device according to a modified example of the fourth embodiment.[0043]
• FIG. 6 is a cross-sectional view of a known semiconductor device.[0044]
• FIGS. 7A through 7E are cross-sectional views illustrating respective process steps for fabricating another known semiconductor device.[0045]
• FIG. 8 illustrates an example of a chemical formula representing a carbon-containing silicon dioxide.[0046]
• FIG. 9 illustrates a chemical formula representing a silicon dioxide obtained when oxygen and a carbon-containing silicon dioxide are bonded together.[0047]
DESCRIPTION OF THE PREFERRED EMBODIMENTS
• [0048]Embodiment 1
• Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. 1.[0049]
• FIG. 1 illustrates a cross-sectional structure of the semiconductor device according to the first embodiment. A first[0050]insulting film2 of silicon dioxide is formed on asilicon substrate1. And a second insulating film3 of carbon-containing silicon dioxide is deposited1 to a thickness of 1000 nm on the first insulatingfilm2 by a plasma CVD process or an SGO process, for example.
• In the second insulating film[0051]3,interconnect grooves5 are formed. And asilicon dioxide layer6 is formed on the bottom and side faces of theinterconnect grooves5. Thesilicon dioxide layer6 has a uniform thickness of about 20 nm or less, preferably between about 10 nm and about 15 nm, and a high density between about 2.0 g/cm³and about 2.1 g/cm³.
• On the[0052]silicon dioxide layer6 inside theinterconnect grooves5,metal interconnects7 are formed. Each of theinterconnects7 is made up of abarrier metal layer7aof tantalum nitride and amain interconnect layer7bof copper.
• In the semiconductor device of the first embodiment, the[0053]silicon dioxide layer6 with a uniform thickness of about 20 nm or less is formed on the bottom and side faces of theinterconnect grooves5. Therefore, a parasitic capacitance generated between themetal interconnects7 is reduced significantly. Further, thesilicon dioxide layer6 can improve the adhesiveness of the second insulating film3 of carbon-containing silicon dioxide to the metal interconnects7. As a result, the adhesiveness of theinterconnects7 to thegrooves5 increases.
• Furthermore, the[0054]silicon dioxide layer6 with a high density between about 2.0 g/cm³and about 2.1 g/cm³is formed on the bottom and side faces of theinterconnect grooves5, thus allowing almost no oxygen to pass therethrough. Therefore, even if oxygen plasma is supplied in a subsequent process step, oxygen ions cannot pass through thesilicon dioxide layer6. Accordingly, the carbon-containing silicon dioxide film surrounding thesilicon dioxide layer6 is not oxidized, and the thickness of thesilicon dioxide layer6, formed on the bottom and side faces of theinterconnect grooves5, does not increase. As a result, the parasitic capacitance generated between themetal interconnects7 can be reduced just as intended. This phenomenon is observed, for example, in the subsequent process step of ashing away a resist pattern for forming via holes over the metal interconnects7. The phenomenon is also observed, for instance, in the subsequent process step of ashing away a resist pattern for forming interconnect grooves for upper-level metal interconnects to be formed over the via holes.
• [0055]Embodiment 2
• Hereinafter, a method for fabricating a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS.[0056]2A through FIGS. 2F.
• First, as shown in FIG. 2A, a first insulating[0057]film12 of silicon dioxide is formed on asilicon substrate11. And a second insulatingfilm13 is deposited on the first insulatingfilm12. The second insulatingfilm13 is formed of a carbon-containing silicon dioxide film with a thickness of 1000 nm by a plasma CVD process or an SOG process, for example.
• Next, the second insulating[0058]film13 is coated with a resist film. Subsequently, the resist film is exposed to KrF excimer laser and patterned. Then, the patterned resist film is developed, thereby defining a resistpattern14 with openings for forming interconnect grooves on the second insulatingfilm13 as shown in FIG. 2B.
• Subsequently, the second insulating[0059]film13 is dry-etched with a plasma, thereby forminginterconnect grooves15 with a depth of about 500 nm in the second insulatingfilm13 as shown in FIG. 2C. Specifically, the plasma is created from an etching gas obtained by adding argon or oxygen gas to an etching gas consisting essentially of fluorine and carbon (e.g., gas containing at least one of CF₄and CHF₃gases). In this manner, the upper part of the resistpattern14 changes into a curedlayer14a. Specifically, the bonding states of atoms in the curedlayer14aare different from those of atoms in the original material of the resistpattern14, which has not yet been plasma-etched. And the curedlayer14ais made of a polymer consisting essentially of fluorine and carbon and has a thickness of about 50 nm.
• Next, as shown in FIG. 2D, the cured[0060]layer14ais removed by a plasma etching process with oxygen gas. In this process step, the resistpattern14 under the curedlayer14ais also removed slightly, but this will not cause a serious problem. Also, in this process step, the surface of theinterconnect grooves15 in the second insulatingfilm13 are also exposed to the oxygen plasma, thus forming asilicon dioxide layer16 on the bottom and side faces of theinterconnect grooves15. However, the plasma etching process is performed using the oxygen gas just to remove the curedlayer14aonly. Therefore, it takes a much shorter time to perform this plasma etching process than the plasma etching process for removing the resistpattern14 entirely. Thus, oxygen ions in the plasma cannot go deeper into the second insulatingfilm13 of carbon-containing silicon dioxide through its surface. As a result, the thinsilicon dioxide layer16 is formed on the bottom and side faces of theinterconnect grooves15.
• Hereinafter, it will be described what are the conditions of the plasma etching process using the oxygen gas.[0061]
• In a first etching method, an etching process is performed for a short time by a down flow technique in a vacuum of 13.3 Pa or less so that the cured[0062]layer14ais removed with most of the resistpattern14 left. According to this method, oxygen ions in the plasma cannot go deeper into the second insulatingfilm13 of carbon-containing silicon dioxide through its surface. As a result, asilicon dioxide layer16 with a thickness of about 20 nm or less is formed on the bottom and side faces of theinterconnect grooves15.
• In a second etching method, an anisotropic RIE (reactive ion etching) process, in which a bias voltage is applied to the[0063]silicon substrate11, is performed so that the curedlayer14ais removed with most of the resistpattern14 left. According to this method, asilicon dioxide layer16 with a high density between about 2.0 g/cm³and about 2.1 g/cm³and a thickness of about 20 nm or less is formed on the bottom and side faces of theinterconnect grooves15. In this case, if the anisotropic RIE process using the oxygen plasma is performed in a vacuum of 13.3 Pa or less, it is possible to form asilicon dioxide layer16 with a high density between about 2.0 g/cm³and about 2.1 g/cm³and a thickness between about 10 nm and about 15 nm.
• Next, the remaining part of the resist[0064]pattern14 is removed by a wet etching process using a chemical solution that can dissolve the resist, e.g., a chemical solution containing amine, as shown in FIG. 2E.
• Subsequently, a tantalum nitride film is deposited over the second insulating[0065]film13 as well as inside theinterconnect grooves15, or over thesilicon dioxide layer16 more exactly, by a sputtering process. Then, a copper film is deposited on the tantalum nitride film by an electroplating process. Thereafter, excessive parts of the copper and tantalum nitride films existing over the second insulatingfilm13, are removed by a CMP process. In this manner, metal interconnects17 are formed inside theinterconnect grooves15 as shown in FIG. 2F. The metal interconnects17 are made up of abarrier metal layer17aof tantalum nitride and amain interconnect layer17bof copper.
• In the second embodiment, if the first etching method is used for the step of removing the cured[0066]layer14aby the plasma etching process using the oxygen gas, asilicon dioxide layer16 with a thickness of about 20 nm or less can be formed on the bottom and side faces of theinterconnect grooves15. That is to say, the thickness of thesilicon dioxide layer16 with a high dielectric constant can be reduced. As a result, a parasitic capacitance between the metal interconnects17 can be reduced just as intended.
• Also, in the second embodiment, if the second etching method is used for the step of removing the cured[0067]layer14aby the plasma etching process with the oxygen gas, asilicon dioxide layer16 with a high density between about 2.0 g/cm³and about 2.1 g/cm³and a thickness of about 20 nm or less can be formed on the bottom and side faces of theinterconnect grooves15. In this process, if an anisotropic RIE process is performed using the oxygen plasma in a vacuum of 13.3 Pa or less, asilicon dioxide layer16 with a high density between about 2.0 g/cm³and about 2.1 g/cm³and a thickness between about 10 nm and about 15 nm can be formed.
• According to the second etching method, an etching process is performed in a higher vacuum (at a lower pressure) using a substrate at lower temperature and the oxygen ions has a higher energy compared to a known ashing process using oxygen plasma. Therefore, a[0068]silicon dioxide layer16 with a high density of 2.0 g/cm³or more can be formed. Thus, even if oxygen plasma is supplied in a subsequent process step, the oxygen ions cannot pass through thesilicon dioxide layer16, and the thickness of thesilicon dioxide layer16 does not increase. As a result, the parasitic capacitance generated between the metal interconnects17 can be reduced just as intended.
• Embodiment 3[0069]
• Hereinafter, a method for fabricating a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS.[0070]3A through FIGS. 3F.
• First, as shown in FIG. 3A, a first insulating[0071]film22 of silicon dioxide is formed on asilicon substrate21. And a second insulatingfilm23 is deposited on the first insulatingfilm22. The second insulatingfilm23 is formed of a carbon-containing silicon dioxide film with a thickness of 1000 nm by a plasma CVD process or an SOG process, for example. Then, a resistpattern24 with openings for forming interconnect grooves is defined on the second insulatingfilm23 as shown in FIG. 3B.
• Subsequently, the second insulating[0072]film23 is dry-etched with a plasma, thereby forminginterconnect grooves25 with a depth of about 500 nm in the second insulatingfilm23 as shown in FIG. 3C. Specifically, the plasma is created from an etching gas obtained by adding argon or oxygen gas to an etching gas consisting essentially of fluorine and carbon (e.g., at least one of CF₄and CHF₃gases). Then, the upper part of the resistpattern24 changes into a curedlayer24a, which is made of a polymer consisting essentially of fluorine and carbon and has a thickness of about 50 nm.
• Next, as shown in FIG. 3D, the cured[0073]layer24ais removed by a plasma etching process using oxygen gas. In this process step, the resistpattern24 under the curedlayer24ais also removed slightly, but this will not cause a serious problem. Further, a thinsilicon dioxide layer26 is formed on the bottom and side faces of theinterconnect grooves25 in the second insulatingfilm23. The conditions of the plasma etching process using the oxygen gas are as described for the second embodiment, so the description thereof will be omitted herein.
• Thereafter, the remaining part of the resist[0074]pattern24 is removed by a wet etching process using a chemical solution that can dissolve the resist, e.g., a chemical solution containing amine. Then, thesilicon dioxide layer26, formed on the bottom and side faces of theinterconnect grooves25, is removed by a wet etching process using a chemical solution that can remove the oxide film (e.g., a chemical solution containing ammonium fluoride) as shown in FIG. 3E.
• Next, a tantalum nitride film is deposited over the second insulating[0075]film23 as well as inside theinterconnect grooves25 by a sputtering process. Then, a copper film is deposited over the tantalum nitride film by an electroplating process. Thereafter, excessive parts of the copper and tantalum nitride films, existing over the second insulatingfilm23, are removed by a CMP process, thereby formingmetal interconnects27 inside theinterconnect grooves25 as shown in FIG. 3F. The metal interconnects27 are made up of abarrier metal layer27aof tantalum nitride and amain interconnect layer27bof copper.
• According to the third embodiment, the[0076]silicon dioxide layer26, existing on the bottom and side faces of theinterconnect grooves25, is removed and then the metal interconnects27 are formed inside theinterconnect grooves25. That is to say, thesilicon dioxide layer26 no longer exists between the metal interconnects27. As a result, a parasitic capacitance produced between the metal interconnects27 can be reduced even more significantly.
• Embodiment 4[0077]
• Hereinafter, a method for fabricating a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS.[0078]4A through FIGS. 4G.
• First, as shown in FIG. 4A, a first insulating[0079]film32 of silicon dioxide is formed on asilicon substrate31. And a second insulatingfilm33 is deposited on the first insulatingfilm32. The second insulatingfilm33 is formed of a carbon-containing silicon dioxide film with a thickness of 1000 nm by a plasma CVD process or an SOG process, for example. Then, a resistpattern34 with openings for forming interconnect grooves is defined on the second insulatingfilm33 as shown in FIG. 4B.
• Subsequently, the second insulating[0080]film33 is dry-etched with a plasma, thereby forminginterconnect grooves35 with a depth of about 500 nm in the second insulatingfilm33 as shown in FIG. 4C. Specifically, the plasma is created from an etching gas obtained by adding argon or oxygen gas to an etching gas consisting essentially of fluorine and carbon (e.g., gas containing at least one of CF₄and CHF₃gases). Then, the upper part of the resistpattern34 changes into a curedlayer34a, which is made of a polymer consisting essentially of fluorine and carbon and has a thickness of about 50 nm.
• Next, as shown in FIG. 4D, a resist[0081]film36 is deposited over the entire surface of the resistpattern34 so that theinterconnect grooves35 are filled with thefilm36.
• Thereafter, as shown in FIG. 4E, excessive part of the resist[0082]film36, existing over the second insulatingfilm33, and the entire resistpattern34 with the curedlayer34ain its upper part are ashed away with oxygen plasma. In this process step, the plasma etching process is performed using oxygen gas for a longer time than the second embodiment by a down flow technique in a vacuum of 13.3 Pa or less. As a result, the resistfilm36 and resistpattern34 are etched back. Also, after the resistpattern34 has been removed, the upper surface (i.e., the surface other than the bottom and side faces of the interconnect grooves35) of the second insulatingfilm33 of carbon-containing silicon dioxide is exposed to the oxygen plasma for just a short time. Accordingly, a thinsilicon dioxide layer37 is formed in the upper part of the second insulatingfilm33. On the other hand, no silicon dioxide layer is formed on the bottom and side faces of theinterconnect grooves35 because theinterconnect grooves35 are filled with the resistfilm36.
• Subsequently, as shown in FIG. 4F, the resist[0083]film36 in theinterconnect grooves35 is removed by a wet etching process using a chemical solution that can dissolve the resist, e.g., a chemical solution containing amine.
• Next, a tantalum nitride film is deposited over the second insulating[0084]film33 as well as inside theinterconnect grooves35 by a sputtering process. Then, a copper film is deposited on the tantalum nitride film by an electroplating process. Thereafter, excessive parts of the copper and tantalum nitride films, existing over the second insulatingfilm33, are removed by a CMP process, thereby formingmetal interconnects38 inside theinterconnect grooves35 as shown in FIG. 4G. The metal interconnects38 are made up of abarrier metal layer38aof tantalum nitride and amain interconnect layer38bof copper. In this process step, thesilicon dioxide layer37 formed in the upper part of the second insulatingfilm33 is also removed by increasing the thickness of the portions removed by the CMP process.
• According to the fourth embodiment, in the step of removing the resist[0085]pattern34 with the oxygen plasma, no silicon dioxide layer is formed on the bottom and side faces of theinterconnect grooves35 because theinterconnect grooves35 are filled with the resistfilm36. As a result, a parasitic capacitance, produced between the metal interconnects38, can be reduced.
• Modified Example of Embodiment 4[0086]
• Hereinafter, a method for fabricating a semiconductor device according to a modified example of the fourth embodiment will be described with reference to FIGS.[0087]5A through FIGS. 5D.
• After the same process steps have been carried out as in the fourth embodiment, an ashing process is performed using oxygen plasma to remove excessive part of the resist[0088]film36, existing over the second insulatingfilm33, and the entire resistpattern34 with the curedlayer34ain its upper part as shown in FIG. 5A. In this process step, the plasma etching process is performed using the oxygen gas for a longer time than the second embodiment by a down flow technique in a vacuum of 13.3 Pa or less. Then, a first thinsilicon dioxide layer37 is formed in the upper part of the second insulatingfilm33 with no silicon dioxide layer formed on the bottom and side faces of theinterconnect grooves35 as in the fourth embodiment.
• Next, as shown in FIG. 5B, the resist[0089]film36 existing in theinterconnect grooves35 is removed by a wet etching process using a chemical solution that can dissolve the resist, e.g., a chemical solution containing amine.
• Subsequently, as shown in FIG. 5C, an anisotropic RIE process, in which a bias voltage is applied to the[0090]silicon substrate31, is performed, thereby forming a secondsilicon dioxide layer39 with a high density between about 2.0 g/cm³and about 2.1 g/cm³and a thickness of about 20 nm or less on the bottom and side faces of theinterconnect grooves35. In this process step, if the anisotropic RIE process is performed in a vacuum of 13.3 Pa or less, it is possible to form a secondsilicon dioxide layer39 with a high density between about 2.0 g/cm³and about 2.1 g/cm³and a thickness between about 10 nm and about 15 nm. It should be noted that the firstsilicon dioxide layer37, existing in the upper part of the second insulatingfilm33, has its density and thickness both increased by this anisotropic RIE process. However, this will not cause a serious problem because the firstsilicon dioxide layer37 will be removed by the next CMP process.
• Thereafter, as shown in FIG. 5D, a tantalum nitride film is deposited by a sputtering process over the second insulating[0091]film33 as well as inside theinterconnect grooves35 having the secondsilicon dioxide layer39 formed thereon. Then, a copper film is deposited on the tantalum nitride film by an electroplating process. Thereafter, excessive parts of the copper and tantalum nitride films, existing over the second insulatingfilm33, are removed by a CMP process, thereby formingmetal interconnects38 inside theinterconnect grooves35, having the secondsilicon dioxide layer39 formed thereon, as shown in FIG. 5D. The metal interconnects38 are made up of abarrier metal layer38aof tantalum nitride and amain interconnect layer38bof copper. In this process step, the siliconfirst dioxide layer37, existing in the upper part of the second insulatingfilm33, is also removed by increasing the thickness of the portions removed by the CMP process.
• According to the modified example of the fourth embodiment, it is possible to form a second[0092]silicon dioxide layer39 with a high density between about 2.0 g/cm³and about 2.1 g/cm³and a thickness of about 20 nm or less on the bottom and side faces of theinterconnect grooves35. Therefore, even if oxygen plasma is supplied in a subsequent process step, oxygen ions cannot pass through the secondsilicon dioxide layer39. Accordingly, the thickness of the secondsilicon dioxide layer39 does not increase. As a result, a parasitic capacitance produced between the metal interconnects38 can be reduced just as intended.

Claims (10)

What is claimed is:

1. A semiconductor device comprising:

an insulating film formed of a carbon-containing silicon dioxide film on a substrate;

an interconnect groove formed in the insulating film;

a silicon dioxide layer, which is formed on the bottom and side faces of the interconnect groove and has a density high enough to allow almost no oxygen to pass therethrough; and

a metal interconnect formed on the silicon dioxide layer inside the interconnect groove.

2. The device of

claim 1

, wherein the silicon dioxide layer has a density of 2.0 g/cm³or more.

3. A semiconductor device comprising:

an insulating film formed of a carbon-containing silicon dioxide film on a substrate;

an interconnect groove formed in the insulating film;

a silicon dioxide layer, which is formed on the bottom and side faces of the interconnect groove and has a small and uniform thickness; and

a metal interconnect formed on the silicon dioxide layer inside the interconnect groove.

4. The device of

claim 1

, wherein the silicon dioxide layer has a thickness of 20 nm or less.

5. A method for fabricating a semiconductor device, comprising the steps of:

a) forming an insulating film of a carbon-containing silicon dioxide film on a substrate;

b) etching the insulating film using a resist pattern as a mask, thereby forming an interconnect groove in the insulating film;

c) performing a dry etching process using an etching gas containing oxygen, thereby removing a cured layer and forming a silicon dioxide layer on the bottom and side faces of the interconnect groove, the cured layer having been formed in an upper part of the resist pattern as a result of the step b);

d) removing the resist pattern by a wet etching process; and

e) filling the interconnect groove with a metal film to form a metal interconnect.

6. The method of

claim 5

, wherein the dry etching process is performed within a plasma ambient at a pressure of 13.3 Pa or less.

7. The method of

claim 6

, wherein the dry etching process is an anisotropic RIE process.

8. The method of

claim 5

, further comprising the step of removing the silicon dioxide layer, existing on the bottom and side faces of the interconnect groove, by a wet etching process.

9. A method for fabricating a semiconductor device, comprising the steps of:

a) forming an insulating film of a carbon-containing silicon dioxide film on a substrate;

b) etching the insulating film using a resist pattern as a mask, thereby forming an interconnect groove in the insulating film;

c) filling the interconnect groove with a resist film;

d) removing a part of the resist film, existing over the interconnect groove, and the resist pattern with a cured layer by a dry etching process using an etching gas containing oxygen, the cured layer having been formed in an upper part of the resist pattern as a result of the step b);

e) removing the other part of the resist film, still existing inside the interconnect groove, by a wet etching process; and

f) filling the interconnect groove with a metal film to form a metal interconnect.

10. The method of

claim 9

, further comprising the step of performing an anisotropic RIE process between the steps e) and f) within a plasma ambient containing oxygen at a pressure of 13.3 Pa or less to form a silicon dioxide layer on the bottom and side faces of the interconnect groove.

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