US20010014049A1 - Apparatus and method for thermal regulation in memory subsystems - Google Patents

Abstract

A memory system configured to provide thermal regulation of a plurality of memory devices is disclosed. The memory system comprises a memory module having a plurality of memory devices coupled to a bus. Additionally, the memory system also comprises a controller coupled to the bus. The controller determines an operating temperature (actual or estimated) of the memory device. Based on the determined operating temperature of the memory device, the controller is further operable to manipulate the operation of the memory system.

Description

CROSS REFERENCE TO RELATED APPLICATION(S)
• This application is a continuation-in-part of U.S. application Ser. No. 09/118,696 filed Jul. 16, 1998.[0001]
FIELD OF THE INVENTION
• The present invention relates to thermal regulation of memory devices in a memory system. More particularly, the present invention relates to an apparatus and method used to control operation of a memory system to regulate the operating temperature of memory devices in the memory system.[0002]
BACKGROUND OF THE INVENTION
• Improvements in microprocessor designs have led to microprocessors with a high operating frequency. Current microprocessor designs have operating frequencies of 400 megahertz (“MHz”) and higher. The increase in operating frequency, however, has not led to fully acceptable performance gains. One of the main factors adversely affecting performance gains is created when the microprocessor idles during delays in external memory access. The delays in external memory access are caused by the conventional design characteristics of static random access memory (“SRAM”) cells, read only memory (“ROM”) cells, and dynamic random access memory (“DRAM”) cells.[0003]
• To counteract the performance losses associated with external memory access, Rambus Inc., of Mountain View, Calif., developed a high speed memory system. FIG. 1 illustrates the Rambus high speed memory system. In particular,[0004]system100 shows a master device, memory controller (“MC”)10, coupled tomemory devices DRAM20,SRAM30, andROM40. Each device is coupled in parallel to signal lines DATA BUS, ADDR BUS, CLOCK, V_REF, GND, and VDD. DATA BUS and ADDR BUS show the data and address lines used by MC10 to access data from the memory devices. CLOCK, V_REF, GND, and VDD are the clock, voltage reference, ground, and power signals shared between the multiple devices. Data is transferred by memory device bus drivers (not shown) driving signals onto the bus. The signals are transmitted over the bus to a destination device, such asMC10 or a central processing unit (“CPU”) (not shown). Accordingly, MC10 coordinates the data transfer between the memory devices ofsystem100 and a destination device.
• To increase the memory access speed,[0005]system100 supports large data block transfers between the input/output (“I/O”) pins of the destination device and the memory devices ofsystem100.System100 may also include design requirements that constrain the length of the transmission bus, the pitch between the bus lines, and the capacitive loading on the bus lines. Using thesedesign requirements system100 operates at a higher frequency than conventional memory systems. Accordingly, by increasing operating frequency the performance ofsystem100 increases, thus reducing the idle time of the destination device coupled tosystem100.
• Although a high operating frequency increases data throughput,[0006]operating system100 at a high frequency typically results in higher power dissipation and correspondingly higher system temperatures. This result is not unexpected when the basic concept of thermal capacities is considered. The heat curve shown in FIG. 2 illustrates this concept.
• Beginning at some ambient temperature (T, ambient), the temperature of an electrical device will rise over time to a maximum, steady state temperature (T, steady state) as constant power is applied. The rate at which the temperature rises is determined by the thermal capacity of the device. The steady state temperature is defined by many factors including the geometry, size, composition, and surrounding environment (such as air flow) of the device.[0007]
• In the particular case of memory devices in a memory system, power is not constant. Rather, the memory device is switched ON and OFF with individual data requests. Thus, the heating curve for a memory device will fluctuate considerably depending on it use in addition to its thermal capacity.[0008]
• Excessive heating of a memory device may cause problems well below the steady state temperature. In fact, memory devices are designed to operate at temperatures below a given junction temperature (“Tj[0009]_,max”)
• Additionally, provided the memory device includes a dynamic cell design, its specification will also include a defined periodic refresh rate. The refresh rate ensures that the storage cells of the dynamic device are periodically recharged. Increasing the operating frequency of a memory system, however, results in the memory devices of the memory system generating high power levels. The high power levels translate into an increase in the operating temperature of the memory devices. If the operating temperature of a memory device surpasses Tj[0010]_,maxthe memory device may fail, thus resulting in the failure of the memory system.
• To ensure lower operating temperatures, prior art memory systems implement conventional thermal management techniques. In particular, to reduce the operating temperature of a memory device, prior art memory systems typically use specific packaging designs and specify the location of memory devices in memory systems. Conventional thermal management techniques, however, create numerous disadvantages.[0011]
• In fact, many of the conventional thermal management techniques are not readily applicable to evolving high frequency memory systems. Conventional thermal management using packaging designs for the memory devices is a good example. In particular, conventional packaging designs are not always effective for dissipating heat generated by memory devices operating at frequencies in excess of 100 Mhz. Accordingly, the application of traditional packaging designs to reduce thermal dissipation prove ineffective in the thermal regulation of[0012]system100.
• Conventional thermal management techniques based on the design layout of memory systems is another good example. In particular, such conventional thermal management techniques require large spacings between components to reduce heat transfer. In[0013]system100, however, the devices are located in relatively close proximity to one another in order to increase data throughput. Accordingly, the application of conventional placement techniques to reduce thermal dissipation prove ineffective in the thermal regulation ofsystem100.
SUMMARY OF THE INVENTION
• In view of the foregoing, a brief summary of some exemplary embodiments will now be presented. Some simplifications and omissions may be made in this summary, which is intended to highlight and introduce some aspects of the present invention, but not to limit its scope in any way. Detailed descriptions of the preferred embodiments adequate to allow those of ordinary skill in the art to make and use the inventive concepts are provided hereafter.[0014]
• The present invention provides a system and method for thermal regulation of a memory system. Memory systems operating at high frequencies are particularly well adapted to the present invention. That is, despite the fact that high frequency operation results in greater power dissipation and increased heat, the present invention yet allows the memory devices in the system to operate below a specified junction temperature, or in the alternative to reliably operate at temperatures above the specified junction temperature with appropriate modification of the system's performance parameters.[0015]
• In one embodiment of the present invention, the operating temperature of the memory device(s) is estimated. In another embodiment, the actual operating temperature of the memory devices(s) is measured. In either embodiment, operating temperature may be derived on a memory device by memory device basis, or on a memory module basis.[0016]
• For example, one aspect the present invention provides a memory system comprising a memory controller coupled to a bus, and at least one memory device coupled to the bus. Typically there are a plurality N of memory devices coupled to the bus. The memory controller comprises a tracking circuit operable to track a number of memory device operations involving M of the N memory devices during a period of time, where M is less than or equal to N. The memory controller also comprises a control circuit operable to manipulate operation of the memory system in response to a comparison of the number of memory operations and a reference.[0017]
• The tracking circuit preferably comprises at least one counter, and more preferably a first counter incremented by each read operation during the period of time, and a second counter incremented by each write operation during the period of time. The at least one counter may comprise a First-In-First-Out (FIFO) buffer.[0018]
• The comparison reference comprises power value data relating a number of memory device operations with an estimated operating temperature for the at least one memory device. Power value data may be stored in the memory controller, in one or more register associated with the at least one memory device, or in a data storage element associated with a memory module. The comparison might, however, be made directly to a counter value in the tracking circuit which maps to a true, known power value.[0019]
• In another aspect, the present invention provides a memory system comprising a memory controller coupled to a bus, a memory device coupled to the bus and having a maximum operating temperature, a temperature sensor measuring an operating temperature associated with the memory device(s). The temperature sensor may be associated with the memory device(s) proper, a thermocouple attached to the memory device(s), or the heat spreader itself.[0020]
• However the operating temperature of the memory device is derived, actually measured or estimated, it is used as a reference in relation to one or more threshold values (for example, the junction temperature noted above) to regulate operation of the memory system in order to regulate the temperature of the memory devices. Thermal regulation may be accomplished in a number of ways.[0021]
• In one aspect, the memory controller further comprises a delay circuit operable to select delays between successive operations, for example a first delay between successive read operations and a second delay between successive write operations on the basis of a control circuit comparison indicating that the number of memory operations exceeds the reference.[0022]
• In another aspect, the memory device(s) in the memory system are operable in first and second modes of operation, wherein the memory device consumes less power in the second mode of operation as compared with the first mode of operation, and the memory controller is operable to select between the first and second modes of operation for the memory device on the basis of the control circuit comparison.[0023]
• In yet another aspect, a method of regulating the operating temperature of a memory device in a memory system is used in which a number of operations involving the memory device during a time period are determined, the number of operations is compared to reference data corresponding to an estimated operating temperature for the memory device, and the operation of the memory system is potentially manipulated on the basis of the comparison between the number of operations and the reference data.[0024]
• For another embodiment, the memory system includes multiple memory devices functionally grouped on a memory module. Thermal loading is often a system characteristic more aptly attributable to a memory module, rather than individual memory devices since the memory module can contain a heat spreader across the span of grouped memory devices. Where the operating temperature is estimated, the estimation may be made in relation to memory system operations occurring in one or more memory devices on the memory module. Where the actual operating temperature is measured, measurement may take place in the memory devices proper, or at one or more thermocouples associated with the memory devices and/or the memory module heat spreader.[0025]
BRIEF DESCRIPTION OF THE DRAWINGS
• The features and advantages of the present invention are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate like elements, and in which:[0026]
• FIG. 1 illustrates a prior art memory system;[0027]
• FIG. 2 is a graph illustrating the concept of thermal capacity;[0028]
• FIG. 3 is a high level flowchart illustrating a method of thermal regulation in a memory subsystem according to one embodiment of the present invention;[0029]
• FIG. 4 shows one embodiment of the present invention in which a memory device is coupled to a memory controller having a thermal regulation circuit;[0030]
• FIG. 5 illustrates a FIFO buffer having application within the embodiment shown in FIG. 4;[0031]
• FIG. 6 shows an exemplary circuit used by a memory controller of present invention to reduce the timing parameters of a memory device;[0032]
• FIG. 7 shows another embodiment of the present invention in which a memory device with a temperature sensing circuit is coupled to a memory controller;[0033]
• FIG. 8 shows an exemplary thermal regulation circuit consistent with one aspect of the present invention;[0034]
• FIG. 9 is a high level flowchart illustrating a method of thermal regulation in a memory subsystem according to another embodiment of the present invention;[0035]
• FIG. 10 shows yet another embodiment of the present invention in which a memory system incorporates thermal regulation circuitry; and, FIG. 11 shows a memory module adapted to the present invention.[0036]
DETAILED DESCRIPTION
• A system and method for thermal regulation of a memory system is disclosed. Nominally, the memory system includes a memory controller and at least one memory device. The present invention is particularly well adapted for use in a memory system operating at relatively high frequencies. Despite the fact that high frequency operation results in greater power dissipation and increased heat, the present invention allows the memory device(s) in the system to operate below a specific junction temperature (“Tj[0037]_,max”). For example, a conventional memory device, such as a dynamic random access memory (“DRAM”), might have a Tj_,maxof one hundred degrees Celsius (100° C.).
• In one embodiment of the present invention, the operating temperature of the memory device(s) is estimated. In another embodiment, the actual operating temperature of the memory devices(s) is measured. In either embodiment, operating temperature may be derived on a memory device by memory device basis, on a memory module basis, or on the entire memory system. However derived, the operating temperature (actual or estimated) of the memory device(s) is used as a reference in relation to a threshold value to regulate operation of the memory system in order to regulate the temperature of the memory device(s).[0038]
• Thermal regulation may be accomplished in a number of ways. For example, the present invention may ensure that the operating temperature of the memory device(s) remains below this Tj[0039]_{,max using one or more of a number of}techniques. Alternatively, the present invention may allow the memory device to operate at a temperature greater than Tj_,max,but increases the refresh rate of dynamic memory device(s) in the system to ensure reliable operation at these higher temperatures.
• In one embodiment, the present invention includes a circuit, preferably incorporated within the memory controller, that estimates the operating temperature of the memory device(s). To estimate the operating temperature of one or more memory devices, the circuit tracks the data transfer operations within the memory system. In particular, the circuit counts and stores the number of read/write operations, as well as the number of other relevant DRAM operations (like refresh operations), involving the memory device(s). Based on the number and types of operations in a given time period, the circuit estimates the operating temperature of the memory device(s). If the operating temperature of the memory device(s) exceeds a threshold value, the circuit regulates operation of the memory system.[0040]
• In another embodiment, the memory device(s) include a temperature sensor coupled to the control circuit in the memory controller. The temperature sensor measures an operating temperature associated with the memory device(s). If the temperature sensor indicates that the memory device is operating above a given threshold temperature, the apparatus regulates the operation of the memory system.[0041]
• The memory system may include multiple memory devices functionally grouped on a module. Thermal loading is often a memory system characteristic more aptly attributable to a memory module, rather than individual memory devices since the memory module may contain a heat spreader across the span of grouped memory devices. Where the operating temperature is estimated, the estimation may be made in relation to memory system operations occurring in one or more memory devices on the memory module. Where the actual operating temperature is measured, measurement may be taken by a special circuit within the memory devices proper, or by one or more thermocouples attached to the memory devices or the memory module heat spreader.[0042]
• Regulating the operation of the memory system results in regulation of the operating temperature of the memory devices in the memory system. A number of regulation schemes are possible. For example, the regulation scheme may consist of increasing the refresh rate of the memory system, dynamically changing the timing parameters of the memory system, dynamically placing components of the memory system in a low power mode, and/or dynamically enabling a cooling system.[0043]
• Effective thermal regulation allows enhanced operating performance in memory systems operating at high frequencies.[0044]
• Turning now to the drawings, FIG. 3 is a high level flowchart illustrating one embodiment of the present invention for implementing thermal regulation in a memory system. In particular,[0045]flowchart240 illustrates a method used to turn off or turn on an exemplary thermal regulation scheme. Instep245, a memory system determines the operating temperature of a memory device. Examples of actual methods and circuitry adapted to determine the temperature of the memory device are described below.
• [0046]Step246 follows the completion ofstep245. Instep246, the operating temperature of the memory device is compared against a predetermined threshold value. If the operational temperature exceeds the threshold value, then step247 is begun. Instep247, the memory system initiates a thermal regulation scheme. Afterstep247 is completed, the memory system returns to step245. If the comparison done instep246 finds that the operational temperature does not exceed the threshold value, however, then step248 is begun.
• In[0047]step248, the memory system determines whether a thermal regulation scheme is active. If a thermal regulation scheme is not active, then the next step isstep245. If duringstep248 the system determines that a thermal regulation scheme is active, then the memory system moves to step249 in which the memory system turns off the regulation scheme because the memory device is operating below the threshold value. Afterstep249, the system returns to step245. For one embodiment, a memory system including thermal regulation circuitry and one or more memory devices follow the steps inflowchart240 to regulate the operating temperature of the memory devices.
• FIG. 4 shows one embodiment of a memory device coupled to a memory controller with thermal regulation circuitry. In particular,[0048]system200 includescontroller210 coupled to bus230 alongline235. Bus230, in turn, is coupled tomemory device220 vialine225. For one embodiment, bus230 transmits address and data betweencontroller210 andmemory device220. Accordingly, using bus230,controller210 reads/writes data directly frommemory device220. Using bus230,controller210 also transfers data frommemory device220 to a second device (not shown) coupled to bus230.
• As illustrated in FIG. 4,[0049]controller210 also includes circuit215 and circuit216. Circuit215 is used to ensure thatmemory device220 does not operate at a temperature exceeding Tj_,max. For one embodiment, circuit216 is used to track the operations ofmemory device220 over a given time period. Data relating the amount of energy/heat expended by atypical memory device220 during various memory system operations is developed empirically. This “power value data” is stored within the memory system, and later used as a reference to estimate the operating temperature of the memory device in relation to a number of memory system operations involving the memory device.
• For example, circuit[0050]215 may use the counted operations data stored in circuit216 in conjunction with the empirically derived power value data to estimate the operational temperature ofmemory device220 during the given time period. If the estimated temperature exceeds the threshold value Tj_,max, a regulation scheme is used to throttle the operation ofsystem200, thus reducing the temperature ofmemory device220.
• For one embodiment, circuit[0051]216 is a memory block used to store the number and types of operations performed bymemory device220. For an alternative embodiment, circuit216 is a first-in first-out (“FIFO”) buffer with each stage of the FIFO buffer including multiple counters.
• FIG. 5 illustrates one embodiment of the FIFO buffer. In particular,[0052]FIFO buffer260 includes three stages (275,285, and295) with each stage including a set of counters.Stage275 includes counters270-272.Stage285 includes counters280-282 andstage295 includes counters290-292. Each set of counters tracks the number of times specific operations are performed bymemory device220 in a given time period “t1.” Thus, each stage inFIFO buffer260 denotes the number of times three specific operations are performed bymemory device220 during a “t1” time period. For example, instage275, counter270 might record the number of precharge operations, counter271 might record the number of read operations, and counter272 might record the number of write operations occurring during period t1. The number of stages of the FIFO buffer determines the extent of time during which the operations ofmemory device220 are tracked.
• For example, for one embodiment, the FIFO has five stages and t1 equals 1 second. Depending on the environment, first order calculations indicate that several million operations occurring in a few seconds can equate to[0053]memory device220 having a temperature of 95 degrees. Circuit215 uses the five entries to calculate the activity ofmemory device220 over this time period. In particular, based on the counter values of the FIFO buffer and empirically determined power value data for each type of operation, circuit216 calculates the total power dissipated bymemory device220. The empirical power value data is used to correlate the total power to the temperature ofmemory device220.
• The empirically determined power value data may be stored in the memory controller, for example, as part of circuit[0054]215. While storing the power value data in the memory controller allows ready access, such data is memory device specific. Since the memory controller manufacturer is often different from the various memory device manufacturers, obtaining and incorporating the power value data into the memory controller can prove difficult.
• Alternatively, the power value data may be stored in one or more registers located directly on each memory device. This embodiment allows each memory device, class of memory devices, or batch of memory devices to accurately indicate its own specific power value data. The memory controller may read the one or more memory registers upon memory system initialization.[0055]
• The power value data may be stored in registers associated with a memory module in the memory system. Those of ordinary skill in the art will recognize that a plurality of memory devices are often grouped and packaged together in module form. Many conventional memory modules include a data storage element sometimes referred to as a “Serial Presence Detect,” device or SPD device. This memory element contains reference data (i.e., number, type, etc.) for the memory devices on the memory module. In one embodiment of the present invention, the SPD device or similar data storage element is used to store the power value data along with the conventional reference data.[0056]
• Returning to the example illustrated in FIGS. 3, 4 and[0057]5, if the circuit216 calculation is below a predeterminedthreshold value system200 operates normally. If the circuit216 calculation is above a predetermined threshold value, thencontroller210 selects a regulation scheme to throttle the operation ofsystem200, thus controlling the operational temperature ofmemory device220.
• In one possible alternative embodiment,[0058]memory system200 includes multiple memory devices, and multiple circuits215, each one governing an individual memory device, are included incontroller210. Multiple circuits215 allowcontroller210 to determine the operating temperature of each memory device and subsequently regulate the operation ofmemory system200. Within this embodiment, different predetermined values may exist for different memory devices, or groups of devices. In effect, the provision of multiple different predetermined reference values establishes multiple trip points which allowsystem200 to initiate one or more different regulation schemes for various trip points. Accordingly,system200 may implement varied or graduated mechanisms to reduce the operating temperature of one or more memory devices. The graduated control approach allowssystem200 to balance memory device temperature control with overall system performance.
• [0059]System200 may incorporate a variety of regulation schemes to ensure thatmemory device220 operates below Tj_,max. In one embodiment, to ensure thatmemory device220 operates below Tj_,max,system200 can increase the timing parameters ofmemory device220—i.e., change the time required formemory device220 to perform specific operations. In an alternative embodiment, to ensure thatmemory device220 operates below Tj_,max,controller210 introduces delays into the instruction sequence ofmemory device220. In particular, if circuit216 indicates a count value above a given threshold,controller210 delays the execution of instructions directed tomemory device220. In yet another embodiment, to ensure thatmemory device220 operates below Tj_,max,controller210 can change the operation mode ofmemory device220 or activate a cooling system.
• FIG. 6 shows one embodiment of a circuit used by[0060]controller210 to reduce the timing parameters ofmemory device220. In particular,circuit300 is coupled to circuit215 and includes four registers (340-355), two select circuits (360 and370), input select330, output read310, and output write320. As illustrated in FIG. 6, registers340 and350 are coupled to selectcircuit360. The output ofselect circuit360 is coupled to read310. Similarly, registers345 and355 are coupled to selectcircuit370. The output ofselect circuit370 is coupled to write320. Bothselect circuits360 and370 are coupled to selectsignal330.
• For one embodiment, read[0061]310 is used to determine the delays ofcontroller210 between successive reads frommemory device210. Similarly, write320 is used to determine the delays ofcontroller210 between successive writes tomemory device210. In the present embodiment, during initialization ofsystem200,memory device220 loads normal operation read/write delays intoregisters340 and345, respectively. Subsequently, to varysystem200timing parameters controller210 uses delays stored inregisters350 and355. In particular, duringnormal operation controller210 movesselect signal330 to a first position. If select330 is in a first position, register340 is coupled to read310 and register345 is coupled to write320. As previously described,registers340 and345 increase delays used during normal operation. Accordingly, during normal operation outputs read310 and write310 generate the data stored inregister340 and345. For example, from the initialization process register340 holds the value four and register345 holds the value six. Thus, duringnormal operation controller210 waits four cycles between successive reads ofmemory device220. Additionally, duringnormal operation controller210 waits six cycles between successive writes tomemory device220.
• If circuit[0062]216 exceeds a threshold value, however,controller210 moves select330 to a second position. When select330 is in a second position, register350 is coupled to read310 and register355 is coupled to write320.Registers340 and345 include delays used during thermal regulation. In contrast to the values stored inregisters340 and345,registers350 and355 hold higher values. For one embodiment, the values stored inregisters350 and355 are derived from empirical data. For example, based on empirical data register340 stores the value twelve and register345 stores the value eighteen. Accordingly, duringthermal regulation controller210 waits twelve cycles between successive reads ofmemory device220. Additionally, duringthermal regulation controller210 waits eighteen cycles between successive writes tomemory device220. Regulating the timing parameter ofsystem200 allowscontroller210 to control the operational temperature ofmemory device210, thus ensuring thatmemory device210 does not exceed Tj_,max.
• To ensure that[0063]memory device220 operates below Tj_,maxsystem200 can also change the operation mode ofmemory device220. For example, for one embodiment,memory device220 has two operational modes. The operational modes include normal operation and low power modes. One low power mode, called a drowsy mode, reduces power dissipation by reducing performance, while another low power mode, called nap, reduces power dissipation by preventing memory access. During low power mode,system200 consumes less power. In particular, during low powermode memory device220 turns off non-essential circuitry. The reduction in the power consumption ofmemory device220 translates to a reduction in the operating temperature ofmemory device220. For one embodiment, if circuit216 indicates a value above a given threshold, thencontroller210places memory device220 in a low power mode.
• As previously described, placing[0064]memory device220 in a low power mode reduces the thermal dissipation of memory device. The low power modes, however, reduce the performance ofsystem200. In particular, during the low powermodes memory device220 disables unnecessary circuitry. For one embodiment,controller210places memory device220 in a low power mode for a predetermined time.
• The aforementioned regulation schemes helps to ensure that the temperature of[0065]memory device220 does not exceed Tj_,max. For one embodiment,memory device210 comprises a dynamic memory device. A regulation scheme that allowsmemory device220 to operate above Tj_,maxis possible. In particular, if circuit216 indicates a count value above a given threshold, then the regulation scheme requires thatcontroller210 increases the refresh rate ofmemory device220. The increased refresh rate allowsmemory device220 to store information that would typically be lost at temperatures above Tj_,max, thereby effectively increasing Tj_,max.The increased refresh rate can also reduce temperature by decreasing the time a device is available to perform new operations.
• FIG. 7 shows one embodiment of a memory device with a temperature sensing circuit coupled to a memory controller. In particular,[0066]system400 includescontroller410 coupled to bus440 alongline435. Bus440, in turn, is coupled tomemory device420 vialine425. For one embodiment, bus440 transmits address and data betweencontroller410 andmemory device420. Accordingly, using bus440,controller410 reads/writes data directly frommemory device420.
• As illustrated in FIG. 7,[0067]controller410 includesregister415 andmemory device420 includescircuit430.Circuit430 is a temperature sensing circuit that is coupled to register415 vialine450.Controller410 usescircuit430 to determine the operating temperature ofmemory device420. In particular, ifmemory device420 is operating above a threshold temperature, thencircuit430 generates a digital signal alongline450. For one embodiment,circuit430 generates a logic “1” to indicate thatmemory device420 is operating above a threshold temperature. The logic “1” signal sets a temperature flag inregister415. Based on the set temperature flag,controller410 initiates a regulation scheme to throttle the operation ofsystem400, thus reducing the temperature ofmemory device420.
• [0068]Controller410 periodically samples register415 to determine whether the temperature flag is set. For one embodiment, the sampling period is derived from empirical data. In particular, the time period betweenmemory device420 reaching a threshold temperature andmemory device420 reaching Tj_,maxis empirically ascertained. The sampling period is set to a value that is less than the sum of the empirically derived time and the time required to initiate regulation. Setting the sampling period to such a value ensures thatcontroller410 initiates a regulation scheme prior tomemory device420 surpassing Tj_,max. For another embodiment,memory device420 loads the sampling period of the memory device intocontroller410 during the initialization ofsystem400.
• For illustrative purposes, the previous description describes a digital signal generated by[0069]circuit430 alongline450. For one embodiment, however,circuit430 is a temperature sensitive diode that generates an analog signal. For an alternative embodiment, the output ofcircuit430 is transmitted along bus440.
• FIG. 8 shows one embodiment of a thermal regulation circuit included in circuit[0070]215. In particular,circuit590 includesinput511,output512, register set541, and sequencer581.Circuit590 also includes,FIFO531 register set521,comparator551, and arithmetic logic unit (“ALU”)561. As illustrated in FIG. 8, sequencer581 is coupled to input511 andoutput512. For one embodiment, during normal operation, instructions fromcontroller210 tomemory device220 are transmitted alonginput511 through sequencer581 and ontooutput512. During thermal regulation, however, sequencer581 modifies the instruction sequence transmitted tomemory device220. For example, for one embodiment, sequencer581 can introduce delay during thermal regulation.
• As further illustrated in FIG. 8, register set[0071]521 andFIFO531 are coupled to the inputs of ALU561. The output of ALU561 is coupled to the first input ofcomparator551. The second input ofcomparator551 is coupled to register set541. The output ofcomparator551 is coupled to sequencer581.
• For one embodiment,[0072]circuit590 usesFIFO531, register set521, register set541,comparator551, and ALU561 to determine whether the thermal regulation ofmemory device220 is necessary. In particular, register set521 includes power value data formemory device220. As previously described,FIFO531 includes counter information for the operations performed bymemory device220. Using the counter information ofFIFO531 and the power value data of register set521, ALU561 performs arithmetic calculations to estimate the operating temperature ofmemory device220. After ALU561 performs the temperature estimation,comparator551 compares the estimated temperature versus the contents of register set541. For one embodiment, register set541 includes empirically derived threshold temperatures.
• As explained above, the power value data stored in register set[0073]521 may initially be stored in the memory controller, in one or more registers associated with the memory device(s), or in a memory module element, such as an SPD device.
• If the comparison between the estimated temperature and the threshold temperatures shows that thermal regulation is necessary, sequencer[0074]581 initiates a regulation scheme. For example, in one embodiment, the regulation scheme consists of increasing the refresh rate ofmemory device220. In an alternative embodiment, regulating the operation of the memory system consists of dynamically changing the timing parameters ofmemory system200. For another embodiment, regulating the operation of the memory system consists of dynamically placingmemory device220 in a low power mode. For yet another embodiment, regulating the operation of the memory system consists of dynamically enabling a cooling system. For another embodiment, regulating the operation of the memory system consist of introducing delays between operations.
• FIG. 9 shows one embodiment of a flowchart used by a thermal regulation circuit to implement a thermal regulation scheme. In particular,[0075]flowchart500 shows the steps followed bycircuit590 during the thermal regulation ofmemory device220. Using steps510 through580,circuit590 ensures thatmemory device220 does not exceed Tj_,max. Step510 is the initial step inflowchart500.
• For one embodiment, step[0076]510 occurs after the power up ofsystem200. In step510,circuit590 initializes the thermal regulation scheme. In particular, in step510,circuit590 resets the counters ofFIFO531. Further, in step510,circuit590 reads the timing parameters and threshold values ofmemory device220 into register set521 and register set521. After the initialization of the regulation scheme, step520 is begun.
• In step[0077]520,circuit590 waits a “t2” time period to read the counter values inFIFO531. For one embodiment, “t2” equals the predetermined time period necessary to acquire data for one stage ofFIFO buffer260 included in circuit216. For an alternative embodiment, “t2” is read by memory controller510 during the initialization stage described in step510. Aftercircuit590 waits “t2” seconds step530 is begun.
• In step[0078]530,circuit590 reads the counter information inFIFO531. Subsequently, instep540, the operating temperature ofmemory device220 is calculated via ALU561. As previously described, for one embodiment, the FIFO counter information is used to compute an estimate of the operating temperature ofmemory device220. For an alternative embodiment, a memory device with a temperature sensing circuit is used insystem200 for example,memory device420 andcircuit430 ofsystem400. In particular, ifmemory device420 is operating above a threshold temperature, then the output ofcircuit430 activates a temperature flag in sequencer581. Instep540, the temperature flag is evaluated to determine the operating temperature of thememory device220. After calculating/evaluating the operating temperature of thememory device220,step550 is begun.
• In[0079]step550, the ALU561 estimated temperature ofmemory device220 is compared against a threshold value. For one embodiment, provided the calculated temperature ofmemory device220 exceeds the threshold value,flowchart500 transitions to step580. Instep580, a thermal regulation scheme is initiated. As previously described, the thermal regulation scheme reduces the operating temperature ofmemory device220, or increases the refresh rate so that the memory device can operate at a temperature above Tj max. For an alternative embodiment, the calculated temperature ofmemory device220 is compared against multiple thresholds. The multiple thresholds allowsystem200 to initiate a different regulation scheme for each threshold. In particular, provided a first threshold is exceed,flowchart500 transitions to step580 to initiate a regulation scheme corresponding to the first threshold. If a second threshold is exceed, then flowchart500 transitions to step580 to initiate a second regulation scheme corresponding to the second threshold. Accordingly, the use of different regulation schemes allowsystem200 to perform graduated steps to reduce the operating temperature ofmemory device220. The graduated steps allowsystem200 to balance temperature control versus system performance. After starting a thermal regulation scheme,flowchart500 returns to step520.
• If the calculated temperature of[0080]memory device220 does not exceed a threshold value,step560 is begun. Instep560,circuit590 determines whether a thermal regulation scheme is active. If all thermal regulation schemes are inactive,flowchart500 transitions to step520. If a thermal regulation scheme is active, then flowchart500 transitions to step570.
• In[0081]step570, for one embodiment,circuit590 stops an active thermal regulation scheme.Circuit590 stops the active thermal regulation scheme because the calculated temperature ofmemory device220 does not exceed a threshold value. Accordingly, the operating temperature ofmemory device220 is not approaching Tj_,maxand the active regulation scheme is unnecessary. For an alternative embodiment, instep570, if the regulation scheme involves multiple threshold values, one or more regulation mechanisms is deactivated depending on which threshold values are exceeded. Afterstep570,flowchart500 returns to step520.
• FIG. 10 shows one embodiment of a memory system. In particular,[0082]system600 includescontroller640 coupled tomemory devices610,620, and630 via bus650. For one embodiment, bus650 transmits address and data betweencontroller640 andmemory device610,620, and630. Accordingly, using bus650controller640 reads/writes data directly from the memory devices.
• [0083]Memory devices610,620, and630 andcontroller640 are also coupled to each other via signal lines655-657. The signal lines form a chain betweencontroller640 and the memory devices. In particular,memory device630 is coupled tomemory device620 viasignal line657. Similarly,memory device620 is coupled tomemory device610 viasignal line656. Finally,memory device610 is coupled tocontroller640 viasignal line655. For one embodiment, during the initialization ofsystem600 signal lines655-657 transfer the timing parameters and refresh rates of the memory devices tocontroller640.
• For one embodiment,[0084]controller640 estimates the memory device operating temperature. As previously described, based on the estimatedoperating temperature controller640 initiates a regulation scheme. The regulation scheme reduces the operating temperature of the memory device(s) operating above a threshold temperature. For an alternative embodiment,memory devices610,620, and630 include temperature sensing circuits. Thus,controller640 determines the actual operating temperature of each memory device. In particular, each temperature sensing circuit outputs a digital signal indicating whether the memory device corresponding to the sensing circuit is operating above a threshold temperature. For one embodiment, signal lines655-657 transfer the digital signals tocontroller640. Based on the digital signals,controller640 initiates a regulation scheme to reduce the temperature of those memory devices operating above a threshold temperature. For an alternative embodiment, the digital signals are transferred tocontroller640 via bus650.
• [0085]Controller640 is also coupled to a cooling system (660 and670) via line680. For one embodiment, a regulation scheme implemented bycontroller640 includes initiating a cooling system. Accordingly,controller640 activatesfan660 andfan670 when the controller determines that one of thememory devices610,620, or630 is approaching Tj_,max.
• As described above, the present invention contemplates thermal management on a memory module basis as well as memory device basis. To further illustrate this point, reference is made to FIG. 11 which illustrates a memory module and its relation to the present invention.[0086]
• In general block diagram form, FIG. 11 illustrates a[0087]memory module700 in card form having a series of plug-inconnectors707, a plurality of memory devices701-704, and a serial presence detect (SPD device)705. The plurality of memory devices are commonly connected to the bus, butSPD device705 generally communicates with memory controller via a separate signal line. While the illustrated example contains an SPD device connected via a dedicated signal line, one of ordinary skill will appreciate that any type of data storage element associated with the memory module and communicating with the memory controller via any reasonable means may be used to store power value data associated with the memory devices. The SPD device is presently preferred because it is already routinely incorporated in memory modules, and interrogated by the memory controller during memory system initialization. Thus, the present invention make efficient use of existing memory system resources to effect novel features and derive their additional benefit.
• In the foregoing specification, the invention has been described with reference to specific exemplary embodiments. It will, however, be evident that various modifications and changes may be made thereof without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.[0088]

Claims (27)

What is claimed is:

1. A memory system comprising:

a memory controller coupled to a bus;

a memory module comprising N memory devices coupled to the bus, each one of the N memory devices operable to receive data from the bus during a write operation and to transmit data onto the bus during a read operation;

wherein the memory controller comprises:

a tracking circuit operable to track a number of memory device operations in M of the N memory devices during a period of time, where M is less than or equal to N; and

a control circuit operable to manipulate operation of the memory system in response to a comparison of the number of memory operations and a reference.

2. The memory system of

claim 1

, wherein the tracking circuit comprises at least one counter.

3. The memory system of

claim 2

, wherein the at least one counter comprises:

a first counter incremented by each read operation during the period of time; and

a second counter incremented by each write operation during the period of time.

4. The memory system of

claim 3

, wherein the at least one counter comprises a First-In-First-Out (FIFO) buffer.

5. The memory system of

claim 1

, wherein the reference comprises power value data relating a number of memory device operations with an estimated operating temperature for the M memory devices.

6. The memory system of

claim 5

, wherein the power value data is stored in the memory controller.

7. The memory system of

claim 5

, wherein the power value data is stored in one or more register on the N memory devices.

8. The memory system of

claim 5

, wherein the memory module further comprises a data storage element storing the power value data for the M memory devices.

9. The memory system of

claim 5

, wherein the memory controller further comprises:

a delay circuit operable to select a first delay between successive read operations to the M memory devices and to select a second delay between successive write operations to the M memory devices on the basis of a control circuit comparison indicating that the number of memory operations exceeds the reference.

10. The memory system of

claim 5

, wherein each of the N memory devices is operable in first and second modes of operation, wherein each of the N memory devices consumes less power in the second mode of operation as compared with the first mode of operation; and

wherein the memory controller is operable to select between the first and second modes of operation for each one of the M memory devices on the basis of the control circuit comparison.

11. A method of regulating the operating temperature of memory devices in a memory system comprising; a memory controller and a memory module comprising a plurality of memory devices, the method comprising:

determining a number of operations involving one or more memory devices on the memory module during a time period;

comparing the number of operations to reference data corresponding to an estimated operating temperature the one or more memory devices;

determining whether to manipulate the operation of the memory system on the basis of the comparison between the number of operations and the reference data.

12. The method of

claim 11

, wherein the number of operations comprises at least one of a number of read operations involving the one or more memory devices, a number of write operations involving the one or more memory devices, and a number of refresh operations involving the one or more memory device.

13. The method of

claim 11

, further comprising:

upon determining to manipulate the operation of the memory system, introducing delays between successive read operations and successive write operations to the one or memory devices.

14. The method of

claim 11

, further comprising:

upon determining to manipulate the operation of the memory system, placing the one or more memory devices in a mode of operation requiring less power.

15. The method of

claim 11

, further comprising:

upon determining to manipulate the operation of the memory system, increasing the refresh rate for the one or more memory device.

16. A memory system comprising:

a memory controller coupled to a bus;

a memory module comprising N memory devices coupled to the bus, each one of the N memory devices having a maximum operating temperature;

at least one temperature sensor measuring an actual operating temperature for M of the N memory devices, where M is less than or equal to N; and

a circuit periodically refreshing data in the M memory devices at a first rate when the actual operating temperature is below the maximum operating temperature, and at a second rate, higher than the first rate, when the actual operating temperature is above the maximum operating temperature.

17. The memory system of

claim 16

, wherein the at least one temperature sensor generates temperature data communicated to the memory controller via the bus.

18. The memory system of

claim 16

, wherein the at least one temperature sensor generates temperature data, and wherein the memory system further comprises a signal line outside the bus connecting the at least one temperature sensor and the memory controller, such that the temperature data is communicated to the memory controller via the signal line.

19. The memory system of

claim 18

, wherein the temperature data comprises a digital flag and wherein the memory controller further comprises a data register connected to the signal line and storing a value associated with the digital flag.

20. The memory system of

claim 16

wherein the memory module further comprises a heat spreader, and wherein at least one temperature sensor is associated with either each one of the M memory devices, or a thermocouple between each one of the M memory devices and the heat spreader.

21. A memory system comprising:

a memory module comprising N memory devices coupled to a bus, each one of the N memory devices being operable in at least a first power mode and a second power mode, and having a maximum threshold temperature;

at least one temperature sensors measuring actual operating temperature for a group M of the N memory devices, where M is less than or equal to N;

a memory controller coupled to the bus, the memory controller selecting the first power mode for each memory device in the group M having an actual operating temperature below the maximum threshold temperature, and selecting the second power mode for each memory device in the group M having an actual operating temperature above the maximum threshold temperature;

wherein each one of the N memory device consumes less power in the second power mode than in the first power mode.

22. The memory system of

claim 21

, wherein the at least one temperature sensor generates temperature data communicated to the memory controller via the bus.

23. The memory system of

claim 21

, wherein the at least one temperature sensor generates temperature data, and wherein the memory system further comprises a signal line outside the bus connecting the at least one temperature sensor and the memory controller, such that the temperature data is communicated to the memory controller via the signal line.

24. The memory system of

claim 23

, wherein the temperature data comprises a digital flag and wherein the memory controller further comprises a data register connected to the signal line and storing a value associated with the digital flag.

25. A method of regulating the operating temperature of memory devices in a memory system comprising a memory controller and a memory module comprising N memory devices, the method comprising:

storing power value data indicative of a maximum threshold temperature for at least one of the N memory devices in a data storage element associated with the memory module;

tracking a number of memory system operations involving M of the N memory devices during a time period, where M is less than or equal to N and where the number of operations is indicative of an estimated operating temperature for the M memory devices;

comparing the number of memory system operations to the power value data; and

upon determining based on the comparison of the number of memory system operations to the power value data that the estimated operating temperature for the M memory devices is greater than the maximum threshold temperature, manipulating the operation of the memory system to reduce the operating temperature of the M memory devices.

26. The method of

claim 25

, further comprising:

reading the power value data from the data storage element during memory system initialization.

27. The method of

claim 25

, wherein the data storage element is a serial presence detect device.

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