US20010011318A1 - Status indicators for flash memory - Google Patents

Abstract

A status register for a memory device. The status register provides a programming suspend status signal and a protection status signal. The programming suspend status signal indicates whether a programming operation is suspended. If the processor knows that a programming operation to a specific memory location is suspended, then the processor may request that a data modification operation to another memory location be performed while the programming operation is suspended. The protection status signal indicates whether an attempted data modification operation failed due to a protected memory block versus another type of device failure. Protecting or locking a memory block prevents the modification of data stored in a particular memory block.

Description

FIELD OF THE INVENTION
• The present invention relates to the field of semiconductor memories. More particularly, the present invention relates to providing a programming suspend status signal and a protection status signal for a nonvolatile memory.[0001]
BACKGROUND OF THE INVENTION
• Status registers are often used to store status information relating to the internal operations of a semiconductor integrated circuit (“IC”). Memory ICs or devices, such as flash electrically erasable programmable read only memory (“EEPROM”) devices, may store information in a status register to indicate whether an operation (e.g., an erase operation, a programming operation, a read operation, etc.) is in progress or is completed. The status register may also indicate whether a specific operation has been completed successfully or unsuccessfully. Such information often provides necessary or desirable information to other components in a system.[0002]
• For example, the processor or CPU in a system may need to know when an erase operation performed on a memory device (such as a flash memory device) is completed before requesting the memory device to perform a programming operation. Additionally, the processor in a system may want to know whether an erase operation to a specific memory location has been suspended. Typically, an erase operation takes a much longer time to complete as compared to a programming or read operation. For example, an erase operation may take a few milliseconds (“ms”), whereas a programming operation may take 7-8 microseconds (“μs”) and a reading operation may take 85 nanoseconds (“ns”). Thus, when an erase operation to a specific memory location is suspended, the processor may program or read data from a different memory location rather than waiting for the completion of the current erase operation. The ability to suspend an erase operation may improve the overall performance of a flash memory device.[0003]
• Typically, a status register stores multiple memory bits in which one or more of the memory bits may be used to provide a specific status signal. The status signal may be sent as an output from the memory device via a designated output pin when polled or via the data input/output (“I/O”) pins of a memory device in response to a read status register command.[0004]
• FIG. 1 illustrates one embodiment of a status register for a prior art flash memory device that is capable of performing programming, erase, and read operations. The status register[0005]100 includes the fivememory locations101 through105 with each memory location storing at least one memory bit. For the embodiment shown in FIG. 5, the status register100 provides five status signals. Thememory location101 stores Vpp status (“VPPS”) information; thememory location102 stores byte write and set lock bit status (“BWSLBS”) information; thememory location103 stores erase and clear lock bits status (“ECLBS”) information; thememory location104 stores erase suspend status (“ESS”) information; and thememory location105 stores write state machine status (“WSMS”) information.
• The VPPS information indicates whether Vpp, the programming voltage, is at an acceptable voltage level or not at an acceptable voltage level. If Vpp is not at an acceptable voltage level, then the current operation may be aborted. The BWSLBS information indicates an unsuccessful byte write operation or a successful byte write operation. Alternatively, the BWSLBS information indicates an unsuccessful set master/block lock bit operation or a successful set master/block lock bit operation. The ECLBS information indicates an unsuccessful block erasure operation or a successful block erasure operation. Alternatively, the ECLBS information indicates an unsuccessful clear lock bits operation or a successful clear lock bits operation. The ESS information indicates that the block erase operation is suspended or that the block erase operation is in progress/completed. The WSMS information indicates that the write state machine is ready or is busy.[0006]
• The VPPS signal, the BWSLBS signal, the ECLBS signal, the ESS signal, and the WSMS signal are provided are outputted in response to a read status register command. Furthermore, the WSMS signal is outputted by polling a dedicated status output pin (e.g., pin).[0007]
• The prior art memory device described above did not, however, provide the feature of suspending a programming operation. Therefore, a programming operation specifying a particular memory location could not be suspended in order to perform another operation, such as a read operation to another memory location, while the programming operation is suspended. In certain situations, it may be more efficient to perform a read operation (which requires less time than a write operation) while a programming operation is suspended, rather than waiting until the programming operation is completed.[0008]
• Additionally, the prior art memory device described above did not provide the feature of indicating whether an unsuccessful program or erase operation was due to an attempt to access data in a protected memory block. A prior art protection mechanism was implemented by the setting and clearing of memory bits (i.e., lock bits) that correspond to the various memory blocks in the memory device. The lock bits are stored in a miniature array referred to as the block lock mini-array. The lock bits within the block lock mini-array are set to indicate that the corresponding memory block is locked, and cleared (or not set) to indicate that the corresponding memory block is unlocked. A read, program, or erase operation may be performed on any unlocked memory block. A program base operation may not, however, be performed on any locked memory block unless an override lock operation is first performed on the locked memory block.[0009]
SUMMARY OF THE INVENTION
• A memory device is described that has a control circuit coupled to a memory array and a register. The register is configured to store at least one bit indicating the suspend status of a write operation. The control circuit is configured to update the register and to control the output of a status signal representing the suspend status of the write operation.[0010]
• A memory device is described that has a control circuit coupled to a memory array and a register. The register is configured to store at least one bit indicating the protection status of a data modification operation. The control circuit is configured to update the register and to control the output of a status signal representing the protection status of the data modification operation.[0011]
• A method is also described for providing the suspend status of a programming operation in a memory device. A programming operation to a memory location is performed. Prior to the completion of the programming operation, a suspend status signal is received. It is determined whether or not to suspend the programming operation. If the programming operation is suspended, a status register is updated, if necessary, to indicate the programming operation is suspended. An output signal is provided to indicate the suspend status of the programming operation.[0012]
• A method is also described for providing the protection status of a data modification operation in a memory device. A data modification operation is issued with respect to a memory location. The protection status of the memory location is determined. An output signal is provided to indicate the protection status of the memory location.[0013]
• Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.[0014]
BRIEF DESCRIPTION OF THE DRAWINGS
• The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:[0015]
• FIG. 1 illustrates a prior art status register.[0016]
• FIG. 2 illustrates a computer system that includes one embodiment of the memory device.[0017]
• FIG. 3 illustrates a CPU coupled to one embodiment of the memory device.[0018]
• FIG. 4 illustrates one embodiment of the status register.[0019]
• FIG. 5 illustrates a flow chart for initializing one embodiment of the status register.[0020]
• FIG. 6 illustrates a flow chart for performing a programming or erase operation for one embodiment of the memory device.[0021]
• FIG. 7 illustrates a flow chart for performing a block lock check for one embodiment of the memory device.[0022]
• FIGS. 8 through 12 illustrate a flow chart for a programming operation.[0023]
• FIGS. 13 through 17 illustrate a flow chart for an erase operation.[0024]
DETAILED DESCRIPTION
• One embodiment of the memory device optimizes the memory to processor interface by providing a programming suspend status signal. The programming suspend status signal is used to indicate the current execution status (i.e., whether a programming operation is suspended or is not suspended) of a programming operation. For one embodiment, the programming operation is a byte write operation. Once the processor is informed that the execution of the current programming operation is suspended, the processor may request that a different read, program or erase operation may be performed while the programming operation is suspended.[0025]
• For example, once the processor is informed that the programming operation to a specific memory location is suspended, then the processor may request that a read operation be performed on another memory location. As such, the processor may not be required to wait until the entire programming operation to a first memory location is completed (which may be an unacceptable time) before reading from a second memory location. In certain situations, this feature may improve the efficiency of the computer system.[0026]
• One embodiment of the memory device optimizes the memory to processor interface by providing a protection status signal. This signal is used to indicate whether the memory location accessed by a program or erase operation resides in a protected memory block or an unprotected memory block.[0027]
• For one embodiment, a protected memory block is referred to as a locked memory block and an unprotected memory block is referred to as an unlocked memory block. The data stored in an unlocked memory block may be modified by a program or erase operation; however, the data stored in a locked memory block may not be modified unless the memory block is first unlocked by an override operation. This feature of providing a protection status signal typically allows the processor to differentiate between a program or erase operation that failed due to an attempt to access a memory location in a memory block that was protected (e.g., block locked) versus a program or erase operation that failed due to a power failure or a bad block. One intent is to improve the efficiency of the computer system.[0028]
• The purpose of the protection status signal is to provide the user with meaningful information about an operation. If the user finds out that the operation (for example, a byte write operation) failed because of block protection, the user can unlock the block and reissue the command. But if the operation failed because of a bad block, then the user will not try to write again to the same location. That is why the differentiation between the two types of failures is advantageous. An analogy would be being unable to open a car door because the door is locked versus because the door is jammed. In the former case, one uses a key to open the door. In the latter case, one calls a mechanic to fix the door.[0029]
• One embodiment of the memory device may be used in various types of computer systems or data processing systems. The computer system within which the memory device, such as a flash memory device, is used can be a personal computer, a notebook computer, a laptop computer, a personal assistant/communicator, a minicomputer, a workstation, a mainframe, a multiprocessor computer, or any other type of computer system. In addition, the system in which the memory device is used can be a printer system, a cellular phone system, a digital answering system, a digital camera, or any other system that requires data storage.[0030]
• FIG. 2 illustrates one embodiment of a general[0031]purpose computer system10. Thecomputer system10 may include apower supply11, a central processing unit (“CPU”)12, amain memory13, aflash memory14, amass storage device15, aframe buffer16, and aninput device18, all of which are coupled to abus19. Data may be transferred among the various components in thesystem10 via thebus19. Theframe buffer16 receives image data which are displayed on thedisplay device17.
• For one embodiment, the[0032]mass storage device15 is a “solid state disk drive” that includes a plurality of flash EEPROM devices for emulating the operation of a magnetic hard disk drive. For another embodiment, themass storage device15 is a hard disk drive.
• The[0033]power supply11 includes a VCC output that provides the VCC operating voltage to the various components in the system via thebus19. Thepower supply11 may also include a VPP output that provides the VPP programming voltage toflash memory14 and flash memory withinmass storage device15.
• FIG. 3 illustrates one embodiment of a block diagram of a[0034]flash memory device200 coupled to aCPU201 in a computer system. Theflash device200 includes amain memory array212, which is subdivided into multiple memory blocks (i.e., block1 through block N). For one embodiment, themain memory212stores1 megabyte of data with each byte storing8 bits of data. The1 megabyte of data may be arranged in sixteen64 kilobyte memory blocks which are individually erasable, lockable, and unlockable in the computer system. The Y decoding andgating circuit210 and theX decoding circuit211 may be used to select the memory locations within themain memory array212 that are accessed by theCPU201.
• For one embodiment,[0035]main memory212 includes flash memory cells that include electrically isolated gates referred to as floating gates. The flash memory cells include a drain region and a source region in a substrate. A polysilicon gate is generally disposed above and between these regions and insulated from these regions by an insulating layer. A second gate, referred to as the floating gate, is disposed above the floating gate and may be fabricated from a second layer of polysilicon. The gate terminals of the flash memory cells are coupled to the word-lines and the drain terminals of the flash memory cells are coupled to the bit-lines.
• The[0036]flash memory device200 includes ablock lock mini-array214 for storing bits referred to as the block lock bits. As noted above, the setting and clearing of the block lock bits is used to prevent or protect data stored in themain memory array212 from being modified. The Y decoding andgating circuit213 and theX decoding circuit215 is used to select the memory locations within theblock lock mini-array214 that are accessed by theCPU201.
• For one embodiment, the protection mechanism incorporating the block lock bits uses a combination of bits, sixteen block lock bits and a master lock bit, to lock and unlock the various memory blocks. The locked block lock bits gate attempts to perform block erase or programming operations, while a locked master lock bit gates attempts to modify the block lock bits. Various lock bit configuration operations (i.e., set block lock bit, set master lock bit, and clear block lock bits commands) are used to configure the bits in the block lock mini-array. For an alternative embodiment, the mini-array[0037]214 is used to store data other than the block lock bits.
• When the[0038]CPU201 accesses a memory location for an operation (e.g., read operation, write operation, erase operation, etc.), the address signals generated by theCPU201 are received by theflash memory device200 via theaddress bus220. The address signals are inputted directly into the multiplexer (“mux”)217 or inputted into theaddress latch216. Theaddress latch216 is coupled to themux217 to provide address signals to themux217 via theinternal bus221. The command state machine (“CSM”)203 provides a control signal to themux217 to select between the input coupled to theaddress bus220 and the input coupled to theaddress latch216. Themux217 provides the address signals generated by theCPU201 over theinternal bus228 to the appropriate decoding circuits (i.e., Y decoding andgating circuit213, X decoding circuit, Y decoding andgating circuit210, and X decoding circuit211).
• The[0039]CSM203, also referred to as the command user interface (“CUI”), serves as the interface between theCPU201 and the internal operation of theflash memory device200. Commands are written into theCSM203 using standard microprocessor write timings. TheCSM203 contents serve as an input to the internal write state machine (“WSM”)205, which controls the various data modification operations of theflash memory device200. For one embodiment, theCSM203 controls the block erase, byte write, and lock bit configuration operations. Functions associated with altering the data in the memory arrays (e.g., block erase, byte write, lock bit configuration, and status operations) are accessed via theCSM203 and are executed under the control of theWSM205. Data stored in thememory arrays212 and214 or data stored in thestatus register206 may be accessed by inputting the appropriate commands into theCSM203. TheCSM203 and theWSM205 are referred to as the control logic.
• Once a valid command or command sequence has been generated by the[0040]CPU201 and written into theCSM203, theflash memory device200 automatically executes the command or commands. In other words, the control logic automatically executes the algorithms and timings necessary for the various data operations.
• The[0041]CPU201 programs (i.e., writes) data into theflash memory device200 via the data bus223. Data bus223 is coupled to the data input/output pins (e.g., DQ₀-DQ₇). The data to be written into themain memory array212 or theblock lock mini-array214 is inputted into the data latch204 via the data bus223 when the appropriate control signals (e.g., {overscore (WE)}) are received from theCPU201, and subsequently inputted into thewrite state machine205 via theinternal bus220. When theCSM203 provides the control signals to theWSM205 via theline270, theWSM205 provides the appropriate program control signals overline290 to thevoltage control circuit209. In response to the program control signals from theWSM205, thevoltage control circuit209 provides the appropriate voltage signals to the flash memory cells selected (i.e., addressed) for programming. For one embodiment, flash memory cells may be programmed by applying 12 volts to the gate terminal of the flash memory cell via the selected word-lines, 6 volts to 7 volts to the drain terminal of the flash memory cell via the selected bit-lines, and by applying ground to the source terminal of the flash memory cell.
• For one embodiment, the data operations of writing or programming data into the memory arrays are performed in byte increments and thus are referred to as byte write operations. For one embodiment, a byte write operation takes approximately 6 μs when Vcc is at 5 volts and Vpp is at 12.0 volts. One embodiment of the[0042]flash memory device200 may also operate in the byte write suspend mode. The byte write suspend mode enables the system to read data or execute code from any other memory location within the flash memory array while the byte write operation is suspended.
• Data stored in the memory arrays (e.g.,[0043]main memory array212, block lock mini-array214) may be erased by applying the appropriate voltage signals to the selected memory cells. During an erase operation, theCSM203 receives an erase command via the data bus223 and the CE# and WE# control signals from theCPU201. Once theCSM203 provides erase control signals to theWSM205, theWSM205 may enable thevoltage control circuit209 to provide the appropriate voltage signals to the selected memory cells. For one embodiment, a block of memory cells may be erased by applying −11 volts to gate terminal of the flash memory cells, 6 volts to the source terminal of the flash memory cells, and by floating the drain terminal. For one embodiment, an entire block may be erased within1 second.
• The[0044]CPU201 reads data stored in the memory arrays (e.g.,main memory array212, block lock mini-array214) via the data bus223. Themain memory array212 is coupled to thesense circuit207 via thebus230, and the block lock mini-array is coupled to thesense circuit208 via thebus229. Thesense circuit207 is used to sense the bit-line voltages of the selected and nonselected memory cells in themain memory array212. Similarly, thesense circuit208 is used to sense the bit-line voltages of the selected and nonselected memory cells in theblock lock mini-array214. Thesense circuit207 provides data signals over thebus227 to the output multiplexer (“mux”)202 and thesense circuit208 provides data signals overbus225 to theoutput mux202. These data signals represent the data read from the selected memory locations. For one embodiment, each memory location accessed for a read operation includes eight bits. When the output mux receives the appropriate read control signals via line254 from theCSM203 and receives an asserted output enable (“OE”) signal from the CPU vialine264, theoutput mux202 outputs the data signals onto the data bus223. TheCPU201 then accesses the data from the data bus223.
• The[0045]flash memory device200 also includes astatus register206. Thestatus register206 includes any type of storage device that is capable of storing the status information. For one embodiment, thestatus register206 includes multiple flip-flop circuits. Although FIG. 3 shows thestatus register206 residing outside ofCSM203, for an alternative embodiment,status register206 resides within theCSM203 or the control logic.
• [0046]Status register206 indicates when theWSM205 has completed a block erase, byte write, or block lock bit configuration operation. Furthermore, thestatus register206 indicates whether these operations have been completed successfully or unsuccessfully.Status register206 also provides other status signals, such as a byte write suspend status signal that indicates whether a byte write operation has been suspended or a protection status signal to indicate whether a byte write operation, a block erase operation, or a block lock bit configuration operation has failed due to attempts to modify a “locked” memory location.
• The[0047]CPU201 accesses the data stored in thestatus register206 by providing a read status register command over the data bus223. In response to a read status register command, theCSM203 provides a read status register control signal overline253 to thestatus register206. The requested status data from thestatus register206 is outputted onto theinternal bus226. When the control signals generated by theCSM203 and received by theoutput mux202 over line254 enables theoutput mux202 to select the data from theinternal bus226, the requested status data is then outputted from theflash memory device200 via the data bus223.
• The status register[0048]206 stores multiple memory bits, and one or more of the memory bits is used to provide a specific status signal. The status signal is outputted from theflash memory200 via an output pin designated to provide a certain status signal or via the data input/output pins (e.g., DQ₀-DQ₇). For one embodiment, theflash memory device200 includes a READY/BUSY# (RY/BY#) pin to indicate whether the flash memory device is ready to receive a new command or is busy performing the previous command. The processor polls the RY/BY# pin to determine the status of the RY/BY# pin. For an alternative embodiment, the status of a specific status signal is read via the data input/output pins (e.g., DQ₀-DQ₇) of theflash memory device200 after inputting a read status register command via the data input/output pins.
• FIG. 4 illustrates one embodiment of the[0049]status register206. The status register400 includes eightmemory locations401 through408. Each of the memory locations stores at least one memory bit and provides at least one status signal. Similar to the prior art status register100, the status register400 stores the Vpp status (“VPPS”) information, the byte write and set lock bit status (“BWSLBS”) information, the erase and clear lock bits status (“ECLBS”) information, the erase suspend status (“ESS”) information, and the write state machine status (“WSMS”) information. More specifically,memory location404 stores the VPPS information.Memory location405 stores the BWSLBS information.Memory location406 stores the ECLBS information.Memory location407 stores the ESS information.Memory location408 stores the WSMS information.
• In addition to storing the status information for the VPP, BWSLBS, ECLB, ES, and WSM, the status register[0050]400 includes additional memory locations for storing the status information related to the suspension of a programming operation and/or the protection of a memory location (or locations) addressed for a data operation. For one embodiment, the status register stores write byte suspend status (“WBSS”) information and/or the data protection status (“DPS”) information. The number of total memory locations may vary for alternative embodiments. Furthermore, the status register400 may include one or more additional memory locations, such as thememory location401, which is designated as a reserved memory location. A reserved memory location is a memory location that is not currently being used to store status information but may be reserved to store status information in the future.
• One embodiment of the[0051]flash memory device200 allows the system software to suspend a programming operation in order to read data from another flash memory array location. A programming operation is suspended by entering a programming suspend command. For one embodiment, a programming operation is referred to as a byte write operation. The programming operation is suspended by entering a byte write suspend command. Once the programming process starts, a programming suspend command causes the control logic to suspend the byte write sequence at one of the predetermined points in the algorithm. The BWSS information indicates whether the programming operation is suspended or not suspended in response to the programming suspend command.
• One embodiment of the flash memory devise[0052]200 stores DPS information. When a data modification operation (i.e., a program or erase operation) is requested, a protect status signal is outputted from theflash memory device200 to inform the CPU (or other devices) that the attempted data modification operation addressed a protected memory location (e.g., a locked memory location) or an unprotected memory location (e.g., an unlocked memory location). For one embodiment, when the requested data modification operation fails, the user is able to distinguish between an operation failure due to locked memory block versus an operation failure due to other failures, such as power failure or a bad block. This allows the user to be better informed as to the causes of the failure so the user can better react to the failure.
• For example, if the requested data modification operation failed due to an attempt to modify data in a locked memory block, the user may the decide to modify data in another memory block that is unlocked or the user may decide to unlock the memory block in order to modify the data. On the other hand, if the requested data modification operation failed due to a bad block, the bad block may be replaced with a redundant block or the[0053]flash memory device200 may be designated as a failed device.
• The following figures illustrate the steps involved in providing the various status signals. For one embodiment, the status register[0054]400 is initialized according to the steps shown in FIG. 5. Theflash memory device200 is powered-up by applying the appropriate power supply signals as shown instep 501. For one embodiment, theflash memory device200 operates with a 3.3 volt or a 5.0 volt VCC power supply. For an alternative embodiment, the flash memory device operates with a 1.8 volt VCC power supply.
• Once the[0055]flash memory device200 is powered-up, the RESET/DEEP POWER-DOWN (RP#) input pin is checked, as shown instep 502. For one embodiment, the RP# pin is used for placing theflash memory device200 in the deep power-down mode and for resetting the internal automation of theflash memory device200. A logic high voltage level on RP# enables the normal operation of theflash memory device200 and a logic low voltage level on RP# inhibits any operations in order to provide data protection during power transitions and to save power. If RP# is at a logical high level, then thememory locations402 through408 are initialized as shown instep503. For one embodiment, thememory locations402 through407 are initialized by being set to “o” and thememory location408 is initialized by being set to “1.”
• When the status register[0056]400 is initialized, thememory location402 indicates an unlocked protection status.Memory location403 indicates a byte write operation is in progress or completed.Memory location404 indicates that the Vpp voltage is at an appropriate voltage level.Memory location405 indicates a successful byte write operation or set master/block lock bit operation.Memory location406 indicates a successful block erase operation or clear lock bits operation.Memory location407 indicates a block erase operation is in progress or is completed.Memory location408 indicates that the control logic is ready to receive a new command or command sequence.
• FIG. 6 illustrates a flow chart for performing a programming or erase operation for one embodiment of the[0057]flash memory device200. According to step 601, a programming command or an erase command is received by theflash memory device200. The programming command or the erase command may include a sequence of commands. Typically, these commands are generated by theCPU201.
• If a programming command (or sequence of commands) is received, the address of the memory location to be written to and the data to be written is received by the[0058]flash memory device200, as shown instep 602. If an erase command is received, the address of the memory location (i.e., memory block) to be erased is received by theflash memory device200, as shown instep 602. Aftersteps 601 and 602 are completed, the control logic controls the programming and programming verify algorithms internally (not shown). Similarly, the control logic controls the erase and erase verify algorithms internally (not shown).
• The[0059]flash memory device200 then performs a block lock check instep603. The block lock check includes a sequence of steps that update the status register (e.g., thememory location402, which stores the protection status information). The block lock check is described in more detail in connection with FIG. 7.
• Next, the control logic determines whether the block lock bit, corresponding to the memory location to be accessed, is set. If the block lock bit is not set, then the programming or erase operation is performed in[0060]step605 and the programming or erase operation is verified instep 607. On the other hand, if the block lock bit is set, then theflash memory device200 determines whether or not to override the setting of the block lock bit corresponding to the memory location addressed for a write or erase operation, as shown instep 606. For one embodiment, the override command may be enabled by RP# being at 12 volts. If the override is not enabled and the block lock bit is set, then the programming or erase operation fails due to a locked memory block.
• On the other hand, if the override is enabled and the set block lock bit is cleared, then the programming or erase operation is performed at[0061]step 605 and then verified as having been successfully performed instep 607. If it is determined instep 607 that the programming or erase operation was not successful, then theflash memory device200 indicates that the programming or erase operation failed for reasons other than an attempt to access a memory location residing within a locked memory block, as shown instep 609. For example, the failure may have been caused by a performing an erase or programming operation on a bad or defective memory block or a power failure. Otherwise, theflash memory device200 indicates that the programming or erase operation was successfully completed.
• The block[0062]lock check step 603 is described in more detail in FIG. 7. For one embodiment, each lock bit corresponds to a block of memory in the main array, and therefore, the lock check may be referred to as a block lock check. As previously mentioned, theflash memory device200 includes ablock lock mini-array214 for storing bits referred to as the block lock bits. The setting and the clearing of the block lock bits is used to prevent or protect data stored in themain memory array212 from being modified. For one embodiment, each block lock bit in the mini-array214 corresponds to a respective block of memory cells in themain memory array212. The programming (i.e., the setting or clearing) of the bits in theblock lock miniarray214 is described below in conjunction with FIG. 8.
• According to step 701, the[0063]flash memory device200 reads the block lock bit in the mini-array214 that corresponds to the memory block in themain array214 that includes the memory location selected (i.e., addressed) for a programming or erase operation. For one embodiment, the memory location addressed for a programming operation is a byte of data and the memory location addressed for an erase operation is a block of data. Step701 typically occurs while the control logic is executing the command sequence for the programming operation or the erase operation.
• While performing the block lock check, the control logic within the[0064]flash memory device200 determines atstep 702 whether the block lock bit is set. For one embodiment, a cleared lock bit is at a logic “0.” A set lock bit is at a logic “1.” If the corresponding block lock bit is set, then the control logic updates thestatus register206 to indicate that the corresponding block lock bit is protected or locked. For one embodiment,memory location402 is updated to indicate that the memory block selected for a data modification operation is locked.
• On the other hand, if the corresponding block lock bit is not set, then the control logic updates the[0065]status register206 to indicate that the corresponding block lock bit is not locked. For one embodiment, thememory location402 is updated to indicate that the memory block selected for a data modification operation is unlocked.
• FIG. 7 illustrates in[0066]step 702 that if the corresponding block lock bit is not set, then the block lock check is completed. For one embodiment, the DPS information in thestatus register206 has already been initialized to indicate that the block lock bits are not set. Thus, when it is determined that the lock bit corresponding to the addressed memory location is not set, the DPS information does not need to be modified.
• FIGS. 8 through 12 provide a detailed description of the programming operation for one embodiment of the[0067]flash memory device200. Unlike the prior art flash memory devices, one embodiment may distinguish between a programming or write operation failure due to a device protect error and a program operation failure (such as a power failure or a bad block). Furthermore, unlike the prior art flash memory devices, one embodiment, allows theflash memory device200 to suspend a programming operation.
• For one embodiment, the[0068]main memory array212 is programmed by performing a programming operation such as a byte write operation. Instep901, the control logic receives a programming command, such as a byte write command, to initiate the programming operation. Once the data to be written and the address to be written into theflash memory device200 is received by the control logic instep 902, thestatus register206 is updated to indicate that the control logic is busy performing a data modification operation instep 903. For one embodiment, thememory location408 in the status register400 is updated to store a logic “0.”
• Once the[0069]status register206 has been updated atstep 903, the control logic performs a block lock check atstep 904. The block lock check instep 904 is performed in accordance with the steps described in FIG. 7. The block lock check ensures that thestatus register206 includes the updated protection status information corresponding to the memory location selected for the programming operation. Next, instep 905, the control logic starts performing the programming operation specified by the programming command.
• The control logic then determines if the programming operation is completed in[0070]step 1001. If the programming operation is completed, then thestatus register206 is updated to indicate that the control logic has completed its previous data modification operation and is ready to receive a new data modification operation instep 1002. After updating thestatus register206, a determination is made instep 1003 whether to perform a full status check. The full status check checks the various status signals to determine whether a specified failure has occurred. FIG. 12 describes the status check in more detail. If a full status check is desired, then the control logic proceeds to step1301. Otherwise, the programming operation is completed.
• On the other hand, if the programming operation is not completed in[0071]step 1001, then the control logic determines whether a programming suspend command has been entered instep 1004. If a programming suspend command has been entered, then the control logic proceeds to step 1101 in FIG. 10.
• Once a programming suspend command has been entered, the control logic may or may not proceed to suspend the programming operation. The programming suspend command requests that the control logic suspend the programming operation sequence at one of the predetermined points in the algorithm. Although a programming suspend command has been received by the control logic, if the program operation has already or is currently executing those commands, the programming operation may not be suspended.[0072]
• If the programming operation is not suspended, the control logic returns to step 1001 to determine if the programming operation is completed. On the other hand, if the programming operation is suspended, the control logic proceeds to step 1002 to update the[0073]status register206 to indicate that the programming operation is suspended. For one embodiment, thememory location403 is updated to store a logic “1” to indicate the programming operation (e.g., byte-write operation) is suspended. Once thestatus register206 is updated to indicate that the programming operation is suspended, thestatus register206 is updated to indicate that the control logic is ready to perform a new data modification operation, as shown instep 1103. For one embodiment, thememory location408 in the status register206 stores the WSMS information.
• Once the[0074]status register206 is updated, the control logic receives a read status register command as shown instep 1104. In response to the read status register command, theflash memory device200 automatically outputs the WSMS signal and the BWSS signal. After the WSMS signal is outputted from theflash memory array200, theflash memory array200 receives a read command for a memory location other than that specified by the write operation that was suspended. In other words, a read operation may not be performed on the same memory location that was specified in the programming operation that is currently being suspended.
• Next, a read operation is performed on the selected memory location in the main memory as shown in[0075]step 1106. The control logic determines when the read operation is completed instep 1106. Once the control logic has completed the read operation, the control logic proceeds to performstep 1201 as shown in FIG. 11.
• Once the read operation is completed, the[0076]flash memory device200 receives a programming resume command atstep 1201. The control logic then updates thestatus register206 to indicate that the control logic is busy completing the programming or write operation. Additionally, thestatus register206 is updated atstep 1203 to indicate that the programming operation is no longer suspended. For one embodiment, thememory location408 and thememory location403 in the status register400 are each updated to store a logic “0.” Aftersteps 1202 and 1203 are completed,step 1001 is repeated.
• Referring back to[0077]step 1003 in FIG. 9, if theflash memory device200 determines that a full status check is to be performed, theflash memory device200 proceeds to step 1301 in FIG. 12. Atstep 1301, the control logic receives a read status register command. For one embodiment, the memory location404 (which stores the VPPS information), the memory location402 (which stores the DPS information), and the memory location405 (which stores the BWSLBS information) may be read from thestatus register206.
• These memory locations within the[0078]status register206 are read to determine the various failures modes. Atstep 1302, theflash memory device200 checks whether the programming voltage Vpp applied to theflash memory device200 is within the appropriate voltage level range. If Vpp is not within an appropriate voltage level (e.g., if Vpp is not greater or equal to 3 volts), then the VPPS signal indicates a Vpp range error instep 1305. On the other hand, if Vpp is within the appropriate range, then another status check is made.
• The[0079]flash memory device200 also checks whether the programming operation is requested to be performed on a memory location within a locked memory block instep 1303. If the selected memory location resides within a memory block that is device protected or locked, then a device protect error results, as shown instep 1306. On the other hand, if the selected memory location resides within an unprotected or unlocked memory block, then another status check is made.
• At[0080]step 1304, theflash memory device200 checks whether the programming operation was performed successfully. If the programming operation was not successfully completed, then theflash memory device200 atstep 1307 detects a program operation error instep 1307 and the code terminates. On the other hand, if the programming operation was successfully completed, then the full status check is completed. For an alternative embodiment, another status check may be made, however.
• FIGS. 13 through 17 describe an erase operation for one embodiment. Unlike the prior art flash memory devices, one embodiment distinguishes between an erase operation failure due to a device protect error and a failure due to an erase operation failure (e.g., a bad memory location).[0081]
• Once the[0082]flash memory device200 receives an erase command (or command sequence) instep 1401 and the address of the memory location to be erased instep 1402, thestatus register206 is updated atstep 1403 to indicate that the control logic is busy performing an erase operation. For one embodiment, thememory location408 in thestatus register206 is updated to store a logic “0.”
• Next, the control logic performs a block lock check as shown in[0083]step 1404. For one embodiment, the block lock check is performed in accordance with the steps provided in FIG. 7. After the block lock check is completed, the control logic proceeds to start the erase operation.
• Next,[0084]step 1501 in FIG. 14 determines whether the erase operation is completed. If the erase operation is completed, then atstep 1502 thestatus register206 is updated to indicate that the control logic is ready to perform a new data modification operation. For one embodiment,memory location408 is updated to store a logic “1.” Theflash memory device200 then determines atstep 1503 whether to perform a full status check. If a full status check is not performed, the erase operation is completed. Otherwise, the control logic proceeds to perform the full status check. For one embodiment, the full status check is performed according to the steps described in FIG. 17.
• On the other hand, if it is determined at[0085]step 1501 that the erase operation is not completed, then the control logic determines whether the control logic has received an erase suspend command. If an erase suspend command has not been entered, then step 1501 is repeated. Otherwise, the control logic proceeds to step 1601 in FIG. 15.
• An erase operation is suspended at designated points in the erase operation algorithm. Once an erase suspend command has been received by the[0086]flash memory device200, the control logic may or may not suspend the erase operation, depending on what stage the control logic is at in performing the erase operation. If the erase operation is not suspended, then step 1501 is repeated. Otherwise, the control logic updates thestatus register206 to indicate that the erase operation is suspended, as shown instep 1602, and the control logic is ready to perform a new data modification operation, as shown instep 1603. For one embodiment, thememory location407 in the status register400 is updated to store a logic “1” and thememory location408 in the status register is updated to store a logic “1.” Atstep 1604, the control logic receives a read status register command. Once thestatus register206 indicates that the control logic is ready to perform a new data modification operation, the control logic receives a read or programming command, as shown instep 1603. Subsequently, the read operation or programming operation is performed instep 1606.
• After the read or program operation is completed in[0087]step 1606,step 1701 is performed as, shown in FIG. 16. Atstep 1701, the control logic receives an erase resume command. Next, thestatus register206 is updated to indicate that the control logic is busy performing the erase operation because the erase operation is no longer suspended. For one embodiment, thememory location408 is updated to store a logic “0” and thememory location407 is updated to store a logic “0.”Step 1501 is then repeated.
• The steps in FIG. 17 are performed if it is determined in[0088]step 1503 that the a full status check is to be performed. The full status check instep 1503 is used to determine the various failure modes. The control logic receives the read status register command instep 1801. For one embodiment, memory location404 (which stores the VPPS information), memory location402 (which stores the DPS information), memory location406 (which stores the ECLBS information), and memory location405 (which stores the BWSLBS information), are read during the full status check.
• A programming voltage Vpp range error is detected in[0089]step 1806 when thestatus register206 indicates that the Vpp level is not in the appropriate range instep 1802. A device protecterror1807 is detected instep 1807 when the status register indicates that the attempted erase operation requested a protected or locked memory block to be modified, as shown in step 1803. A command sequence error is detected instep 1808 if atstep 1804 both thememory locations405 and406 are found to be set to a logic “1.” An erase operation error is detected instep 1809 when the status register indicates that the erase operation was not successfully completed. For one embodiment, the full status check is completed after performing the four status checks described above.
• In the foregoing specification, the invention has been described with references to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.[0090]

Claims (29)

What is claimed is:

1. A memory device, comprising:

a memory array;

a register configured to store at least one bit indicating a suspend status of a write operation; and

a control circuit coupled to said memory array and said register, said control circuit configured to update said register and to control the output of a status signal representing said suspend status of said write operation.

2. The memory device of

claim 1

, wherein said register resides within said control circuit.

3. The memory device of

claim 1

, wherein said control circuit is configured to receive a status request signal and said register is configured to output said status signal in response to said status request signal, said status signal having a first state to indicate said write operation is suspended and a second state to indicate said write operation is not suspended.

4. The memory device of

claim 3

, further comprising at least one data input/output coupled to said control circuit, wherein at least one data inputs/output is configured to receive said status request signal from a processor and to provide said status signal to said processor.

5. The memory device of

claim 1

, further comprising a status output coupled to said register, wherein said status output is configured to provide a second status signal when said status output is polled, said second status signal having a first state to indicate said write operation is suspended and a second state to indicate said write operation is not suspended.

6. The memory device of

claim 5

, wherein said status output represents an output pin.

7. The memory device of

claim 1

, wherein said write operation represents a byte write operation.

8. The memory device of

claim 1

, wherein said control circuit includes a first state machine configured to update at least one of said bits indicating said suspend status of said write operation in response to a suspend signal.

9. The memory device of

claim 8

, wherein said suspend signal represents a byte write suspend command.

10. The memory device of

claim 8

, wherein said control circuit further includes a second state machine coupled to said first state machine and configured to control the output said status signal in response to a status request signal.

11. The memory device of

claim 10

, wherein said status request signal is a read status register command.

12. A memory device, comprising:

a memory array;

a register is configured to store at least one bit indicating a protection status of a data modification operation; and

a control circuit coupled to said memory array and said register, said control circuit is configured to update said register and to control the output of a status signal representing said protection status of said data modification operation.

13. The memory device of

claim 12

, wherein said register resides within said control circuit.

14. The memory device of

claim 12

, wherein said control circuit is configured to receive a status request signal and said register is configured to output said status signal in response to said status request signal, said status signal having a first state to indicate said data modification operation attempted to access at least one memory location within a protected memory block and a second state to indicate said data modification operation accessed at least one of said memory locations within an unprotected memory block.

15. The memory device of

claim 14

, further comprising at least one data input/output coupled to said control circuit, wherein at least one data inputs/output is configured to receive said status request signal from a processor and to provide said status signal to said processor.

16. The memory device of

claim 12

, wherein said data modification operation is a programming operation or an erase operation.

17. The memory device of

claim 12

, wherein said control circuit includes a first state machine configured to update at least one of said bits indicating said protection status of said data modification operation in response to a block lock configuration signal.

18. The memory device of

claim 17

, wherein said block lock configuration signal includes a set block lock bit command.

19. The memory device of

claim 18

, wherein said control circuit further includes a second state machine coupled to said first state machine and configured to control the output said status signal in response to a status request signal.

20. A method of providing the suspend status of a programming operation in a memory device, comprising the steps of:

(a) performing a programming operation to a first memory location;

(b) prior to the completion of said programming operation, receiving a suspend signal;

(c) determining whether or not to suspend said programming operation;

(d) if said programming operation is suspended, updating, if necessary, a status register to indicate said programming operation is suspended; and

(e) providing an output signal to indicate said suspend status of programming operation.

21. The method of

claim 20

, wherein step (e) comprises the steps of:

(1) receiving a read status register signal; and

(2) providing said output signal in response to said read status register signal.

22. The method of

claim 20

, wherein step (e) comprises the step of providing said output signal at a dedicated status output.

23. The method of

claim 20

, further comprising the steps of:

(f) performing a second data modification operation to a second memory location;

(g) after the completion of said second data modification operation, updating, if necessary, said status register to indicate said write operation is not suspended; and

(h) resuming said first data modification operation.

24. The method of

claim 23

, wherein said second data modification operation is a read operation.

25. The method of

claim 20

, further comprising, prior to step (a), the step of:

(f) initializing said status register to indicate said write operation is not suspended.

26. A method of providing the protection status of a data modification operation in a memory device, comprising the steps of:

(a) performing a data modification operation to a memory location;

(b) determining said protection status of said memory location;

(c) providing an output signal to indicate said protection status of said memory location.

27. The method of

claim 26

, wherein step (c) comprises the steps of:

(1) receiving a read status signal; and

(2) providing said output signal in response to said read status signal.

28. The method of

claim 26

, further comprising, prior to step (a), the step of:

(d) initializing a status register to indicate said memory location is protected from data modifications.

29. The method of

claim 26

, wherein step (b) comprises the steps of:

(1) performing a read operation to a location within a block lock memory array that corresponds to said memory location; and

(2) updating a status register.

Images