US12197510B2 - Traversal of S portion of a graph problem to be solved using automata processor - Google Patents

Abstract

An apparatus includes a state machine engine. The state machine engine may also include an automaton, whereby the automaton is configured to analyze data from a query related to solving a graph. The automaton may further be configured to report an event representative of a satisfaction of a node solving a hop of the graph by a portion of the input data stream.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Non-Provisional application claiming priority to U.S. Provisional Patent Application No. 62/410,686, entitled “Graph Traversal Using Automata Processor”, filed Oct. 20, 2016, which is herein incorporated by reference.

BACKGROUNDField of Invention

Embodiments relate generally to electronic devices and, more specifically, in certain embodiments, to electronic devices with parallel devices for data analysis.

Description of Related Art

Complex pattern recognition can be inefficient to perform on a conventional von Neumann based computer. A biological brain, in particular a human brain, however, is adept at performing pattern recognition. Current research suggests that a human brain performs pattern recognition using a series of hierarchically organized neuron layers in the neocortex. Neurons in the lower layers of the hierarchy analyze “raw signals” from, for example, sensory organs, while neurons in higher layers analyze signal outputs from neurons in the lower levels. This hierarchical system in the neocortex, possibly in combination with other areas of the brain, accomplishes the complex pattern recognition that enables humans to perform high level functions such as spatial reasoning, conscious thought, and complex language.

In the field of computing, pattern recognition tasks are increasingly challenging. Ever larger volumes of data are transmitted between computers, and the number of patterns that users wish to identify is increasing. For example, spam or malware are often detected by searching for patterns in a data stream, e.g., particular phrases or pieces of code. The number of patterns increases with the variety of spam and malware, as new patterns may be implemented to search for new variants. Searching a data stream for each of these patterns can form a computing bottleneck. Often, as the data stream is received, it is searched for each pattern, one at a time. The delay before the system is ready to search the next portion of the data stream increases with the number of patterns. Thus, pattern recognition may slow the receipt of data.

Hardware has been designed to search a data stream for patterns, but this hardware often is unable to process adequate amounts of data in an amount of time given. Some devices configured to search a data stream do so by distributing the data stream among a plurality of circuits. The circuits each determine whether the data stream matches a portion of a pattern. Often, a large number of circuits operate in parallel, each searching the data stream at generally the same time. The system may then further process the results from these circuits, to arrive at the final results. These “intermediate results”, however, can be larger than the original input data, which may pose issues for the system. The ability to use a cascaded circuits approach, similar to the human brain, offers one potential solution to this problem. However, there has not been a system that effectively allows for performing pattern recognition in a manner more comparable to that of a biological brain. Development of such a system is desirable.

BRIEF DESCRIPTION OF DRAWINGS

FIG.1 illustrates an example of system having a state machine engine, according to various embodiments;

FIG.2 illustrates an example of an FSM lattice of the state machine engine ofFIG.1, according to various embodiments;

FIG.3 illustrates an example of a block of the FSM lattice ofFIG.2, according to various embodiments;

FIG.4 illustrates an example of a row of the block ofFIG.3, according to various embodiments;

FIG.4A illustrates a block as inFIG.3 having counters in rows of the block, according to various embodiments of the invention;

FIG.5 illustrates an example of a Group of Two of the row ofFIG.4, according to embodiments;

FIG.6 illustrates an example of a finite state machine graph, according to various embodiments;

FIG.7 illustrates an example of two-level hierarchy implemented with FSM lattices, according to various embodiments;

FIG.7A illustrates a second example of two-level hierarchy implemented with FSM lattices, according to various embodiments;

FIG.8 illustrates an example of a method for a compiler to convert source code into a binary file for programming of the FSM lattice ofFIG.2, according to various embodiments;

FIG.9 illustrates a state machine engine, according to various embodiments;

FIG.10 illustrates representation of an example of a graph;

FIG.11 illustrates solutions to a problem to be solved for the graph ofFIG.10,

FIG.12 illustrates a first embodiment of a graphical automaton representation for reporting of one or more events generated in the automaton;

FIG.13 illustrates a second embodiment of a graphical automaton representation for reporting of one or more events generated in the automaton;

FIG.14 illustrates a third embodiment of a graphical automaton representation for reporting of an event generated in the automaton;

FIG.15 illustrates a fourth embodiment of a graphical automaton representation for reporting of an event generated in the automaton; and

FIG.16 illustrates a fifth embodiment of a graphical automaton representation for reporting of an event generated in the automaton.

DETAILED DESCRIPTION

Turning now to the figures,FIG.1 illustrates an embodiment of a processor-based system, generally designated byreference numeral 10. It should be noted that as used in the present application, an apparatus may be a device or a system. Thesystem10 may be any of a variety of types such as a desktop computer, laptop computer, pager, cellular phone, personal organizer, portable audio player, control circuit, camera, etc. Thesystem10 may also be a network node, such as a router, a server, or a client (e.g., one of the previously-described types of computers). Thesystem10 may be some other sort of electronic device, such as a copier, a scanner, a printer, a game console, a television, a set-top video distribution or recording system, a cable box, a personal digital media player, a factory automation system, an automotive computer system, or a medical device. (The terms used to describe these various examples of systems, like many of the other terms used herein, may share some referents and, as such, should not be construed narrowly in virtue of the other items listed.)

In a typical processor-based device, such as thesystem10, aprocessor12, such as a microprocessor, controls the processing of system functions and requests in thesystem10. Further, theprocessor12 may comprise a plurality of processors that share system control. Theprocessor12 may be coupled directly or indirectly to each of the elements in thesystem10, such that theprocessor12 controls thesystem10 by executing instructions that may be stored within thesystem10 or external to thesystem10.

In accordance with the embodiments described herein, thesystem10 includes astate machine engine14, which may operate under control of theprocessor12. Alternatively, thesystem10 may be separate from and coupled to thestate machine engine14, with thestate machine engine14 operating under control of theseparate system10 and, more particularly, aprocessor12 therein. Thestate machine engine14 may employ any one of a number of state machine architectures, including, but not limited to Mealy architectures, Moore architectures, Finite State Machines (FSMs), Deterministic FSMs (DFSMs), Bit-Parallel State Machines (BPSMs), etc. Though a variety of architectures may be used, for discussion purposes, the application refers to FSMs. However, those skilled in the art will appreciate that the described techniques may be employed using any one of a variety of state machine architectures.

As discussed further below, thestate machine engine14 may include a number of (e.g., one or more) finite state machine (FSM) lattices (e.g., core of a chip). For purposes of this application the term “lattice” refers to an organized framework (e.g., routing matrix, routing network, frame) of elements (e.g., Boolean cells, counter cells, state machine elements, state transition elements). Furthermore, the “lattice” may have any suitable shape, structure, or hierarchical organization (e.g., grid, cube, spherical, cascading). Each FSM lattice may implement multiple FSMs that each receive and analyze the same data in parallel. Further, the FSM lattices may be arranged in groups (e.g., clusters), such that clusters of FSM lattices may analyze the same input data in parallel. Further, clusters of FSM lattices of thestate machine engine14 may be arranged in a hierarchical structure wherein outputs from state machine lattices on a lower level of the hierarchical structure may be used as inputs to state machine lattices on a higher level. By cascading clusters of parallel FSM lattices of thestate machine engine14 in series through the hierarchical structure, increasingly complex patterns may be analyzed (e.g., evaluated, searched, etc.).

Further, based on the hierarchical parallel configuration of thestate machine engine14, thestate machine engine14 can be employed for complex data analysis (e.g., pattern recognition or other processing) in systems that utilize high processing speeds. For instance, embodiments described herein may be incorporated in systems with processing speeds of 1 GByte/sec. Accordingly, utilizing thestate machine engine14, data from high speed memory devices or other external devices may be rapidly analyzed. Thestate machine engine14 may analyze a data stream according to several criteria (e.g., search terms), at about the same time, e.g., during a single device cycle. Each of the FSM lattices within a cluster of FSMs on a level of thestate machine engine14 may each receive the same search term from the data stream at about the same time, and each of the parallel FSM lattices may determine whether the term advances thestate machine engine14 to the next state in the processing criterion. Thestate machine engine14 may analyze terms according to a relatively large number of criteria, e.g., more than 100, more than 110, or more than 10,000. Because they operate in parallel, they may apply the criteria to a data stream having a relatively high bandwidth, e.g., a data stream of greater than or generally equal to 1 GByte/sec, without slowing the data stream.

In one embodiment, thestate machine engine14 may be configured to recognize (e.g., detect) a great number of patterns in a data stream. For instance, thestate machine engine14 may be utilized to detect a pattern in one or more of a variety of types of data streams that a user or other entity might wish to analyze. For example, thestate machine engine14 may be configured to analyze a stream of data received over a network, such as packets received over the Internet or voice or data received over a cellular network. In one example, thestate machine engine14 may be configured to analyze a data stream for spam or malware. The data stream may be received as a serial data stream, in which the data is received in an order that has meaning, such as in a temporally, lexically, or semantically significant order. Alternatively, the data stream may be received in parallel or out of order and, then, converted into a serial data stream, e.g., by reordering packets received over the Internet. In some embodiments, the data stream may present terms serially, but the bits expressing each of the terms may be received in parallel. The data stream may be received from a source external to thesystem10, or may be formed by interrogating a memory device, such as thememory16, and forming the data stream from data stored in thememory16. In other examples, thestate machine engine14 may be configured to recognize a sequence of characters that spell a certain word, a sequence of genetic base pairs that specify a gene, a sequence of bits in a picture or video file that form a portion of an image, a sequence of bits in an executable file that form a part of a program, or a sequence of bits in an audio file that form a part of a song or a spoken phrase. The stream of data to be analyzed may include multiple bits of data in a binary format or other formats, e.g., base ten, ASCII, etc. The stream may encode the data with a single digit or multiple digits, e.g., several binary digits.

As will be appreciated, thesystem10 may includememory16. Thememory16 may include volatile memory, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Synchronous DRAM (SDRAM), Double Data Rate DRAM (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, etc. Thememory16 may also include non-volatile memory, such as read-only memory (ROM), PC-RAM, silicon-oxide-nitride-oxide-silicon (SONOS) memory, metal-oxide-nitride-oxide-silicon (MONOS) memory, polysilicon floating gate based memory, and/or other types of flash memory of various architectures (e.g., NAND memory, NOR memory, etc.) to be used in conjunction with the volatile memory. Thememory16 may include one or more memory devices, such as DRAM devices, that may provide data to be analyzed by thestate machine engine14. As used herein, the term “provide” may generically refer to direct, input, insert, issue, route, send, transfer, transmit, generate, give, make available, move, output, pass, place, read out, write, etc. Such devices may be referred to as or include solid state drives (SSDs), MultimediaMediaCards (MMCs), SecureDigital (SD) cards, CompactFlash (CF) cards, or any other suitable device. Further, it should be appreciated that such devices may couple to thesystem10 via any suitable interface, such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Small Computer System Interface (SCSI), IEEE 1394 (Firewire), or any other suitable interface. To facilitate operation of thememory16, such as the flash memory devices, thesystem10 may include a memory controller (not illustrated). As will be appreciated, the memory controller may be an independent device or it may be integral with theprocessor12. Additionally, thesystem10 may include anexternal storage18, such as a magnetic storage device. The external storage may also provide input data to thestate machine engine14.

Thesystem10 may include a number of additional elements. For instance, acompiler20 may be used to configure (e.g., program) thestate machine engine14, as described in more detail with regard toFIG.8. Aninput device22 may also be coupled to theprocessor12 to allow a user to input data into thesystem10. For instance, aninput device22 may be used to input data into thememory16 for later analysis by thestate machine engine14. Theinput device22 may include buttons, switching elements, a keyboard, a light pen, a stylus, a mouse, and/or a voice recognition system, for instance. Anoutput device24, such as a display may also be coupled to theprocessor12. Thedisplay24 may include an LCD, a CRT, LEDs, and/or an audio display, for example. They system may also include anetwork interface device26, such as a Network Interface Card (NIC), for interfacing with a network, such as the Internet. As will be appreciated, thesystem10 may include many other components, depending on the application of thesystem10.

FIGS.2-5 illustrate an example of aFSM lattice30. In an example, theFSM lattice30 comprises an array ofblocks32. As will be described, eachblock32 may include a plurality of selectively couple-able hardware elements (e.g., configurable elements and/or special purpose elements) that correspond to a plurality of states in a FSM. Similar to a state in a FSM, a hardware element can analyze an input stream and activate a downstream hardware element, based on the input stream.

The configurable elements can be configured (e.g., programmed) to implement many different functions. For instance, the configurable elements may include state transition elements (STEs)34,36 (shown inFIG.5) that are hierarchically organized into rows38 (shown inFIGS.3 and4) and blocks32 (shown inFIGS.2 and3). The STEs each may be considered an automaton, e.g., a machine or control mechanism designed to follow automatically a predetermined sequence of operations or respond to encoded instructions. Taken together, the STEs form an automata processor asstate machine engine14. To route signals between the hierarchically organizedSTEs34,36, a hierarchy of configurable switching elements can be used, including inter-block switching elements40 (shown inFIGS.2 and3), intra-block switching elements42 (shown inFIGS.3 and4) and intra-row switching elements44 (shown inFIG.4).

As described below, the switching elements may include routing structures and buffers. ASTE34,36 can correspond to a state of a FSM implemented by theFSM lattice30. TheSTEs34,36 can be coupled together by using the configurable switching elements as described below. Accordingly, a FSM can be implemented on theFSM lattice30 by configuring theSTEs34,36 to correspond to the functions of states and by selectively coupling together theSTEs34,36 to correspond to the transitions between states in the FSM.

FIG.2 illustrates an overall view of an example of aFSM lattice30. TheFSM lattice30 includes a plurality ofblocks32 that can be selectively coupled together with configurableinter-block switching elements40. Theinter-block switching elements40 may include conductors46 (e.g., wires, traces, etc.) and buffers48,50. In an example, buffers48 and50 are included to control the connection and timing of signals to/from theinter-block switching elements40. As described further below, thebuffers48 may be provided to buffer data being sent betweenblocks32, while thebuffers50 may be provided to buffer data being sent betweeninter-block switching elements40. Additionally, theblocks32 can be selectively coupled to an input block52 (e.g., a data input port) for receiving signals (e.g., data) and providing the data to theblocks32. Theblocks32 can also be selectively coupled to an output block54 (e.g., an output port) for providing signals from theblocks32 to an external device (e.g., another FSM lattice30). TheFSM lattice30 can also include aprogramming interface56 to configure (e.g., via an image, program) theFSM lattice30. The image can configure (e.g., set) the state of theSTEs34,36. For example, the image can configure theSTEs34,36 to react in a certain way to a given input at theinput block52. For example, aSTE34,36 can be set to output a high signal when the character ‘a’ is received at theinput block52.

In an example, theinput block52, theoutput block54, and/or theprogramming interface56 can be implemented as registers such that writing to or reading from the registers provides data to or from the respective elements. Accordingly, bits from the image stored in the registers corresponding to theprogramming interface56 can be loaded on theSTEs34,36. AlthoughFIG.2 illustrates a certain number of conductors (e.g., wire, trace) between ablock32,input block52,output block54, and aninter-block switching element40, it should be understood that in other examples, fewer or more conductors may be used.

FIG.3 illustrates an example of ablock32. Ablock32 can include a plurality ofrows38 that can be selectively coupled together with configurableintra-block switching elements42. Additionally, arow38 can be selectively coupled to anotherrow38 within anotherblock32 with theinter-block switching elements40. Arow38 includes a plurality ofSTEs34,36 organized into pairs of elements that are referred to herein as groups of two (GOTs)60. In an example, ablock32 comprises sixteen (16)rows38.

FIG.4 illustrates an example of arow38. AGOT60 can be selectively coupled to other GOTs60 and any other elements (e.g., a special purpose element58) within therow38 by configurableintra-row switching elements44. AGOT60 can also be coupled toother GOTs60 inother rows38 with theintra-block switching element42, orother GOTs60 inother blocks32 with aninter-block switching element40. In an example, aGOT60 has a first andsecond input62,64, and anoutput66. Thefirst input62 is coupled to afirst STE34 of theGOT60 and thesecond input64 is coupled to asecond STE36 of theGOT60, as will be further illustrated with reference toFIG.5.

In an example, therow38 includes a first and second plurality ofrow interconnection conductors68,70. In an example, aninput62,64 of aGOT60 can be coupled to one or morerow interconnection conductors68,70, and anoutput66 can be coupled to one or morerow interconnection conductor68,70. In an example, a first plurality of therow interconnection conductors68 can be coupled to eachSTE34,36 of eachGOT60 within therow38. A second plurality of therow interconnection conductors70 can be coupled to only oneSTE34,36 of eachGOT60 within therow38, but cannot be coupled to theother STE34,36 of theGOT60. In an example, a first half of the second plurality ofrow interconnection conductors70 can couple to first half of theSTEs34,36 within a row38 (oneSTE34 from each GOT60) and a second half of the second plurality ofrow interconnection conductors70 can couple to a second half of theSTEs34,36 within a row38 (theother STE34,36 from each GOT60), as will be better illustrated with respect toFIG.5. The limited connectivity between the second plurality ofrow interconnection conductors70 and theSTEs34,36 is referred to herein as “parity”. In an example, therow38 can also include aspecial purpose element58 such as a counter, a configurable Boolean logic element, look-up table, RAM, a field configurable gate array (FPGA), an application specific integrated circuit (ASIC), a configurable processor (e.g., a microprocessor), or other element for performing a special purpose function.

In an example, thespecial purpose element58 comprises a counter (also referred to herein as counter58). In an example, thecounter58 comprises a 12-bit configurable down counter. The 12-bitconfigurable counter58 has a counting input, a reset input, and zero-count output. The counting input, when asserted, decrements the value of thecounter58 by one. The reset input, when asserted, causes thecounter58 to load an initial value from an associated register. For the 12-bit counter58, up to a 12-bit number can be loaded in as the initial value. When the value of thecounter58 is decremented to zero (0), the zero-count output is asserted. Thecounter58 also has at least two modes, pulse and hold. When thecounter58 is set to pulse mode, the zero-count output is asserted when thecounter58 reaches zero. For example, the zero-count output is asserted during the processing of an immediately subsequent next data byte, which results in thecounter58 being offset in time with respect to the input character cycle. After the next character cycle, the zero-count output is no longer asserted. In this manner, for example, in the pulse mode, the zero-count output is asserted for one input character processing cycle. When thecounter58 is set to hold mode the zero-count output is asserted during the clock cycle when thecounter58 decrements to zero, and stays asserted until thecounter58 is reset by the reset input being asserted.

In another example, thespecial purpose element58 comprises Boolean logic. For example, the Boolean logic may be used to perform logical functions, such as AND, OR, NAND, NOR, Sum of Products (SoP), Negated-Output Sum of Products (NSoP), Negated-Output Product of Sum (NPoS), and Product of Sums (PoS) functions. This Boolean logic can be used to extract data from terminal state STEs (corresponding to terminal nodes of a FSM, as discussed later herein) inFSM lattice30. The data extracted can be used to provide state data toother FSM lattices30 and/or to provide configuring data used to reconfigureFSM lattice30, or to reconfigure anotherFSM lattice30.

FIG.4A is an illustration of an example of ablock32 havingrows38 which each include thespecial purpose element58. For example, thespecial purpose elements58 in theblock32 may includecounter cells58A andBoolean logic cells58B. While only therows38 inrow positions 0 through 4 are illustrated inFIG.4A (e.g., labeled38A through38E), eachblock32 may have any number of rows38 (e.g., 16 rows38), and one or morespecial purpose elements58 may be configured in each of therows38. For example, in one embodiment,counter cells58A may be configured in certain rows38 (e.g., inrow positions 0, 4, 8, and 12), while theBoolean logic cells58B may be configured in the remaining of the 16 rows38 (e.g., inrow positions 1, 2, 3, 5, 6, 7, 9, 10, 11, 13, 14, 15, and 16). TheGOT60 and thespecial purpose elements58 may be selectively coupled (e.g., selectively connected) in eachrow38 throughintra-row switching elements44, where eachrow38 of theblock32 may be selectively coupled with any of theother rows38 of theblock32 throughintra-block switching elements42.

In some embodiments, eachactive GOT60 in eachrow38 may output a signal indicating whether one or more conditions are detected (e.g., a search result is detected), and thespecial purpose element58 in therow38 may receive theGOT60 output to determine whether certain quantifiers of the one or more conditions are met and/or count a number of times a condition is detected. For example, quantifiers of a count operation may include determining whether a condition was detected at least a certain number of times, determining whether a condition was detected no more than a certain number of times, determining whether a condition was detected exactly a certain number of times, and determining whether a condition was detected within a certain range of times.

Outputs from thecounter58A and/or theBoolean logic cell58B may be communicated through theintra-row switching elements44 and theintra-block switching elements42 to perform counting or logic with greater complexity. For example, counters58A may be configured to implement the quantifiers, such as asserting an output only when a condition is detected an exact number of times.Counters58A in ablock32 may also be used concurrently, thereby increasing the total bit count of the combined counters to count higher numbers of a detected condition. Furthermore, in some embodiments, differentspecial purpose elements58 such ascounters58A andBoolean logic cells58B may be used together. For example, an output of one or moreBoolean logic cells58B may be counted by one ormore counters58A in ablock32.

FIG.5 illustrates an example of aGOT60. TheGOT60 includes afirst STE34 and asecond STE36 coupled tointra-group circuitry37. For example, thefirst STE34 and asecond STE36 may haveinputs62,64 andoutputs72,74 coupled to anOR gate76 and a 3-to-1multiplexer78 of theintra-group circuitry37. The 3-to-1multiplexer78 can be set to couple theoutput66 of theGOT60 to either thefirst STE34, thesecond STE36, or theOR gate76. TheOR gate76 can be used to couple together bothoutputs72,74 to form thecommon output66 of theGOT60. In an example, the first andsecond STE34,36 exhibit parity, as discussed above, where theinput62 of thefirst STE34 can be coupled to some of therow interconnection conductors68 and theinput64 of thesecond STE36 can be coupled to otherrow interconnection conductors70 thecommon output66 may be produced which may overcome parity problems. In an example, the twoSTEs34,36 within aGOT60 can be cascaded and/or looped back to themselves by setting either or both of switchingelements79. TheSTEs34,36 can be cascaded by coupling theoutput72,74 of theSTEs34,36 to theinput62,64 of theother STE34,36. TheSTEs34,36 can be looped back to themselves by coupling theoutput72,74 to theirown input62,64. Accordingly, theoutput72 of thefirst STE34 can be coupled to neither, one, or both of theinput62 of thefirst STE34 and theinput64 of thesecond STE36. Additionally, as each of theinputs62,64 may be coupled to a plurality of row routing lines, an OR gate may be utilized to select any of the inputs from these row routing lines alonginputs62,64, as well as theoutputs72,74.

In an example, eachSTE34,36 comprises a plurality ofmemory cells80, such as those often used in dynamic random access memory (DRAM), coupled in parallel to a detectline82. Onesuch memory cell80 comprises a memory cell that can be set to a data state, such as one that corresponds to either a high or a low value (e.g., a 1 or 0). The output of thememory cell80 is coupled to the detectline82 and the input to thememory cell80 receives signals based on data on thedata stream line84. In an example, an input at theinput block52 is decoded to select one or more of thememory cells80. The selectedmemory cell80 provides its stored data state as an output onto the detectline82. For example, the data received at theinput block52 can be provided to a decoder (not shown) and the decoder can select one or more of the data stream lines84. In an example, the decoder can convert an 8-bit ACSII character to the corresponding 1 of 256 data stream lines84.

Amemory cell80, therefore, outputs a high signal to the detectline82 when thememory cell80 is set to a high value and the data on thedata stream line84 selects thememory cell80. When the data on thedata stream line84 selects thememory cell80 and thememory cell80 is set to a low value, thememory cell80 outputs a low signal to the detectline82. The outputs from thememory cells80 on the detectline82 are sensed by adetection cell86.

In an example, the signal on aninput line62,64 sets therespective detection cell86 to either an active or inactive state. When set to the inactive state, thedetection cell86 outputs a low signal on therespective output72,74 regardless of the signal on the respective detectline82. When set to an active state, thedetection cell86 outputs a high signal on therespective output line72,74 when a high signal is detected from one of thememory cells82 of therespective STE34,36. When in the active state, thedetection cell86 outputs a low signal on therespective output line72,74 when the signals from all of thememory cells82 of therespective STE34,36 are low.

In an example, anSTE34,36 includes 256memory cells80 and eachmemory cell80 is coupled to a differentdata stream line84. Thus, anSTE34,36 can be programmed to output a high signal when a selected one or more of thedata stream lines84 have a high signal thereon. For example, theSTE34 can have a first memory cell80 (e.g., bit0) set high and all other memory cells80 (e.g., bits1-255) set low. When therespective detection cell86 is in the active state, theSTE34 outputs a high signal on theoutput72 when thedata stream line84 corresponding tobit0 has a high signal thereon. In other examples, theSTE34 can be set to output a high signal when one of multipledata stream lines84 have a high signal thereon by setting theappropriate memory cells80 to a high value.

In an example, amemory cell80 can be set to a high or low value by reading bits from an associated register. Accordingly, theSTEs34 can be configured by storing an image created by thecompiler20 into the registers and loading the bits in the registers into associatedmemory cells80. In an example, the image created by thecompiler20 includes a binary image of high and low (e.g., 1 and 0) bits. The image can configure theFSM lattice30 to implement a FSM by cascading theSTEs34,36. For example, afirst STE34 can be set to an active state by setting thedetection cell86 to the active state. Thefirst STE34 can be set to output a high signal when thedata stream line84 corresponding tobit0 has a high signal thereon. Thesecond STE36 can be initially set to an inactive state, but can be set to, when active, output a high signal when thedata stream line84 corresponding tobit1 has a high signal thereon. Thefirst STE34 and thesecond STE36 can be cascaded by setting theoutput72 of thefirst STE34 to couple to theinput64 of thesecond STE36. Thus, when a high signal is sensed on thedata stream line84 corresponding tobit0, thefirst STE34 outputs a high signal on theoutput72 and sets thedetection cell86 of thesecond STE36 to an active state. When a high signal is sensed on thedata stream line84 corresponding tobit1, thesecond STE36 outputs a high signal on theoutput74 to activate anotherSTE36 or for output from theFSM lattice30.

In an example, asingle FSM lattice30 is implemented on a single physical device, however, in other examples two ormore FSM lattices30 can be implemented on a single physical device (e.g., physical chip). In an example, eachFSM lattice30 can include a distinctdata input block52, adistinct output block54, adistinct programming interface56, and a distinct set of configurable elements. Moreover, each set of configurable elements can react (e.g., output a high or low signal) to data at their correspondingdata input block52. For example, a first set of configurable elements corresponding to afirst FSM lattice30 can react to the data at a firstdata input block52 corresponding to thefirst FSM lattice30. A second set of configurable elements corresponding to asecond FSM lattice30 can react to a seconddata input block52 corresponding to thesecond FSM lattice30. Accordingly, eachFSM lattice30 includes a set of configurable elements, wherein different sets of configurable elements can react to different input data. Similarly, eachFSM lattice30, and each corresponding set of configurable elements can provide a distinct output. In some examples, anoutput block54 from afirst FSM lattice30 can be coupled to aninput block52 of asecond FSM lattice30, such that input data for thesecond FSM lattice30 can include the output data from thefirst FSM lattice30 in a hierarchical arrangement of a series ofFSM lattices30.

In an example, an image for loading onto theFSM lattice30 comprises a plurality of bits of data for configuring the configurable elements, the configurable switching elements, and the special purpose elements within theFSM lattice30. In an example, the image can be loaded onto theFSM lattice30 to configure theFSM lattice30 to provide a desired output based on certain inputs. Theoutput block54 can provide outputs from theFSM lattice30 based on the reaction of the configurable elements to data at thedata input block52. An output from theoutput block54 can include a single bit indicating a search result of a given pattern, a word comprising a plurality of bits indicating search results and non-search results to a plurality of patterns, and a state vector corresponding to the state of all or certain configurable elements at a given moment. As described, a number ofFSM lattices30 may be included in a state machine engine, such asstate machine engine14, to perform data analysis, such as pattern-recognition (e.g., speech recognition, image recognition, etc.) signal processing, imaging, computer vision, cryptography, and others.

FIG.6 illustrates an example model of a finite state machine (FSM) that can be implemented by theFSM lattice30. TheFSM lattice30 can be configured (e.g., programmed) as a physical implementation of a FSM. A FSM can be represented as a diagram90, (e.g., directed graph, undirected graph, pseudograph), which contains one ormore root nodes92. In addition to theroot nodes92, the FSM can be made up of severalstandard nodes94 andterminal nodes96 that are connected to theroot nodes92 and otherstandard nodes94 through one or more edges98. Anode92,94,96 corresponds to a state in the FSM. Theedges98 correspond to the transitions between the states.

Each of thenodes92,94,96 can be in either an active or an inactive state. When in the inactive state, anode92,94,96 does not react (e.g., respond) to input data. When in an active state, anode92,94,96 can react to input data. Anupstream node92,94 can react to the input data by activating anode94,96 that is downstream from the node when the input data matches criteria specified by anedge98 between theupstream node92,94 and thedownstream node94,96. For example, afirst node94 that specifies the character ‘b’ will activate asecond node94 connected to thefirst node94 by anedge98 when thefirst node94 is active and the character ‘b’ is received as input data. As used herein, “upstream” refers to a relationship between one or more nodes, where a first node that is upstream of one or more other nodes (or upstream of itself in the case of a loop or feedback configuration) refers to the situation in which the first node can activate the one or more other nodes (or can activate itself in the case of a loop). Similarly, “downstream” refers to a relationship where a first node that is downstream of one or more other nodes (or downstream of itself in the case of a loop) can be activated by the one or more other nodes (or can be activated by itself in the case of a loop). Accordingly, the terms “upstream” and “downstream” are used herein to refer to relationships between one or more nodes, but these terms do not preclude the use of loops or other non-linear paths among the nodes.

In the diagram90, theroot node92 can be initially activated and can activatedownstream nodes94 when the input data matches anedge98 from theroot node92.Nodes94 can activatenodes96 when the input data matches anedge98 from thenode94.Nodes94,96 throughout the diagram90 can be activated in this manner as the input data is received. Aterminal node96 corresponds to a search result of a sequence of interest in the input data. Accordingly, activation of aterminal node96 indicates that a sequence of interest has been received as the input data. In the context of theFSM lattice30 implementing a pattern recognition function, arriving at aterminal node96 can indicate that a specific pattern of interest has been detected in the input data.

In an example, eachroot node92,standard node94, andterminal node96 can correspond to a configurable element in theFSM lattice30. Eachedge98 can correspond to connections between the configurable elements. Thus, astandard node94 that transitions to (e.g., has anedge98 connecting to) anotherstandard node94 or aterminal node96 corresponds to a configurable element that transitions to (e.g., provides an output to) another configurable element. In some examples, theroot node92 does not have a corresponding configurable element.

As will be appreciated, although thenode92 is described as a root node andnodes96 are described as terminal nodes, there may not necessarily be a particular “start” or root node and there may not necessarily be a particular “end” or output node. In other words, any node may be a starting point and any node may provide output.

When theFSM lattice30 is programmed, each of the configurable elements can also be in either an active or inactive state. A given configurable element, when inactive, does not react to the input data at a correspondingdata input block52. An active configurable element can react to the input data at thedata input block52, and can activate a downstream configurable element when the input data matches the setting of the configurable element. When a configurable element corresponds to aterminal node96, the configurable element can be coupled to theoutput block54 to provide an indication of a search result to an external device.

An image loaded onto theFSM lattice30 via theprogramming interface56 can configure the configurable elements and special purpose elements, as well as the connections between the configurable elements and special purpose elements, such that a desired FSM is implemented through the sequential activation of nodes based on reactions to the data at thedata input block52. In an example, a configurable element remains active for a single data cycle (e.g., a single character, a set of characters, a single clock cycle) and then becomes inactive unless re-activated by an upstream configurable element.

Aterminal node96 can be considered to store a compressed history of past search results. For example, the one or more patterns of input data required to reach aterminal node96 can be represented by the activation of thatterminal node96. In an example, the output provided by aterminal node96 is binary, for example, the output indicates whether a search result for a pattern of interest has been generated or not. The ratio ofterminal nodes96 tostandard nodes94 in a diagram90 may be quite small. In other words, although there may be a high complexity in the FSM, the output of the FSM may be small by comparison.

In an example, the output of theFSM lattice30 can comprise a state vector. The state vector comprises the state (e.g., activated or not activated) of configurable elements of theFSM lattice30. In another example, the state vector can include the state of all or a subset of the configurable elements whether or not the configurable elements corresponds to aterminal node96. In an example, the state vector includes the states for the configurable elements corresponding toterminal nodes96. Thus, the output can include a collection of the indications provided by allterminal nodes96 of a diagram90. The state vector can be represented as a word, where the binary indication provided by eachterminal node96 comprises one bit of the word. This encoding of theterminal nodes96 can provide an effective indication of the detection state (e.g., whether and what sequences of interest have been detected) for theFSM lattice30.

As mentioned above, theFSM lattice30 can be programmed to implement a pattern recognition function. For example, theFSM lattice30 can be configured to recognize one or more data sequences (e.g., signatures, patterns) in the input data. When a data sequence of interest is recognized by theFSM lattice30, an indication of that recognition can be provided at theoutput block54. In an example, the pattern recognition can recognize a string of symbols (e.g., ASCII characters) to, for example, identify malware or other data in network data.

FIG.7 illustrates an example ofhierarchical structure100, wherein two levels ofFSM lattices30 are coupled in series and used to analyze data. Specifically, in the illustrated embodiment, thehierarchical structure100 includes afirst FSM lattice30A and asecond FSM lattice30B arranged in series. EachFSM lattice30 includes a respectivedata input block52 to receive data input, aprogramming interface block56 to receive configuring signals and anoutput block54.

Thefirst FSM lattice30A is configured to receive input data, for example, raw data at a data input block. Thefirst FSM lattice30A reacts to the input data as described above and provides an output at an output block. The output from thefirst FSM lattice30A is sent to a data input block of thesecond FSM lattice30B. Thesecond FSM lattice30B can then react based on the output provided by thefirst FSM lattice30A and provide acorresponding output signal102 of thehierarchical structure100. This hierarchical coupling of twoFSM lattices30A and30B in series provides a means to provide data regarding past search results in a compressed word from afirst FSM lattice30A to asecond FSM lattice30B. The data provided can effectively be a summary of complex matches (e.g., sequences of interest) that were recorded by thefirst FSM lattice30A.

FIG.7A illustrates a second two-level hierarchy100 of FSM lattices30A,30B,30C, and30D, which allows the overall FSM100 (inclusive of all or some of FSM lattices30A,30B,30C, and30D) to perform two independent levels of analysis of the input data. The first level (e.g.,FSM lattice30A,FSM lattice30B, and/or FSM lattice30C) analyzes the same data stream, which includes data inputs to theoverall FSM100. The outputs of the first level (e.g.,FSM lattice30A,FSM lattice30B, and/or FSM lattice30C) become the inputs to the second level, (e.g.,FSM lattice30D).FSM lattice30D performs further analysis of the combination the analysis already performed by the first level (e.g.,FSM lattice30A,FSM lattice30B, and/or FSM lattice30C). By connectingmultiple FSM lattices30A,30B, and30C together, increased knowledge about the data stream input may be obtained byFSM lattice30D.

The first level of the hierarchy (implemented by one or more ofFSM lattice30A,FSM lattice30B, and FSM lattice30C) can, for example, perform processing directly on a raw data stream. For example, a raw data stream can be received at aninput block52 of the firstlevel FSM lattices30A,30B, and/or30C and the configurable elements of the firstlevel FSM lattices30A,30B, and/or30C can react to the raw data stream. The second level (implemented by theFSM lattice30D) of the hierarchy can process the output from the first level. For example, the secondlevel FSM lattice30D receives the output from anoutput block54 of the firstlevel FSM lattices30A,30B, and/or30C at aninput block52 of the secondlevel FSM lattice30D and the configurable elements of the secondlevel FSM lattice30D can react to the output of the firstlevel FSM lattices30A,30B, and/or30C. Accordingly, in this example, the secondlevel FSM lattice30D does not receive the raw data stream as an input, but rather receives the indications of search results for patterns of interest that are generated from the raw data stream as determined by one or more of the firstlevel FSM lattices30A,30B, and/or30C. Thus, the secondlevel FSM lattice30D can implement aFSM100 that recognizes patterns in the output data stream from the one or more of the firstlevel FSM lattices30A,30B, and/or30C. However, it should also be appreciated that the secondlevel FSM lattice30D can additionally receive the raw data stream as an input, for example, in conjunction with the indications of search results for patterns of interest that are generated from the raw data stream as determined by one or more of the firstlevel FSM lattices30A,30B, and/or30C. It should be appreciated that the secondlevel FSM lattice30D may receive inputs from multiple other FSM lattices in addition to receiving output from the one or more of the firstlevel FSM lattices30A,30B, and/or30C. Likewise, the secondlevel FSM lattice30D may receive inputs from other devices. The secondlevel FSM lattice30D may combine these multiple inputs to produce outputs. Finally, while only two levels of FSM lattices30A,30B,30C, and30D are illustrated, it is envisioned that additional levels of FSM lattices may be stacked such that there are, for example, three, four, 10, 100, or more levels of FSM lattices.

FIG.8 illustrates an example of amethod110 for a compiler to convert source code into an image used to configure a FSM lattice, such aslattice30, to implement a FSM.Method110 includes parsing the source code into a syntax tree (block112), converting the syntax tree into an automaton (block114), optimizing the automaton (block116), converting the automaton into a netlist (block118), placing the netlist on hardware (block120), routing the netlist (block122), and publishing the resulting image (block124).

In an example, thecompiler20 includes an application programming interface (API) that allows software developers to create images for implementing FSMs on theFSM lattice30. Thecompiler20 provides methods to convert an input set of regular expressions in the source code into an image that is configured to configure theFSM lattice30. Thecompiler20 can be implemented by instructions for a computer having a von Neumann architecture. These instructions can cause aprocessor12 on the computer to implement the functions of thecompiler20. For example, the instructions, when executed by theprocessor12, can cause theprocessor12 to perform actions as described inblocks112,114,116,118,120,122, and124 on source code that is accessible to theprocessor12.

In an example, the source code describes search strings for identifying patterns of symbols within a group of symbols. To describe the search strings, the source code can include a plurality of regular expressions (regexes). A regex can be a string for describing a symbol search pattern. Regexes are widely used in various computer domains, such as programming languages, text editors, network security, and others. In an example, the regular expressions supported by the compiler include criteria for the analysis of unstructured data. Unstructured data can include data that is free form and has no indexing applied to words within the data. Words can include any combination of bytes, printable and non-printable, within the data. In an example, the compiler can support multiple different source code languages for implementing regexes including Perl, (e.g., Perl compatible regular expressions (PCRE)), PHP, Java, and .NET languages.

Atblock112 thecompiler20 can parse the source code to form an arrangement of relationally connected operators, where different types of operators correspond to different functions implemented by the source code (e.g., different functions implemented by regexes in the source code). Parsing source code can create a generic representation of the source code. In an example, the generic representation comprises an encoded representation of the regexes in the source code in the form of a tree graph known as a syntax tree. The examples described herein refer to the arrangement as a syntax tree (also known as an “abstract syntax tree”) in other examples, however, a concrete syntax tree as part of the abstract syntax tree, a concrete syntax tree in place of the abstract syntax tree, or other arrangement can be used.

Since, as mentioned above, thecompiler20 can support multiple languages of source code, parsing converts the source code, regardless of the language, into a non-language specific representation, e.g., a syntax tree. Thus, further processing (blocks114,116,118,120) by thecompiler20 can work from a common input structure regardless of the language of the source code.

As noted above, the syntax tree includes a plurality of operators that are relationally connected. A syntax tree can include multiple different types of operators. For example, different operators can correspond to different functions implemented by the regexes in the source code.

Atblock114, the syntax tree is converted into an automaton. An automaton comprises a software model of a FSM which may, for example, comprise a plurality of states. In order to convert the syntax tree into an automaton, the operators and relationships between the operators in the syntax tree are converted into states with transitions between the states. Moreover, in one embodiment, conversion of the automaton is accomplished based on the hardware of theFSM lattice30.

In an example, input symbols for the automaton include the symbols of the alphabet, the numerals 0-9, and other printable characters. In an example, the input symbols are represented by the byte values 0 through 255 inclusive. In an example, an automaton can be represented as a directed graph where the nodes of the graph correspond to the set of states. In an example, a transition from state p to state q on an input symbol a, i.e. δ(p, α), is shown by a directed connection from node p to node q. In an example, a reversal of an automaton produces a new automaton where each transition p→q on some symbol α is reversed q→p on the same symbol. In a reversal, start states become final states and the final states become start states. In an example, the language recognized (e.g., matched) by an automaton is the set of all possible character strings which when input sequentially into the automaton will reach a final state. Each string in the language recognized by the automaton traces a path from the start state to one or more final states.

Atblock116, after the automaton is constructed, the automaton is optimized to reduce its complexity and size, among other things. The automaton can be optimized by combining redundant states.

Atblock118, the optimized automaton is converted into a netlist. Converting the automaton into a netlist maps each state of the automaton to a hardware element (e.g.,STEs34,36, other elements) on theFSM lattice30, and determines the connections between the hardware elements.

Atblock120, the netlist is placed to select a specific hardware element of the target device (e.g.,STEs34,36, special purpose elements58) corresponding to each node of the netlist. In an example, placing selects each specific hardware element based on general input and output constraints for of theFSM lattice30.

Atblock122, the placed netlist is routed to determine the settings for the configurable switching elements (e.g.,inter-block switching elements40,intra-block switching elements42, and intra-row switching elements44) in order to couple the selected hardware elements together to achieve the connections describe by the netlist. In an example, the settings for the configurable switching elements are determined by determining specific conductors of theFSM lattice30 that will be used to connect the selected hardware elements, and the settings for the configurable switching elements. Routing can take into account more specific limitations of the connections between the hardware elements than can be accounted for via the placement atblock120. Accordingly, routing may adjust the location of some of the hardware elements as determined by the global placement in order to make appropriate connections given the actual limitations of the conductors on theFSM lattice30.

Once the netlist is placed and routed, the placed and routed netlist can be converted into a plurality of bits for configuring aFSM lattice30. The plurality of bits are referred to herein as an image (e.g., binary image).

Atblock124, an image is published by thecompiler20. The image comprises a plurality of bits for configuring specific hardware elements of theFSM lattice30. The bits can be loaded onto theFSM lattice30 to configure the state ofSTEs34,36, thespecial purpose elements58, and the configurable switching elements such that the programmedFSM lattice30 implements a FSM having the functionality described by the source code. Placement (block120) and routing (block122) can map specific hardware elements at specific locations in theFSM lattice30 to specific states in the automaton. Accordingly, the bits in the image can configure the specific hardware elements to implement the desired function(s). In an example, the image can be published by saving the machine code to a computer readable medium. In another example, the image can be published by displaying the image on a display device. In still another example, the image can be published by sending the image to another device, such as a configuring device for loading the image onto theFSM lattice30. In yet another example, the image can be published by loading the image onto a FSM lattice (e.g., the FSM lattice30).

In an example, an image can be loaded onto theFSM lattice30 by either directly loading the bit values from the image to theSTEs34,36 and other hardware elements or by loading the image into one or more registers and then writing the bit values from the registers to theSTEs34,36 and other hardware elements. In an example, the hardware elements (e.g.,STEs34,36,special purpose elements58,configurable switching elements40,42,44) of theFSM lattice30 are memory mapped such that a configuring device and/or computer can load the image onto theFSM lattice30 by writing the image to one or more memory addresses.

Method examples described herein can be machine or computer-implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code can include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, the code may be tangibly stored on one or more volatile or non-volatile computer-readable media during execution or at other times. These computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.

Referring now toFIG.9, an embodiment of the state machine engine14 (e.g., a single device on a single chip) is illustrated. As previously described, thestate machine engine14 is configured to receive data from a source, such as thememory16 over a data bus. In the illustrated embodiment, data may be sent to thestate machine engine14 through a bus interface, such as a double data rate three (DDR3)bus interface130. TheDDR3 bus interface130 may be capable of exchanging (e.g., providing and receiving) data at a rate greater than or equal to 1 GByte/sec. Such a data exchange rate may be greater than a rate that data is analyzed by thestate machine engine14. As will be appreciated, depending on the source of the data to be analyzed, thebus interface130 may be any suitable bus interface for exchanging data to and from a data source to thestate machine engine14, such as a NAND Flash interface, peripheral component interconnect (PCI) interface, gigabit media independent interface (GMMI), etc. As previously described, thestate machine engine14 includes one ormore FSM lattices30 configured to analyze data. EachFSM lattice30 may be divided into two half-lattices. In the illustrated embodiment, each half lattice may include 24K STEs (e.g.,STEs34,36), such that thelattice30 includes 48K STEs. Thelattice30 may comprise any desirable number of STEs, arranged as previously described with regard toFIGS.2-5. Further, while only oneFSM lattice30 is illustrated, thestate machine engine14 may includemultiple FSM lattices30, as previously described.

Data to be analyzed may be received at thebus interface130 and provided to theFSM lattice30 through a number of buffers and buffer interfaces. In the illustrated embodiment, the data path includes input buffers132, aninstruction buffer133, process buffers134, and an inter-rank (IR) bus andprocess buffer interface136. The input buffers132 are configured to receive and temporarily store data to be analyzed. In one embodiment, there are two input buffers132 (input buffer A and input buffer B). Data may be stored in one of the twodata input132, while data is being emptied from theother input buffer132, for analysis by theFSM lattice30. Thebus interface130 may be configured to provide data to be analyzed to the input buffers132 until the input buffers132 are full. After the input buffers132 are full, thebus interface130 may be configured to be free to be used for other purpose (e.g., to provide other data from a data stream until the input buffers132 are available to receive additional data to be analyzed). In the illustrated embodiment, the input buffers132 may be 32 KBytes each. Theinstruction buffer133 is configured to receive instructions from theprocessor12 via thebus interface130, such as instructions that correspond to the data to be analyzed and instructions that correspond to configuring thestate machine engine14. The IR bus andprocess buffer interface136 may facilitate providing data to theprocess buffer134. The IR bus andprocess buffer interface136 can be used to ensure that data is processed by theFSM lattice30 in order. The IR bus andprocess buffer interface136 may coordinate the exchange of data, timing data, packing instructions, etc. such that data is received and analyzed correctly. Generally, the IR bus andprocess buffer interface136 allows the analyzing of multiple data sets in parallel through a logical rank ofFSM lattices30. For example, multiple physical devices (e.g.,state machine engines14, chips, separate devices) may be arranged in a rank and may provide data to each other via the IR bus andprocess buffer interface136. For purposes of this application the term “rank” refers to a set ofstate machine engines14 connected to the same chip select. In the illustrated embodiment, the IR bus andprocess buffer interface136 may include a 32 bit data bus. In other embodiments, the IR bus andprocess buffer interface136 may include any suitable data bus, such as a 128 bit data bus.

In the illustrated embodiment, thestate machine engine14 also includes a de-compressor138 and a compressor140 to aid in providing state vector data through thestate machine engine14. The compressor140 and de-compressor138 work in conjunction such that the state vector data can be compressed to minimize the data providing times. By compressing the state vector data, the bus utilization time may be minimized. The compressor140 and de-compressor138 can also be configured to handle state vector data of varying burst lengths. By padding compressed state vector data and including an indicator as to when each compressed region ends, the compressor140 may improve the overall processing speed through thestate machine engine14. The compressor140 may be used to compress results data after analysis by theFSM lattice30. The compressor140 and de-compressor138 may also be used to compress and decompress configuration data. In one embodiment, the compressor140 and de-compressor138 may be disabled (e.g., turned off) such that data flowing to and/or from the compressor140 and de-compressor138 is not modified.

As previously described, an output of theFSM lattice30 can comprise a state vector. The state vector comprises the state (e.g., activated or not activated) of theSTEs34,36 of theFSM lattice30 and the dynamic (e.g., current) count of thecounter58. Thestate machine engine14 includes astate vector system141 having a statevector cache memory142, a statevector memory buffer144, a state vectorintermediate input buffer146, and a state vector intermediate output buffer148. Thestate vector system141 may be used to store multiple state vectors of theFSM lattice30 and to provide a state vector to theFSM lattice30 to restore theFSM lattice30 to a state corresponding to the provided state vector. For example, each state vector may be temporarily stored in the statevector cache memory142. For example, the state of eachSTE34,36 may be stored, such that the state may be restored and used in further analysis at a later time, while freeing theSTEs34,36 for further analysis of a new data set (e.g., search terms). Like a typical cache, the statevector cache memory142 allows storage of state vectors for quick retrieval and use, here by theFSM lattice30, for instance. In the illustrated embodiment, the statevector cache memory142 may store up to 512 state vectors.

As will be appreciated, the state vector data may be exchanged between different state machine engines14 (e.g., chips) in a rank. The state vector data may be exchanged between the differentstate machine engines14 for various purposes such as: to synchronize the state of theSTEs34,36 of theFSM lattices30 of thestate machine engines14, to perform the same functions across multiplestate machine engines14, to reproduce results across multiplestate machine engines14, to cascade results across multiplestate machine engines14, to store a history of states of theSTEs34,36 used to analyze data that is cascaded through multiplestate machine engines14, and so forth. Furthermore, it should be noted that within astate machine engine14, the state vector data may be used to quickly configure theSTEs34,36 of theFSM lattice30. For example, the state vector data may be used to restore the state of theSTEs34,36 to an initialized state (e.g., to prepare for a new input data set), or to restore the state of theSTEs34,36 to prior state (e.g., to continue searching of an interrupted or “split” input data set). In certain embodiments, the state vector data may be provided to thebus interface130 so that the state vector data may be provided to the processor12 (e.g., for analysis of the state vector data, reconfiguring the state vector data to apply modifications, reconfiguring the state vector data to improve efficiency of theSTEs34,36, and so forth).

For example, in certain embodiments, thestate machine engine14 may provide cached state vector data (e.g., data stored by the state vector system141) from theFSM lattice30 to an external device. The external device may receive the state vector data, modify the state vector data, and provide the modified state vector data to thestate machine engine14 for configuring theFSM lattice30. Accordingly, the external device may modify the state vector data so that thestate machine engine14 may skip states (e.g., jump around) as desired.

The statevector cache memory142 may receive state vector data from any suitable device. For example, the statevector cache memory142 may receive a state vector from theFSM lattice30, another FSM lattice30 (e.g., via the IR bus and process buffer interface136), the de-compressor138, and so forth. In the illustrated embodiment, the statevector cache memory142 may receive state vectors from other devices via the statevector memory buffer144. Furthermore, the statevector cache memory142 may provide state vector data to any suitable device. For example, the statevector cache memory142 may provide state vector data to the statevector memory buffer144, the state vectorintermediate input buffer146, and the state vector intermediate output buffer148.

Additional buffers, such as the statevector memory buffer144, state vectorintermediate input buffer146, and state vector intermediate output buffer148, may be utilized in conjunction with the statevector cache memory142 to accommodate rapid retrieval and storage of state vectors, while processing separate data sets with interleaved packets through thestate machine engine14. In the illustrated embodiment, each of the statevector memory buffer144, the state vectorintermediate input buffer146, and the state vector intermediate output buffer148 may be configured to temporarily store one state vector. The statevector memory buffer144 may be used to receive state vector data from any suitable device and to provide state vector data to any suitable device. For example, the statevector memory buffer144 may be used to receive a state vector from theFSM lattice30, another FSM lattice30 (e.g., via the IR bus and process buffer interface136), the de-compressor138, and the statevector cache memory142. As another example, the statevector memory buffer144 may be used to provide state vector data to the IR bus and process buffer interface136 (e.g., for other FSM lattices30), the compressor140, and the statevector cache memory142.

Likewise, the state vectorintermediate input buffer146 may be used to receive state vector data from any suitable device and to provide state vector data to any suitable device. For example, the state vectorintermediate input buffer146 may be used to receive a state vector from an FSM lattice30 (e.g., via the IR bus and process buffer interface136), the de-compressor138, and the statevector cache memory142. As another example, the state vectorintermediate input buffer146 may be used to provide a state vector to theFSM lattice30. Furthermore, the state vector intermediate output buffer148 may be used to receive a state vector from any suitable device and to provide a state vector to any suitable device. For example, the state vector intermediate output buffer148 may be used to receive a state vector from theFSM lattice30 and the statevector cache memory142. As another example, the state vector intermediate output buffer148 may be used to provide a state vector to an FSM lattice30 (e.g., via the IR bus and process buffer interface136) and the compressor140.

Once a result of interest is produced by theFSM lattice30, an event vector may be stored in an event vector memory150, whereby, for example, the event vector indicates at least one search result (e.g., detection of a pattern of interest). The event vector can then be sent to anevent buffer152 for transmission over thebus interface130 to theprocessor12, for example. As previously described, the results may be compressed. The event vector memory150 may include two memory elements, memory element A and memory element B, each of which contains the results obtained by processing the input data in the corresponding input buffers132 (e.g., input buffer A and input buffer B). In one embodiment, each of the memory elements may be DRAM memory elements or any other suitable storage devices. In some embodiments, the memory elements may operate as initial buffers to buffer the event vectors received from theFSM lattice30, alongresults bus151. For example, memory element A may receive event vectors, generated by processing the input data from input buffer A, alongresults bus151 from theFSM lattice30. Similarly, memory element B may receive event vectors, generated by processing the input data from input buffer B, alongresults bus151 from theFSM lattice30.

In one embodiment, the event vectors provided to the event vector memory150 may indicate that a final result has been found by theFSM lattice30. For example, the event vectors may indicate that an entire pattern has been detected. Alternatively, the event vectors provided to the event vector memory150 may indicate, for example, that a particular state of theFSM lattice30 has been reached. For example, the event vectors provided to the event vector memory150 may indicate that one state (i.e., one portion of a pattern search) has been reached, so that a next state may be initiated. In this way, the event vector memory150 may store a variety of types of results.

In some embodiments, IR bus andprocess buffer interface136 may provide data tomultiple FSM lattices30 for analysis. This data may be time multiplexed. For example, if there are eightFSM lattices30, data for each of the eightFSM lattices30 may be provided to all of eight IR bus and process buffer interfaces136 that correspond to the eightFSM lattices30. Each of the eight IR bus and process buffer interfaces136 may receive an entire data set to be analyzed. Each of the eight IR bus and process buffer interfaces136 may then select portions of the entire data set relevant to theFSM lattice30 associated with the respective IR bus andprocess buffer interface136. This relevant data for each of the eightFSM lattices30 may then be provided from the respective IR bus and process buffer interfaces136 to therespective FSM lattice30 associated therewith.

The event vector memory150 may operate to correlate each received result with a data input that generated the result. To accomplish this, a respective result indicator may be stored corresponding to, and in some embodiments, in conjunction with, each event vector received from theresults bus151. In one embodiment, the result indicators may be a single bit flag. In another embodiment, the result indicators may be a multiple bit flag. If the result indicators may include a multiple bit flag, the bit positions of the flag may indicate, for example, a count of the position of the input data stream that corresponds to the event vector, the lattice that the event vectors correspond to, a position in set of event vectors, or other identifying information. These results indicators may include one or more bits that identify each particular event vector and allow for proper grouping and transmission of event vectors, for example, to compressor140. Moreover, the ability to identify particular event vectors by their respective results indicators may allow for selective output of desired event vectors from the event vector memory150. For example, only particular event vectors generated by theFSM lattice30 may be selectively latched as an output. These result indicators may allow for proper grouping and provision of results, for example, to compressor140. Moreover, the ability to identify particular event vectors by their respective result indicators allow for selective output of desired event vectors from the event vector memory150. Thus, only particular event vectors provided by theFSM lattice30 may be selectively provided to compressor140.

Additional registers and buffers may be provided in thestate machine engine14, as well. In one embodiment, for example, a buffer may store information related to more than one process whereas a register may store information related to a single process. For instance, thestate machine engine14 may include control and status registers154. In addition, a program buffer system (e.g., restore buffers156) may be provided for initializing theFSM lattice30. For example, initial (e.g., starting) state vector data may be provided from the program buffer system to the FSM lattice30 (e.g., via the de-compressor138). The de-compressor138 may be used to decompress configuration data (e.g., state vector data, routing switch data,STE34,36 states, Boolean function data, counter data, match MUX data) provided to program theFSM lattice30.

Similarly, a repair map buffer system (e.g., save buffers158) may also be provided for storage of data (e.g., save maps) for setup and usage. The data stored by the repair map buffer system may include data that corresponds to repaired hardware elements, such as data identifying whichSTEs34,36 were repaired. The repair map buffer system may receive data via any suitable manner. For example, data may be provided from a “fuse map” memory, which provides the mapping of repairs done on a device during final manufacturing testing, to the save buffers158. As another example, the repair map buffer system may include data used to modify (e.g., customize) a standard programming file so that the standard programming file may operate in aFSM lattice30 with a repaired architecture (e.g.,bad STEs34,36 in aFSM lattice30 may be bypassed so they are not used). The compressor140 may be used to compress data provided to the savebuffers158 from the fuse map memory. As illustrated, thebus interface130 may be used to provide data to the restorebuffers156 and to provide data from the save buffers158. As will be appreciated, the data provided to the restorebuffers156 and/or provided from the save buffers158 may be compressed. In some embodiments, data is provided to thebus interface130 and/or received from thebus interface130 via a device external to the state machine engine14 (e.g., theprocessor12, thememory16, thecompiler20, and so forth). The device external to thestate machine engine14 may be configured to receive data provided from the save buffers158, to store the data, to analyze the data, to modify the data, and/or to provide new or modified data to the restore buffers156.

Thestate machine engine14 includes a lattice programming andinstruction control system159 used to configure (e.g., program) theFSM lattice30 as well as provide inserted instructions, as will be described in greater detail below. As illustrated, the lattice programming andinstruction control system159 may receive data (e.g., configuration instructions) from theinstruction buffer133. Furthermore, the lattice programming andinstruction control system159 may receive data (e.g., configuration data) from the restore buffers156. The lattice programming andinstruction control system159 may use the configuration instructions and the configuration data to configure the FSM lattice30 (e.g., to configure routing switches,STEs34,36, Boolean cells, counters, match MUX) and may use the inserted instructions to correct errors during the operation of thestate machine engine14. The lattice programming andinstruction control system159 may also use the de-compressor138 to de-compress data and the compressor140 to compress data (e.g., for data exchanged with the restore buffers156 and the save buffers158).

Thestate machine engine14 includes a lattice programming andinstruction control system159 used to configure (e.g., program) theFSM lattice30 as well as provide inserted instructions, as will be described in greater detail below. As illustrated, the lattice programming andinstruction control system159 may receive data (e.g., configuration instructions) from theinstruction buffer133. Furthermore, the lattice programming andinstruction control system159 may receive data (e.g., configuration data) from the restore buffers156. The lattice programming andinstruction control system159 may use the configuration instructions and the configuration data to configure the FSM lattice30 (e.g., to configure routing switches,STEs34,36, Boolean cells, counters, match MUX) and may use the inserted instructions to correct errors during the operation of thestate machine engine14. The lattice programming andinstruction control system159 may also use the de-compressor138 to de-compress data and the compressor140 to compress data (e.g., for data exchanged with the restore buffers156 and the save buffers158).

In some embodiments, thestate machine engine14 may be utilized to solve particular classes of problems. One such class of problems includes traversal of a graph. For example, thestate machine engine14 may be utilized, such that an arbitrary directed or non-directed graph can be represented within thestate machine engine14. A host (e.g.,processor12 or a separate device), in conjunction with thestate machine engine14, can then perform a series of query/response operations that cause the graph to be traversed. In this manner, thestate machine engine14 may be utilized to provide analysis of the graph and supply results thereof to the host (e.g., processor12) to allow the host (e.g., processor12) to discover and/or to be informed of, for example, the shortest path from any arbitrary node in the graph to any other node in the graph (if a path exists).

Thestate machine engine14 is a pattern matching engine that may be an automata processor. Automatons (e.g., taken together to be an automata network that may be implemented as part of thestate machine engine14 and, more particularly, the FSM lattice30) that are believed to be particularly useful in solving graphs are now presented. Graphs can be used to model types of relations and processes in physical, biological, social, and information systems such that many practical problems can be represented by graphs. A graph may be a representation of a set of objects in which a node (vertex) is a fundamental unit of which the graph is formed. The graph may also include one or more edges, whereby each edge has two (or in hypergraphs, more) nodes to which it is attached, called its endpoints. The edges may be directed or undirected. In an undirected graph, an edge may be represented as the set of its nodes, and in a directed graph it may be represented as an ordered pair of its nodes. An edge that connects nodes “x” and “y” is sometimes written “xy.” The graph may be an undirected graph in which edges have no orientation (e.g., an edge [x, y] is identical the edge [y, x]) or a directed graph in which the edges have orientations and is written as an ordered pair where the graph=(V, A), with “V” being a set of nodes and “A” being a set of ordered pairs of nodes called arrows, directed edges, directed arcs, or directed lines. A graph may be illustrated whereby a node is represented by a circle with a label, and an edge is represented by a line or arrow extending from one node to another.

As noted above, automatons (e.g., automata networks that may be implemented as part of thestate machine engine14 and, more particularly, the FSM lattice30) can be used in solving graphs, for example, thestate machine engine14 can be utilized to represent graph edges as patterns within thestate machine engine14. Each graph edge representation is embodied within an automaton (e.g., one or moreparticular STEs34,36) specific to that edge. The host (e.g., processor12) delivers a list of nodes as a query string to the programmedstate machine engine14 for analysis. Each automaton within thestate machine engine14 evaluates whether or not it contains an edge that originates on one of the nodes in the query string. If an automaton does match this condition, that automaton will report the destination node of the edge it represents. Thus, the host (e.g., processor12) can start at any arbitrary node (the origin), and it can determine via thestate machine engine14 what nodes can be reached from the origin node. A list of nodes that can be reached from the set of query nodes (e.g., an origin node and/or additionally provided nodes) is returned by thestate machine engine14 to the host (e.g., processor12). The host (e.g., processor12) can utilize the set of one-hop reachable nodes and deliver that set of nodes as a new query to thestate machine engine14 for analysis. Thestate machine engine14 can respond by reporting the set of nodes reachable from the one-hop reachable nodes as representative of the two-hop reachable nodes. This process may be continued iteratively, with the host (e.g., processor12) discovering new nodes reachable at increasingly greater distances from the origin node. Eventually the host (e.g., processor12) will find within the result set the target destination node (at which point processing stops) or thestate machine engine14 returns an empty result set (indicating the target node is not reachable from the origin node). If the target node is discovered during this iterative process, the host (e.g., processor12) has determined (1) the target node is reachable from the origin node and (2) the distance from the origin node to the target node. Additionally, logging, tracking, and/or similar techniques via the host (e.g., processor12) and/or thestate machine engine14 may be utilized to discover that path from the origin node to the target node.

In some embodiments, thestate machine engine14 may be configured (e.g., programmed) via thecompiler20 for each edge and each node of a particular graph to be solved. For example, one ormore STEs34,36 may be programmed to each represent a node to be evaluated while an edge may be programmed as a hardware connection (e.g., one or more interblock switching elements40,intra-block switching elements42,intra-row switching elements44, and/or anintra-group circuitry37 coupled to therespective STE34,36). However, direct implementation of an entirety of a graph in this manner (e.g., through direct assignment ofrespective STEs34,36, and their respective hardware connections to reproduce or mimic the graph to be solved) may exceed the size of thestate machine engine14 and/or lead to routing problems related to the hardware connections (e.g., the interconnection of one or more interblock switching elements40,intra-block switching elements42,intra-row switching elements44, and/or anintra-group circuitry37 coupled to therespective STEs34,36). Accordingly, alternate techniques for utilization of thestate machine engine14 to solve a particular graph may be undertaken.

FIG.10 illustrates a representation of agraph160 to be solved to determine one or more of a shortest path between two nodes (e.g., a shortest path problem), a longest path between two nodes, a travelling salesman problem, travel through the graph between two points with no node repetition, ability to traverse the graph between two points, and the like. As illustrated, thegraph160 includesnodes162,164,166,168,170,171,174,176,178, and180. Additionally, thegraph160 includesedges182,184,186,188,190,192,194,196,198,200,202,204, and206. One problem to be solved forgraph160 may be, for example, can traversal betweennode166 “C” andnode174 “G” be accomplished? A second problem (as a subset of the first problem to be solved) may be described as finding the shortest path betweennode166 “C” andnode174 “G” that is available. Thegraph160 may be represented as an edge list, as set forth below:

• • A→B
  • A→C
  • B→I
  • C→B
  • C→D
  • D→F
  • E→B
  • E→G
  • E→H
  • F→J
  • H→J
  • I→E
  • J→I

This edge list may represent a graph as just a list, or array, of edges. To represent an edge, the two nodes that correspond to the nodes that the edges are incident on are set forth as objects. In the present example, no weight factors are present, however, in situations where the edges have weights, a third element may be added to the array or more information may be added to the objects, giving weight to the edge.

The use of an edge list, or a modified version thereof, may be helpful in representing potential solutions for the traversal of thegraph160. For example, there are two solutions for traversal of thegraph160 betweennode166 “C” andnode174 “G.” These solutions are illustrated inFIG.11 as a solution diagram208. As illustrated, the solution diagram208 includes afirst level210, asecond level212, athird level214, a fourth level216 afifth level218, and a sixthsecond level220. Each of thelevels210,212,214,216,218, and220 (or hops) may represent all transitions from a node (e.g., node166) to all associated nodes (e.g.,node164 or node168) coupled thereto along respective edges (e.g.,edge204 or edge186). In this manner, each of thelevels210,212,214,216,218, and220 may represent an event. That is, one ormore STEs34,36 of the one ormore FSM lattices30 of thestate machine engine14 may be programmed to correspond to a node that can be reached from a given node based on the analysis of an input character. This analysis generates a report (e.g., outputs a signal indicating whether the input character was matched in the respective node), that is, when the stored value (e.g., character) of a node matches the input data, an event is generated to be reported. In this manner, all nodes in the graph can be evaluated and a solution of whether the graph problem can be solved and, if so, how many levels (hops) required to solve the graph can be determined.

As illustrated inFIG.11, the solution diagram208 includes afirst solution path222 and asecond solution path224.Node166 “C” has two edges,204 and186 that connectnode166 “C” to each ofnode164 “B” andnode168 “D,” respectively, as the first level210 (e.g., a first hop fromoriginal node166 “C”). Repeating the traversal process from thenodes164 “B” and168 “D” of thefirst level210,node164 “B” has asingle edge192 tonode178 “I,” whilenode168 “D” has asingle edge188 tonode172 “F.” This portion of the traversal process represents the second level212 (e.g., a second hop fromoriginal node166 “C”). Continuing the traversal of thegraph160 from thesecond level212, thenode178 “I” has asingle edge196 tonode170 “E,” whilenode172 “F” has asingle edge188 tonode190 “J.” This portion of the traversal process represents the third level214 (e.g., a third hop fromoriginal node166 “C”).

From thethird level214, there exists threeedges206,198, and200 tonode164 “B,”node174 “G,” andnode176 “H,” respectively. Likewise, there exits oneedge194 fromnode190 “J” tonode178 “I.” In combination, these represent the fourth level216 (e.g., a fourth hop fromoriginal node166 “C”). With respect to thefirst solution path222, traversal of thegraph160 fromoriginal node166 “C” tonode174 “G” is complete at thefourth level216. Accordingly, a solution (e.g., the first solution path222) for the problem of graph traversal fromnode166 “C” tonode174 “G” has been found and it includes afourth level216 of traversals (e.g., four hops) to traverse thegraph160 fromnode166 “C” tonode174 “G.” In some embodiments, the process may be halted, as the optimum (shortest path solution) has been found as thefirst solution path222. However, in other embodiments, additional traversal of thegraph160 may be continued along thesecond solution path224 to identify any additional solutions of the problem being analyzed.

From thefourth level216, oneedge196 fromnode178 “I” tonode170 “E.” This portion of the traversal process represents the fifth level218 (e.g., a fifth hop fromoriginal node166 “C”). From thefifth level218, there exists threeedges206,198, and200 tonode164 “B,”node174 “G,” andnode176 “H,” respectively, as the sixth level220 (e.g., a sixth hop fromoriginal node166 “C”). With respect to thesecond solution path224, traversal of thegraph160 fromoriginal node166 “C” tonode174 “G” is complete at thesixth level216. Accordingly, a second solution (e.g., the second solution path224) for the problem of graph traversal fromnode166 “C” tonode174 “G” has been found and it includes asixth level220 of traversals (e.g., six hops) to traverse thegraph160 fromnode166 “C” tonode174 “G.” As no other solutions to traversal of the graph160 (without crossing thesame edge182,184,186,188,190,192,194,196,198,200,202,204, and206 twice) exist, the analysis the example problem for traversal of thegraph160 is complete. Two solutions (e.g., thefirst solution path222 and the second solution path224) have been discovered and their respective levels (e.g., thefourth level216 and the sixth level220) may be associated with the respective solutions. Likewise, as previously discussed, once a single solution (e.g., the first solution path222) has been discovered (as well as its level, e.g., the fourth level216), the analysis of thegraph160 may be complete, for example, if only the optimal (e.g., shortest path) solution is desired. Examples of the use of thestate machine engine14 to perform the analysis describes above (or similar graph problem solving) will be discussed in detail below.

As previously noted, thestate machine engine14 may be configured (e.g., programmed) via thecompiler20 for each edge (e.g., edges182,184,186,188,190,192,194,196,198,200,202,204, and206) and each node (e.g.,nodes162,164,166,168,170,171,174,176,178, and180) of a particular graph (e.g., graph160) to be solved. For example, for example a given graph problem to be solved may be reduced to an edge list with pairs of nodes. The input data to the state machine engine14 (e.g., provided to one ormore FSM lattices30 via respective input blocks52) may be provided such that given a particular node, a report (e.g., output a signal indicating whether one or more conditions of are detected) can be generated when any the variable of that node matches the input data. Additionally, a node may be programmed (e.g., represented) in thestate machine engine14 asindividual STEs34,36, whereby eachprogrammed STE34,36 corresponds to a particular edge of the node.

Examples of automatons (e.g., as part of an automata network that may be implemented as part of thestate machine engine14 and, more particularly, the FSM lattice30) that are believed to be particularly useful in solving graph problems are now presented. For example, the automaton (e.g., one or moreparticular STEs34,36) corresponding to a portion of a graph may recognize an input character and transmit a report of a match of that character via the automaton.

A corresponding example of two such automatons (e.g.,respective STEs34,36) that may be used to analyze data with respect to afirst node162 “A” ofgraph160 are illustrated inFIG.12.STE symbol226 andSTE symbol228 ofFIG.12 may each represent a single STE (e.g., one of arespective STE34,36) to analyze an input data stream and report any results (e.g., when the input data of the input data stream matches the setting of therespective STE34,36, thus generating an event to be reported).STE symbols226 and228 may be generated in conjunction with, for example, the Micron Automata Processor Workbench tool. As illustrated,STE symbol226 may include a start indicator230 (e.g., “∞” as an all-input attribute) that indicates that the STE represented bySTE symbol226 is active on all input symbol cycles. Similarly,STE symbol228 also includes a start indicator232 (e.g., “∞” as an all-input attribute).STE symbol226 includes a symbol set234 of “AAB” andSTE symbol228 includes a symbol set236 of “AAc”, whereby the symbol sets234 and236 are a programmed symbol set of the STE represented bySTE symbols226 and228 to be compared against a current input symbol (e.g., the input data) of the input data stream. Anactive STE34,36 will respond to the current input symbol and if the input symbol matches the programmed symbol set of theSTE34,36, theSTE34,36 will generate an output (e.g., an activate-on-match that activates anySTEs34,36 to which it is connected, possibly including itself or a report-on-match to generate a report of the event).

Accordingly, the STE represented bySTE symbol226 is activated by any input data symbol (based onstart indicator230 being an all-input attribute). If the input data symbol (e.g., current input symbol) to the STE represented bySTE symbol226 is the character “A,” the input data symbol operates as a match to the symbol set234 of the STE represented bySTE symbol226 as an event, at which time the STE represented by STE symbol226 (which has a “AAB” as a symbol set234), will generate a report (indicated by report indicator238) that an event was generated in conjunction with the respective portion of the input data stream being analyzed by the STE represented bySTE symbol226. This report that is generated corresponds to edge182, since the “AAB” as asymbol set234 corresponds to theedge182 betweennode162 “A” andnode164 “B.”

Likewise, the STE represented bySTE symbol228 is activated by any input data symbol (based onstart indicator232 being an all-input attribute). If the input data symbol (e.g., current input symbol) to the STE represented bySTE symbol228 is the character “A,” the input data symbol operates as a match to the symbol set236 of the STE represented bySTE symbol228 as an event, at which time the STE represented by STE symbol228 (which has a “AAc” as a symbol set236), will generate a report (indicated by report indicator240) that an event was generated in conjunction with the respective portion of the input data stream being analyzed by the STE represented bySTE symbol228. This report that is generated corresponds to edge184, since the “AAc” as asymbol set236 corresponds to theedge184 betweennode162 “A” andnode166 “C.”

Each of the reports generated may be transmitted to the host (e.g., processor12), which may identify the respective result as corresponding to the respective edge and node being reported. For example, upon receipt of a result from the STE symbol represented bySTE symbol226 as an event, the host (e.g., processor12) may associate the received result withgraph160 traversal fromnode162 “A” tonode164 “B.” Similarly, upon receipt of a result from the STE represented bySTE symbol228 as an event, the host (e.g., processor12) may associate the received result withgraph160 traversal fromnode162 “A” tonode166 “C.” Thus, host (e.g., processor12) may transmit a data input data symbol (e.g., a character) to be analyzed by one or more automata networks, which may be implemented as part of thestate machine engine14 and, more particularly, theFSM lattice30 via programmed automatons (e.g., one or moreparticular STEs34,36). The input data can be analyzed by the automatons and if the input data matches the respective symbol set of anSTE34,36, thatSTE34,36 can transmit a result as an indication of an event to the host (e.g., processor12).

Each received result from the automatons of the automata network (e.g., the state machine engine14) can be categorized as corresponding to a particular edge having a particular level. These categorizations can be tracked and/or stored (e.g., stored in memory16). Categorizations of the results by the host (e.g., processor12) can also be used to initiate subsequent transmissions of one or more input data symbols to be analyzed, whereby the input data symbols transmitted correspond to the categorized received results. For example, upon receipt of results from the STEs represented bySTE symbols226 and228, the host (e.g., processor12) may identify the respective received results as reporting of the characters “B” and “C,” which become the next characters to be input as a data stream to thestate machine engine14 for analysis. It may be appreciated that when more than one character is to be sent to thestate machine engine14 for analysis, the respective characters may be sent together as batched input data. Likewise, when more than one result is to be sent from thestate machine engine14, the results may be sent together as batched results.

An example graphical representation of the above noted process undertaken by the host (e.g., processor12) to utilize thestate machine engine14 to solve a graph problem, for example, graph traversal ofgraph160 betweennode166 “C” andnode174 “G” discussed above with respect toFIGS.10 and11, is set forth below in Table 1:

	TABLE 1
		Automata Network
	Host Transmits	Report Categorization	Level Classification
	“C”	“B” and “D”	Level 1
	“B” and “D”	“I” and “F”	Level 2
	“I” and “F”	“E” and “J”	Level 3
	“E” and “J”	(“B” and “G” and “H”)	Level 4
		and “J”

Thus, as illustrated in Table 1, the host (e.g., processor12) operates to effectively transform (e.g., convert) a graph problem to be solved into discrete segments to be analyzed (e.g., processed) by thestate machine engine14. Through iterative solving of the discrete segments (e.g., traversal from one node to another of a node pair connected by a respective edge) and through tracking, categorization, and application of those solutions (e.g., events reported as results), the host (e.g., processor12) can undertake solving of a problem associated with a graph using thestate machine engine14.

It may be appreciated that a graph problem to be solved may be complex and, thus, involve a large number of node pairs to be analyzed. Accordingly, techniques may be applied to allow for the solving of large and/or complex graph problems. For example,FIG.13 illustrates an automaton that may includeSTE symbols242,244,246,248,250, and252 that may each represent an STE (e.g.,respective STEs34,36). TheSTE symbols242,244, and246 each include, respectively, asymbol set254,256, and258 of “*” representative of a “don't care” character (e.g., an event will be generated by any input character). TheSTE symbols248,250, and252 each include, respectively, asymbol set260,262, and264 of “I_d1,” “I_d2,” and “Id₃” representative of a multi-character node (e.g., a three character node). Additionally,STE symbols242 and248 include arespective start indicator266 and268 (e.g., “1” as a start input attribute) that indicates that the STEs represented bySTE symbols242 and248 are active when a first input cycle (e.g., a first data input) is transmitted from the host (e.g., processor12) to thestate machine engine14. Finally, the STE represented bySTE symbol252 is able to generate a report (indicated by report indicator270) that an event was generated in conjunction with the respective portion of the input data stream being analyzed by the STEs represented bySTE symbols248,250, and252 (comprising a multi-character node match).

It may be understood that the operation of automaton ofFIG.13 may be representative of the operation and interconnectivity of the underlying respective STEs that correspond to STEsymbols242,244,246,248,250, and252. As illustrated,STE symbols242 and248 may include startindicators266 and268 that indicate that the STEs represented bySTE symbols242 and248 are active in response to a first data input.STE symbol242 includes a symbol set254 of “*,” whereby the symbol set254 is a programmed symbol set of the STE represented bySTE symbol242 to be compared against a current input symbol (e.g., the input data) of the input data stream. Anactive STE34,36 will respond to the current input symbol and if the input symbol matches the programmed symbol set of theSTE34,36, whereby theSTE34,36 will generate an output (e.g., an activate-on-match that activates anySTEs34,36 to which it is connected, possibly including itself or a report-on-match to generate a report of the event).

The STE represented bySTE symbol242 may correspond to a first character of a multi-character node (e.g., a three character node). Accordingly, a first character input as part of the input data transmitted to the STE represented bySTE symbol242 may be compared as the current input symbol against the “*” of symbol set254 (due to thestart indicator266 that indicates that the STE represented bySTE symbol242 is active in response to a first data input). As any character will match with the “*” of symbol set254, thus generating an event, the STE represented bySTE symbol242 may activate the respective STE represented bySTE symbol244 as an activate-on-match response. The transition272 emanating fromSTE symbol242 indicates theSTE symbol244 and its underlying STE that will be activated for processing the next character when the source STE (e.g., the STE represented by STE symbol242) matches the current input symbol (e.g., the first character of the input data stream) with the symbol set (e.g., symbol set254) of the source STE (e.g., the STE represented by STE symbol242).

The STE represented bySTE symbol244 may correspond to a second character of a multi-character node (e.g., a three character node). Accordingly, a second character input as part of the input data transmitted to the STE represented bySTE symbol244 may be compared as the current input symbol against the “*” of symbol set256 (due to activation of the STE represented by theSTE symbol244 being activated along transition272). As any character will match with the “*” of symbol set256, thus generating an event, the STE represented bySTE symbol244 may activate the respective STE represented by STE symbol246 as an activate-on-match response. Thetransition274 emanating fromSTE symbol244 indicates the STE symbol246 and its underlying STE that will be activated for processing the next character when the source STE (e.g., the STE represented by STE symbol244) matches the current input symbol (e.g., the second character of the input data stream) with the symbol set (e.g., symbol set256) of the source STE (e.g., the STE represented by STE symbol244).

The STE represented by STE symbol246 may correspond to a third character of a multi-character node (e.g., a three character node). Accordingly, a third character input as part of the input data transmitted to the STE represented by STE symbol246 may be compared as the current input symbol against the “*” of symbol set258 (due to activation of the STE represented by the STE symbol246 being activated along transition274). As any character will match with the “*” of symbol set258, thus generating an event, the STE represented by STE symbol246 may activate the respective STEs represented bySTE symbols242 and248 as an activate-on-match response. Thetransitions276 and278 emanating from STE symbol246 indicate theSTE symbols242 and248 and their underlying STEs that will be activated for processing the next character when the source STE (e.g., the STE represented by STE symbol246) matches the current input symbol (e.g., the third character of the input data stream) with the symbol set (e.g., symbol set258) of the source STE (e.g., the STE represented by STE symbol246).

Thus, the STE represented bySTE symbol242 will be activated to analyze a fourth character of an input data stream (e.g., a first character of a second multi-character node). Moreover, the process of comparisons and activations of subsequent STEs alongtransitions272,274, and276 by the STEs represented bySTE symbols242,244, and246 can be repeated for the second multi-character node (as well as additional multi-character nodes) in a manner similar to that described above.

Additionally, the STE represented bySTE symbol248 may correspond to a first character of a multi-character node (e.g., a three character node). Accordingly, a first character input as part of the input data transmitted to the STE represented bySTE symbol248 may be compared as the current input symbol against the “Id₁” of symbol set260 (due to thestart indicator268 that indicates that the STE represented bySTE symbol248 is active in response to a first data input). If the first character input does not match the character stored as the “Id₁” of symbol set260, no additional processing of a second character of the multi-character node will occur (e.g., the STE represented bySTE symbol250 will not be activated). However, if the first character input matches the character stored as the “Id₁” of symbol set260, thus generating an event, the STE represented bySTE symbol248 may activate the respective STE represented bySTE symbol250 as an activate-on-match response. Thetransition280 emanating fromSTE symbol248 indicates theSTE symbol250 and its underlying STE that will be activated for processing the next character when the source STE (e.g., the STE represented by STE symbol248) matches the current input symbol (e.g., the first character of the input data stream) with the symbol set (e.g., symbol set260) of the source STE (e.g., the STE represented by STE symbol248).

The STE represented bySTE symbol250 may correspond to a second character of a multi-character node (e.g., a three character node). Accordingly, a second character input as part of the input data transmitted to the STE represented bySTE symbol250 may be compared as the current input symbol against the “Id₂” of symbol set262 (due to activation of the STE represented by theSTE symbol250 being activated along transition280). If the second character input does not match the character stored as the “Id₂” of symbol set262, no additional processing of a third character of the multi-character node will occur (e.g., the STE represented bySTE symbol252 will not be activated). However, if the second character input matches the character stored as the “Id₂” of symbol set262, thus generating an event, the STE represented bySTE symbol250 may activate the respective STE represented bySTE symbol252 as an activate-on-match response. Thetransition282 emanating fromSTE symbol250 indicates theSTE symbol252 and its underlying STE that will be activated for processing the next character when the source STE (e.g., the STE represented by STE symbol250) matches the current input symbol (e.g., the second character of the input data stream) with the symbol set (e.g., symbol set262) of the source STE (e.g., the STE represented by STE symbol250).

The STE represented bySTE symbol252 may correspond to a third character of a multi-character node (e.g., a three character node). Accordingly, a third character input as part of the input data transmitted to the STE represented bySTE symbol252 may be compared as the current input symbol against the “Id₃” of symbol set264 (due to activation of the STE represented by theSTE symbol252 being activated along transition282). If the third character input does not match the character stored as the “Id₃” of symbol set264, no reporting of an event (e.g., result) will occur. However, if the third character input matches the character stored as the “Id₃” of symbol set264, thus generating an event, the STE represented bySTE symbol252 may generate a report (indicated by report indicator270) that an event was generated in conjunction with the respective portion of the input data stream being analyzed by the STEs represented bySTE symbols248,250, and252 (comprising a multi-character node match).

Thus, if the first three characters of an input data stream generate an event, the reporting of the event can cease processing in the automaton and the event (e.g., result) may be transmitted to the host (e.g., processor12) for characterization and level classification (in a manner similar to that outlined above in conjunction with Table 1). Moreover, since transition278 emanating from STE symbol246 operates to activate a match of when the source STE (e.g., the STE represented by STE symbol246) matches the current input symbol (e.g., the third character of the input data stream) with the symbol set (e.g., symbol set258) of the source STE (e.g., the STE represented by STE symbol246), the STE represented bySTE symbol248 will also be activated to analyze a fourth character of an input data stream (e.g., a first character of a second multi-character node). Moreover, the process of comparisons and activations of subsequent STEs alongtransitions280 and282 by the STEs represented bySTE symbols248 and250 can be repeated for the second multi-character node (as well as additional multi-character nodes) in a manner similar to that described above. Likewise, the process of reporting an event (e.g., a result) by the STE represented bySTE symbol252 may also be repeated for the second multi-character node (as well as additional multi-character nodes) in a manner similar to that described above.

In this manner, the automaton ofFIG.13 is able to analyze multi-character nodes. Likewise, the automaton ofFIG.13 can identify multi-character nodes at the start of an input data stream as well as subsequent to the transmission of characters representative of a first multi-character node. It should be noted that the automaton ofFIG.13 analyzes multi-character nodes having three characters therein. However, the same techniques applied to the automaton inFIG.13 can be applied to multi-character nodes having two characters, four characters, or more characters. Additionally, other automatons may be used in conjunction with or separate from the automaton ofFIG.13.

For example, the automaton ofFIG.14 may search input data that includes a control character (e.g., a designated start symbol) used indicate that transmission of multi-character nodes are starting. The automaton ofFIG.14 includes STEsymbols284,286,288,290, and292 that may each represent an STE (e.g.,respective STEs34,36). TheSTE symbol284 includes a symbol set294 “!” representative of a designated start symbol. TheSTE symbols286,288,290, and292 each include, respectively, asymbol set296,298,300, and302 of “Id₁,” “Id₂,” “Id₃,” and “Id_N” representative of a multi-character node (e.g., an N-character node). Additionally, the STE represented bySTE symbol284 includes a start indicator304 (e.g., “∞” as an all-input attribute) while the STE represented bySTE symbol292 is able to generate a report (indicated by report indicator306) that an event was generated in conjunction with the respective portion of the input data stream being analyzed by the STEs represented bySTE symbols284,286,288,290, and292 (comprising an N-character node match). It may be understood that the operation of the automaton ofFIG.14 may be representative of the operation and interconnectivity of the underlying respective STEs that correspond to STEsymbols284,286,288,290, and292.

As illustrated, the STE represented bySTE symbol284 may correspond to a start of node STE. Moreover, each character input as part of the input data transmitted to the STE represented bySTE symbol284 may be compared as the current input symbol against the “!” of symbol set294 (due to thestart indicator304 that indicates that the STE represented bySTE symbol284 is active in response to all data inputs). If the first character input does not match the “!” of symbol set294 (e.g., the designated start symbol), no additional processing by the automaton will occur (e.g., the STE represented bySTE symbol286 will not be activated). However, if the first character input matches the “!” of symbol set294, thus generating an event, the STE represented bySTE symbol284 may activate the respective STE represented bySTE symbol286 as an activate-on-match response. Thetransition308 emanating fromSTE symbol284 indicates theSTE symbol286 and its underlying STE that will be activated for processing the next character when the source STE (e.g., the STE represented by STE symbol284) matches the current input symbol (e.g., the first character of the input data stream) with the symbol set (e.g., symbol set294) of the source STE (e.g., the STE represented by STE symbol284).

The STE represented bySTE symbol286 may correspond to a first character of a multi-character node (e.g., an N-character node). Accordingly, a first node character input as part of the input data transmitted to the STE represented bySTE symbol286 may be compared as the current input symbol against the “Id₁” of symbol set296. If the first node character input does not match the character stored as the “Id₁” of symbol set296, no additional processing of a second node character of the multi-character node will occur (e.g., the STE represented bySTE symbol288 will not be activated). However, if the first node character input matches the character stored as the “Id₁” of symbol set286, thus generating an event, the STE represented bySTE symbol286 may activate the respective STE represented bySTE symbol288 as an activate-on-match response. Thetransition310 emanating fromSTE symbol286 indicates theSTE symbol288 and its underlying STE that will be activated for processing the next character when the source STE (e.g., the STE represented by STE symbol286) matches the current input symbol (e.g., the first node character of the input data stream) with the symbol set (e.g., symbol set296) of the source STE (e.g., the STE represented by STE symbol286).

The STE represented bySTE symbol288 may correspond to a second character of a multi-character node (e.g., an N-character node). Accordingly, a second node character input as part of the input data transmitted to the STE represented bySTE symbol288 may be compared as the current input symbol against the “Id₂” of symbol set298 (due to activation of the STE represented by theSTE symbol288 being activated along transition310). If the second node character input does not match the character stored as the “Id₂” of symbol set298, no additional processing of a third node character of the multi-character node will occur (e.g., the STE represented bySTE symbol290 will not be activated). However, if the second node character input matches the character stored as the “Id₂” of symbol set298, thus generating an event, the STE represented bySTE symbol288 may activate the respective STE represented bySTE symbol290 as an activate-on-match response. Thetransition312 emanating fromSTE symbol288 indicates theSTE symbol290 and its underlying STE that will be activated for processing the next character when the source STE (e.g., the STE represented by STE symbol288) matches the current input symbol (e.g., the second node character of the input data stream) with the symbol set (e.g., symbol set298) of the source STE (e.g., the STE represented by STE symbol288).

The STE represented bySTE symbol290 may correspond to a third character of a multi-character node (e.g., an N-character node). Accordingly, a third node character input as part of the input data transmitted to the STE represented bySTE symbol290 may be compared as the current input symbol against the “Id₃” of symbol set300 (due to activation of the STE represented by theSTE symbol298 being activated along transition312). If the third node character input does not match the character stored as the “Id₃” of symbol set300, no additional processing of a fourth or additional node character of the multi-character node will occur (e.g., the STE represented bySTE symbol292 will not be activated). However, if the third node character input matches the character stored as the “Id₃” of symbol set300, thus generating an event, the STE represented bySTE symbol290 may activate the next respective STE (and the process may continue in a similar manner until the STE represented bySTE symbol292 is activated as an activate-on-match response). Thetransition314 indicates theSTE symbol292 and its underlying STE that will be activated for processing the Nth character when the source STEs (e.g., the STE represented bySTE symbol290 and any STEs thereafter prior to the STE represented by STE symbol292) matches the current input symbol (e.g., the respective node character of the input data stream) with the symbol set of the source STE.

Finally, the STE represented bySTE symbol292 may correspond to an Nth character of a multi-character node (e.g., an N-character node). Accordingly, a Nth character input as part of the input data transmitted to the STE represented bySTE symbol292 may be compared as the current input symbol against the “Id_N” of symbol set302 (due to activation of the STE represented by theSTE symbol292 being activated along transition314). If the Nth character input does not match the character stored as the “Id_N” of symbol set302, no reporting of an event (e.g., result) will occur. However, if the Nth character input matches the character stored as the “Id_N” of symbol set302, thus generating an event, the STE represented bySTE symbol292 may generate a report (indicated by report indicator306) that an event was generated in conjunction with the respective portion of the input data stream being analyzed by the STEs represented bySTE symbols284,286,288,290, (any additional STEs), and the STE represented by STE symbol292 (comprising a N-character node match).

Thus, if the N-characters following a control character (e.g., a designated start symbol) of an input data stream generate an event, the reporting of the event can cease processing in the automaton ofFIG.14 and the event (e.g., result) may be transmitted to the host (e.g., processor12) for characterization and level classification (in a manner similar to that outlined above in conjunction with Table 1). In some embodiments, the N-characters may be eight characters, chosen from a set of characters including capital letters (e.g., A-Z), lowercase letters (e.g., a-z), and numbers (e.g., 0-9). However, the number and type of characters chosen to represent the N-characters may differ from those described above.

It may be advantageous to transmit multiple edges during a single round or level to thestate machine engine14 for analysis. It may also be advantageous to report all results from respective automatons of thestate machine engine14 at the same time. Accordingly, instead of the STEs represented bySTE symbols234,236,264, and302 generating reports (indicated byreport indicators238,240,270, and306), each result to be indicated can operate to activate a STE represented bySTE symbol308 alongtransition310, as illustrated inFIG.15. The symbol set312 ofSTE symbol308 may include all characters being transmitted (e.g., all capital letters A-Z, lowercase letters a-z, and numbers 0-9). As long as one of these characters is present as a data input, the STE represented bySTE symbol308 will self activate, as illustrated bytransition312. In this manner, the STE represented bySTE symbol308 may operate as a holding STE that operates to “remember” if an automaton had a result transmitted to it. The STE represented bySTE symbol308 may also be utilized with an end of data character in the reporting of that generated result.

For example, as illustrated inFIG.16, a STE represented bySTE symbol316 may be representative of any of the STEs represented bySTE symbols234,236,264, and302. However, instead of transmitting a result viaresult indicator238,240,270, or306, the STE represented bySTE316 may transmit an activate signal to both the STE represented by STE symbol308 (along transmission310) and to the STE represented by STE symbol318 (along transition320). The STE represented bySTE symbol318 may include a symbol set322 of a “?,” which may correspond to an end of data character. Once this end of data character is received at the STE represented by STE symbol322 (having been activated viatransition320 or324), the STE represented by STE symbol318 (as indicated by report indicator326) may report that an event was generated in conjunction with the respective portion of the input data stream being analyzed (comprising either a single or an N-character node match). Through utilization of the automaton reporting illustrated inFIG.16, all automatons of thestate machine engine14 can report results simultaneously and/or in parallel (e.g., upon receipt of the end of data character at the respective automatons, since each of the automatons analyzes the input data simultaneously).

In some embodiments, a tangible, non-transitory computer-readable medium, such as a hard drive, memory, or the like (e.g.,memory16 orexternal storage18 of system10) may be provided and may store instructions executable by a processor of an electronic device (e.g., byprocessor12 of system10). These instructions may include instructions to represent an automaton configured to generate an event representative of a satisfaction of a portion of a problem of a graph to be solved. Examples of these automatons are illustrated inFIGS.10-16. However, it may be appreciated that these illustrated graphs are not exclusive and other graphs may be developed and implemented. The instructions may further include instructions to receive an input (e.g., a user input) and simulate operation of an automaton based on the input and/or instructions to generate an indication of a result of the simulation of the operation of the automaton. In this manner, a user (for example) may be able to interface with a visual graph when developing one or more automatons to be used in satisfaction of one or more portions of a graph problem to be solved.

While the various modifications and alternative forms are envisioned, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the embodiments are not intended to be limited to the particular forms disclosed. Rather, the embodiments are to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the following appended claims.

Claims (30)

What is claimed is:

1. A state machine engine, comprising:

a plurality of configurable elements programmed to correspond to a graph problem to be solved, wherein the graph problem to be solved comprises a determination of a shortest path from a plurality of paths corresponding to whether a target node as a first configurable element of the plurality of configurable elements is reachable from an origin node as a second configurable element of the plurality of configurable elements, wherein the shortest path between the origin node and the target node from the plurality of paths is determined upon determining that the target node is reachable from the origin node by:

(a) the state machine engine receiving a list of nodes as a query string from a processor, wherein the query string is at least a part of an input data stream transmitted to the state machine engine, wherein each node of the list of nodes corresponds to a respective character of a set of characters;

(b) each automaton comprising a portion of the plurality of configurable elements within the state machine engine evaluating whether or not it contains an edge that originates on one of the nodes in the query string;

(c) when an automaton does match this condition, reporting via the automaton a destination node of an edge it represents, wherein the destination node corresponds to a first character of the set of characters, to allow the processor to begin at any arbitrary node as the origin node to determine what nodes can be reached from the origin node;

(d) returning a list of nodes that can be reached from a set of query nodes as the origin node and/or additionally provided nodes from the state machine engine to the processor as destination nodes having a corresponding level associated with a maximum number of hops undertaken to reach the destinations nodes;

(e) utilizing a set of one-hop reachable nodes to deliver to the state machine engine as a new query for analysis;

(f) porting from the state machine engine a set of nodes reachable from the one-hop reachable nodes as representative of two-hop reachable nodes; and

(g) discovering new nodes reachable at increasingly greater distances from the origin node until the processor finds the target node within a result set or the state machine engine returns an empty result set indicating the target node is not reachable from the origin node; and

wherein, each configurable element of the plurality of configurable elements comprising a state transition element (STE) comprising a memory cell programmed with configuration data to selectively set a state of the memory cell to a binary high value or a binary low value, wherein the STE is configured to analyze at least a portion of the input data stream based on the state of the memory cell and to output a result of the analysis as an event representative of a satisfaction of traversal of a portion of the graph problem to be solved based on the at least a portion of the input data stream, wherein the STE is configured to represent a node of a graph edge as the portion of the graph problem to be solved, wherein the STE evaluates the at least a portion of the input data stream to determine whether the node matches the at least a portion of the input data stream, wherein the STE is configured to report the node of the graph edge as the result of the analysis upon an occurrence of the node of the graph edge matching the at least a portion of the input data stream.

2. The state machine engine ofclaim 1, wherein the STE is configured to report the event representative of the satisfaction of traversal of the portion of the graph problem to be solved based on a match of the at least a portion of the input data stream with a stored value as the state of the memory cell.

3. The state machine engine ofclaim 1, wherein the STE is configured to report only one instance of the event representative of the satisfaction of traversal of the portion of the graph problem to be solved.

4. The state machine engine ofclaim 1, comprising a second STE, wherein the second STE comprises a second memory cell programmed with second configuration data to selectively set a state of the second memory cell to a binary high value or a binary low value, wherein the second STE is configured to analyze at least a second portion of the input data stream based on the state of the second memory cell and to output a second result of the analysis as an event representative of a satisfaction of a traversal of a second portion of the graph problem to be solved based on the second portion of the input data stream.

5. The state machine engine ofclaim 1, wherein the STE is configured to report the event representative of the satisfaction of traversal of the portion of the graph problem to be solved to a host device coupled to the state machine engine.

6. The state machine engine ofclaim 1, wherein the STE is configured to analyze the at least a portion of the input data stream to match a character present in the input data stream with a programmed value as the configuration data of the STE.

7. The state machine engine ofclaim 1, wherein at least one configurable element of the plurality of configurable elements is utilized in analysis of the input data stream until an end of data signal is received.

8. The state machine engine ofclaim 1, wherein the STE is configured to report the event when an end of data signal in the input data stream is received.

9. A device, comprising:

a processor when in operation transmits an input data stream to be analyzed by a plurality of configurable elements programmed to correspond to a graph problem to be solved, wherein the graph problem to be solved comprises a determination of a shortest path from a plurality of paths corresponding to whether a target node as a first configurable element of the plurality of configurable elements is reachable from an origin node as a second configurable element of the plurality of configurable elements, wherein the shortest path between the origin node and the target node from the plurality of paths is determined upon determining that the target node is reachable from the origin node by:

(a) a state machine engine comprising the plurality of configurable elements receiving a list of nodes as a query string from the processor, wherein the query string is at least a part of the input data stream transmitted to the state machine engine, wherein each node of the list of nodes corresponds to a character;

(b) each automaton comprising a portion of the plurality of configurable elements within the state machine engine evaluating whether or not it contains an edge that originates on one of the nodes in the query string;

(c) when an automaton does match this condition, reporting via the automaton a destination node of an edge it represents, wherein the destination node corresponds to a first character of a set of characters, to allow the processor to begin at any arbitrary node as the origin node to determine what nodes can be reached from the origin node;

(d) returning a list of nodes that can be reached from a set of query nodes as the origin node and/or additionally provided nodes from the state machine engine to the processor as destination nodes having a corresponding level associated with a maximum number of hops undertaken to reach the destinations nodes;

(e) utilizing a set of one-hop reachable nodes to deliver to the state machine engine as a new query for analysis;

(f) reporting from the state machine engine a set of nodes reachable from the one-hop reachable nodes as representative of two-hop reachable nodes; and

(g) discovering new nodes reachable at increasingly greater distances from the origin node until the processor finds the target node within a result set or the state machine engine returns an empty result set indicating the target node is not reachable from the origin node; and

wherein, each configurable element of the plurality of configurable elements comprising a state transition element (STE) comprising a memory element programmed with configuration data to selectively set a data state of the memory element as one of a high state and a low state, wherein the STE is configured to analyze at least a portion of the input data stream based on the data state of the memory element and to output a result of the analysis as an event, wherein the STE is configured to represent a node of a graph edge as the portion of the graph problem to be solved, wherein the STE evaluates the at least a portion of the input data stream to determine whether the node matches the at least a portion of the input data stream, wherein the STE is configured to report the node of the graph edge as the event upon an occurrence of the node matching the at least a portion of the input data stream, wherein the processor when in operation receives a report of the event representative of a satisfaction of traversal of a portion of a graph problem to be solved based on the at least a portion of the input data stream.

10. The device ofclaim 9, wherein the processor when in operation identifies the report as corresponding to a respective edge and a respective node of the graph problem to be solved.

11. The device ofclaim 10, wherein the processor when in operation transmits a second portion of the input data stream to be analyzed by a second STE based on the graph problem to be solved.

12. The device ofclaim 10, comprising a memory coupled to the processor, wherein the processor when in operation categorizes the report and stores the categorized report in the memory.

13. A device, comprising:

a state transition element (STE), wherein the STE comprises a memory element programmed with configuration data corresponding to programming a portion of a graph problem to be solved, wherein the graph problem to be solved comprises a determination of a shortest path from a plurality of paths corresponding to whether a target node as a first configurable element of a plurality of configurable elements is reachable from an origin node as a second configurable element of the plurality of configurable elements, wherein the shortest path between the origin node and the target node from the plurality of paths is determined upon determining that the target node is reachable from the origin node by:

(a) a state machine engine comprising the plurality of configurable elements receiving a list of nodes as a query string from a processor, wherein the query string is at least a part of an input data stream transmitted to the state machine engine, wherein each node of the list of nodes corresponds to a respective character of a set of characters;

(b) each automaton comprising a portion of the plurality of configurable elements within the state machine engine evaluating whether or not it contains an edge that originates on one of the nodes in the query string;

(c) when an automaton does match this condition, reporting via the automaton a destination node of an edge it represents, wherein the destination node corresponds to a first character of the set of characters, to allow the processor to begin at any arbitrary node as an origin node to determine what nodes can be reached from the origin node;

(d) returning a list of nodes that can be reached from a set of query nodes as the origin node and/or additionally provided nodes from the state machine engine to the processor as destination nodes having a corresponding level associated with a maximum number of hops undertaken to reach the destinations nodes;

(e) utilizing a set of one-hop reachable nodes to deliver to the state machine engine as a new query for analysis;

(f) reporting from the state machine engine a set of nodes reachable from the one-hop reachable nodes as representative of two-hop reachable nodes; and

(g) discovering new nodes reachable at increasingly greater distances from the origin node until the processor finds the target node within a result set or the state machine engine returns an empty result set indicating the target node is not reachable from the origin node; and

wherein the configuration data sets a data state of the memory element as one of a high state and a low state, wherein the STE is configured to analyze portions of the input data stream based on the data state of the memory element and to output a result of the analysis as and generate an indication of an event representative of satisfaction of traversal of a portion of the graph problem to be solved based on the portions of the input data stream, wherein the STE is configured to represent a node of a graph edge as the portion of the graph problem to be solved, wherein the STE evaluates the portions of the input data stream to determine whether the node matches the portions of the input data stream, wherein the STE is configured to report the node of the graph edge as the result of the analysis upon an occurrence of the node matching the portions of the input data stream.

14. The device ofclaim 13, comprising a second STE, wherein the second STE is configured to analyze second portions of the input data stream and generate an indication of a second event representative of satisfaction of traversal of a second portion of the graph problem to be solved.

15. The device ofclaim 14, wherein the STE and the second STE are configured to transmit the indication of the event and the indication of the second event, respectively, in parallel.

16. The device ofclaim 14, wherein the STE and the second STE are configured to transmit the indication of the event and the indication of the second event, respectively, in response to receipt of an end of data character at the STE and the second STE.

17. The device ofclaim 13, wherein the STE is configured to analyze the portions of the input data stream via comparison of a character present in the portions of the input data stream with a stored value as the data state in the STE.

18. The device ofclaim 17, wherein the STE is configured to generate the indication of the event based on the comparison of the character present in the portions of the input data stream with the stored value as the data state in the STE.

19. The device ofclaim 17, wherein the STE comprises a second STE, wherein the second STE is configured analyze the portions of the input data stream via comparison of a second character present in the portions of the input data stream with a stored value as a second data state in the second STE.

20. The device ofclaim 19, wherein the STE is configured to store a first portion of a node identification value of a node of the graph as the stored value in the STE.

21. The device ofclaim 20, wherein the second STE is configured to store a second portion of the node identification value of the node of the graph as the stored value in the second STE.

22. The device ofclaim 13, comprising a host processor coupled to the STE, wherein the host processor is configured to receive the indication of the event generated by the STE.

23. The device ofclaim 22, wherein the host processor is configured to generate a second data stream and transmit the second data stream to the STE for analysis.

24. The device ofclaim 23, wherein the host processor is configured to generate the second data stream based upon the indication of the event generated by the STE.

25. A device, comprising:

a memory configured to store instructions executable by the device, wherein the instructions comprise a compiler configured to a program a plurality of state transition elements (STEs) of a finite state machine lattice to correspond to a graph problem to be solved, wherein the graph problem to be solved comprises a determination of a shortest path from a plurality of paths corresponding to whether a target node as a first configurable element of a plurality of configurable elements is reachable from an origin node as a second configurable element of the plurality of configurable elements by:

(a) a state machine engine comprising the plurality of configurable elements receiving a list of nodes as a query string from a processor, wherein the query string is at least a part of an input data stream transmitted to the state machine engine, wherein each node of the list of nodes corresponds to a respective character of a set of characters;

(b) each automaton comprising a portion of the plurality of configurable elements within the state machine engine evaluating whether or not it contains an edge that originates on one of the nodes in the query string;

(c) when an automaton does match this condition, reporting via the automaton a destination node of an edge it represents, wherein the destination node corresponds to a first character of the set of characters, to allow the processor to begin at any arbitrary node as the origin node to determine what nodes can be reached from the origin node;

(d) returning a list of nodes that can be reached from a set of query nodes as the origin node and/or additionally provided nodes from the state machine engine to the processor as destination nodes having a corresponding level associated with a maximum number of hops undertaken to reach the destinations nodes;

(e) utilizing a set of one-hop reachable nodes to deliver to the state machine engine as a new query for analysis;

(f) reporting from the state machine engine a set of nodes reachable from the one-hop reachable nodes as representative of two-hop reachable nodes; and

(g) discovering new nodes reachable at increasingly greater distances from the origin node until the processor finds the target node within a result set or the state machine engine returns an empty result set indicating the target node is not reachable from the origin node; and

wherein the shortest path between the origin node and the target node from the plurality of paths is determined upon determining that the target node is reachable from the origin node, wherein each STE of the plurality of STEs is programmed with a respective stored value representative of an identification of a node of the graph problem to be solved for comparison against a character in the input data stream, wherein each STE of the plurality of STEs is configured to report the node as a result of an analysis of a portion of the graph problem to be solved upon an occurrence of the identification matching the character in the input data stream.

26. The device ofclaim 25, wherein the compiler is configured to program the finite state machine lattice by generating a binary image of high and low bits for storage in memory cells of the finite state machine lattice as the stored value.

27. The device ofclaim 26, where in the compiler is configured to reprogram the finite state machine lattice by generating a second binary image of high and low bits for storage in the memory cells of the finite state machine lattice as the stored value subsequent to generation of a match in the state machine lattice based on the comparison.

28. A tangible, non-transitory computer-readable medium configured to store instructions executable by a processor of an electronic device, wherein the instructions comprise instructions to represent a plurality of configurable elements programmed to correspond to a graph problem to be solved, wherein the graph problem to be solved comprises a determination of a shortest path from a plurality of paths corresponding to whether a target node as a first configurable element of the plurality of configurable elements is reachable from an origin node as a second configurable element of the plurality of configurable elements, wherein the shortest path between the origin node and the target node from the plurality of paths is determined upon determining that the target node is reachable from the origin node by:

(a) a state machine engine comprising the plurality of configurable elements receiving a list of nodes as a query string from the processor, wherein the query string is at least a part of an input data stream transmitted to the state machine engine, wherein each node of the list of nodes corresponds to a respective character of a set of characters;

(b) each automaton comprising a portion of the plurality of configurable elements within the state machine engine evaluating whether or not it contains an edge that originates on one of the nodes in the query string;

(c) when an automaton does match this condition, reporting via the automaton a destination node of an edge it represents, wherein the destination node corresponds to a first character of the set of characters, to allow the processor to begin at any arbitrary node as the origin node to determine what nodes can be reached from the origin node;

(d) returning a list of nodes that can be reached from a set of query nodes as the origin node and/or additionally provided nodes from the state machine engine to the processor as destination nodes having a corresponding level associated with a maximum number of hops undertaken to reach the destinations nodes;

(e) utilizing a set of one-hop reachable nodes to deliver to the state machine engine as a new query for analysis;

(f) reporting from the state machine engine a set of nodes reachable from the one-hop reachable nodes as representative of two-hop reachable nodes; and

(g) discovering new nodes reachable at increasingly greater distances from the origin node until the processor finds the target node within a result set or the state machine engine returns an empty result set indicating the target node is not reachable from the origin node; and

wherein, each configurable element of the plurality of configurable elements comprising a state transition element (STE) comprising a memory element programmed with configuration data to selectively set a data state of the memory element as one of a high state and a low state, wherein the STE is configured to analyze at least a portion of the input data stream based on the data state of the memory element and to output a result of the analysis as an event representative of a satisfaction of traversal of a portion of the graph problem to be solved, wherein the STE is configured to represent a node of a graph edge as the portion of the graph problem to be solved, wherein the STE evaluates the at least a portion of the input data stream to determine whether the node matches the at least a portion of the input data stream, wherein the STE is configured to report the node of the graph edge as the result of the analysis upon an occurrence of the node matching the at least a portion of the input data stream.

29. The computer-readable medium ofclaim 28, comprising instructions to receive an input and simulate operation of the STE based on the input.

30. The computer-readable medium ofclaim 29, comprising instructions to generate an indication of a result of the simulation of the operation of the STE.

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