US11269803B1

Movatterモバイル変換

Info

Publication number: US11269803B1
Application number: US17/108,733
Authority: US
Inventors: Le-Sheng CHOU; Sz-Chin Shih; Shuen-Hung WANG
Original assignee: Quanta Computer Inc
Current assignee: Quanta Computer Inc
Priority date: 2020-12-01
Filing date: 2020-12-01
Publication date: 2022-03-08
Anticipated expiration: 2040-12-01
Also published as: CN114579500B; TWI775325B; TW202223673A; CN114579500A

Abstract

A system and method for providing efficient communication between a processor and a device. An interposer is provided to send signals from the processor to the device. The interposer includes a printed circuit board, a first interconnection port communicating with the processor, and a second interconnection port communicating with the device. A retimer/redriver circuit is coupled to the first interconnection port and the second interconnection port, and the retimer/redriver circuit routes signals from the first interconnection port to the second interconnection port.

Description

TECHNICAL FIELD

The present disclosure relates generally to high speed signals in computing systems. More particularly, aspects of this disclosure relate to an interposer that may facilitate data communication between processors and expansion devices.

BACKGROUND

Computing servers increasingly are centered around processors such as CPUs or specialized processors such as graphic processing unit (GPUs). Multiple processors require fast communication between each other when programming operations are split between the processors. Such processors may also communicate with additional devices on expansion cards through a high speed bus.

The peripheral component interconnect express (PCIe) standard has been adopted for connection of high-speed components in computing devices. Devices have PCIe input/output (TO) units with multiple lanes to communicate data. Such IO units may include 4, 8, or 16 lanes that may be split into separate communication channels for connection to different PCIe devices. A bifurcation control mechanism from a basic input output system (BIOS) allows bifurcating a bus IO unit, such as a PCI Express bus IO unit into smaller buses, for different PCIe devices.

According to the PCIe specification, bifurcation provides flexibility for devices with PCIe IO units to match the lane width of connectors for communicating with the components of the system they are installed on. A wider lane width requires more actual hardware connection pins but provides higher communication speed. In a computer system with PCIe device support capability, PCIe root ports are usually provided by the CPU or chipset for connection to PCIe devices.

A wider width (e.g., one ×16 width port) provides higher communication speed with a PCIe device but reduces the total number of supported PCIe devices of the system. In contrast, a narrower width (e.g., four ×4 width ports) provides lower speed but more ports for PCIe devices to be connected. Such flexibility in the number of lanes per port provides a computer system designer the ability to provide different systems supporting different numbers and types of PCIe devices with the same CPU/chipset.

CPU and GPU technology changes rapidly as more and more features and higher density circuits are being introduced. Computer mother board designs thus need to be flexible to support different configurations of processors and expansion cards. For example, a mother board may be required to support one or two CPUs, and multiple PCIe devices in combination. The flexibility of such designs allows an optimal choice of components for maximizing cost/performance impact. One limitation of existing processors is their limited option for data bus types that are used to communicate with other processors and devices on the mother board. Typically, a processor can only support one type of bus configuration, and thus the expansion devices are limited to devices that are compatible with the bus configuration of the processor.

FIG. 1 shows a typical knownmulti-processor system10 with limited options for data communication. Thesystem10 includes aprocessor20 which may be a CPU or GPU. In this example, theprocessor20 may be connected to

high speed interconnects

22 and24 to receive data from other devices. Each of the

high speed interconnects

22 and24 may provide data communication from other devices such as other CPUs or GPUs such as the

CPUs

26 and28. In this example, the

high speed interconnects

22 and24 are PCIe or (Compute Express Link)

CXL type interconnects

22 and24. Theprocessor20 transmits signals from the

32 and34 may be directly coupled to devices such as PCIe devices or to expansion slots, that may in turn be connected to expansion cards or other devices.

The system design in a server system is usually complicated. A CPU/chipset may have many groups of PCIe lanes, and each group can have an individual bifurcation setting. It is a challenge to identify different systems that require different bifurcation configurations. For example, two systems may have the same motherboard with different PCIe riser cards. Riser cards are an extension board which can be installed on the motherboard to route PCIe signals from motherboard to the PCIe cards installed on the riser card. Thus, different PCIe riser cards may need different PCIe bifurcation configurations. For example, a first riser card may route all 16 PCIe lanes to a single x16 width PCIe slot while a second riser card may route the 16 PCIe lanes to two x8 width PCIe slots. To complicate things further, a third system may have a totally different motherboard.

The use of theprocessor10 as an intermediate device between other processors and devices causes delays. Further, the signals on the

interconnects

22 and24 may not be efficiently transmitted to the

high speed busses

32 and34 because of the translation operations between high speed protocols required to be performed by theprocessor10 to transfer such signals.

Thus, there is a need for a CPU/GPU interposer to provide different bus bifurcation configurations between a processor and expansion devices. There is also a need for a processor interposer with a retimer/redriver circuit to move data from one high speed communication protocol to a different high speed protocol. There is a need for an interposer between a processor and PCIe end devices, to support such PCIe end devices to configure different bus bifurcation.

SUMMARY

One disclosed example is a system for communicating high speed data. The system has a processor and a first high speed connection coupled to the processor. The system has a second high speed connection and a device coupled to the second high speed connection. An interposer is coupled to the first high speed connection and the second high speed connection. The interposer includes a retimer/redriver circuit that transmits signals received from the processor via the first high speed connection to the device via the second high speed connection.

Another disclosed example is an interposer providing communication between a processor and a device. The interposer has a printed circuit board and a first interconnection port on the printed circuit board communicating with the processor. The interposer has a second interconnection port on the printed circuit board communicating with the device. A retimer/redriver circuit is coupled to the first interconnection port and the second interconnection port. The retimer/redriver circuit routes signals from the first interconnection port to the second interconnection port.

Another disclosed example is a method of providing high speed data communications between a processor and a device. The method includes connecting an input port of an interposer having a retimer/redriver circuit to the processor. An output port of the interposer is connected to the device. The processor and device are booted. The interposer is configured to transmit signals received from the processor via the input port to the device via the output port.

The above summary is not intended to represent each embodiment or every aspect of the present disclosure. Rather, the foregoing summary merely provides an example of some of the novel aspects and features set forth herein. The above features and advantages, and other features and advantages of the present disclosure, will be readily apparent from the following detailed description of representative embodiments and modes for carrying out the present invention, when taken in connection with the accompanying drawings and the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure will be better understood from the following description of exemplary embodiments together with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a prior art processor design showing connections between a processor and expansion devices;

FIG. 2 is a diagram of an example interposer that allows communication between a processor and expansion devices;

FIG. 3 is a block diagram of the use of the example interposer inFIG. 2 for communicating different communication protocols between a processor and a device;

FIG. 4 is a block diagram of an example single processor system using the interposer inFIG. 2 to provide high speed signals to expansion cards;

FIG. 5 is an example board arrangement of the example interposer on a dual processor motherboard;

FIG. 6 is a block diagram of a quad processor system using the example interposer;

FIG. 7 is a block diagram of an eight processor system using the example interposer; and

FIG. 8 is a flow diagram of a routine that initializes the example interposer.

The present disclosure is susceptible to various modifications and alternative forms. Some representative embodiments have been shown by way of example in the drawings and will be described in detail herein. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

The present inventions can be embodied in many different forms. Representative embodiments are shown in the drawings, and will herein be described in detail. The present disclosure is an example or illustration of the principles of the present disclosure, and is not intended to limit the broad aspects of the disclosure to the embodiments illustrated. To that extent, elements and limitations that are disclosed, for example, in the Abstract, Summary, and Detailed Description sections, but not explicitly set forth in the claims, should not be incorporated into the claims, singly or collectively, by implication, inference, or otherwise. For purposes of the present detailed description, unless specifically disclaimed, the singular includes the plural and vice versa; and the word “including” means “including without limitation.” Moreover, words of approximation, such as “about,” “almost,” “substantially,” “approximately,” and the like, can be used herein to mean “at,” “near,” or “nearly at,” or “within 3-5% of,” or “within acceptable manufacturing tolerances,” or any logical combination thereof, for example.

The present disclosure provides a CPU/GPU interposer circuit board with a high speed retimer/redriver circuit to support different high speed signal connection types. The interposer board may be plugged into a processor socket for use in multi-processor systems. The interposer circuit thus provides an interposer with a retimer/redriver circuit between processors and end devices that saves costs by replacing costly processors that currently perform the retiming and redriving functions. The example interposer supports PCIe end devices with less power consumption than using a processor. The example interposer may configure different bus bifurcations for a multi-lane bus such as a PCIe bus based on configurations provided by the BIOS. Thus the BIOS may configure the example interposer to support different high speed busses (e.g. CXL or PCIe) and bifurcation modes (e.g. x16, x8/x8, or x4/x4/x4/x4).

FIG. 2 is anexample interposer100 that allows the transmission from a first type of high speed interconnection, such as a (Compute Express Link) CXL interconnection, to a second, different type of high speed connector, such as a high speed bus (e.g., a PCIe bus). Theinterposer100 has a footprint that allows it to be installed in a standard CPU orGPU socket110. Theinterposer100 includes acircuit board114 that includes a retimer/redriver chip112. In this example, thechip112 includes either a retimer or a redriver. Thechip112 may include a redriver if the input signals are sufficiently robust to require only amplification of the signal. Alternatively, thechip112 may include a more complex retimer if a retransmission of a fresh signal is required for the passing of the signal. Thecircuit board114 may include support circuits for the retimer/redriver chip112, such as a voltage regulator controller and various passive resistors and capacitors. The retimer/redriver chip112 modulates signals from one high speed protocol to another high speed protocol. The retimer/redriver chip112 may include a strap pin that may be configured by the BIOS for high speed bus bifurcation. Alternatively, the pin may be configured by an on board jumper setting. Thus thecircuit board114 includes a high speedinput interconnect port120 and high speedoutput interconnect port122. In this example, the highspeed input interconnect120 port may be connected to a CXL connection from a processor such as a CPU or GPU. The high speedoutput interconnect port122 may be connected to a high speed PCIe bus. The PCIe bus may provide signals from theinterposer100 to PCIe devices.

FIG. 3 is a block diagram of anexample system200 that employs anexample interposer210. In this example, theinterposer210 has acircuit board220 with two retimer/redriver chips222. Each of the retimer/redriver chips222 has a high speedinput connector port224 and a high speedoutput connector port226. In this example, the high speedinput connector ports224 are connected to ahigh speed interconnect230, such as a CXL interconnection that is coupled to aCPU240. The high speedoutput connector port226 is coupled to ahigh speed bus232 such as a PCIe bus. Thehigh speed bus232 transmits the output signals to either an end PCIe device or an expansion slot that allows PCIe devices or cards to be connected in this example.

FIG. 4 is a block diagram of an examplesingle processor system400. Thesystem400 includes aprocessor board410, aninterposer carrier board412, and ariser card414. Theprocessor board410 has aprocessor socket420 that holds aprocessor422 that may be a CPU or GPU. Theprocessor422 has ahigh speed port424 that provides high speed interconnections to other processors. In this example, thehigh speed port424 is a CXL interconnection port, but other types of high speed protocols may be used for the interconnection.

Theinterposer carrier board412 includes a retimer/redriver chip430 that is coupled to a highspeed input port432, and coupled to a highspeed output port434. In this example, the highspeed input port432 may accept signals from a high speed processor interconnection such as a CXL interconnection. In this example, the highspeed output port434 may be connected to a high speed bus such as a PCIe bus. In this example, acable436 connects the highspeed interconnection port424 of theprocessor board410 to the high speedinput connector port432. In this example, the highspeed output port434 is a PCIe expansion slot.

Theriser card414 includes anedge connector440 that may be plugged into the expansion slot of theinterposer carrier board412. Theriser card414 includes two

PCIe connector sockets

442 and444. Expansion cards or

devices

450 and452 may be inserted in the

sockets

442 and444. In this example, theoutput port434 is a 16-lane PCIe channel, and the two

sockets

442 and444 on theriser card414 are 8-lane PCIe sockets. The retimer/redriver chip430 thus bifurcates theoutput port434 into two 8-lane PCIe channels. Thus, the

devices

450 and452 each have an 8-lane PCIe port.

In this example, theinterposer carrier board412 may be set up to allow theprocessor422 on thesingle board410 to support an additional PCIe connector. Theinterposer carrier board412 allows the processor to communicate with the

PCIe devices

450 and452 without having an additional PCIe connector. First, the high speed interconnection port424 (CXL) to theprocessor422 is set up. Thecable436 is connected to theinput port432 of theinterposer carrier board412 and the highspeed connector port424 of theprocessor board410. Theriser card414 is then installed in the expansion slot to support the one or two

PCIe cards

450 and452 that may be attached to theriser card414.

In this example, the PCIe cards that may be attached to theriser card414 may be any PCIe compatible device. For example, such devices or cards may include a network interface card (NIC), a non-volatile memory express (NVMe) device, a redundant array of independent disks (RAID) card, a host bus adapter (HBA) card, a video card, a sound card, a graphics processing unit (GPU) card, a field programmable gate array (FPGA) card, and a PCIe switch.

FIG. 5 is a block diagram of asingle processor system500 using a dual processor mother board510. The dual processor mother board510 includes two

processor sockets

512 and514. One of the processor sockets holds aprocessor520. Theprocessor520 may be a CPU or a GPU in this example. Thesecond socket514 holds aninterposer chip530. Both of the

processor sockets

512 and514 include a respective highspeed connector ports532 and534. In this example, the highspeed connector ports532 and534 are a 16-lane PCIe connector. Ahigh speed cable536 connects the highspeed connector ports532 and534 to each other.

The dual processor board510 also includes two

PCIe expansion slots

540 and542. Theexpansion slot540 is connected to an 8-lane PCIe bus550 in this example. Theother expansion slot542 is connected to another 8-lane PCIe bus552. Theinterposer530 has a high speedoutput connector port538 that is connected to the PCIe busses550 and552. In this example, the high speedoutput connector port538 is a 16-lane PCIe connector that is bifurcated into two 8-lane PCIe channels by theinterposer530.

Theinterposer530 thus receives high speed signals from theprocessor520 via theinput connector534 through a 16-lane PCIe channel. Theinterposer530 bifurcates the 16-lane PCIe bus signals from theinput connector534 to the two 8-lane PCIe busses550 and552. Thus, theinterposer530 outputs the signals received from theprocessor520 on one of the two high speed PCIe busses550 or552. The signals are received by devices connected to the

expansion slots

540 or542. The advantage of using the two socket motherboard with theinterposer530 is that for a specific workload that requires less processor performance but more support for end devices, this configuration allows for greater support for such end devices via theinterposer530.

The configuration of thesystem500 includes first installing theprocessor520 in thesocket512. Theprocessor520 is designated as the master CPU. Theinterposer530 is then installed in thesocket514, which is the slave CPU socket. In this example, theinterposer530 is configured during system boot up by the BIOS to redirect signals from theprocessor520 to the high speed busses550 and552 to expansion devices connected to the

expansion slots

540 and542.

FIG. 6 is a block diagram of aquad processor system600 using an example interposer to facilitate data communication. Thesystem600 includes two

dual processor boards

610 and612. Thedual processor board610 includes two

processor sockets

614 and616. One of theprocessor sockets614 holds aprocessor620. Theprocessor620 may be a CPU or a GPU in this example. Thesecond socket616 holds aninterposer chip630. Both of the

processor sockets

614 and616 include a

high speed connector

632 and634 respectively. In this example the

high speed connectors

632 and634 are both 24-channel PCIe connectors. Ahigh speed cable640 connects the

high speed connectors

632 and634 to each other as an 8-lane PCIe bus.

The otherdual processor board612 has two processor sockets with corresponding interposers (not shown). A firsthigh speed cable642 connects a high speed connector of one of the processor sockets of thedual processor board612 with thehigh speed connector632. In this example, thehigh speed connector632 is bifurcated into two 8-channel PCIe interconnections. Thus, the firsthigh speed cable642 is an 8-lane PCIe bus that is connected to one of the interposers in one of the sockets of thedual processor board612. A secondhigh speed cable644 is connected to the interposer on the other processor socket of thedual processor board612. In this example, the secondhigh speed cable644 is an 8-lane PCIe bus that is connected to the other interposer on thedual processor board612.

Thedual processor board610 also includes an expansion slot area that supports two

PCIe expansion slots

650 and652 in this example. Theexpansion slot650 is connected to an 8-lane PCIe bus660 in this example. Theother expansion slot652 is connected to another 8-lane PCIe bus662. In this example, the PCIe busses660 and662 are traces on thecircuit board610 that route signals between theprocessor620 and the

expansion slots

650 and652. Theinterposer630 has a highspeed output connector636 that accesses the PCIe busses650 and652. In this example, the highspeed output connector636 is a 16 lane PCIe connector that is bifurcated into two separate 8 lane PCIe channels for the respective PCIe busses650 and652. The otherdual processor board612 has similar PCIe expansion slots that are connected to each of the processor sockets through respective PCIe busses.

Theinterposer630 thus receives high speed signals from theprocessor620 via theinput connector634 through an 8-lane PCIe channel. Theprocessor620 may receive data from other expansion devices connected to the expansion slots on theboard612 via either the

cables

642 or644. In this manner, theprocessor620 may directly access additional expansion devices on the corresponding expansion slots on thedual processor board612 through the interposers on that board. Theinterposer630 directs the PCIe input bus signals and outputs the signals on one of the two high speed PCIe busses660 or662. The signals are thus received by devices connected to the

expansion slots

650 or652.

The configuration of thesystem600 includes first installing theprocessor620 in thesocket614. Theprocessor620 is designated as the first boot CPU. Theinterposer630 is then installed in thesocket616, which is the slave CPU socket. Theinterposer630 is thus configured to redirect signals from theprocessor620 to the high speed busses660 and662 to expansion devices connected to the

expansion slots

650 and652.

FIG. 7 is a block diagram of an eightprocessor system700 using an interposer to facilitate high speed communication. Thesystem700 includes four dual

processor circuit boards

702,704,706, and708. The main dualprocessor circuit board702 includes twoprocessor sockets710 and712. One of the processor sockets710 holds a processor720. The processor720 may be a CPU or a GPU in this example. Thesecond socket712 holds aninterposer chip730. Both of theprocessor sockets710 and712 include ahigh speed connector732 and734 respectively. In this example thehigh speed connectors732 and734 are a 16 channel PCIe connector. Ahigh speed cable740 connects thehigh speed connectors732 and734 to each other.

The other

dual processor boards

704,706, and708 each have two processor sockets with a processor and an interposer attached (not shown). A firsthigh speed cable742 connects a high speed connector of one of the processor sockets of thedual processor board704 with the high speed connector732. In this example, the high speed connector732 is bifurcated in four 4 channel PCIe interconnections. Thus, the firsthigh speed cable742 is a 4-lane PCIe bus that is connected to the interposer on thedual processor board704. A secondhigh speed cable744 is connected to the interposer in one of the processor sockets of thedual processor board706. In this example, the secondhigh speed cable744 is an 4-lane PCIe bus that is connected to the interposer on thedual processor board706. A thirdhigh speed cable746 is connected to the interposer in one of the processor sockets of thedual processor board708. In this example, the thirdhigh speed cable746 is a 4-lane PCIe bus that is connected to the interposer on thedual processor board708.

The main dualprocessor circuit board702 also includes an expansion slot area that supports two

PCIe expansion slots

750 and752 in this example. Theexpansion slot750 is connected to an 8lane PCIe bus760 in this example. Theother expansion slot752 is connected to another 8lane PCIe bus762. Theinterposer730 has a high speed output connector736 that accesses the PCIe busses750 and752. In this example, the high speed output connector736 is a 16-lane PCIe connector that is bifurcated into two separate 8-lane PCIe channels for the respective PCIe busses760 and762.

Theinterposer730 thus receives high speed signals from the processor720 via theinput connector734 through an 8 lane PCIe channel. The processor720 may receive data from the other processors on the

boards

704,706, and708 via the

respective cables

742,744, or746. Theinterposer730 directs the PCIe input bus signals and outputs the signals on one of the two high speed PCIe busses760 or762. The signals are thus received by devices connected to the

expansion slots

750 or752. In addition, theinterposer730 accepts high speed signals from the processors on the

dual processor boards

704,706, and708 that are directed through the processor720.

The configuration of thesystem700 includes first installing the processor720 in the socket710. The processor720 is designated as the first boot CPU. Theinterposer730 is then installed in thesocket712, which is the slave CPU socket. Theinterposer730 is thus configured to redirect signals from the processor720 to the high speed busses760 and762 to expansion devices connected to the

expansion slots

750 and752.

The flow diagram inFIG. 8 is representative of example machine readable instructions for the process of initializing a processor and expansion device for communication through an example interposer. In this example, the machine readable instructions comprise an algorithm for execution by: (a) a processor; (b) a controller; and/or (c) one or more other suitable processing device(s). The algorithm may be embodied in software stored on tangible media such as flash memory, CD-ROM, floppy disk, hard drive, digital video (versatile) disk (DVD), or other memory devices. However, persons of ordinary skill in the art will readily appreciate that the entire algorithm and/or parts thereof can alternatively be executed by a device other than a processor and/or embodied in firmware or dedicated hardware in a well-known manner (e.g., it may be implemented by an application specific integrated circuit [ASIC]; a programmable logic device [PLD]; a field programmable logic device [FPLD]; a field programmable gate array [FPGA]; discrete logic; etc.). For example, any or all of the components of the interfaces can be implemented by software, hardware, and/or firmware. Also, some or all of the machine readable instructions represented by the flowcharts may be implemented manually. Further, although the example algorithm is described with reference to the flowcharts illustrated inFIG. 5, persons of ordinary skill in the art will readily appreciate that many other methods of implementing the example machine readable instructions may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined.

FIG. 8 is a flow diagram800 of the process of initializing an interposer such as theinterposer530 inFIG. 5. The routine first detects that the system is powered on and begins the boot process of theprocessor520 and the interposer530 (810). During the boot process, the BIOS detects the interposer system configuration and initiates the high speed bus bifurcation (812). The configurations may include configuring theinterposer530 for a CXL or PCIe interface. The configuration may include a bifurcation such as a PCIe x16, x8/x8 or x4/x4/x4/x4. The configuration may also include different versions of PCIe such as PCIe Gen3/Gen4 orGen 5. For example, inFIG. 5, the BIOS configures the bifurcation to split the output PCIe channel into two 8-lane PCIe channels for the two

expansion slots

540 and542. The routine then configures the retimer/redriver circuit on theinterposer530 to redirect signals received fromprocessor520 signal to end devices connected to theinterposer530 such as devices plugged into theexpansion slots540 and542 (814). The end devices such as PCIe devices plugged into the

expansion slots

540 and542 are then initiated (816).

The interposer may have a set of pins that may mate with processor sockets. In configurations such as inFIGS. 5-7, an interposer allows a single processor to access multiple PCIe slots without having to employ a more expensive second processor. Thus, in applications that require only a single processor, the interposer saves resources by using an existing dual socket motherboard, to increase the available PCIe devices. The interposer performs the relative simple task of communication between high speed connections, and thus does not include the additional processing cores and supporting circuits of a general purpose processor. The interposer is cheaper to obtain when compared to a general purpose processor. Thus, costs associated with building a computing system, such as one with a dual socket motherboard, may be reduced. Further, since the interposer is dedicated to facilitating communication between high speed connections, delays that a processor may impose if it is used to facilitate communications with the other PCIe slots because it performs other computational tasks may be avoided by the interposer.

As used in this application, the terms “component,” “module,” “system,” or the like generally refer to a computer-related entity, either hardware (e.g., a circuit), a combination of hardware and software, software, or an entity related to an operational machine with one or more specific functionalities. For example, a component may be, but is not limited to being, a process running on a processor (e.g., digital signal processor), a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a controller, as well as the controller, can be a component. One or more components may reside within a process and/or thread of execution, and a component may be localized on one computer and/or distributed between two or more computers. Further, a “device” can come in the form of specially designed hardware; generalized hardware made specialized by the execution of software thereon that enables the hardware to perform specific function; software stored on a computer-readable medium; or a combination thereof.

The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms “including,” “includes,” “having,” “has,” “with,” or variants thereof, are used in either the detailed description and/or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Furthermore, terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Although the invention has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur or be known to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the invention should be defined in accordance with the following claims and their equivalents.

Claims

What is claimed is:

1. A system for communicating high speed data, the system comprising:

a first dual socket processor main board;

a first processor socket on the first dual socket processor board;

a second processor socket on the first dual socket processor board;

a first processor in the first processor socket;

a first high speed connection coupled between the first processor socket and the second processor socket;

a second high speed connection coupled to the second processor socket;

a first device coupled to the second high speed connection;

a first interposer installed in the second processor socket, the first interposer coupled to the first high speed connection and the second high speed connection, the first interposer including a retimer/redriver circuit that transmits signals received from the first processor via the first high speed connection to the first device via the second high speed connection, wherein the first interposer directly and exclusively transmits signals from the first high speed connection to the second high speed connection to the first device without selectively switching the signals; and

a second dual socket processor main board having a third processor socket, a fourth processor socket, a second device, and a second interposer installed in the third processor socket, wherein the second interposer is coupled to the first processor via a third high speed connection, and wherein the second device is coupled to the second interposer via a fourth high speed connection, wherein the second interposer directly transmits signals from the fourth high speed connection to the third high speed connection.

2. The system ofclaim 1, wherein a first communication protocol of the first high speed connection is one of a CXL or PCIe protocol.

3. The system ofclaim 1, wherein a second communication protocol of the second high speed connection is different from the first communication protocol.

4. The system ofclaim 3, wherein the first interposer modulates signals of the first communication protocol to the second communication protocol.

5. The system ofclaim 1, wherein the first device is selected from the group consisting of a network interface card (NIC), a non-volatile memory express (NVMe) device, a redundant array of independent disks (RAID) card, a host bus adapter (HBA) card, a video card, a sound card, a graphics processing unit (GPU) card, a field programmable gate array (FPGA) card, and a PCIe switch.

6. The system ofclaim 1, wherein the first processor is one of a CPU or a GPU.

7. The system ofclaim 1, further comprising a riser card having a plurality of expansion card slots, the riser card coupled to the second high speed interconnection.

8. The system ofclaim 1, wherein the first and second interconnections are coupled to PCIe busses, and wherein the first interposer is operable to bifurcate PCIe channels of the second interconnection.

9. The system ofclaim 1, further comprising a second processor installed in the fourth processor socket, wherein the first processor is interconnected with the second processor.

10. A method of providing high speed data communications between a first processor and a first device on a first dual processor main board, and a second dual processor main board, wherein the first processor is installed in a first socket of the first dual processor main board, the method comprising:

connecting an input port of a first a # interposer in a second socket of the first dual processor main board, the first interposer having a retimer/redriver circuit, to the first processor;

connecting an output port of the first interposer to the first device, the first interposer operable to exclusively and directly transmit signals from the input port to the output port without selectively switching the signals;

coupling the first processor to an input port of a second interposer on a third socket of the second dual socket processor main board via a first high speed connection;

connecting an input port of the second interposer in a fourth socket of the second dual processor main board;

connecting an output port of the second interposer to a second device on the second dual socket processor main board via a second high speed connection, wherein the second interposer directly transmits signals from the second high speed connection to the first high speed connection;

booting the first processor and the first device; and

configuring the first interposer to exclusively and directly transmit signals received from the first processor via the input port to the first device via the output port.

11. The method ofclaim 10, wherein a first communication protocol of a first high speed connection between the input port of the first interposer and the first processor is one of a CXL or PCIe protocol.

12. The method ofclaim 11, wherein a second communication protocol of a second high speed connection between the first interposer and the first device is different from the first communication protocol.

13. The method ofclaim 12, wherein the first interposer modulates signals of the first communication protocol to the second communication protocol.

14. The system ofclaim 12, wherein the first and second interconnections are coupled to PCIe busses, and wherein the first interposer is operable to bifurcate PCIe channels of the second interconnection.

15. The method ofclaim 11, wherein the first device is selected from the group consisting of a network interface card (NIC), a non-volatile memory express (NVMe) device, a redundant array of independent disks (RAID) card, a host bus adapter (HBA) card, a video card, a sound card, a graphics processing unit (GPU) card, a field programmable gate array (FPGA) card, and a PCIe switch.

16. The method ofclaim 11, wherein the first processor is one of a CPU or a GPU.

17. The method ofclaim 11, further comprising coupling a riser card having a plurality of expansion card slots to a second high speed interconnection between the first interposer and the first device.

18. The method ofclaim 11, further comprising:

installing a second processor is in the fourth processor socket; and

interconnecting the first processor with the second processor.