US10576265B2 - Pulse definition circuitry for creating stimulation waveforms in an implantable pulse generator - Google Patents

Abstract

Improved stimulation circuitry for controlling the stimulation delivered by an implantable stimulator is disclosed. The stimulation circuitry includes memory circuitry that stores pulse programs that define pulse shapes, steering programs that define electrode configurations, and aggregate programs that link a selected pulse program with a selected steering program. Each steering program defines the stimulation polarity and the allocation of current of the specified stimulation polarity for each of the pulse generator's electrodes. Each pulse program includes one or more pulse instructions, where each instruction defines the parameters of a single phase of the pulse program. Pulse definition circuits in the stimulation circuitry execute aggregate programs to generate stimulation waveforms, which stimulation waveforms can be generated simultaneously by the different pulse definition circuits.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This is a non-provisional application based on U.S. Provisional Patent Application Ser. No. 62/386,000, filed Sep. 10, 2016, which is incorporated herein by reference in its entirety, and to which priority is claimed.

FIELD OF THE INVENTION

The present invention relates generally to implantable medical devices, and more particularly to improved stimulation circuitry for creating pulses and improved measurement circuitry for measuring values in an implantable medical device.

BACKGROUND

Implantable stimulation devices are devices that generate and deliver electrical stimuli to body nerves and tissues for the therapy of various biological disorders, such as pacemakers to treat cardiac arrhythmia, defibrillators to treat cardiac fibrillation, cochlear stimulators to treat deafness, retinal stimulators to treat blindness, muscle stimulators to produce coordinated limb movement, spinal cord stimulators to treat chronic pain, cortical and deep brain stimulators to treat motor and psychological disorders, and other neural stimulators to treat urinary incontinence, sleep apnea, shoulder subluxation, etc. The description that follows will generally focus on the use of the invention within a Spinal Cord Stimulation (SCS) system, such as that disclosed in U.S. Pat. No. 6,516,227. However, the present invention may find applicability in any implantable medical device system, including a Deep Brain Stimulation (DBS) system.

As shown inFIGS. 1A-1C, an SCS system typically includes an Implantable Pulse Generator (IPG)10 (Implantable Medical Device (IMD)10 more generally), which includes abiocompatible device case12 formed of a conductive material such as titanium for example. Thecase12 typically holds the circuitry and power source (e.g., battery)14 (FIG. 1C) necessary for the IPG10 to function, although IPGs can also be powered via external RF energy and without a battery. The IPG10 is coupled toelectrodes16 via one or more electrode leads18, such that theelectrodes16 form anelectrode array20. Theelectrodes16 are carried on aflexible body22, which also houses theindividual signal wires24 coupled to each electrode. In the illustrated embodiment, there are eight electrodes (Ex) on two leads18 for a total of sixteenelectrodes16, although the number of leads and electrodes is application specific and therefore can vary. The leads18 couple to the IPG10 usinglead connectors26, which are fixed in anon-conductive header material28, which can comprise an epoxy for example.

As shown in the cross-section ofFIG. 1C, the IPG10 typically includes a printed circuit board (PCB)30, along with variouselectronic components32 mounted to thePCB30, some of which are discussed subsequently. Two coils (more generally, antennas) are shown in the IPG10: atelemetry coil34 used to transmit/receive data to/from an external controller (not shown); and acharging coil36 for charging or recharging the IPG'sbattery14 using an external charger (not shown), although theIPG10's battery may also be non-rechargeable, in which case thecharging coil36 would not be necessary.FIG. 1B shows these aspects in perspective with thecase12 removed for easier viewing. Telemetrycoil34 may alternatively comprise a short range RF antenna for wirelessly communicating in accordance with a short-range RF standard such as Bluetooth, WiFi, MICS, Zigbee, etc., as described in U.S. Patent Application Publication 2016/0051825.

FIG. 2A shows aprior art architecture40 for the circuitry in IPG10, which is disclosed in U.S. Patent Application Publications 2012/0095529, 2012/0092031 and 2012/0095519 (“ASIC Publications”), which are incorporated by reference in their entireties.Architecture40 includes a microcontroller integratedcircuit50 and an Application Specific Integrated Circuit (ASIC)60 in communication with each other by abus90. Stated simply, themicrocontroller50 provides master control for thearchitecture40, while ASIC60 takes commands from and provides data to the microcontroller. ASIC60 provides specific IPG functionality. For example, and as explained in further detail below, ASIC60 sends stimulation current to and reads measurements from the sixteenelectrodes16. ASIC60 comprises a mixed mode IC carrying and processing both analog and digital signals, whereasmicrocontroller50 comprises a digital IC carrying and processing only digital signals.

Microcontroller50 and ASIC60 comprise monolithic integrated circuits each formed on their own semiconductive substrates (“chips”), and each may be contained in its own package and mounted to the IPG10'sPCB30.Architecture40 may also include additional memory (not shown) for storage of programs or data beyond that provided internally in themicrocontroller50. Additional memory may be connected to themicrocontroller50 by a serial interface (SI) as shown, but could also communicate with themicrocontroller50 viabus90.Bus90 may comprise a parallel address/data bus, and may include a clock signal and various control signals to dictate reading and writing to various memory locations, as explained in the '529 Publication.Bus90 and the signals it carries may also take different forms; for example,bus90 may include separate address and data lines, may be serial in nature, etc.

As explained in the above-referenced ASIC Publications,architecture40 is expandable to support use of a greater number ofelectrodes16 in the IPG10. For example, and as shown in dotted lines inFIG. 2A,architecture40 may include anotherASIC60′ identical in construction to ASIC60, thus expanding the number of electrodes supported by the IPG10 from sixteen to thirty two. Various off-bus connections54 (i.e., connections not comprising part of bus90) can facilitate such expansion, and may further (e.g., by bond programming; see inputs M/S) designate ASIC60 as a master andASIC60′ as a slave. Such differentiation between theASICs60 and60′ can be useful, as certain redundant functionality in the slave ASIC60′ can be disabled in favor of the master ASIC60. Off-bus communications54 can allow the voltage at theelectrode nodes61a(E1′-EN′) of one of the ASICs (60′; OUT1, OUT2) to be sent to the other ASIC (60; IN1, IN2) to be measured. Off-bus connections54 are further useful in generation and distribution of a clock signal governing communications on thebus90 as well as in the ASIC(s)60. As these concepts are discussed in detail in the above-referenced ASIC Publications, they are not elaborated upon here.

FIG. 2B shows various functional circuit blocks withinASIC60, which are briefly described. ASIC60 includes an internal bus92 which can couple toexternal bus90 and which may duplicatebus90's signals. Note that each of the functional blocks includesinterface circuitry88 enabling communication on the internal bus92 and ultimatelyexternal bus90, as the above-referenced ASIC Publications explain.Interface circuitry88 includes circuitry to help each block recognize when bus92 is communicating data with addresses belonging to that block. ASIC60 contains several terminals61 (e.g., pins, bond pads, solder bumps, etc.), such as those necessary to connect to thebus90, thebattery14, thecoils34,36, external memory (not shown).Terminals61 includeelectrode node terminals61a(E1′-EN′) which connect to the electrodes16 (E1-EN) on the lead(s)18 by way of DC-blockingcapacitors55. As is known, DC-blockingcapacitors55 are useful to ensure that DC current isn't inadvertently (e.g., in the event of failure of theASIC60's circuitry) injected into the patient's tissue, and hence provide safety to theIPG10. Such DC-blockingcapacitors55 can be located on or in the IPG10's PCB30 (FIG. 1C) inside of the IPG'scase12. See U.S. Patent Application Publication 2015/0157861.

Each of the circuit blocks in ASIC60 performs various functions in IPG10. Telemetry block64 couples to theIPG telemetry coil34, and includes transceiver circuitry for wirelessly communicating with an external device according to a telemetry protocol. Such protocol may comprise Frequency Shift Keying (FSK), Amplitude Shift Keying (ASK), or various short-range RF standards such as those mentioned above. Charging/protection block62 couples to theIPG charging coil36, and contains circuitry for rectifying power wirelessly received from an external charger (not shown), and for charging thebattery14 in a controlled fashion.

Analog-to-Digital (A/D)block66 digitizes various analog signals for interpretation by theIPG10, such as the battery voltage Vbat or voltages appearing at the electrodes, and is coupled to an analog bus67 containing such voltages. A/D block66 may further receive signals from sample and holdblock68, which as the ASIC Publications explain can be used to measure such voltages, or differences between two voltages. For example, sample and holdcircuitry68 may receive voltages from two electrodes and provide a difference between them (see, e.g., VE1-VE2 inFIG. 3A, discussed subsequently), which difference in voltage may then be digitized at A/D block66. Knowing the difference in voltage between two electrodes when they pass a constant current allows for a determination of the (tissue) resistance between them, which is useful for a variety of reasons.

Sample and holdblock68 may also be used to determine one or more voltage drops across theDAC circuitry72 used to create the stimulation pulses (see, e.g., Vp and Vn inFIG. 3A, explained subsequently). This is useful to setting the compliance voltage V+ to be output by a compliancevoltage generator block76. Compliance voltage VH powers theDAC circuitry72, and the measured voltage drops ensure that the compliance voltage VH produced is optimal for the stimulation current to be provided—i.e., VH is not too low as to be unable to produce the current required for the stimulation, nor too high so as to waste power in theIPG10. Compliancevoltage generator block76 includes circuitry for boosting a power supply voltage such as the battery voltage, Vbat, to a proper level for VH. Such circuitry (some of which may be located off chip) can include an inductor-based boost converter or a capacitor-based charge pump, which are described in detail in U.S. Patent Application Publication 2010/0211132.

Clock generation block74 can be used to generate a clock for theASIC60 and communication on the bus.Clock generation block74 may receive an oscillating signal from an off-chip crystal oscillator56, or may comprise other forms of clock circuitry located completely on chip, such as a ring oscillator. U.S. Patent Application Publication 2014/0266375 discloses another on-chip circuit that can be used to generate a clock signal on theASIC60.

Master/slave control block86 can be used to inform theASIC60 whether it is to be used as a master ASIC or as a slave ASIC (e.g.,60′), which may be bond programmed at M/S terminal61. For example, M/S terminal may be connected to a power supply voltage (e.g., Vbat) to informASIC60 that it will operate as a master ASIC, or to ground to inform that it will operate as a slave, in which case certain function blocks will be disabled, as the ASIC Publications explain.

Interruptcontroller block80 receives various interrupts (e.g., INT1-INT4) from other circuit blocks, which because of their immediate importance are received independent of the bus92 and its communication protocol. Interrupts may also be sent to themicrocontroller50 via thebus90.Internal controller82 in theASIC60 may receive indication of such interrupts, and act as a controller for all other circuit blocks, to the extent microcontroller50 (FIG. 2A) does not handle such interrupt through theexternal bus90. Further, each of the functional circuit blocks contain set-up and status registers (not shown) written to by thecontroller82 upon initialization to configure and enable each block. Each functional block can then write pertinent data at its status registers, which can in turn be read by thecontroller82 via internal bus92 as necessary, or by themicrocontroller50 viaexternal bus90. The functional circuit blocks can function as simple state machines to manage their operation, which state machines are enabled and modified via each block's set-up and status registers.

Nonvolatile memory (NOVO) block78 caches any relevant data in the system (such as log data). Additional memory (not shown) can also be provided off-chip via aserial interface block84.

ASIC60 further includes astimulation circuit block70, which includes circuitry for receiving and storing stimulation parameters from themicrocontroller50 viabuses90 and92. Stimulation parameters define the shape and timing of stimulation pulses to be formed at the electrodes, and can include parameters such as which electrodes E1-EN will be active; whether those active electrodes are to act as anodes that source current to a patient's tissue, or cathodes that sink current from the tissue; and the amplitude (A), duration (d), and frequency (f) of the pulses. Amplitude may comprise a voltage or current amplitude. Such stimulation parameters may be stored in registers in thestimulation circuitry block70. See, e.g., U.S. Patent Application Publications 2013/0289661; 2013/0184794.

Block70 also includes a Digital-to-Analog Converter (DAC)72 for receiving the stimulation parameters from the registers and for forming the prescribed pulses at the selected electrodes.FIG. 3A shows a simple example ofDAC circuitry72 as used to provide a current pulse between selected electrodes E1 and E2 and through a patient's tissue,R. DAC circuitry72 as shown comprises two portions, denoted as PDAC72pandNDAC72n. These portions ofDAC circuitry72 are so named because of the polarity of the transistors used to build them and the polarity of the current they provide. Thus, PDAC72pis formed from P-channel transistors and is used to source a current +I to the patient's tissue R via a selected electrode E1 operating as an anode.NDAC72nis formed of N-channel transistors and is used to sink current −I from the patient's tissue via a selected electrode E2 operating as a cathode. It is important that current sourced to the tissue at any given time equal that sunk from the tissue to prevent charge from building in the tissue, although more than one anode electrode and more than one cathode electrode may be operable at a given time.

PDAC72pandNDAC72nreceive digital control signals from the registers in thestimulation circuitry block70, denoted <Pstim> and <Nstim> respectively, to generate the prescribed pulses with the prescribed timing. In the example shown, PDAC72pandNDAC72ncomprise current sources, and in particular include current-mirrored transistors for mirroring (amplifying) a reference current Iref to produce pulses with an amplitude (A). PDAC72pandNDAC72ncould however also comprise constant voltage sources. Control signals <Pstim> and <Nstim> also prescribe the timing of the pulses, including their duration (D) and frequency (f), as shown in the example waveform inFIG. 3B. The PDAC72pandNDAC72nalong with the intervening tissue R complete a circuit between a power supply VH—the compliance voltage as already introduced—and ground. As noted earlier, the compliance voltage VH is adjustable to an optimal level at compliance voltage generator block76 (FIG. 2B) to ensure that current pulses of a prescribed amplitude can be produced without unnecessarily wasting IPG power.

The DAC circuitry72 (PDAC72pandNDAC72n) may be dedicated at each of the electrodes, and thus may be activated only when its associated electrode is to be selected as an anode or cathode. See, e.g., U.S. Pat. No. 6,181,969. Alternatively, one or more DACs (or one or more current sources within a DAC) may be distributed to a selected electrode by a switch matrix (not shown), in which case optional control signals <Psel> and <Nsel> would be used to control the switch matrix and establish the connection between the selected electrode and the PDAC72porNDAC72n. See, e.g., U.S. Pat. No. 8,606,362.DAC circuitry72 may also use a combination of these dedicated and distributed approaches. See, e.g., U.S. Pat. No. 8,620,436.

In the example waveform shown inFIG. 3B, the pulses provided at electrodes E1 and E2 are biphasic, meaning that each pulse includes a stimulation phase of a first polarity and an active recovery phase of an opposite polarity (along with additional phases that are not therapeutically meaningful that are described below). This is useful as a means of active recovery of charge that may build up on the DC-blockingcapacitors55. Thus, while charge will build up on thecapacitors55 during the stimulation phase, the active recovery phase will recover that charge, particularly if the total amount of charge is equal in each phase (i.e., if the area under the stimulation and active recovery pulse phases are equal). Recovery of excess charge on the DC-blockingcapacitors55 is important to ensure that theDAC circuit72 will operate as intended: if the charge/voltage across the DC-blockingcapacitors55 is not zero at the end of each pulse, remaining charge/voltage will skew formation of subsequent pulses, which may therefore not provide the prescribed amplitude.

During the stimulation phase, electrode E1 acts as the anode or source for the current pulse, while electrode E2 acts of the cathode or sink for the current pulse. Thus, sourced current of the desired amplitude is issued from the PDAC72pto E1 while sunk current of that same amplitude is drawn into theNDAC72nfrom E2. This causes the current to flow from E1 to E2 through the patient's tissue (R). Notice that the pulses at E1 and E2 during the stimulation phase have the same amplitude (although of opposite polarities) and the same pulse width (pw), so that an excess of charge does not build up in the patient's tissue, R. The stimulation phase is eventually followed by the active recovery phase during which E1 acts as the cathode (sunk current is drawn into theNDAC72nfrom E1) and E2 as the anode (source current is issued from PDAC72pto E2), such that current flows through the tissue R in the opposite direction.

To ensure complete recovery of any stored charge, the active recovery phase is followed by a passive recovery phase. In this passive recovery phase, the decoupling capacitors C1-C2 connected to previously-active electrodes E1 and E2 are shorted to a common potential via passive recovery switches96 (FIG. 3A). In the example illustrated, this common potential, Vbat, comprises the voltage of the battery within theIPG100, although other reference potentials could be used as well. Shorting the capacitors to Vbat effectively shorts them through the patient's tissue, and thus equilibrates any stored charge to assist in charge recovery. Some architectures may short only the previously-active electrodes by closing only the passive recovery switches86 coupled to those electrodes, while other architectures will short all of the electrodes by closing all of the passive recovery switches96.

Other pulse phases in each period are shown inFIG. 3B. Preceding the stimulation phase is a pre-pulse phase, which is of low amplitude and long duration, and of opposite polarity to the stimulation phase that follows it. Experimentation suggests that the use of such a pre-pulse can help to assist in recruiting deeper nerves in an SCS application, although use of such a pre-pulse is not strictly necessary. An interpulse period between the stimulation and active recovery phases of short duration allows the nerves to stabilize after being stimulated. A quiet phase follows the passive recovery phase, and essentially acts as a waiting phase before the next period issues. The duration of the quiet phase will depend on the durations of the phases that precede it in the period, as well as the frequency (f) at which the pulse issues.

The various phases of each pulse are controlled by thestimulation circuitry70, which provides digital control signals to theDAC circuitry72. Thestimulation circuitry70 receives and stores the data necessary to define the various phases in each pulse. Such information is provided to thestimulation circuitry70 frommicrocontroller50 viabuses90 and92. Themicrocontroller50 in turn typically receives information about the structure of the pulses wirelessly from an external device, such as an external controller through which the patient or clinician could select the various pulse parameters (amplitude, pulse width, frequency), the electrodes, and whether they are to act as anodes or cathodes.

As illustrated inFIG. 3C, the stimulation circuitry includes atimer94 and aregister bank98. Thetimer94 stores the durations (pulse widths) of the phases in the pulse, while theregister bank98 stores control, amplitude, active electrode, and electrode polarity information for the phases. Thus, a first register in thetimer94 stores the pulse width of the first pulse phase in the period, the pre-pulse (pw_pp) in the example ofFIG. 3B, and the corresponding first register in theregister bank98 stores its amplitude (amp_pp), active electrode, and electrode polarities. A second register in thetimer94 stores the pulse width of the next pulse phase, the stimulation phase (pw_s), and the corresponding second register in theregister bank98 stores the amplitude (amp_s), active electrode, and electrode polarity for the stimulation phase. Data for subsequent pulse phases (interphase (ip), active recovery (ar), passive recovery (pr), and quiet (q)) are similarly stored in thetimer94 and registerbank98. Thetimer94 may comprise a state machine in one example.

The control data in the registers (cntl) contains information necessary for proper control of theDAC circuitry72 for each phase. For example, during the passive recovery phase, the control data (cntl_pr) would instruct certain passive recovery switches96 to close, and would disable the PDAC72pand theNDAC72n. By contrast, during active phases, the control data would instruct the passive recovery switches96 to open, and would enable the PDAC72pand theNDAC72n.

Each register in theregister bank98 is, in one example, 96 bits in length, with the control data for the phase in the first 16 bits, the amplitude of the phase specified in the next 16 bits, followed by eight bits for each electrode. Each of the eight electrode bits in turn specifies the polarity (P) of the electrode in a single bit, with the remaining 7 bits specifying the percentage (%) of the amplitude that that electrode will receive. Thus, for the pre-pulse phase, the polarity bit P for E1 would be a ‘1’, specifying that that electrode is to act as a cathode, and thus will sink current of the specified amplitude (amp_pp) toNDAC72n. The remaining seven bits for E1 would digitally represent 100%, indicating that E1 is to receive the entirety of the cathodic current during the pre-pulse phase. In more complicated examples, the sourced or sunk currents could be shared between electrodes, and thus smaller percentages would be indicated in the trailing seven bits. The polarity bit P for E2 during the pre-pulse phase would be a ‘0’, specifying that that electrode is to act as an anode, and thus will receive current as controlled by PDAC72p. Again, the remaining seven bits for E2 would digitally represent 100%, indicating that E2 is to receive the entirety of the anodic current during the pre-pulse phase.

The other registers inregister bank98 are programmed similarly for each phase. For example, all of the bits for E3-E8 in all of the registers would be set to zero for the example pulses ofFIG. 3B, because those electrodes are not implicated. The amplitudes for the interphase (amp_ip), passive recovery (amp_pr), and quiet (amp_q) phases would be set to zero as those phases do not require the PDAC72porNDAC72nto actively issue any current.

The goal of thestimulation circuitry70 is to send data from an appropriate register in theregister bank98 to theDAC circuitry72 at an appropriate point in time, and this occurs by control of thetimer94. As noted earlier, the pulse widths of the various phases are stored in thetimer94. Also stored at the timer is the frequency, f, of the pulse, the inverse of which (1/f) comprises the duration of each period. Knowing this period, thetimer94 can cycle through the durations of each of the pulse widths, and send the data in theregister bank98 to theDAC circuitry72 at the appropriate time. Thus, at the start of the period, thetimer94 enables themultiplexer99 to pass the values stored in the first register for the pre-pulse data to theDAC circuitry72 to establish the pre-pulse phase at electrodes E1 and E2. After time pw_pphas passed, thetimer94 enables themultiplexer99 to pass the values stored in the second register for the stimulation phase to theDAC circuitry72 to establish the stimulation phase at the electrodes E1 and E2. The other registers are similarly controlled by thetimer94 to send their data at appropriate times. This process of cycling through the various pulse phases continues, and eventually at the end of quiet phase, i.e., at the end of pw_q, thetimer94 once again enables the pre-pulse data, and a new period of the pulse is established.

This approach for controlling theDAC circuitry72 in accordance with each phase of the pulse period is adequate, but the inventors have found that this approach also suffers from certain shortcomings. A significant shortcoming is the lack of flexibility that thestimulation circuitry70 provides to define more complex pulses. Because the parameters of each phase of a pulse are specified by dedicated registers in theregister bank98, pulses are limited to the number of phases that theregister bank98 is designed to accommodate (e.g., the six phases shown inFIGS. 3B and 3C) each of which specify a constant pulse amplitude. Therefore, more complex pulses having, for example, ramped portions cannot be created using thecircuitry70. Thecircuitry70 could be modified to accommodate additional pulse phases to approximate ramped pulse portions using a stair-step approach, but this would require additional registers in theregister bank98. Assume, for example, that to form a suitably-smooth ramp it would be necessary to parse both of the stimulation and active recovery phases into ten smaller phases. The pulse would then comprise 24 different phases: the 20 phases needed in each of the stimulation and active recovery phases, the pre-pulse phase, the inter-pulse phase, the passive recovery phase, and the quiet phase. Because theregister bank98 must contain a register for each phase in the period, thatbank98 would then need 24 different registers. The 96 bits needed for each register in thebank98 typically comprise flip flops, and so in this example 2304 (96*24) flip flops would be required, or more if theIPG100 supports further numbers of electrodes.

Flip flops require significant layout area on theASIC60. Further, the flip flops consume power when they are clocked, which can lead to complexity in gating the clocks to save power. The problem of excessive layout space is compounded by the fact that thestimulation circuitry70 may includemultiple timer94/register bank98/multiplexer99 units operating in parallel (although only a single example is shown). Based on the existing architecture, theASIC60 must either include an undue number of area-intensive registers inregister bank98 to potentially handle the design of complex pulses, or provide a limited number of such registers and forego the use of such complex pulses; neither option is desirable.

A better solution is therefore needed to address the aforementioned problems, and is provided by this disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1C show an implantable pulse generator (IPG), and the electrode arrays coupled to the IPG in accordance with the prior art.

FIGS. 2A-2B show an architecture for the circuitry in the IPG in accordance with the prior art.

FIG. 3A shows the operation of a Digital-to-Analog Converter (DAC) circuit in delivering a stimulation pulse to electrodes in accordance with the prior art.

FIG. 3B shows an example stimulation waveform that can be produced by an IPG in accordance with the prior art.

FIG. 3C shows the data arrangement to define the stimulation waveform inFIG. 3B and the stimulation circuitry that processes the control data in the data arrangement in accordance with the prior art.

FIGS. 4A-4B show an improved architecture for the circuitry in an IPG in accordance with an embodiment of the disclosure.

FIGS. 5A-5C illustrate components of the stimulation circuitry, including DAC circuitry, of the improved architecture in accordance with an embodiment of the disclosure.

FIG. 6 illustrates an example arrangement of microcode to define a steering program in accordance with an embodiment of the disclosure.

FIGS. 7-9 illustrate an example arrangement of microcode to define the parameters of individual phases of a pulse and the arrangement of instructions to define one or more pulse programs in accordance with an embodiment of the disclosure.

FIG. 10 illustrates an example arrangement of microcode in an aggregate instruction that links a pulse program with a steering program in accordance with an embodiment of the disclosure.

FIG. 11 illustrates an example arrangement of aggregate instructions within a memory in accordance with an embodiment of the disclosure.

FIG. 12 illustrates the electrode configurations defined by example steering programs in accordance with an embodiment of the disclosure.

FIG. 13 is a timing diagram that illustrates the execution of instructions by various logic blocks in a pulse definition circuit in accordance with an embodiment of the disclosure.

FIG. 14 illustrates the stimulation waveforms generated simultaneously by two different pulse definition circuits executing two different aggregate programs in accordance with an embodiment of the disclosure.

FIG. 15 illustrates an example arrangement of configuration parameters that are specific to a pulse definition circuit in accordance with an embodiment of the disclosure.

FIG. 16 illustrates the operation of an arbitration manager block in the stimulation circuitry to prevent the allocation of current by two or more different pulse definition circuits to a single electrode simultaneously in accordance with an embodiment of the disclosure.

FIG. 17 illustrates the operation of an amplitude scale parameter in adjusting the amplitude of a pulse as defined by a pulse program in accordance with an embodiment of the disclosure.

FIG. 18 illustrates the effects of a ramp start feature and a ramp repeat feature with differing parameters on a stimulation waveform generated by the stimulation circuitry in accordance with an embodiment of the disclosure.

FIG. 19 illustrates the operation of a burst mode feature in accordance with an embodiment of the disclosure.

FIG. 20 illustrates the control signals generated by the stimulation circuitry in different scenarios in accordance with an embodiment of the disclosure.

FIG. 21 illustrates the components of a measure circuitry block, which controls a sample and hold circuit block and an analog-to-digital (A/D) circuit block in accordance with an embodiment of the disclosure.

FIG. 22 illustrates components of the sample and hold circuitry and the A/D circuitry in accordance with an embodiment of the disclosure.

FIGS. 23A and 23B illustrate the arrangement of microcode to form instructions that cause a measure logic block in the measure circuitry to perform actions in accordance with an embodiment of the disclosure.

FIG. 24 illustrates various types of triggers, issued upon the occurrence of different events by pulse definition circuits in the stimulation circuitry, which are utilized by the measure circuitry in accordance with an embodiment of the disclosure.

FIG. 25 illustrates a steering memory in the measure circuitry and its use in configuring a steering program in the stimulation circuitry in accordance with an embodiment of the disclosure.

FIGS. 26A-26G illustrate an example set of measure instructions to measure a voltage between two electrode nodes in accordance with an embodiment of the disclosure.

FIGS. 27A and 27B illustrate an example set of instructions to measure a voltage between different pairs of electrode nodes by updating the stimulation circuitry's steering program in accordance with an embodiment of the disclosure.

DETAILED DESCRIPTION

FIGS. 4A and 4B show an improved architecture140 andASIC160 for an IPG. Elements in architecture140 andASIC160 that can remain unchanged from theprior art architecture40 andASIC60 described in the Background bear the same element numerals, and are not described again.

Improved ASIC160 includes amicrocontroller block150, which as shown inFIG. 4B can communicate with other functional blocks in theASIC160 via internal bus92.Microcontroller block150 may receive interrupts independent of the bus92 and its communication protocol, although interrupts may also be sent to themicrocontroller150 via the bus92 as well. Even thoughASIC160 includes amicrocontroller block150, theASIC160 may still couple to anexternal bus90, as shown inFIG. 4A. This can facilitate communications between theASIC160 and another device, such as a memory integrated circuit (not shown) that might be coupled to thebus90.Bus90 can also facilitate use of and communication with another identically-constructedASIC160′, shown in dotted lines inFIG. 4A. As described in the Background, use of an additional (slave)ASIC160′ allows the number ofelectrodes16 theIPG10 supports to be doubled, and many of the same off-bus connections54 can be used as described earlier, and as described in the above-referenced ASIC Publications. In one example, themicrocontroller block150 can comprise circuitry from an ARM Cortex-M0+ Processor, which may be incorporated into the monolithic integrated circuit of theASIC160 by licensing various necessary circuits from the library that comprises that processor.

Improved stimulation circuitry170 is illustrated in block diagram form inFIG. 5A. In theimproved stimulation circuitry170, memory circuits store microcode that is processed by one or more pulse definition circuits (PDCs)171, which operate as control circuits to generate the control signals that are sent to theDAC circuitry172. The memory circuits include asteering memory502 that contains steering microcode that defines electrode steering programs, apulse memory504 that contains pulse microcode that defines pulse programs, and anaggregate memory506 that contains aggregate microcode that links pulse programs and steering programs to create a desired pulse therapy program. Thestimulation circuitry170 additionally includes aconfiguration memory508 that stores configuration parameters some of which are global (apply across multiple PDCs171) and some of which are specific to aparticular PDC171. Thememories502,504,506, and508 can be read from and written to by themicrocontroller150, but, as described below, the microcode and configuration parameters in these memories can be processed by thePDCs171 without intervention by themicrocontroller150. Themicrocontroller150 is configured to operate in either a high-power state or a reduced-power state. The ability of thePDCs171 to process the microcode and configuration parameters without intervention by themicrocontroller150 enables themicrocontroller150 to remain in the reduced-power state during the delivery of stimulation, which saves power in the IPG.

Each location (e.g., each 32-bit location) in the memories may be formed as a register of multiple flip-flops or as an addressable location in a more typical memory. Regardless of the structure, the microcode stored in the memories is generically described as being stored in memory circuitry, which memory circuitry may comprise separate memory circuits or a single memory circuit. The microcode and configuration parameters that are stored in the memory circuitry are processed by logic blocks in the PDCs171 (four such PDCs are shown). These logic blocks include asteering logic block512, apulse logic block514, and anaggregate logic block516. Before returning to describe the control signals issued by thestimulation circuitry170 to theDAC circuitry172, the structure of the microcode and the configuration parameters and the processing of such microcode and configuration parameters by the logic blocks inPDCs171 is described.

FIG. 6 illustrates an example arrangement of microcode within memory locations within the steering memory to form a steering program that defines the polarity and current allocation for 33 electrodes (e.g., 32 lead electrodes and a case electrode). In the illustrated arrangement, each memory location includes 32 bits, and a steering program is defined by nine consecutive memory locations. For each electrode, the polarity and the allocation of current of the specified polarity is defined by one byte within one of the memory locations, and the bytes are arranged in consecutive order of the electrodes across the nine memory locations. In each byte, the most significant bit defines the electrode's stimulation polarity and the remaining bits (or some portion thereof) define the percentage of the total current of the specified polarity that is allocated to the electrode. An electrode's “stimulation polarity” as defined in the steering program refers to the polarity of the electrode during a stimulation pulse phase, which is opposite of the electrode's polarity during an active recovery pulse phase. For example, electrode E1 may be allocated 100% of the stimulation anodic current by settingbit7 ofaddress1 to ‘0’ and by providing a binary representation of 100% in bits0-6 ofaddress1. Similarly, electrodes E2 and E5 may be allocated 25% and 75%, respectively, of the stimulation cathodic current by settingbit15 ofaddress1 andbit7 ofaddress2 to ‘1’ and by providing a binary representation of 25% in bits8-14 ofaddress1 and a binary representation of 75% in bits0-6 ofaddress2. Note that while the example steering program defines each electrode's stimulation polarity, the steering program could alternatively define each electrode's active recovery polarity.

As will be described below, the resolution at which current can be allocated among the electrodes in thestimulation circuitry170 can vary depending upon the mode of operation, and thus the number of bits within an electrode's seven-bit allocation range that are utilized can also vary based on the mode of operation. In a standard current mode, thestimulation circuitry170 enables 4% resolution and only the five most significant bits in the seven-bit allocation range are used, but, in a high resolution current, thestimulation circuitry170 enables 1% resolution and all seven bits in the seven-bit allocation range are used. As shown by the example allocations of anodic current to electrode E2, there is no difference in the bit patterns for these two modes of operation for the current allocations that are attainable in the first mode of operation (i.e., current allocations that are a multiple of 4%). While a single steering program is shown, multiple steering programs may be stored within thesteering memory502. For example, 16 different steering programs may be stored in 144 contiguous memory locations (e.g., a first steering program is defined by microcode in memory locations 1-9, a second steering program is defined by microcode in memory locations 10-18, and so on). Thesteering memory502 thus stores a library of steering programs (each of which defines a particular electrode configuration) that can be used in conjunction with a pulse program as described below. It will be understood that the described steering program layout is merely illustrative and that the same features can be accomplished using different microcode arrangements.

Having described an example arrangement of microcode within thesteering memory502 to define a steering program, we turn now to an example arrangement of microcode within thepulse memory504 to define a pulse program, which example is illustrated with reference toFIGS. 7-9. In the example arrangement, each 32-bit memory location stores a pulse instruction that defines the properties of a single phase of the pulse. The arrangement of parameters for the different types of instructions (which define different types of phases) is illustrated inFIG. 7. The first type of instruction that is shown inFIG. 7 defines the parameters of an active phase. During an active phase, current is actively sourced from aPDAC172pand sunk from anNDAC172n. In the active phase instruction, bits0-7 (i.e., the least significant byte) define an amplitude parameter of the active phase. The eight bits enable the assignment of 256 different amplitude values. In a preferred embodiment, the maximum current that can be delivered by theDAC circuitry172 in conjunction with the execution of the pulse microcode is divided into 255 (i.e., the number of non-zero current values) units and the binary representation in the amplitude portion of the active phase instruction defines the quantity of those current units. For example, if the associatedDAC circuitry172 supports a maximum current of 25.5 mA, a binary representation of 100 units in the amplitude portion of the active phase instruction would specify a current amplitude of 10 mA.

The next byte (bits8-15) in the active phase instruction defines the pulse width (i.e., the duration of the active phase). As with the amplitude portion of the active phase instruction, the eight bits in the pulse width range enable the assignment of 256 different pulse width values by providing a binary representation of the number of clock cycles over which the active phase extends. By way of example, for a 100 kHz clock, the value within the pulse width range can specify a pulse width from 0-2.55 milliseconds in 10 microsecond increments.

Bit16 is a return bit that is set to ‘1’ when the active phase is the last phase in a pulse program.Bit17 is a compliance voltage bit that is set to ‘1’ when it is desired to evaluate a status of the compliance voltage VH at the termination of the active phase.Bits18 and19 specify one of four different instruction types. The four types include a stimulation active phase instruction, an active recovery active phase instruction, a delay phase instruction, and an active delay phase instruction. A single active phase instruction arrangement is illustrated inFIG. 7 because the stimulation and active recovery active phase instructions differ only in the value in the type bit range. When the value in the type bit range corresponds to the stimulation active phase instruction, the active phase is applied in accordance with the steering program. However, when the value in the type bit range corresponds to the active recovery active phase instruction, the phase is applied with the opposite polarity of that specified in the steering program (i.e., the cathodic and anodic electrodes in the steering program are reversed).Bit20 is an interrupt bit that is set to ‘1’ when it is desired to provide an indication to themicrocontroller150 of the execution of the pulse phase. Such an interrupt may be communicated via the bus92 or independent of the bus92 via INT1, for example (FIG. 4B). The interrupt could be utilized to cause themicrocontroller150 to take a specified action (e.g., cause a measurement to be taken, update a steering program in thesteering memory502, etc.) at a time corresponding to the execution of the active phase.

The second type of instruction that is shown inFIG. 7 is a delay phase instruction. During a delay phase, no current is actively sourced or sunk by theDAC circuitry172. In the delay phase instruction, bits0-7 (i.e., the least significant byte) define the period of the delay. The eight bits in the delay range enable the assignment of 256 different delay period values by providing a binary representation of the number of time periods over which the delay phase extends. The time period can be the clock period, butbits8 and9 of the delay phase instruction are delay multiplier bits that enable the assignment of three additional time period values. For example, the four values that can be specified by the delay multiplier bits can represent the clock time period, the clock time period multiplied by 8, the clock time period multiplied by 16, and the clock time period multiplied by 256. Using these example multiplier values and a 100 kHz clock as an example, the period of the delay can be set from 0-2.55 milliseconds in 10 microsecond increments, from 0-20.4 milliseconds in 80 microsecond increments, from 0-40.8 milliseconds in 0.16 millisecond increments, or from 0-652.8 milliseconds in 2.56 millisecond increments. It will be understood that other delay multiplier values could be selected to achieve desired pulse characteristics.

Bit10 of the delay phase instruction is a passive recovery bit that is set to ‘1’ if passive recovery is to be performed during the delay phase.Bits11 and12 of the delay phase instruction are active stimulation and active recovery preparation bits, respectively. These bits can be used to signify that the next phase is either a first (prepare stimulation) or a second (prepare recovery) active phase type. This enables thePDC171 to prepare theDAC circuitry172 for the coming active phase. For example, if the prepare stimulation bit is set, the operational amplifiers180 (FIG. 5C) corresponding to electrodes identified in the steering program as cathodic can be enabled in theNDAC172nand theoperational amplifiers180 corresponding to electrodes identified in the steering program as anodic can be enabled in thePDAC172pduring the delay phase. The prepare recovery bit would obviously flip this behavior.Bits16,18-19, and20 are return, type, and interrupt bits that function in the same manner as the corresponding bits of the active phase instruction.

The third type of instruction that is shown inFIG. 7 is an active delay phase instruction. An active delay phase is similar to a delay phase in that no current is actively sourced or sunk to the electrodes by theDAC circuitry172. However, during an active delay phase, the current generation circuitry in theDAC circuitry172 is maintained in an active state. As described below, this current generation circuitry includes the “master DAC”185 (FIG. 5C), which mirrors a reference current to generate an amplified current in accordance with an issued amplitude control signal, andoperation amplifiers168. An active delay phase can be utilized, for example, during a short delay phase to set the amplitude value to themaster DAC185 to the value corresponding to the amplitude in a subsequent active phase and to enable theoperational amplifier168. Thus, while all electrode branch switches178 (FIG. 5C) are open during an active delay phase such that no current is sourced to or sunk from any electrode, the current generation circuitry remains active so that the desired current in the subsequent pulse phase can be immediately delivered by closing the appropriate electrode branch switches178. In the active delay instruction, bits0-3 define the period of the delay and bits4-5 define the delay multiplier. The delay period and the delay multiplier function in the same manner as the corresponding parameters of the delay phase instruction. However, the four-bit delay period of the active delay instruction enables 16 different delay period values by providing a binary representation of the number of time periods over which the delay phase extends. Using the same time period multipliers as described with respect to the delay phase instruction (i.e., 1, 8, 16, and 256) and a 100 kHz clock as an example, the period of the active delay can be set from 0-160 microseconds in 10 microsecond increments, from 0-1.28 milliseconds in 80 microsecond increments, from 0-2.56 milliseconds in 0.16 millisecond increments, or from 0-40.96 milliseconds in 2.56 millisecond increments.Bits6,7, and8, are passive recovery, prepare stimulation, and prepare recovery bits, which function in the same manner as the corresponding bits in the delay phase instruction. Bits9-16 define the amplitude value and function in the same manner as the corresponding data in the active phase instruction. As described above, this value would logically be set to the amplitude of the current to be delivered in the immediately succeeding active phase such that theDAC circuitry172 is prepared to deliver the specified current even though the electrode branch switches178 are open during the active delay phase.Bit17 is a return bit,bits18 and19 are type bits, and bit20 is an interrupt bit, each of which functions in the same manner as corresponding bits in the active phase and delay phase instructions.

As illustrated inFIG. 8, the different types of instructions are arranged in contiguous memory locations in thepulse memory504 to create pulse programs. Each pulse program consists of the instructions that define the phases in a single period of a pulse. For example, pulse program A defines thepulse802, which was described in the background section.FIG. 9 illustrates the configuration of pulse program A's six instructions, each of which defines the parameters of one of thepulse802's phases. In addition,FIG. 9 illustrates the linkage of pulse program A with a steering program A to apply thepulse802 to electrodes E1 and E2 in the same manner as described in the background section. Steering program A specifies that electrode E1 is to receive 100% of the stimulation anodic current and that electrode E2 is to receive 100% of the stimulation cathodic current of the pulse defined by the pulse program.

The first phase in thepulse802 is the pre-pulse phase, which is defined by the instruction at memory location X in pulse program A. Because the pre-pulse phase has a non-zero amplitude of A1, current is actively driven by theDAC circuitry172 during this phase. Thus, the instruction at memory location X is configured as an active phase instruction. More specifically, the instruction is configured as an active recovery active phase instruction (bits18-19), which reverses the polarity of the electrodes defined by steering program A such that electrode E1 operates as a cathode (current sink) and electrode E2 operates as an anode (current source) during the pre-pulse phase. The instruction at memory location X additionally specifies the amplitude A1 (bits0-7) and the pulse width PW1 (bits8-15) of the pre-pulse phase and specifies that the pre-pulse phase is not the last phase in pulse program A (bit16) and that no compliance voltage measurement is to be taken (bit17) and no interrupt is to be issued (bit20) in association with the pre-pulse phase.

The stimulation phase ofpulse802 is defined by the instruction at memory location X+1. This instruction is also configured as an active phase instruction, but it is configured as a stimulation active phase instruction (bits18-19), which utilizes the polarities defined by steering program A such that electrode E1 operates as an anode (current source) and electrode E2 operates as a cathode (current sink) during the stimulation phase. The instruction at memory location X+1 additionally defines the amplitude A2 (bits0-7) and the pulse width PW2 (bits8-15) of the stimulation phase and specifies that the stimulation phase is not the last phase in pulse program A (bit16) and that no compliance voltage measurement is to be taken (bit17) and no interrupt is to be issued (bit20) in association with the stimulation phase.

The inter-pulse phase is defined by the instruction at memory location X+2. Because the amplitude during the inter-pulse phase is zero and the inter-pulse phase is of a short duration and followed by an active phase, the instruction at memory location X+2 is configured as an active delay phase instruction (bits18-19), which, as described above, enables the current generation circuitry in theDAC circuitry172 to be enabled and set to the amplitude of the subsequent phase. The instruction at memory location X+2 defines the pulse width PW3 of the inter-pulse phase (bits0-5) and the amplitude A4 of the succeeding active recovery phase (bits9-16) and specifies that no passive recovery is to be performed during the inter-pulse phase (bit6), that the inter-pulse phase is not the last phase in pulse program A (bit17), and that no interrupt is to be issued (bit20) in association with the inter-pulse phase. The instruction additionally specifies that the succeeding phase is an active recovery active phase (bits7-8), which enables theoperational amplifiers180 to be enabled based on the opposite of the polarities defined by the steering program A. While the inter-pulse phase is illustrated as being configured using an active delay phase instruction, it could also be configured using a delay phase instruction.

The active recovery phase is defined by the instruction at memory location X+3. The instruction at memory location X+3 is configured as an active recovery active phase instruction (bits18-19) and defines the amplitude A4 (bits0-7) and the pulse width PW4 (bits8-15) of the active recovery phase. Memory location X+3 additionally specifies that the active recovery phase is not the last phase in pulse program A (bit16) and that no compliance voltage measurement is to be taken (bit17) and no interrupt is to be issued (bit20) in association with the active recovery phase.

The passive recovery and quiet phases are defined by the instructions at memory locations X+4 and X+5, respectively. The instructions at memory locations X+4 and X+5 are configured as delay phase instructions (bits18-19) that define the pulse widths PW5 and PW6 (bits0-9) of the passive recovery and quiet phases, respectively. These instructions additionally specify that there is no subsequent pulse phase (bits11-12) and that no interrupt is to be issued (bit20) in association with the passive recovery or quiet phases. The instructions in memory locations X+4 and X+5 differ only in that the former specifies that passive recovery is to be performed (bit10) during the passive recovery phase and the latter specifies that the quiet phase is the final phase (bit16) of the pulse program A.

Referring back toFIG. 8, in addition to the simple types of biphasic pulses (such as pulse802) that can be configured using the priorart stimulation circuitry70, the instructions in thepulse memory504 can also be configured to create more complex pulse programs. For example, pulse program B definespulse804, which mimics a sine wave, and pulse program C definespulse806, which includes multiple ramp portions. Pulse program B is created by 58 contiguous instructions in thepulse memory504, one instruction for each of the 58 phases in a single period ofpulse804, which instructions begin immediately following the final instruction associated with pulse program A. The first phase ofpulse804 is defined by the instruction at memory location X+6, and the final phase ofpulse804 is defined by the instruction at memory location X+63. The first phase ofpulse806 is defined by the instruction at memory location X+64, and the final phase ofpulse806 is defined by the instruction at memory location X+101. As will be understood, the “smoothness” of a curve that is approximated using constant-current phases (as in thepulse804, for example) is improved by increasing the number of phases and decreasing the phase pulse width.

Note that the configurability of the pulse instructions and in their arrangement within thepulse memory504 enables the creation of pulses having practically any imaginable properties. In addition to the different types of pulse shapes, thepulses802,804, and806 have different durations (1/f_A, 1/f_B, and 1/f_C, respectively) and maximum stimulation amplitudes (A_A,STIM, A_B,STIM, and A_C,STIM, respectively), which properties may differ significantly (even though the pulses are shown at different scales that suggest the properties are closer in value). Moreover, any number of different pulse programs can be created within the space limitations of thepulse memory504, which may include, for example, 256 memory locations or more. Thepulse memory504 thus stores a library of pulse programs (each of which defines a pulse shape) that can be used in combination with the steering programs by thePDCs171 to generate desired stimulation waveforms. A stimulation waveform is the pattern of stimulation across a set of active electrodes.

FIG. 9 described the linkage of a pulse program with a steering program. This linkage is accomplished through the configuration of aggregate instructions in theaggregate memory506.FIG. 10 shows an example arrangement of an aggregate instruction. The first eight bits (bits0-7) in an aggregate instruction specify the starting pulse memory address. To execute pulse program A, for example, the pulse address portion of the aggregate instruction would include a binary representation of the numeric address of X in thepulse memory504. Bits8-11 of the aggregate instruction specify the steering program to be linked with the pulse program. The four bits in the steering program portion of the aggregate instruction enable the selection of 16 different steering programs. This range of bits could obviously be extended to accommodate additional steering programs. Bits12-19 enable specification of the number of times that the selected pulse is to be repeated. The eight bits in this repeat range enable the specification of up to 255 repeats. As described below, execution of the aggregate instruction results in the sequential execution of the instructions in a pulse program starting at the address specified in the aggregate instruction and ending at the subsequent “return” instruction in thepulse memory504. This sequential execution is repeated the number of times specified in the repeat range of the aggregate instruction. While it may be typical for the specified pulse memory address to correspond to the first phase of a pulse program such that the executed pulse corresponds to a complete pulse program, this is not strictly necessary.Bit20 specifies whether an interrupt is to be executed following execution of the aggregate instruction. Any one or more aggregate instructions represent an aggregate program that defines a stimulation waveform. Note that while the starting and ending addresses in an aggregate program are specified as configuration parameters of anindividual PDC171, the aggregate instruction arrangement could also include a return bit such that the instruction itself identifies that it is the final instruction in a program similar to the return bit in a pulse program.

FIG. 11 illustrates the arrangement of aggregate instructions within theaggregate memory506. In the example configuration illustrated, the instruction at memory location Y specifies the linkage of pulse program A (which begins at pulse memory address X) with steering program A for two repetitions with no interrupt, the instruction at memory location Y+1 specifies the linkage of pulse program A with steering program B for five repetitions with no interrupt, the instruction at memory location Y+2 specifies the linkage of pulse program B (which begins at pulse memory address X+6) with steering program C for 13 repetitions with no interrupt, the instruction at memory location Y+3 specifies the linkage of pulse program A with steering program C for five repetitions with no interrupt, the instruction at memory location Y+4 specifies the linkage of pulse program C (which begins at pulse memory address X+64) with steering program D for five repetitions with no interrupt, and the instruction at memory location Y+5 specifies the linkage of pulse program B with steering program D for seven repetitions with no interrupt. Theaggregate memory506 stores a library of aggregate instructions. One or more aggregate instructions define an aggregate program, which program's start and end addresses (i.e., start and end instructions) are defined by the configuration parameters of anindividual PDC171. An aggregate program, by way of its linkage of one or more pulse programs with one or more steering programs, is a program that, when executed, generates a stimulation waveform in accordance with its underlying pulse and steering programs.

FIG. 12 shows the parameters of the steering programs that are listed in conjunction withFIG. 11. Steering program A, as described above, specifies that electrode E1 is to receive 100% of the stimulation anodic current and electrode E2 is to receive 100% of the stimulation cathodic current. Steering program B specifies that electrodes E1 and E2 are to receive 40% and 60% of the stimulation anodic current, respectively, and electrode E3 is to receive 100% of the stimulation cathodic current. Steering program C specifies that electrode E4 is to receive 100% of the stimulation anodic current and electrode E5 is to receive 100% of the stimulation cathodic current. Steering program D specifies that electrode E4 is to receive 100% of the stimulation anodic current and electrodes E5 and E6 are to receive 80% and 20% of the stimulation cathodic current, respectively. The example aggregate instructions shown inFIG. 11 and the example steering programs shown inFIG. 12 are referenced in the description and figures that follow.

Having described the arrangement of the steering, pulse, and aggregate microcode, we turn now to the operation of theaggregate logic block516,pulse logic block514, andsteering logic block512 in executing such microcode to deliver control signals to theDAC circuitry172 at the appropriate times.FIG. 13 is a timing diagram that shows the values of various parameters of theaggregate logic block516,pulse logic block514, and steering logic duringblock512 execution of an example portion of an aggregate program. As will be understood, execution of an aggregate program involves execution of the corresponding pulse and steering programs. At time t0, PDC171(1) is enabled. The pulse definition enable bit is a parameter ofconfiguration memory508 and is specific to PDC171(1). In response to the PDC being enabled, itsaggregate logic block516 retrieves the aggregate instruction start and end addresses, which addresses are also specific to PDC171(1) and stored inmemory508. In the example shown, the aggregate start and stop addresses are Y and Y+1, respectively. Therefore, when enabled, theaggregate logic block516 in PDC171(1) executes the instructions stored between these addresses in theaggregate memory506. Theaggregate logic block516 initially retrieves and decodes the instructions stored at the aggregate start address (Y) in theaggregate memory506. As illustrated inFIG. 11, the instruction stored at aggregate address Y links pulse program A (which begins at pulse memory address X) and steering program A for 2 repetitions. Theaggregate logic block516 stores the repeat setting (2) and provides the pulse memory address (X) to thepulse logic block514 and the steering memory address (steering program A corresponds to address1) to thesteering logic block512, which logic blocks retrieve the microcode from the respective addresses.

Thepulse logic block514 manages the sequencing of the individual phases of the pulse program. This is accomplished by maintaining a phase accumulator that is incremented in accordance with the system clock (CLK) and any clock multiplier parameters in the pulse instruction that is being processed. As shown in the example inFIG. 13, upon retrieval of the pulse instruction at address X, thepulse logic block514 begins incrementing the phase accumulator. As described above, the instruction at address X defines an active phase and does not include a clock multiplier parameter. Accordingly, the phase accumulator is incremented by one with each clock cycle until the accumulated value is equal to the pulse width value specified by the instruction (PW1). When the accumulated value is equal to the pulse width value and the instruction is not defined as the last phase in a pulse program (i.e., the instruction's return bit is not set), thepulse logic block514 increments its address parameter and obtains the instruction stored at the new address value in thepulse memory504, clears the phase accumulator value, and repeats the process for the retrieved instruction. This process continues as thepulse logic block514 moves sequentially through the addresses associated with the pulse program.

In addition to managing the sequencing of the individual phases of the pulse program, thepulse logic block514 additionally communicates signals to thesteering logic block512 when the instruction being executed by thepulse logic block514 necessitates a modification to the steering program. For example, as described above, during an active recovery phase, the electrode polarities are reversed from the polarities indicated in the steering program. Thus, during execution of an active recovery active phase instruction, thepulse logic block514 communicates a reverse polarity (“RP”) signal to thesteering logic block512. Similarly, during any delay phase, no current is sourced to or sunk from an electrode, and this information must also be communicated to thesteering logic block512. During execution of a delay phase instruction, thepulse logic block514 communicates a delay (“D”) signal to thesteering logic block512.

When thepulse logic block514 completes the processing of an instruction that defines the last phase in a pulse program (i.e., when the instruction's return bit is set and the phase accumulator's accumulated value is equal to the specified pulse width), thepulse logic block514 communicates a pulse complete (“PC”) indication to theaggregate logic block516. In the example shown this occurs at time t1. In response to the receipt of the pulse complete indication from thepulse logic block514, theaggregate logic block516 increments its repeat accumulator value (from 0 to 1 at t1). The repeat accumulator value is initialized to zero prior to the execution of each new aggregate instruction and represents the number of times that a specified pulse has been executed for the current aggregate instruction.Aggregate logic block516 then compares its repeat accumulator value (1) to the repeat setting (2) and determines that, because the repeat accumulator value is still less than the repeat setting, the pulse specified is to be repeated. Accordingly theaggregate logic block516 provides the pulse memory address that is specified as the aggregate start address (X) to thepulse logic block514 again. Because there hasn't been a change in the aggregate instruction as a result of the pulse completion (i.e., the repeat accumulator value has not reached the repeat setting), the steering address is unchanged and is therefore not provided to thesteering logic block512 again. In response to the receipt of the pulse memory address, thepulse logic block514 sequentially executes the instructions from pulse memory address X to pulse memory address X+5 in the same manner as before. When thepulse logic block514 completes the execution of the instruction at pulse memory address X+5 (which corresponds to the last phase in pulse program A), the pulse logic block540 again issues a pulse complete signal to theaggregate logic block516. In the example shown this occurs at time t2.

As before, theaggregate logic block516 increments its repeat accumulator value (from 1 to 2 at t2) and compares the incremented value to the repeat setting. In this instance, the repeat accumulator value is equal to the repeat setting, which signifies the completion of the current aggregate instruction. As a result, theaggregate logic block516 determines whether its current address is equal to the aggregate end address. If the current aggregate address is equal to the aggregate end address, theaggregate logic block516 reverts to the aggregate start address, but if the current aggregate address is not equal to the aggregate end address, theaggregate logic block516 increments the aggregate address. In either case, theaggregate logic block516 additionally increments its aggregate accumulator value, which value represents the number of aggregate instructions that have been executed since thePDC171 was enabled. Because, in this case, the current aggregate address (Y) is not equal to the aggregate end address (Y+1), theaggregate logic block516 increments its address value and retrieves and decodes the instruction stored at the incremented address value (Y+1) of theaggregate memory506.

As illustrated inFIG. 11, the instruction stored at aggregate memory location Y+1 links pulse program A (which begins at pulse address X) and steering program B for 5 repetitions. Theaggregate logic block516 stores the repeat setting (5) and provides the pulse memory address (X) to thepulse logic block514 and the steering memory address (steering program B corresponds to address10) to thesteering logic block512, which logic blocks retrieve the microcode from the respective addresses. While the aggregate instruction at address Y specifies the same pulse memory starting address (X) as does aggregate instruction at address Y+1, this will not always be the case. For example, the transition between aggregate instructions at addresses Y+1 and Y+2 results in the execution of a different pulse program. Thus, while the example illustrated inFIG. 13 depicts the execution of the same pulse program after a transition between aggregate instructions, such transition may commonly result in the provision of an entirely different pulse memory address to thepulse logic block514.

As will be understood from the diagram inFIG. 13, aggregate instructions are executed by theaggregate logic block516 as an outer loop program, which specifies the parameters of an inner loop program. The parameters of the inner loop program that are specified by the outer loop program include the pulse memory address and the steering memory address. The inner loop program is executed by thepulse logic block514 in conjunction with thesteering logic block512. As will be understood, the sequencing provided by the outer loop and inner loop programs ensure that the active instructions are referenced by the respective logic blocks at any given time. As will be described below, this sequencing operation enables the control signals that are provided to theDAC circuitry172 to be determined at a given time based upon the active instructions. It should also be appreciated that, as described above, the sequencing operations that are performed by thestimulation circuitry170 do not rely on themicrocontroller150. Therefore, sequencing can be performed while themicrocontroller150 operates in the reduced-power mode, which saves power in the IPG.

FIG. 14 shows the pulse pattern at electrodes E1, E2, and E3 as a result of the execution of the example aggregate program inFIG. 13. During execution of the aggregate instruction at memory location Y, pulse program A is repeated twice with 100% of the stimulation anodic current being delivered to electrode E1 and 100% of the stimulation cathodic current being delivered to electrode E2. During execution of the aggregate instruction at memory location Y+1, pulse program A is repeated five times with the stimulation anodic current being shared between electrodes E1 and E2 at 40% and 60%, respectively, and 100% of the stimulation cathodic current being delivered to electrode E3. As indicated, theaggregate logic block516 repeatedly loops through the instructions between the aggregate start address (Y) and the aggregate end address (Y+1) as long as PDC171(1) is enabled.

A beneficial aspect of theimproved stimulation circuitry170 is that each ofmultiple PDCs171 can access the instructions in theaggregate memory506, thepulse memory504, and thesteering memory502. In the standard current mode, each of thedifferent PDCs171 can access the same library of aggregate instructions and generate different stimulation patterns simultaneously. In the example inFIG. 14, at the same time PDC171(1) executes the aggregate instructions between addresses Y and Y+1, PDC171(2) executes the aggregate instructions between addresses Y+2 and Y+5. During execution of the aggregate instruction at memory location Y+2, pulse program B is repeated 13 times with 100% of the stimulation anodic current being delivered to electrode E4 and 100% of the stimulation cathodic current being delivered to electrode E5. During execution of the aggregate instruction at memory location Y+3, pulse program A is repeated five times with 100% of the stimulation anodic current being delivered to electrode E4 and 100% of the stimulation cathodic current being delivered to electrode E5. During execution of aggregate instruction at memory location Y+4, pulse program C is repeated five times with 100% of the stimulation anodic current being delivered to electrode E4 and the stimulation cathodic current being shared between electrodes E5 and E6 at 80% and 20%, respectively. During execution of the aggregate instruction at memory location Y+S, pulse program B is repeated seven times with 100% of the stimulation anodic current being delivered to electrode E4 and the stimulation cathodic current being shared between electrodes E5 and E6 at 80% and 20%, respectively. While a single sequence of the execution of the aggregate instructions between memory locations Y+2 and Y+5 is shown inFIG. 14, PDC171(2) would repeatedly execute this sequence as long as PDC171(2) is enabled in the same manner as described above with respect to PDC171(1).

While stimulation can be provided simultaneously by thePDCs171, the allocation of current during an active phase to the same electrode bydifferent PDCs171 may be prevented (unless arbitration is enabled for thePDCs171 as described below). This may be accomplished in different ways such as preventing the assignment of a steering program having an overlapping electrode to two different PDCs or by allowing the assignment of steering programs with overlapping electrodes to twodifferent PDCs171 if it can be determined that no current will be allocated to the overlapping electrodes simultaneously during an active phase (i.e., the frequency, etc. prevent any actual conflict). These preventions may be implemented in external software such as software in a clinician's programmer that causes themicrocontroller150 to write the instructions and configuration parameters to the memory circuitry. For example, if a user attempts to define a program that would result in the allocation of current to the same electrode during an active phase by twodifferent PDCs171, the external software may prevent communication of the program to the IPG or require the enablement of arbitration for the twoPDCs171.

A notable exception to the prevention of the allocation of current by twodifferent PDCs171 to a single electrode simultaneously is that the case electrode is allowed to receive such overlapping currents. The sharing of current delivered by multiple PDCs is described in U.S. Patent Publication 2016/0184591, which is incorporated herein by reference. The ability to allow the case electrode to receive current based on the operation ofdifferent PDCs171 simultaneously requires a few configuration changes. First, a “shared case” bit in theconfiguration memory508 causes status flags that are generated when twoPDCs171 allocate current to the same electrode simultaneously to be blocked for the case electrode to prevent the unnecessary status flags. Additionally, one of the PDAC/NDAC172p/172npairs is selected for supply of the reference voltage Vref to the case electrode'soperational amplifier180.

FIG. 13 described some of the basic parameters of theconfiguration memory508 that are utilized by aPDC171 during the execution of an aggregate program. An example arrangement of these parameters as well as other configuration parameters is illustrated inFIG. 15. These configuration parameters include adjustment parameters that adjust the timing or amplitude parameters defined by a pulse program. The enable, aggregate start address, and aggregate end address values discussed in reference toFIG. 13 are stored in a first configuration memory location asbit0, bits8-15, and bits16-23, respectively. The first configuration memory location additionally stores an arbitration enable bit (bit1) and an arbitration mode bit (bit2). These arbitration parameters, when implemented, modify the timing of stimulation delivery between thevarious PDCs171 as described in greater detail below. The first configuration memory location additionally stores an amplitude scale value in bits24-31. The amplitude scale value is a multiplier between 0 and 1 (with 255 units of resolution) that modifies the amplitude of stimulation as compared to the value defined in a pulse instruction. This functionality is described below.

The second configuration memory location includes the parameters of a ramp start feature and a ramp repeat feature. These features, when implemented, cause the amplitude of the current generated by theDAC circuitry172 to be increased to a desired maximum over a specified number of steps. The ramp start feature is applied to a sequence of pulses immediately following the enablement of thePDC171. The ramp repeat feature is implemented for each execution of a new aggregate instruction following the last pulse in the ramp start group of pulses. In all other aspects, these ramp features operate in the same manner and have the same parameters, which include an enable bit (bits0 and12), a step size (bits1-3 and13-15), and a division factor (bits4-11 and16-23). The enable bit specifies whether the feature is implemented. The step size parameter is set to one of eight values that represent the number of steps over which the ramp scale value is increased. For example, the step size parameter may specify two, four, eight, 16, or 32 steps to full amplitude. The division factor parameter specifies the number of pulses at each step. The ramp features are described in detail below.

The second configuration memory location additionally includes a burst enable bit (bit24) and a burst period value (bits25 through26). The burst enable bit determines whether a burst feature is implemented. The burst feature, when implemented, toggles thePDC171's enable bit on and off at specified intervals. The burst period value specifies one of four period values (e.g., 6.25 ms, 50 ms, 100 ms, and 200 ms). The burst on and off values in the third configuration memory location specify the number of the burst periods during which thePDC171's enable bit will be on (bits0-15) and off (bits16-31). The sixteen bits in each of the on and off values enable the specification of between 0 and 65535 burst periods.

The fourth configuration memory location includes an arbitration holdoff value (bits0-15) that specifies the number of clock cycles associated with aPDC171's arbitration feature, which is described below. The fourth configuration memory location additionally includes a start delay value (bits16-31), which specifies the number of clock cycles after thePDC171's enable bit is set that the execution of the specified aggregate instruction is initiated. The start delay value may be useful, for example, for staggering stimulation betweenPDCs171 when thePDCs171 are enabled at the same time. Note that the values in each of the four configuration memory location described with reference toFIG. 15 are specific to aparticular PDC171. Therefore, these parameters exist for each of thePDCs171 at different memory location and can contain different values that are relevant only to thePDC171 to which the parameters apply.

FIG. 16 illustrates an example of the manner in which the arbitration feature modifies the timing of stimulation delivery for twoPDCs171 that have enabled arbitration. In the example shown, PDC171(1) is configured to execute a single aggregate instruction that specifies three repetitions of pulse program A and PDC171(2) is configured to execute a single aggregate instruction that specifies four repetitions of pulse program B. While these simple pulse patterns are selected for purposes of illustration, the arbitration feature is not so limited and can be enabled where aPDC171 is configured to execute an aggregate program having multiple aggregate instructions and for more than twoPDCs171.

The arbitration feature can be utilized to prevent stimulation generated by afirst PDC171 from overlapping with stimulation generated by asecond PDC171 when the arbitration feature is enabled for both the first andsecond PDCs171. Note that enablement of the arbitration feature does not prevent all other stimulation during the delivery of arbitrated stimulation but only the execution of other stimulation that is also arbitrated. The arbitration feature may be valuable for enabling the delivery of stimulation waveforms from two or moredifferent PDCs171 to overlapping sets of electrodes. By enabling arbitration for each of thePDCs171 that are configured to deliver stimulation to one or more common electrodes, it can be ensured that there is no simultaneous delivery of stimulation to a single electrode fromdifferent PDCs171.

When aPDC171's arbitration feature is enabled, thePDC171 requests approval from anarbitration manager block1602 before it proceeds. Thearbitration manager block1602 is part of thestimulation circuitry170 and is common to all of thePDCs171. The timing of the stimulation request from thePDC171 is dependent upon the selected arbitration mode. In the aggregate arbitration mode, thePDC171 requests approval prior to executing an aggregate instruction. Upon the grant of approval, thePDC171 executes the full aggregate instruction. This is illustrated in the aggregate mode portion ofFIG. 16.

At time t0, PDC171(1) communicates a request to thearbitration manager block1602. Because there is no active holdoff timer, thearbitration manager block1602 communicates the grant to PDC171(1) at t1 and starts accumulating the holdoff timer. Upon receiving the grant at t1, PDC171(1) executes an aggregate instruction. At t2, PDC171(2) requests approval from thearbitration manager block1602. However, because the holdoff timer associated with the grant to PDC171(1) is active, the request from PDC171(2) is queued. At t3, PDC171(1) completes the execution of the aggregate instruction and communicates a request to execute the subsequent aggregate instruction (in this case the same aggregate instruction as the aggregate program is only one instruction in length) to thearbitration manager block1602. Because the holdoff timer associated with PDC171(1) is still active and the request from PDC171(2) is already in the queue, PDC171(1)'s request is queued behind the request from PDC171(2). At t4, when the accumulated holdoff time is equal to the value specified in the PDC171(1) configuration settings, thearbitration manager block1602 communicates a grant to PDC171(2) and begins accumulating the holdoff timer associated with the grant to PDC171(2). Upon receiving the grant at t4, PDC171(2) executes its aggregate instruction. This process repeats with eachPDC171 executing a full aggregate instruction at a time.

The pulse arbitration mode functions similarly to the aggregate arbitration mode except that eachPDC171 requests approval from thearbitration manager block1602 prior to the execution of a single pulse. This is illustrated in the pulse mode portion ofFIG. 16. Like the aggregate arbitration mode example, at t0, PDC171(1) communicates a request to thearbitration manager block1602, and, because there is no active holdoff timer, thearbitration manager block1602 communicates the grant to PDC171(1) at t1 and starts accumulating the holdoff timer. However, upon receiving the grant at t1, PDC171(1) executes a single pulse rather than a full aggregate instruction. At t2, PDC171(2) requests approval from thearbitration manager block1602. However, because the holdoff timer associated with the grant to PDC171(1) is active, the request from PDC171(2) is queued. At t3, PDC171(1) completes the execution of the pulse and communicates a request to execute the subsequent pulse to thearbitration manager block1602. Because the holdoff timer associated with PDC171(1) is still active and the request from PDC171(2) is already in the queue, PDC171(1)'s request is queued behind the request from PDC171(2). At t4, when the accumulated holdoff time is equal to the value specified in the PDC171(1) configuration settings, thearbitration manager block1602 communicates a grant to PDC171(2) and begins accumulating the holdoff timer associated with the grant toPDC2. Upon receiving the grant at t4, PDC171(2) executes a single pulse. This process repeats with each PDC executing a single pulse at a time. While the examples shown illustrate twoPDCs171 that each operate in the same arbitration mode, this is not necessary and arbitration can also be implemented with different PDCs operating in different arbitration modes.

In a preferred embodiment, arbitration processing is handled on the PDC side by theaggregate logic block516. In such an embodiment, theaggregate logic block516 communicates the arbitration request to thearbitration manager block1602 when its repeat accumulator equals its repeat setting for aggregate mode arbitration and upon receipt of a pulse complete communication from the pulse logic block for pulse mode arbitration. In either case, theaggregate logic block516 delays communication of the pulse and steering addresses to thepulse logic block514 andsteering logic block512 until it receives the arbitration grant from thearbitration manager block1602. It will be noted that aPDC171's holdoff time setting should meet or exceed the time period of the longest pulse that it is configured to execute for pulse mode arbitration and the time period of the sequence of pulses associated with the longest aggregate instruction that it is configured to execute for aggregate mode arbitration in order to ensure that there is no overlap with any other arbitratedPDC171. Thearbitration manager block1602 may be configured to resolve simultaneous arbitration requests. For example, thearbitration manager block1602 may always give preference to the lowest numberedPDC171.

FIG. 17 illustrates the operation of aPDC171's amplitude scale value. As illustrated, the amplitude scale value is applied to each pulse phase of a pulse program. Thus, if the microcode for a particular pulse phase specifies an amplitude of 10 mA and thePDC171 has a 50% amplitude scale value, the control signal output from thePDC171 to theDAC circuitry172 will represent a current value of 5 mA. The amplitude scale value enables a pulse program stored in thepulse memory504 to be tailored to a particular need as opposed to creating a new pulse program. For example, assume that pulse program B is configured with a stimulation amplitude of 10 mA. Pulse program B can be utilized by PDC171(1) at its full value (100% amplitude scale value) to deliver a sine wave pattern of stimulation that fluctuates between −10 mA and 10 mA and can also be utilized by PDC171(2) at 25% of its full value (25% amplitude scale value) to deliver a sine wave pattern of stimulation that fluctuates between −2.5 mA and 2.5 mA. Without the amplitude scale value, a new pulse program would need to be created in order to enable the stimulation pattern provided by stimulation circuit171(2), which additional pulse program would require 58 additional pulse instructions in thepulse memory504.

FIG. 18 illustrates the effects of the ramp start and ramp repeat features. Each stimulation pattern1800 includes afirst portion1802 that represents execution of an aggregate instruction that specifies 16 repetitions of pulse program A, asecond portion1804 that represents execution of an aggregate instruction that specifies a delay period, and athird portion1806 that represents execution of an aggregate instruction that specifies 12 repetitions of pulseprogram B. Portion1802 is executed immediately after thePDC171 is enabled.

The ramp start and ramp repeat features each act to slowly increase the amplitude of pulses in a sequence of pulses defined by an aggregate program to the full normal value (as specified by the pulse instruction and any applied amplitude scale value). Both the ramp start and ramp repeat features include a step size parameter and a division factor parameter. The step size parameter specifies the number of steps over which the pulses in a series are increased to the full normal value. For example, for a step size of eight, the amplitude of the pulse or pulses in the first step would be scaled to 12.5%, the amplitude of the pulse or pulses in the second step would be scaled to 25%, and so on. The division factor value specifies the number of pulses in each step. Together, the step size parameter and the division factor parameter specify the number of pulses (the product of the step size parameter and the division factor parameter) in a group of pulses in a pulse sequence to which the scale factor is to be applied and the number of sub-groups (or step groups) within the group. For example, a step size parameter of two and a division factor parameter of five defines a group of 10 pulses to which the ramp scale factor is to be applied and two sub-groups within the group. Note that the ramp scale factor applied to the last sub-group is equal to one and therefore the amplitude of the pulses in that sub-group are not modified from the amplitude defined by the pulse program and any amplitude scale factor. Nonetheless, the pulses in the last sub-group are still considered to be in the group.

The ramp scale factor (which is a separate scale factor applied in addition to any amplitude scale) can be calculated as the step number divided by the step size parameter for any pulse within the group to which the ramp scale factor applies. The step number can be calculated based on a pulse's sequential position within the group (i.e., the first pulse in the group is pulse one, the second pulse in the group is pulse two, etc.) divided by the division factor with non-integer values rounded up to the next integer. For example, the seventh pulse in a group having a step size parameter of four and a division factor parameter of four would have a step number of two (i.e., 7/4=1.75 rounded up to 2), which would result in a ramp scale factor of 50% (i.e., step number/step size= 2/4=50%). Similarly, the seventh pulse in a group having a step size parameter of four and a division factor parameter of three would have a step number of three (i.e., 7/3=2.33 rounded up to 3), which would result in a ramp scale factor of 75% (i.e., step number/step size=¾=75%). While the ramp features are described and illustrated as being used to increase the amplitude at various steps over a group of pulses, the ramp features could also be utilized to decrease the amplitude at various steps over a group of pulses (e.g., from a full amplitude defined by a pulse program to zero). For example, while the ramp start feature may increase the amplitude at the beginning of a sequence of pulses, the ramp repeat feature may either increase the amplitude over a group of pulses corresponding to a new instruction or the ramp repeat may decrease the amplitude over a group of pulses (e.g., decrease sequentially at each sub-group).

In thestimulation pattern1800A, neither the ramp start nor the ramp repeat feature is enabled. In the second stimulation pattern1800B, the ramp start feature is enabled with a step size parameter of four and a division factor parameter of two, and the ramp repeat feature is disabled. In thethird stimulation pattern1800C, the ramp start feature is enabled with a step size parameter of eight and a division factor parameter of one, and the ramp repeat feature is disabled. In the fourth stimulation pattern1800D, the ramp start feature is enabled with a step size parameter of four and a division factor of three, and the ramp repeat feature is enabled with a step size parameter of four and a division factor parameter of one. Although the ramp repeat feature is only illustrated as being applied toportion1806, it would also be applied to any pulses defined by a new aggregate instruction following the last pulse in a group of pulses to which a ramp feature (either ramp start or ramp repeat). The fifth stimulation pattern1800E shows that a ramp feature define a group of pulses that extends across aggregate instructions. In the fifth stimulation pattern1800E, the ramp start feature is enabled with a step size parameter of four and a division factor parameter of six, and the ramp repeat feature is also enabled. Note that the group of pulses in the pulse sequence to which the ramp start scale factor applies extends into theportion1806, which is defined by a different aggregate instruction than theportions1802 and1804. Specifically, the first sub-group in the ramp start group includes the first six pulses (all of which are inportion1802 and which are applied with a ramp scale factor of 25%), the second sub-group in the ramp start group includes pulses7-12 (all of which are inportion1802 and which are applied with a ramp scale factor of 50%), the third sub-group of pulses in the ramp start group includes pulses13-18 (four of which are in theportion1802 and two of which are in theportion1806 and which are all applied with a ramp scale factor of 75%), and the fourth sub-group of pulses in the ramp start group includes pulses19-24 (all of which are inportion1806 and which are applied with a ramp scale factor of 100%). Note that even though the ramp repeat feature is enabled, it is not applied to any of the pulses in theportion1806 because the ramp repeat feature is applied only to a group of pulses defined by a new aggregate instruction following the last pulse in a particular ramp group. Thus, the ramp repeat feature would be applied in the example sequence1800E to a first group of pulses defined by an aggregate instruction executed after the aggregate instruction corresponding to portion1806 (which may be the aggregate instruction corresponding to theportion1802 in a subsequent execution of the aggregate program, for example).

FIG. 19 illustrates the effects of the burst feature. When the burst feature is enabled, thePDC171's enable bit is toggled on and off in accordance with the burst on and burst off time parameters. When thePDC171's enable bit is toggled on, a burst timer in thePDC171 begins counting. When the burst timer reaches the burst on setting, the enable bit is toggled off and the burst timer is reset and begins counting again. When the burst timer reaches the burst off setting, the enable bit is toggled back on. This pattern continues such that stimulation is delivered by thePDC171 in bursts during the burst on periods.

Having described the microcode structure and configuration settings as well as their processing via the relevant logic blocks in thePDCs171, we now discuss the generation of the control signals that are passed to theDAC circuitry172. The primary function of thestimulation circuitry170 is to deliver control signals to theDAC circuitry172 at the appropriate times. As described above, theaggregate logic block516,pulse logic block514, andsteering logic block512 manage the sequencing of instructions such that the appropriate instruction is referenced at any given time. For example, the active pulse instruction is referenced by the address parameter of thepulse logic block514 and the active steering program is referenced by the address parameter of thesteering logic block512. The control signals are a function of the instructions and can therefore be generated based on the parameters of the active instructions. Referring toFIG. 5A, the primary control signals generated by thePDCs171 are the branch switch control signals <C> and the current amplitude control signals <J>. EachPDC171 additionally asserts the passive recovery bit P during execution of a delay phase for which passive recovery is specified. The control signal K is issued globally by the stimulation circuitry170 (i.e., it is not issued by any particular PDC171), and its function is described below. Additional control signals issued by the stimulation circuitry include the signals to enable theoperational amplifiers168 and180 as described above.

FIGS. 5B and 5C illustrate the structure of anexample DAC circuit172 that can be controlled by thestimulation circuit170. Theexample DAC circuit172 is described in detail in U.S. Provisional Patent Application Ser. No. 62/393,003, filed Sep. 10, 2016, which is incorporated herein by reference in its entirety. Because theDAC circuit172 is described fully in that related application, its structure is only summarized here for the purpose of illustrating the utilization of the control signals issued by thestimulation circuitry170. As shown inFIG. 5B, theDAC circuitry172 includes four different stages, each stage including aPDAC172pand anNDAC172n. Each of these four stages is, in the standard current mode, linked to one of thePDCs171 such that eachPDC171 controls a designated PDAC/NDAC pair172p/172n. Note that control signal K described above is distributed to each of thePDACs172pandNDACs172n. In addition to the control signals illustrated inFIG. 5A, each of thePDACs172pandNDACs172nreceives a control signal <R>, which signal is relevant to trimming a specific component of theDAC circuitry172 and is not relevant to the function of thePDCs171. ThePDACs172pandNDACs172nmay additionally receive passive recovery signals <Rec> (not shown), which are generated as a function of the signals <P> and a specified passive recovery mode. Generation of the passive recovery signals <Rec> is described in detail in U.S. Provisional Patent Application Ser. No. 62/393,007, filed Sep. 10, 2016, which is incorporated herein by reference in its entirety.

In the illustrated embodiment, thePDACs172p1-4 are coupled to a compliance voltage VH, which is formed at the compliancevoltage generator block76 on the ASIC160 (FIG. 4B). TheNDACs172n1-4 are coupled to ground (GND). Notice that corresponding electrode outputs of each of thePDACs172p1-172p4 and corresponding electrode outputs of each of theNDACs172n1-172n4 are connected together, and connected to its corresponding electrode node (E1′-Ec′)61a. This allows each of the PDACs to source a current to any of the electrode nodes (thus establishing an anode electrode) and each of the NDACs to sink a current from any of the electrode nodes (thus establishing a cathode electrode). More than one anode electrode and more than one cathode electrode can be established at a given time.

FIG. 5C shows the circuitry details for one of theNDACs172n1 that is used to sink current from the electrode nodes, thus allowing electrodes coupled to those nodes to operate as cathodes.NDAC172n1 receives control signals <Jn1> and <Cn1> from its associated PDC171(1).NDACs172n2-4 would be similar in construction, although they would receive different control signals from their PDCs171(2)-(4).PDACs172p1-4 would have a similar basic construction, although the circuitry would be “inverted.” For example, current producing portions of thePDAC172p1 are coupled to the compliance voltage VH instead of ground, thus allowing thePDAC172pto source current to theelectrode nodes61a. Further, the polarity of many of the transistors is changed from N-channel devices to P-channel devices. Otherwise, and as one skilled in the art will understand, the PDAC functions similarly to theNDAC172n1 ofFIG. 5C.

Input to theNDAC172n1 is a reference current Iref provided by a referencecurrent source195. Note inFIG. 5B that this reference current can be provided to each of theNDACs172n1-4 andPDACs172p1-4. The reference current Iref is mirrored by a well-known current mirror configuration into atransistor174. The reference current Iref is further mirrored fromtransistor173 into transistor(s)186 incircuit185 to produce an amplified current J*Iref atnode164. The value of the scalar J depends on the number oftransistors186 that are selectively included in the current mirror, which is adjustable in accordance with control signals <Jn1>. In this regard, becausecircuit185 plays a significant role in setting the analog current in accordance with digital control signals <Jn1>,circuit185 itself comprises a DAC within each ofPDACs172nandNDAC172nand is referred to as a master DAC.

The amplified current J*Iref passes through aresistance block187, formed in this example by M (e.g., four) paralleled transistors188 (only one is shown). Included in series with eachtransistor188 is a selection transistor, one of which is always on. A control signal Kn1 (which is generated from signal K) controls the other selection transistors. Kn1 is not asserted in the standard current mode, but is asserted in the high resolution current mode. When Kn1 is asserted in the high resolution mode, alltransistors188 are placed in parallel.

The gate oftransistors188 in theresistance block187 are connected atnode166 to the gates ofseveral branch transistors184, each of which is connected to a column ofswitches178 inswitch matrix190. Notice thattransistors188 and184 are not coupled in a current mirror configuration (gate node166 is not coupled tonode164 as would occur in a current mirror configuration; comparetransistors173 and174). Rows of theswitches178 in theswitch matrix190 are connected tonodes191 in each of the electrodes' output paths. In the example shown, there are 25branch transistors184, and 33 electrode nodes (E1′ through E32′ and Ec′), and thus switchmatrix190 comprises 25 times 33 switches and control signals <Cn1> to control each. Of course, differing numbers of branch transistors and electrode nodes could also be used.

Switch matrix190 allows current to be provided to one or more selected electrodes with eachbranch transistor184 providing a single “unit” of current. For example, assume it is desired to sink L (e.g., three) units of current from electrode E2. This can be accomplished by asserting any L of the control signals <Cn1> that service electrode node E2′ (e.g., C_1,2, C_2,2, and C_3,2; again, any L control signals C_X,2could be asserted). This would allow L branch transistors (e.g.,184(1),184(2) and184(3)) to each sink a unit of current from E2′, and which in sum sinks three units of current from E2′. The 25 branch transistors enable the provision of 25 “units” of current, with each being directed to one selectedelectrode node61a. Thus, the full amount of current provided byDAC172n1 can be sunk from a single electrode by selecting all 25 of that electrode's control signals <Cn1> or from multiple electrodes by selecting other electrodes' control signals <Cn1>. In any event, each branch would sink 4% of the total current that is provided by theDAC172n1. Current can be sourced to one ormore electrode nodes61ain a similar manner in aPDAC172p.

The magnitude of the “unit” of current that is provided through eachbranch transistor184 can be calculated as: Ibranch=Z*J*Iref, where Z is a ratio that is based on the properties of thetransistors188 and184 and the number oftransistors188 that are asserted. The properties of thetransistors188 and184 are fixed, and therefore the ratio Z only changes as a function of the number oftransistors188 that are asserted, which is determined based on the assertion of the control signal Kn1. In a preferred embodiment, Ibranch is four times greater in the standard current mode than in the high resolution current mode (i.e., Z_standard=4*Z_high), although other ratios could also be employed.

In high resolution current mode, each of thePDCs171 executes the same aggregate instructions in unison. Thus, each of thePDCs171 outputs the same current amplitude signals <J> (i.e., <Jp1>=<Jn1>=<Jp2>, etc.). Because Kn1 is asserted, the current, Ibranch, through each of thetransistors184 in each of thePDACs172pandNDACs172nis one-fourth of the value of Ibranch without Kn1 asserted. While each PDAC/NDAC pair172p/172ncan only deliver one-fourth of the current that it can provide in the standard current mode, the four pairs operating in unison can provide the same amount of current as can be provided from a single pair in the standard current mode. Moreover, this current is provided in “units” of Ibranch that are one-fourth the value of the standard current mode “unit,” but with the ability to select up to four times the number of branch switches178 (i.e.,100 source branch switches178 across the fourPDACs172pand100 sink branch switches178 across the fourNDACs172n). This enables the delivery of current with a higher degree of resolution. For example, assume it is desired to split the anodic current between electrodes E1 and E2 with exactly 50% of the current delivered to each. This division cannot be accomplished in the standard current mode, because thePDAC172ponly enables allocation of current in 4% intervals. The closest allocation that could be accomplished in the standard current mode would deliver 48% of the current to one of the electrodes (12branch switches178 asserted) and 52% of the current to the other electrode (13branch switches178 asserted). In high resolution mode, however, thePDCs171 could all process the same aggregate instructions in unison with 50 branch switches directing current to electrode E1 (e.g., all of the E1 switches inPDACs172p1 and172p2) and the remaining 50 branch switches directing current to E2 (e.g., all of the E2 switches in172p3 and172p4). Note that this requires the allocation of switches across multiple PDAC/NDAC pairs, where such pairs are dedicated to asingle PDC171 in the standard current mode. This allocation is accomplished by theelectrode combiner520 illustrated inFIG. 5A. Theelectrode combiner520 is a logic block that determines which signals <C> to deliver to theDAC circuitry172.

As described above, in the standard current mode, only the upper five bits in the current allocation portion of the steering program for each electrode are utilized. These five bits define the number of branch switches178 (out of a maximum of 25) that are closed for each electrode. In the standard current mode, theelectrode combiner520 determines which of aPDC171'scorresponding PDAC172pandNDAC172nbranch switches are to be closed. For example, theelectrode combiner520 may receive an E1 signal “010100” (80% anode) and an E2 signal “000100” (20% anode) from PDC171(1), where the first bit indicates that each of E1 and E2 operate as anodes and the remaining five bits specify that 20 E1 branch switches178 are to be closed and five E2 branch switches178 are to be closed. In response, theelectrode combiner520 issues control signals <Cp1> to close the appropriate number of branch switches for each of E1 and E2 in thePDAC172p1. The particular branch switches178 that are to be closed can be determined in different ways. For example, theelectrode combiner520 may close the specified number of branch switches178 for each electrode in electrode number and branch switch number order (e.g., close C_1,1through C_20,1and C_21,2through C_25,2in the above example).

In the high resolution current mode, all seven bits in the current allocation portion of the steering program for each electrode are utilized. These seven bits define the number of branch switches178 (out of a maximum 100) that are closed for each electrode, which branch switches can span across different PDAC/NDAC pairs. In the high resolution current mode, theelectrode combiner520 allocates the branch switches178 across multiple PDAC/NDAC pairs. For example, theelectrode combiner520 may receive an E1 signal “01010011” (83% anode) and an E2 signal “00010001” (17% anode) from PDC171(1), where the first bit indicates that each of E1 and E2 operate as anodes and the remaining seven bits specify that 83 E1 branch switches178 are to be closed and 17 E2 branch switches178 are to be closed. Note that the electrode allocation signals may also be received fromother PDCs171 but will necessarily be redundant because thePDCs171 operate in unison in high resolution current mode.

As the 83 and 17branch switches178 obviously span acrossmultiple PDACs172p(because eachPDAC172pincludes just 25 switches178), theelectrode combiner520 determines which switches are to be closed and sends the appropriate signals to thePDACs172p. For example, theelectrode combiner520 may send the signals <Cp1>, <Cp2>, and <Cp3> instructingPDACs172p1,172p2, and172p3 to close all 25 E1 branch switches178 and signal <Cp4> instructingPDAC172p4 to close 8 E1 branch switches178 and 17 E2 branch switches. As in the standard current mode, the particular branch switches178 that are to be closed can be determined in different ways. For example, theelectrode combiner520 may close the specified number of branch switches178 for each electrode in electrode number, PDAC/NDAC number, and branch switch number order.

FIG. 20 summarizes the control signals <J> and <C> that are generated in different scenarios. In the standard current mode, the control signals <Cp> and <Cn> instruct theDAC circuitry172 to open allbranch switches178 during any delay phase (i.e., when thepulse logic block514 asserts the delay “D” signal). During a stimulation active phase instruction, the <Cp> signals are determined on the basis of the upper five bits of the steering program's allocation range for any electrode identified as a stimulation anode and the <Cn> signals are determined on the basis of the upper five bits of the steering program's allocation range for any electrode identified as a stimulation cathode. During an active recovery active phase instruction, the <Cp> signals are determined on the basis of the upper five bits of the steering program's allocation range for any electrode identified as a stimulation cathode and the <Cn> signals are determined on the basis of the upper five bits of the steering program's allocation range for any electrode identified as a stimulation anode. Note that the polarity reversal between the stimulation and active recovery scenarios is accomplished as a result of the assertion of the reverse polarity “RP” signal by thepulse logic block514. The polarity reversal may be implemented in thesteering logic block512 such that the instructions provided to theelectrode combiner520 correctly identify the intended anode and cathode. Alternatively, the “RP” signal may be passed through to theelectrode combiner520 along with the original steering program microcode such that theelectrode combiner520 can itself implement the polarity reversal logic. For all phases other than a normal delay phase, the <Jp> and <Jn> control signals are determined by multiplying the amplitude value specified by the pulse instruction with thePDC171's amplitude scale value and ramp scale value. The resulting value is the stimulation amplitude (i.e., the total amount of current that thePDAC172psources and that theNDAC172nsinks). For example, if an active phase instruction specifies a 10 mA amplitude and thePDC171 has an amplitude scale value of 50%, and the ramp scale value is calculated as 75%, the <Jp> and <Jn> signals are set to 10*0.5*0.75=3.75 mA, which causes thePDAC172pto source 3.75 mA and theNDAC172nto sink 3.75 mA through the selected electrodes. During a normal delay phase, the <Jp> and <Jn> signals are set to zero. In the high resolution current mode, the control signals differ only in that <Cp> and <Cn> are determined on the basis of all seven bits of the steering program's allocation range during any stimulation or recovery phase. As will be understood, the format of the control signals is dependent upon the structure of theDAC circuitry172. While anexample DAC circuit172 was illustrated, thestimulation circuitry170 is not limited to any particular DAC structure.

Having described thestimulation circuitry170, we turn now to themeasure circuitry167 as depicted inFIG. 21, which controls the sample and holdcircuitry168 and the A/D circuitry166 to measure analog signals and to store digitized values of the measured analog signals in the memory624 (which may be a first in, first out (FIFO) memory), which values may be accessed, for example, by themicrocontroller150 to control various operations of the IPG. Thememory624 is part of the memory circuitry of the IPG. The sample and holdcircuitry168 selects from analog values on the analog bus67 and is particularly useful in calculating the resistance between two electrodes as well as other voltages of interest during biphasic or monophasic pulsing. As will be understood, the desired measurements must be coordinated with the delivery of stimulation by thestimulation circuitry170. Such coordination is complicated by the flexibility of thestimulation circuitry170, which, as described above, enables non-arbitrated stimulation acrossmultiple PDCs171. In order to ensure that measurements are collected at the appropriate times,measure circuitry167 includes a measure logic block612 that processes measure microcode stored inmeasure memory602 to generate control signals that are issued to the sample and holdcircuitry168 and theADC622. In its operation, the measure logic block612 additionally retrieves and stores values in avariable memory604 and asteering memory606, whichsteering memory606 is utilized to populate thesteering memory502 in thestimulation circuitry170 as described below.

Before describing the structure of the measure instructions and the operation of the measure logic block612 in processing such instructions, it is useful to describe the operation of the sample and holdcircuitry168 in providing an analog value to theADC622.FIG. 22 illustrates the components of the sample and holdcircuitry168 and A/D circuitry166. In the disclosed embodiment, selection of analog signals from the analog bus67 occurs using two multiplexers, MUXA and MUXB. The inputs to each MUX are essentially the same and comprise the electrode voltages (E1-E33); the compliance voltage used by the DAC circuitry172 (VH); and ground (GND). As will be seen in the examples that follow, MUXA is generally used to select a higher voltage, such as an anode electrode or a supply voltage (e.g., VH), while MUXB is generally used to select a lower voltage, such as a cathode electrode or ground. An additional common mode input (CM) can be used during voltage monitoring, and the relevance of this input will be described later. Also, the output of each MUX is sent to the other MUX in case it is of interest to select such other output for a given measurement. Other analog signals of importance within the IPG may be included as inputs to the MUXes, and the inputs shown should not be understood as exhaustive. The input selected by MUXA and MUXB is dictated in accordance with control signals <SEL A> and <SEL B>, respectively. In one embodiment, the <SEL> signals may each comprise seven bits, which enables selection of up to 128 different inputs from a MUX.

Signals selected by the MUXes are held by circuitry that comprises two capacitors, CX and CY and a plurality of switches, S0-S4. Capacitors CX and CY are preferably identical, and may have a capacitance of 4.7 microfarads for example. As will be seen, monitored voltages are impressed or stored on these capacitors CX and CY, with a voltage selected by MUXA being presented to the top plates of CX and CY, and a voltage selected by MUXB being presented to the bottom plates of CX and CY. The switches S0 through S4 are controlled by the signals <S> from the measure logic block612 as described below. Nodes A and B are input to adifferential amplifier632, which outputs their difference (i.e., VA−VB) as ananalog signal634. Additional details regarding the sample and holdcircuitry168 can be found in U.S. Pat. No. 9,061,140, which is incorporated herein by reference in its entirety.

Thesignal634 is passed to the A/D circuitry166, where it is input intoADC MUX620.ADC MUX620 selects between thesignal634 output from the sample and holdcircuitry168 and other analog signals at different voltage levels, such as Vbat, which additional signals are not impacted by operation of thestimulation circuitry170 and which are therefore not discussed in detail. The input selected by theADC MUX620 is dictated in accordance with control signal <SEL ADC>, which may comprise four bits to enable selection of up to 16 different inputs. The output of theADC MUX620 is provided to theADC622, which digitizes the value at its input to store measurements in thememory624 in accordance with the signal <ADC>, which specifies various parameters for a particular measurement.

FIGS. 23A and 23B illustrate the structure of the measure microcode for different types of instructions that can be executed by the measure logic block612. Each instruction is stored in a single memory location within themeasure memory602. The type of each measure instruction is represented by its upper four bits (bits28-31). This four bit range enables the specification of up to 16 different types of instructions, and the bit range for the type identifier is common for each of the different types of instructions and is therefore not repeated in the description of each specific instruction. The wait instruction specifies a number of clock cycles for which the measure logic block612 is to hold before proceeding to the next measure instruction in thememory602. Bits0-15 of the wait instruction specify the number of clock cycles, bit16 of the wait instruction, when set, instructs the measure logic block612 to issue an interrupt when the wait period is complete, and bit19 of the wait instruction, when set, instructs the measure logic block612 to halt execution.

Whereas the wait instruction causes the measure logic block612 to wait for a specified time period before proceeding to the next instruction, the wait trigger instruction causes the measure logic block612 to wait for a specified number of a specified trigger type from a specifiedPDC171 before proceeding to the next measure instruction. Bits0-11 specify the number of triggers that the measure logic block612 should wait to receive before proceeding to the next measure instruction, bits12-13 specify the type of trigger and bits14-15 specify thePDC171 that applies to the instruction. The four different types of triggers that can be specified by the two-bit trigger type range of the wait trigger instruction are generated by eachPDC171 upon the occurrence of different events during the execution of aggregate and pulse instructions, and the triggers can be communicated to the measure logic block612 via the bus92 or via an off-bus link between thestimulation circuitry170 and themeasure circuitry167.

FIG. 24 illustrates the events that lead to the generation of each of the different types of triggers for the example execution of aggregate instructions by aparticular PDC171. In the example shown, the aggregate program includes a first aggregate instruction (Aggregate1) that specifies a number of repetitions of pulse program B, a second aggregate instruction (Aggregate2) that specifies a number of repetitions of pulse program C, and a third aggregate instruction (Aggregate3) that specifies a number of repetitions of pulse program A. The assigned steering program is not relevant to the generation of the triggers. As illustrated, the aggregate program trigger (Trigger00) is generated when theaggregate logic block516 begins executing the aggregate instruction at the aggregate start address. In the illustrated example, this trigger is generated at the start of the execution of the first aggregate instruction (Aggregate1). The aggregate trigger (Trigger01) is generated when theaggregate logic block516 begins executing a new aggregate instruction. In the illustrated example, this trigger is generated at the start of the execution of the first, second, and third aggregate instructions. The pulse trigger (Trigger10) is generated when thepulse logic block514 begins executing a pulse instruction at an address delivered to it by the aggregate logic block516 (i.e., at the beginning of the execution of a pulse program). The phase trigger (Trigger11) is generated when thepulse logic block514 begins executing any pulse instruction (i.e. at the beginning of the execution of each phase of a pulse program). The wait trigger instruction enables an action to be performed at a particular point during stimulation. For example, if it is desired to take an action at the beginning of the 32^ndphase of the third pulse during the execution of the second aggregate instruction (i.e., the position denoted as2400), a series of wait trigger instructions could be arranged to wait for one occurrence of the aggregate program trigger followed by one occurrence of the aggregate trigger followed by two occurrences of the pulse trigger followed by 31 occurrences of the phase trigger.

Returning toFIG. 23A, the measure instruction passes parameters to the ADC622 (via signals <ADC>) to indicate a number of measurements to store in thememory624. Bits0-11 specify a number of samples to store in thememory624. Bits12-16 specify an accumulate value. The accumulate value specifies a number of measurements to add together to be stored as a single sample. This can be useful, for example, to compute an average value while only storing a single sample in thememory624. While the sample and accumulate values can be entered directly in their respective ranges of the measure instruction,bits17 and18 enable the use of a variable to specify the accumulate and sample values, respectively. When the accumulate and/or sample variable bits are set, the lower four bits of the respective value field (i.e., bits12-15 for accumulate and bits0-3 for sample) provide an address, and the value at the specified address in thevariable memory604 is used as the sample or accumulate value for the measure instruction. The use of variables for the sample and accumulate values enables the same instruction to be repeated with different parameters by updating the values in the specified addresses of thevariable memory604. The use of the lower four bits of the sample and accumulate ranges of the measure instruction as the address assumes that thevariable memory604 contains 16 memory locations. The number of bits used to represent the address can be adjusted to accommodate a different size ofvariable memory604.

The write label instruction causes the measure logic block612 to write the 17-bit value in the label range of the instruction (i.e., bits0-16) to thememory624. This can be used for example, before or after a measure instruction to provide an indicator of what the data preceding or succeeding the label represents. When the label variable bit (i.e., bit17) of the write label instruction is set, the lower four bits of the label range of the instruction are used as an address to retrieve a 12-bit value from thevariable memory604. The upper five bits of the label range of the instruction will be written with the 12-bit value retrieved from thememory604 to thememory624.

The set switches instruction is used to set the <S>, <SEL A>, and <SEL B> values that are passed to the sample and holdblock168. Bits0-4 of the set switches instruction correspond directly to the state of the S0 through S4 switches. Bits5-11 specify the <SEL A> value and bits12-18 specify the <SEL B> value, which values determine which input of the respective MUX is selected. In one embodiment, a defined fixed value in these fields can be used to retrieve the value from a MUX address in thevariable memory604. For example, a decimal value of 126 in either the MUX A or MUX B select fields causes the measure logic block612 to retrieve a value from a MUX A address (e.g., address13) in thevariable memory604 and a decimal value of 127 causes the measure logic block612 to retrieve a value from a MUX B address (e.g., address14) in thevariable memory604.Bit20 is a blanking bit that causes all of the switches in the sample and holdcircuit166 to open for a partial clock cycle before the MUX select and switch S0 through S4 signals go to the values specified in the instruction.

Referring toFIG. 23B, the jump instruction specifies an address in themeasure memory602 to which the measure logic block612 should proceed (either unconditionally or if specified conditions are met). This differs from the processing of other instructions, after which the measure logic block612 simply proceeds to the instruction in the next memory location. Bits0-6 of the jump instruction specify the address in themeasure memory602 to which the measure logic block612 is to proceed. Bits7-9 specify one of a number of different jump conditions, which include an unconditional jump (jump to address immediately), a return jump (jump to address succeeding the address stored in the return field), jump to variable address (use lower four bits of address range of jump instruction as address to retrieve the jump to address value from the variable memory604), different conditional jumps (jump to address if A>B, A<B, A≥B, A≤B, or A=B), and a branch jump (unconditional jump to a specified address that stores the address of the branch jump instruction in the return field such that a subsequent return jump returns to that point). Bits11-14 and15-18 specify the variable A address and the variable B address in thevariable memory604 for use with any of the conditional jump types.Bit19 of the jump instruction enables the value in one of the variable ranges of the instruction to be incremented and bit20 specifies whether the variable A value (bits11-14) or the variable B value (bits15-18) is to be incremented.

The measure configuration instruction sets the parameters of theADC622 according to which a measurement is to be taken. Bits0-11 specify the number of clock cycles to delay before storing a sample in thememory624 during execution of a measure instruction. Bits12-16 specify the number of clock cycles to delay before accumulating a measured value.Bit17 specifies whether the sample delay value should be implemented prior to the first sample being stored. Ifbit17 is set, the sample delay will only be implemented between samples (i.e., not prior to the first sample), but, if it is not set, the sample delay will be implemented prior to storing each sample (even the first sample of a measure instruction).Bit18, when set, implements continuous sampling mode, which causes theADC622 to continuously store measurements in thememory624 until a measure instruction is halted.Bit19 enables the differential amplifier632 (signal DAEn) andbit20 enables theADC622.Bit21 chooses between a normal clock (e.g., 100 kHz) and a fast clock (e.g., 8 MHz) to be used by theADC622. Bits22-24 specify the <SEL ADC> value, which determines which input to theADC MUX620 is passed to theADC622.

The steering configuration instruction is used to populate thesteering memory606 and to define the way in which its values are populated into an associated steering program in thesteering memory502. Before describing the parameters of the steering configuration instruction, it is useful to understand the structure of thesteering memory606, which is illustrated inFIG. 25. Thesteering memory606 includes nine memory locations, which are arranged in essentially the same manner as a single steering program in thesteering memory502. As shown, each 32-bit location in thesteering memory606 specifies the parameters of four electrodes, with each electrode defined by a single byte that specifies the electrode's stimulation polarity and allocation of current of the specified stimulation polarity. The parameters of the various electrodes are also arranged in the same manner in thesteering memory606 as in a steering program in the steering memory502 (e.g., bits0-7 ofaddress1 specify parameters of electrode E1, bits8-15 ofaddress2 specify parameters of electrodes E2, etc.). Thesteering memory606 differs from a steering program insteering memory502 only in that it enables the assignment of parameters for two additional electrodes inaddress9. These additional electrodes are a virtual electrode VA, which is associated with MUX A and has parameters that are defined by bits8-15 ofaddress9, and a virtual electrode VB, which is associated with MUX B and has parameters that are defined by bits16-23 ofaddress9. The specified parameters of these virtual electrodes can be written into the parameters of a “real” electrode in thesteering memory606 based upon the select signal of the associated MUX as described below.

Returning toFIG. 23B, bits0-7 of the steering configuration instruction specify an individual electrode's steering value, which is arranged in the same manner as described above with respect to the steering memory502 (i.e. the most significant bit defines the stimulation polarity and the remaining seven bits define the allocation of current of the specified polarity).Bit8 of the steering configuration instruction, when set, prevents the specified steering value from being overwritten by the value from one of the virtual electrodes. Bits9-13 specify the electrode number to which the steering value applies.Bit14, when set, causes the measure logic block612 to write the specified steering value to the location of the specified electrode in thesteering memory606.Bit15, when set, clears all of the values in thesteering memory606.Bits16 specifies whether the parameters in thesteering memory606 for virtual electrode VA are to be written to the location in thesteering memory606 that corresponds to the electrode specified by the value in the MUX A address in thevariable memory604, and bit17 specifies the same properties with respect to virtual electrode VB and MUX B.

The variable instruction includes a value range (bits0-11), a variable address range (bits12-15), an operation range (bits16-19), and a clear operation range (bits20-23). The operation and clear operation bit ranges enable the specification of a particular type of operation such as write, copy, add, subtract, and various logical operations, which can be performed to manipulate the data in thevariable memory604 according to the specified variable address and value.

FIGS. 26A-26G illustrate an example use of the measure instructions (any one or more measure instructions define a measure program) to measure the voltage between electrode nodes E1′ and E2′ during provision of a pulse, and more particularly to measure the resistance between those electrode nodes. Referring toFIG. 26A, PDC171(1) generates a stimulation waveform that is formed through the execution of two aggregate instructions: a first aggregate instruction2610 that specifies 1000 repetitions of pulse program B (which begins at pulse memory location X+6) according to the electrode configuration in steering program C and asecond aggregate instruction2612 that specifies 1000 repetitions of pulse program D (which begins at pulse memory location X+102) according to the electrode configuration in steering program A. Pulse program D, while not introduced to this point, is described below.

Determination of the resistance between electrodes E1 and E2 is accomplished by measuring the voltage between the corresponding nodes E1′ and E2′ while electrodes E1 and E2 are being used to deliver stimulation of a known current, I. In the example inFIG. 26A, the known stimulation current flows between E1 and E2 during stimulation and active recovery phases during the execution of thesecond aggregate instruction2612. The example shown inFIG. 26A illustrates an example set ofinstructions2616 in themeasure memory602 executed by the measure logic block612 to control the sample and holdcircuitry166 and the A/D circuitry168 to measure the voltage across E1′ and E2′ during the appropriate time periods (i.e., a portion of the stimulation phase and a portion of the active recovery phase) of the first execution of pulse program D during a specific execution of theaggregate instruction2614 by PDC171(1).

The first instruction (WT1) in theinstruction set2616 is a wait trigger instruction that causes the measure logic block612 to wait for 2000 occurrences of the start of execution of an aggregate program (i.e., the start of execution of the aggregate instruction at the PDC's aggregate start address). During execution of the WT1 instruction, the measure logic block612 maintains a count of the specified trigger received from PDC171(1). When the count reaches the value specified in the WT1 instruction (2000), the measure logic block proceeds to the next instruction, which is stored in the next address in themeasure memory602. The next instruction (WT2) is also a wait trigger instruction. The WT2 instruction causes the measure logic block612 to wait for a single occurrence of the aggregate trigger. As illustrated in the time line, the WT2 instruction is executed immediately following the receipt of the 2000^thaggregate program trigger following execution of the WT1 instruction. An aggregate trigger is also received at the same time as the 2000^thaggregate program trigger, but the WT2 instruction is executed on the next clock cycle. Thus, the next aggregate trigger represents the start of the execution of theaggregate instruction2614 during which the E1′-E2′ voltage measurement is to be taken.FIG. 26B illustrates the stimulation waveform generated during execution ofaggregate instruction2614. As illustrated, pulse program D includes a pre-pulse phase, a stimulation phase, an active recovery phase, a passive recovery phase, and a quiet phase. Each of the phases of pulse program D has a pulse width of 100 μs with the exception of the quiet phase, which has a pulse width of 300 μs. During the stimulation phase, a stimulation current of I is sourced to electrode E1 and a sunk from electrode E2. During the active recovery phase, current flows in the opposite direction, and I is sourced to E2 and sunk from E1.

When the measure logic block612 receives the single aggregate trigger specified by the WT2 instruction from PDC171(1), it proceeds to the next instruction in thememory602, which is a set switches instruction (SS1). As illustrated in the timeline inFIG. 26B, the SS1 instruction is executed at the beginning of the execution of theaggregate instruction2614, during the pre-pulse phase of the first execution of pulse program D. The SS1 instruction causes the measure logic block to send the <SEL A>, <SEL B>, and <S> control signals to the sample and holdcircuitry166 to close all of the S0-S4 switches and to select the ground input from each of MUX A and MUX B. This preparation stage is illustrated inFIG. 26C, which shows that the ground signals being passed by MUX A and MUX B are shorted together and both plates of the capacitors CX and CY are shorted to ground to ensure that there are no residual voltages across the capacitors prior to taking measurements. Note that the SS1 instruction is executed with the blanking bit set, which causes the switches S0 through S4 to open prior to going to the specified state.

After executing the SS1 instruction, the measure logic block612 proceeds to the WT3 instruction, which causes the measure logic block612 to wait for the next occurrence of a phase trigger, which phase trigger corresponds to the start of the execution of the stimulation pulse phase. In the expanded portions of the stimulation pulse and active recovery phases2602 and2604, each dashed tick represents a clock cycle (i.e., ten 100 kHz clock cycles during each 100 μs phase). When the measure logic block612 receives the phase trigger corresponding to the WT3 instruction, it executes the W1 instruction at the next clock cycle. The W1 instruction causes the measure logic block612 to delay for two clock cycles before executing the SS2 instruction. In the example shown, this delay is utilized to measure the E1′-E2′ voltage during the central portion of the pulse phase (i.e., the central 40 μs), during which time the current I passing through the electrodes is most likely to be stable, but the instructions could also be configured to measure the voltage during other phase portions.

The SS2 instruction causes the measure logic block612 to issue control signals to the sample and holdcircuitry168 to select the E1 input from MUX A and the E2 input from MUX B and to close the S0 and S3 switches and open the S1, S2, and S4 switches. As illustrated inFIG. 26D, the voltage V_Xbetween electrode nodes E1′ and E2′ is impressed or stored on capacitor CX, which voltage will equal the sum of the two parasitic voltages across the decoupling capacitors C1 and C2 (V_C1+V_C2) and the drop across the patient's tissue (IR), i.e., V_X=V_C1+IR+V_C2(see, e.g.,FIG. 3A). Note that leaving switches S1, S2, and S4 open isolates capacitor CY, whose voltage drop remains zero by virtue of being grounded during the preparation stage.

During the clock cycle following execution of the SS2 instruction, the measure logic block executes the W2 instruction, which causes the measure logic block612 to wait for three clock cycles before executing the SS3 instruction. The SS3 instruction causes the measure logic block612 to issue control signals to the sample and holdcircuitry168 to select no inputs from either MUX A or MUX B and to perform a blanking operation. After executing the SS3 instruction, the measure logic block612 executes the WT4 instruction, which causes the measure logic block612 to wait for the occurrence of the next phase trigger, which phase trigger corresponds to the beginning of the active recovery phase. Instructions W3 through SS5 essentially mirror instructions W1 through SS3, except that the SS4 instruction causes the measure logic block612 to issue control signals to the sample and holdcircuitry168 to select the E2 input from MUX A and the E1 input from MUX B and to close the S1 and S2 switches and open the S0, S3, and S4 switches. As illustrated inFIG. 26E, the voltage V_Ybetween electrode nodes E2′ and E1′ is impressed or stored on capacitor CY, which voltage will again equal the sum of the two parasitic voltages across the decoupling capacitors C1 and C2 and the drop across the patient's tissue (IR). However, because the polarity of stimulation is reversed in the active recovery phase, these parasitic voltages are now subtracted, such that V_Y=−V_C2+IR−V_C1. Note that leaving switches S0, S3, and S4 open isolates capacitor CX, whose voltage remains V_Xby virtue of the sample collected earlier during the stimulation phase. Note also that although the blocking capacitors C1 and C2 charge and discharge over the stimulation and active recovery phases, collecting the samples during corresponding time periods in the stimulation pulse phase and the active recovery pulse phase ensures that the values are essentially the same over the sample period and thus that these values can be cancelled out as described below.

Following execution of the SS5 instruction, the measure logic block executes the W5 instruction, which causes the measure logic block612 to wait for four clock cycles before executing the SS6 instruction. Due to the wait associated with the W5 instruction, the SS6 instruction is executed during the passive recovery phase. The SS6 instruction causes the measure logic block612 to issue control signals to the sample and holdcircuitry166 to select the common mode (CM) inputs from both MUX A and MUX B and to close the S1, S3, and S4 switches and open the S0 and S2 switches. As illustrated inFIG. 26F, in this orientation, capacitors CX and CY are connected in series by closing switch S4 and are provided a reference voltage via the common mode inputs to the MUXes. The voltage across the series-connected capacitors CX and CY is equal to the sum of the previously-stored V_Xand V_Yvalues, namely 2IR. Notice that the parasitic voltages across the decoupling capacitors, V_C1and V_C2, are canceled by this series addition, thus removing them from the measurement, which enables a more accurate determination of the resistance R of the patient's tissue. Additionally, selecting the common mode input CM at each of the MUXes and closing switches S1 and S3 causes the common node between the capacitors CX and CY to be set to a reference voltage of V+/2. Notice that the common mode inputs are wired differently at the MUXes: the common mode input at MUX A is coupled to the compliance voltage V+ via a resistor R1, while the common mode input at MUX B is coupled to ground via a resistor R2. In the example shown, R1 and R2 are identical, and of a relatively high value on the order of 250 k-ohm each. When both common mode inputs are selected and shorted at the common node between the capacitors via switches S1 and S3, R1 and R2 form a voltage divider between V+ and ground, resulting in the common mode voltage of V+/2. Because the 2IR voltage across the series-connected capacitors is preserved, the effect is to present a voltage of (V+/2)+IR and a voltage of (V+/2)−IR to thedifferential amplifier632.

Following execution of the SS6 instruction, the measure logic block612 executes the W6 instruction, which causes the measure logic block612 to wait for four clock cycles before executing the SS7 instruction, which, as illustrated inFIG. 26G, causes the measure logic block612 to issue control signals to the sample and holdcircuitry168 to de-select the common mode voltage at each of the MUXes and open switches S1 and S3 while keeping S4 closed to maintain the series connection of CX and CY and the corresponding presentation of the 2IR value to thedifferential amplifier632. Immediately following the execution of the SS7 instruction, the measure logic block612 executes the M1 measure command, which causes the measure logic block612 to issue control signals to theADC622 to store a digitized value of the analog signal online634 in thememory block624. Note that this M1 measure instruction assumes that the ADC MUX was previously configured to pass the signal from the sample and holdcircuitry168. In the illustrated example, the measure instruction specifies a single sample with no accumulate value, but this could obviously be tailored to desired settings.

The example set ofinstructions2616 is shown in long form for purposes of illustration. It will be appreciated that a jump instruction could be utilized to re-use a set of instructions to perform a similar process. Note that the set ofinstructions2616 is specific to a single PDC171(1) (i.e., the wait trigger instructions look only for triggers from this circuit and the instructions are configured based on the known timing of the stimulation associated with this PDC). Other instruction sets may be configured to acquire measurements based on stimulation provided byother PDCs171. The instruction sets may be configured to, upon obtaining the desired measurements associated with onePDC171, jump to the instruction set associated with anotherPDC171 such that all desired measurements can be obtained.

The example measurement sequence described with respect toFIGS. 26A-26G relies upon the electrode configuration in the steering program assigned by thestimulation circuitry170. For example, during execution of theaggregate instruction2614, the only electrode voltages that can be measured are those that are defined as active in the steering program A (i.e., electrodes E1 and E2).FIGS. 27A and 27B illustrate a similar type of measurement sequence in which the aggregate instruction specifies a steering program that can be adjusted by themeasurement circuitry167. As shown below, the ability of themeasure circuitry167 to alter the electrode configuration in a steering program enables themeasure circuitry167 to control the delivery of current to selected electrodes and to measure the voltages at the selected electrodes.

In the example shown inFIG. 27A,aggregate instruction2714 replacesaggregate instruction2614 in the aggregate program executed by PDC171(1), which aggregate program otherwise mirrors the aggregate program described with respect toFIGS. 26A-26G.Aggregate instruction2714 specifies 1000 repetitions of pulse program D in accordance with the electrode configuration specified by steering program P. Steering program P, as shown inFIG. 25, is capable of being adjusted based on the values in thesteering memory606 in themeasure circuit167. This type of aggregate instruction (i.e., using a steering program that is adjustable by the measure circuit167) may be utilized for the sole purpose of enabling themeasure circuitry167 to perform desired measurements. In fact, the steering program P may only be populated during the time that the measurements are being performed. Therefore, while theaggregate instruction2714 is executed during each execution of the aggregate program, all of the branch electrode switches178 may be open, thus preventing current from flowing to any electrode, at all times other than when themeasure circuitry167 populates the steering program P to perform desired measurements. Even when current is delivered due to the execution of theaggregate program2714, the amplitude may be at a “sub-threshold” level that is not recognizable by the patient.

The set ofinstructions2716 is similar in most aspects to the set ofinstructions2616 described above with respect toFIGS. 26A-26G. However, the set ofinstructions2716 manipulates the steering program P to collect measurements across multiple pairs of electrodes as is now described. The first difference between the set ofinstructions2716 and the set ofinstructions2616 is the insertion of a set ofconfiguration instructions2710 between the WT1 and WT2 instructions. The first instruction in the set ofconfiguration instructions2710 is a steering configuration instruction SC1 that clears the values in thesteering memory606, which is followed by a steering instruction SC2 that writes a 100% stimulation anode configuration to the virtual electrode VA (i.e., electrode34) and a steering instruction SC3 that writes a 100% stimulation cathode configuration to the virtual electrode VB (i.e., electrode35) and specifies that the virtual electrode configurations are to be written to the electrodes in thesteering memory606 according to the values in the MUXA and MUXB addresses in thevariable memory604. The remaining instructions in the set ofconfiguration instructions2710 write values to these MUXA and MUXB addresses. Specifically, the V1 instruction writes the E1 selection value to the MUXA address in the variable memory604 (address13 in this example) and the V2 instruction writes the E2 selection value to the MUXB address in the variable memory604 (address14 in this example). The combination of SC3, V1, and V2 results in the electrode configuration for virtual electrode VA being written to the E1 portion of thesteering memory606 and the electrode configuration for the virtual electrode VB being written to the E1 portion of thesteering memory606. Because thesteering memory606 is written to the steering program P (which can be done continuously or upon any change in the memory606), this causes electrode E1 to be configured to receive 100% of the stimulation anodic current and electrode E2 to be configured to receive 100% of the stimulation cathodic current.

The WT2 through W1 instructions mirror those described above. The SS2 instruction differs from that described above in that rather than specifying the MUXA and MUXB inputs, the MUXA address and the MUX B address are specified for the MUXA and MUXB select signals. This is accomplished by selecting pre-defined values126 (for the MUXA address) and127 (for the MUXB address) in the MUXA and MUXB fields of the set switch instruction in the example shown. Based on the values written to the MUXA and MUXB memory locations (i.e., addresses13 and14) in thevariable memory604 by the V1 and V2 instructions, this results in the measure logic block612 generating control signals <SEL A> and <SEL B> that cause the selection of E1 (which is the anode during the stimulation phase) by MUXA and E2 (which is the cathode during the stimulation phase) by MUXB. In the same manner as described above, the voltage V_Xbetween electrode nodes E1′ and E2′, which is equal to the sum of the two parasitic voltages across the decoupling capacitors C1 and C2 (V_C0+V_C1) and the drop across the patient's tissue (IR), i.e., V_X=V_C1+IR+V_C2, is impressed or stored on capacitor CX.

The W2 through W3 instructions mirror those described above. The SS4 instruction is similar to the SS2 instruction in that it utilizes the MUX addresses in thememory604 to retrieve the MUX select values. However, the MUXA portion of the SS4 instruction points to the MUXB address (which stores the value for E2) and the MUXB portion of the SS4 instruction points to the MUX A address (which stores the value for E1). Thus, in the same way as described above, the voltage V_Ybetween electrode nodes E2′ and E1′ is impressed or stored on capacitor CY, which voltage will again equal the sum of the two parasitic voltages across the decoupling capacitors C1 and C2 and the drop across the patient's tissue (IR). The W4 through M1 instructions mirror those described above, and thus the same measurement of the voltage between E1 and E2 (which is equal to 2IR) is obtained.

After the M1 instruction, the measurement logic block612 executes the V3 instruction, which is a variable instruction that increments the value in the MUXB address of thevariable memory604 such that the value corresponds to E3. Because the SC3 instruction specifies that the electrode configurations of virtual electrodes VA and VB are to be written to the electrodes in thesteering memory606 according to the values in the MUXA and MUXB addresses in thevariable memory604, thesteering memory606 is updated to reflect that E1 (which is still identified in the MUXA address) is to receive 100% of the stimulation anodic current and E3 (which is now identified in the MUXB address) is to receive 100% of the stimulation cathodic current. Once again, thesteering memory606 is written to steering program P of thesteering memory502, which changes the electrode configuration utilized in conjunction with the execution of theaggregate instruction2714.

The WT5 instruction, which is executed after the V3 instruction, causes the measure logic block612 to wait for two occurrences of a pulse trigger. After receipt of the two pulses specified by the WT5 instruction, the measure logic block612 executes the J1 jump instruction. The J1 instruction is a conditional jump instruction that causes the measure logic block612 to loop back to the address of the SS1 instruction if the value in the MUXB address of the variable memory604 (i.e., address14) is less than the value inaddress1 of thevariable memory604. This example assumes that the value inaddress1 of thevariable memory604 has been previously set to a desired value.

FIG. 27B illustrates the stimulation waveform generated as a result of execution of the set ofinstructions2716. The voltage between electrode nodes E1′ and E2′ is sampled and measured during themeasure1 period, the voltage between electrode nodes E1′ and E3′ is sampled and measured during themeasure2 period, and the voltage between electrode nodes E1′ and E4′ is sampled and measured during themeasure3 period. Between themeasure1 and measure2 periods, the V3 instruction causes the electrode associated with the MUXB address to be incremented from E2 to E3, which, in turn, causes the steering program P to be updated such that stimulation is configured between E1 and E3. The WT5 instruction causes measurements to be taken every other pulse and is included only as an example. The process of measuring the voltage between E1′ and thenext electrode node61ain sequence continues until the incremented electrode number matches the value inaddress1 in thevariable memory604. As can be appreciated, the ability of themeasure circuit167 to track the stimulation sequence of each of thePDCs171 and to update the steering program enables great flexibility in the measurement of desired analog values.

While voltage measurements between electrode nodes have been described, it will be appreciated that other valuable measurements can also be made by configuring an appropriate set of instructions in themeasure memory602. For example, as discussed in U.S. Pat. No. 7,444,181, it can be particularly useful to know the voltage drop appearing across the current sources and sinks, i.e., thePDACs172pandNDACs172n, which voltage drops can only be known in part by monitoring the electrode voltages used during stimulation. By monitoring these voltage drops, the compliance voltage V+ can be set at a magnitude that is sufficient to deliver the required therapeutic current without loading, but not excessively high so as to waste power in the IPG. Such measurements can be taken by sampling the appropriate voltages (i.e., between an active electrode node and VH forPDAC172pand between an active electrode node and ground forNDAC172n) during a single phase of a pulse using the sample and holdcircuitry168 as described in U.S. Pat. No. 9,061,140. A beneficial aspect of themeasure circuit167 is that it enables measurements to be taken without intervention by themicrocontroller150, which allows themicrocontroller150 to remain in the reduced-power state. Thus, themicrocontroller150 can intermittently “wake up” and retrieve values from thememory624 without having to manage the collection of such measurements, which results in power savings in the IPG.

Although particular embodiments of the present invention have been shown and described, it should be understood that the above discussion is not intended to limit the present invention to these embodiments. It will be obvious to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention. Thus, the present invention is intended to cover alternatives, modifications, and equivalents that may fall within the spirit and scope of the present invention as defined by the claims.

Claims (15)

What is claimed is:

1. A pulse generator, comprising:

a plurality of electrodes;

memory circuitry configured to store

a plurality of pulse programs, wherein each of the pulse programs defines a pulse shape,

a plurality of steering programs, wherein each of the plurality of steering programs defines for each of the plurality of electrodes a stimulation polarity and an allocation of a current, and

a plurality of aggregate instructions, wherein each of the aggregate instructions is configured to link one of the plurality of pulse programs with one of the plurality of steering programs; and

one or more control circuits configured to execute one or more of the aggregate instructions, wherein each aggregate instruction when executed forms a stimulation waveform having the pulse shape defined by its linked pulse program at the plurality of electrodes in accordance with their stimulation polarities and their allocations of the current as defined by its linked steering program.

2. The pulse generator ofclaim 1, wherein each of the plurality of pulse programs comprises one or more pulse instructions.

3. The pulse generator ofclaim 2, wherein each of the one or more pulse instructions defines parameters of a single phase of the pulse shape defined by the pulse program.

4. The pulse generator ofclaim 3, wherein the parameters specify one of one or more types of phases.

5. The pulse generator ofclaim 4, wherein the types of phases comprise a stimulation phase, an active recovery phase, a delay phase, and an active delay phase.

6. The pulse generator ofclaim 3, wherein the parameters specify a duration of the single phase.

7. The pulse generator ofclaim 1, wherein each of the plurality of aggregate instructions specifies a number of times to repeat the one of the plurality of pulse programs, such that each aggregate instruction when executed forms the stimulation waveform having the pulse shape the specified number of times at the plurality of electrodes.

8. The pulse generator ofclaim 1, wherein the one or more control circuits comprise a plurality of circuits that are each configured to execute one or more of the aggregate instructions to form a plurality of stimulation waveforms simultaneously.

9. The pulse generator ofclaim 8, further comprising an arbitration manager block configured to prevent an electrode from being allocated current by two or more of the control circuits simultaneously.

10. The pulse generator ofclaim 1, wherein the one or more control circuits are configured to apply one or more adjustment parameters to form the stimulation waveform.

11. The pulse generator ofclaim 10, wherein the one or more adjustment parameters comprise an amplitude scale parameter configured to adjust an amplitude for the current defined by one of the plurality of pulse programs.

12. The pulse generator ofclaim 10, wherein the one or more adjustment parameters comprise one or more ramp parameters configured to gradually increase an amplitude of the stimulation waveform over a sequence of the pulse shapes.

13. The pulse generator ofclaim 1, further comprising a microcontroller, wherein the one or more control circuits are adapted to be configured by the microcontroller and to execute the one or more aggregate instructions without intervention by the microcontroller.

14. The pulse generator ofclaim 13, wherein the microcontroller is configured to operate in a high-power state and a reduced-power state, and wherein the one or more control circuits are configured to leave the microcontroller in the reduced-power state during execution of the aggregate instructions.

15. The pulse generator ofclaim 1, wherein the one or more control circuits are configured to execute the plurality of aggregate instructions sequentially.

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