TWI887292B - Etching method and plasma processing apparatus - Google Patents
Etching method and plasma processing apparatusDownload PDFInfo
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- TWI887292B TWI887292BTW109138387ATW109138387ATWI887292BTW I887292 BTWI887292 BTW I887292BTW 109138387 ATW109138387 ATW 109138387ATW 109138387 ATW109138387 ATW 109138387ATW I887292 BTWI887292 BTW I887292B
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Abstract
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Translated fromChinese本發明所例示之實施方式係關於一種蝕刻方法及電漿處理裝置。The embodiment of the present invention is related to an etching method and a plasma processing device.
於電子器件之製造中，對基板之含矽膜進行電漿蝕刻。於含矽膜之電漿蝕刻時，使用包含氟碳氣體之處理氣體。此種電漿蝕刻記載於美國專利申請公開第2016/0343580號說明書中。In the manufacture of electronic devices, plasma etching is performed on a silicon-containing film of a substrate. During the plasma etching of the silicon-containing film, a processing gas containing a fluorocarbon gas is used. Such plasma etching is described in the specification of U.S. Patent Application Publication No. 2016/0343580.
本發明提供一種於含矽膜之電漿蝕刻時抑制橫向蝕刻之技術。The present invention provides a technology for suppressing lateral etching during plasma etching of silicon-containing films.
一例示性實施方式提供一種蝕刻方法。蝕刻方法包含如下步驟，即，於電漿處理裝置之腔室內準備基板。基板包含含矽膜。蝕刻方法進而包含如下步驟，即，藉由源自在腔室內由處理氣體所形成之電漿之化學物種，對含矽膜進行蝕刻。處理氣體含有鹵素元素及磷。An exemplary embodiment provides an etching method. The etching method includes the steps of preparing a substrate in a chamber of a plasma processing device. The substrate includes a silicon-containing film. The etching method further includes the steps of etching the silicon-containing film by chemical species derived from a plasma formed by a processing gas in the chamber. The processing gas contains a halogen element and phosphorus.
根據一例示性實施方式，能夠於含矽膜之電漿蝕刻時抑制橫向蝕刻。According to an exemplary embodiment, lateral etching can be suppressed during plasma etching of a silicon-containing film.
1:電漿處理裝置1: Plasma treatment device
10:腔室10: Chamber
10s:內部空間10s: Inner space
12:腔室本體12: Chamber body
12e:排氣口12e: Exhaust port
12g:閘閥12g: Gate valve
12p:通路12p: Passage
13:支持部13: Support Department
14:基板支持器14: Substrate support
16:電極板16: Electrode plate
18:下部電極18:Lower electrode
18f:流路18f:Flow path
20:靜電吸盤20: Electrostatic suction cup
20p:直流電源20p: DC power supply
20s:開關20s: switch
22a:配管22a:Piping
22b:配管22b:Piping
24:氣體供給管線24: Gas supply pipeline
25:邊緣環25: Edge Ring
30:上部電極30: Upper electrode
32:構件32: Components
34:頂板34: Top plate
34a:複數個氣體噴出孔34a: Multiple gas ejection holes
36:支持體36: Support body
36a:氣體擴散室36a: Gas diffusion chamber
36b:複數個氣體孔36b: Multiple gas holes
36c:氣體導入口36c: Gas inlet
38:氣體供給管38: Gas supply pipe
40:氣體源群40: Gas source group
41:流量控制器群41: Traffic controller group
42:閥群42: Valve group
46:防護罩46: Protective shield
48:隔板48: Partition
50:排氣裝置50: Exhaust device
52:排氣管52: Exhaust pipe
62:第1高頻電源62: No. 1 high frequency power supply
64:第2高頻電源64: Second high frequency power supply
66:匹配器66:Matcher
68:匹配器68:Matcher
80:控制部80: Control Department
MK:遮罩MK:Mask
ML:多層膜ML: Multi-layer film
PF:保護膜PF: Protective film
SF:含矽膜SF: Silicon-containing film
SL:單層膜SL: Single-layer film
UR:基底區域UR: basal region
W:基板W: substrate
圖1係一例示性實施方式之蝕刻方法之流程圖。FIG1 is a flow chart of an etching method of an exemplary implementation.
圖2係可應用圖1所示之蝕刻方法之一例之基板的局部放大剖視圖。FIG2 is a partially enlarged cross-sectional view of a substrate to which the etching method shown in FIG1 can be applied.
圖3係概略地表示一例示性實施方式之電漿處理裝置之圖。FIG3 is a diagram schematically showing a plasma processing device of an exemplary embodiment.
圖4(a)係應用圖1所示之蝕刻方法之一例之基板的局部放大剖視圖，圖4(b)係利用由不含磷之處理氣體形成之電漿進行蝕刻之一例之基板的局部放大剖視圖。FIG. 4(a) is a partially enlarged cross-sectional view of a substrate in which the etching method shown in FIG. 1 is applied, and FIG. 4(b) is a partially enlarged cross-sectional view of a substrate in which etching is performed using plasma formed by a phosphorus-free processing gas.
圖5(a)係可應用圖1所示之蝕刻方法之另一例之基板的局部放大剖視圖，圖5(b)係應用圖1所示之蝕刻方法之另一例之基板的局部放大剖視圖。FIG. 5(a) is a partially enlarged cross-sectional view of another example of a substrate to which the etching method shown in FIG. 1 can be applied, and FIG. 5(b) is a partially enlarged cross-sectional view of another example of a substrate to which the etching method shown in FIG. 1 can be applied.
圖6係表示第1實驗中求出之、處理氣體中之PF3氣體之流量與氧化矽膜之蝕刻速率的關係之曲線圖。FIG. 6 is a graph showing the relationship between the flow rate of PF3 gas in the process gas and the etching rate of the silicon oxide film obtained in the first experiment.
圖7係表示第1實驗中求出之、處理氣體中之PF3氣體之流量與形成於氧化矽膜之開口之最大寬度的關係之曲線圖。FIG. 7 is a graph showing the relationship between the flow rate ofPF3 gas in the process gas and the maximum width of the opening formed in the silicon oxide film, which is obtained in the first experiment.
圖8係表示第3實驗中求出之、PF3氣體之流量比率與蝕刻速率之比的曲線圖。FIG. 8 is a graph showing the ratio of the flow rate ratio of the PF3 gas to the etching rate obtained in the third experiment.
以下，對各種例示性實施方式進行說明。Various exemplary implementations are described below.
一例示性實施方式提供一種蝕刻方法。蝕刻方法包含如下步驟，即，於電漿處理裝置之腔室內準備基板。基板包含含矽膜。蝕刻方法進而包含如下步驟，即，藉由源自在腔室內由處理氣體所形成之電漿之化學物種，對含矽膜進行蝕刻。處理氣體含有鹵素元素及磷。An exemplary embodiment provides an etching method. The etching method includes the steps of preparing a substrate in a chamber of a plasma processing device. The substrate includes a silicon-containing film. The etching method further includes the steps of etching the silicon-containing film by chemical species derived from a plasma formed by a processing gas in the chamber. The processing gas contains a halogen element and phosphorus.
根據上述實施方式，於劃分形成開口之側壁面上形成包含矽及處理氣體中所含之磷之保護膜，該開口係藉由蝕刻而形成於含矽膜中。一面藉由該保護膜保護側壁面，一面對含矽膜進行蝕刻。因此，能夠於含矽膜之電漿蝕刻時抑制橫向蝕刻。According to the above-mentioned implementation method, a protective film containing silicon and phosphorus contained in the processing gas is formed on the sidewall surface of the opening formed by the division, and the opening is formed in the silicon-containing film by etching. The sidewall surface is protected by the protective film while the silicon-containing film is etched. Therefore, lateral etching can be suppressed during plasma etching of the silicon-containing film.
於一例示性實施方式中，蝕刻方法可進而包含如下步驟，即，於劃分形成由蝕刻形成之開口之側壁面上形成保護膜。該保護膜含有處理氣體中所含之磷。In an exemplary embodiment, the etching method may further include the step of forming a protective film on the sidewall surface of the opening formed by etching. The protective film contains phosphorus contained in the processing gas.
於一例示性實施方式中，進行蝕刻之步驟與形成保護膜之步驟可同時進行。In an exemplary embodiment, the etching step and the protective film forming step can be performed simultaneously.
於一例示性實施方式中，處理氣體可包含PF3、PCl3、PF5、PCl5、POCl3、PH3、PBr3或PBr5中之至少一者作為含磷分子。In an exemplary embodiment, the process gas may include at least one of PF3 , PCl3 , PF5 , PCl5 , POCl3 , PH3 , PBr3 , or PBr5 as the phosphorus-containing molecule.
於一例示性實施方式中，處理氣體可進而含有碳及氫。In one exemplary embodiment, the process gas may further contain carbon and hydrogen.
於一例示性實施方式中，處理氣體可包含H2、HF、CxHy、CHxFy或NH3中之至少一者作為含氫分子。此處，x及y分別為自然數。In an exemplary embodiment, the process gas may include at least one of H2 , HF, Cx Hy , CHx Fy or NH3 as the hydrogen-containing molecule. Here, x and y are natural numbers, respectively.
於一例示性實施方式中，鹵素元素可為氟。In an exemplary embodiment, the halogen element may be fluorine.
於一例示性實施方式中，處理氣體可進而含有氧。In one exemplary embodiment, the process gas may further contain oxygen.
於一例示性實施方式中，含矽膜可為含矽之介電膜。In an exemplary embodiment, the silicon-containing film may be a silicon-containing dielectric film.
於一例示性實施方式中，含矽膜亦可包含氧化矽膜、氮化矽膜或矽膜中之至少一種膜。In an exemplary embodiment, the silicon-containing film may also include at least one of a silicon oxide film, a silicon nitride film, or a silicon film.
於一例示性實施方式中，含矽膜亦可包含兩個以上之具有互不相同之膜種之含矽膜。In an exemplary embodiment, the silicon-containing film may also include two or more silicon-containing films having different film species.
於一例示性實施方式中，兩個以上之含矽膜可包含氧化矽膜及氮化矽膜。或者，兩個以上之含矽膜亦可包含氧化矽膜及矽膜。或者，兩個以上之含矽膜亦可包含氧化矽膜、氮化矽膜及矽膜。In an exemplary embodiment, the two or more silicon-containing films may include a silicon oxide film and a silicon nitride film. Alternatively, the two or more silicon-containing films may include a silicon oxide film and a silicon film. Alternatively, the two or more silicon-containing films may include a silicon oxide film, a silicon nitride film, and a silicon film.
於一例示性實施方式中，基板可進而具有設置於含矽膜上之遮罩。In one exemplary embodiment, the substrate may further have a mask disposed on the silicon-containing film.
於一例示性實施方式中，蝕刻步驟開始時，基板之溫度可設定為0℃以下之溫度。In an exemplary embodiment, when the etching step begins, the temperature of the substrate can be set to a temperature below 0°C.
另一例示性實施方式提供一種電漿處理裝置。電漿處理裝置具備腔室、基板支持器、氣體供給部及高頻電源。基板支持器構成為於腔室內支持基板。氣體供給部構成為將用以對含矽膜進行蝕刻之處理氣體供給至腔室內。處理氣體含有鹵素元素及磷。高頻電源構成為產生高頻電力以於腔室內由處理氣體生成電漿。Another exemplary embodiment provides a plasma processing device. The plasma processing device includes a chamber, a substrate support, a gas supply unit, and a high-frequency power supply. The substrate support unit is configured to support the substrate in the chamber. The gas supply unit is configured to supply a processing gas for etching a silicon-containing film into the chamber. The processing gas contains a halogen element and phosphorus. The high-frequency power supply is configured to generate high-frequency power to generate plasma from the processing gas in the chamber.
以下，參照圖式對各種例示性實施方式詳細地進行說明。再者，各圖式中對相同或相當之部分標註相同之符號。Below, various exemplary implementations are described in detail with reference to the drawings. Furthermore, the same symbols are used to mark the same or equivalent parts in each drawing.
圖1係一例示性實施方式之蝕刻方法之流程圖。圖1所示之蝕刻方法(以下稱作「方法MT」)包含步驟ST1及步驟ST2。方法MT適用於具有含矽膜之基板。方法MT係對含矽膜進行蝕刻。FIG. 1 is a flow chart of an etching method of an exemplary implementation. The etching method shown in FIG. 1 (hereinafter referred to as "method MT") includes step ST1 and step ST2. Method MT is applicable to a substrate having a silicon-containing film. Method MT etches the silicon-containing film.
圖2係可應用圖1所示之蝕刻方法之一例之基板的局部放大剖視圖。圖2所示之基板W可用於製造如DRAM(Dynamic Random Access Memory，動態隨機存取記憶體)、3D(three dimensional，三維)-NAND(Not AND，反及)之器件。基板W具有含矽膜SF。基板W可進而具有基底區域UR。含矽膜SF可設置於基底區域UR上。含矽膜SF可為含矽之介電膜。含矽之介電膜可包含氧化矽膜或氮化矽膜。含矽之介電膜只要為含有矽之膜，則亦可為具有其他膜種之膜。又，含矽膜SF亦可包含矽膜(例如多晶矽膜)。又，含矽膜SF亦可包含兩個以上之具有互不相同之膜種之含矽膜。兩個以上之含矽膜可包含氧化矽膜及氮化矽膜。含矽膜SF例如可為包含交替積層之一個以上之氧化矽膜及一個以上之氮化矽膜的多層膜。或者，兩個以上之含矽膜亦可包含氧化矽膜及矽膜。含矽膜SF例如亦可為包含交替積層之一個以上之氧化矽膜及一個以上之矽膜的多層膜。或者，兩個以上之含矽膜亦可包含氧化矽膜、氮化矽膜及矽膜。FIG. 2 is a partially enlarged cross-sectional view of an example of a substrate to which the etching method shown in FIG. 1 can be applied. The substrate W shown in FIG. 2 can be used to manufacture devices such as DRAM (Dynamic Random Access Memory) and 3D (three dimensional)-NAND (Not AND). The substrate W has a silicon-containing film SF. The substrate W may further have a base region UR. The silicon-containing film SF may be disposed on the base region UR. The silicon-containing film SF may be a silicon-containing dielectric film. The silicon-containing dielectric film may include a silicon oxide film or a silicon nitride film. As long as the silicon-containing dielectric film is a film containing silicon, it may also be a film having other film types. Furthermore, the silicon-containing film SF may also include a silicon film (e.g., a polycrystalline silicon film). Furthermore, the silicon-containing film SF may include two or more silicon-containing films having different film types. The two or more silicon-containing films may include a silicon oxide film and a silicon nitride film. The silicon-containing film SF may be, for example, a multilayer film including one or more silicon oxide films and one or more silicon nitride films alternately stacked. Alternatively, the two or more silicon-containing films may include a silicon oxide film and a silicon film. The silicon-containing film SF may be, for example, a multilayer film including one or more silicon oxide films and one or more silicon films alternately stacked. Alternatively, the two or more silicon-containing films may include a silicon oxide film, a silicon nitride film, and a silicon film.
基板W可進而具有遮罩MK。遮罩MK設置於含矽膜SF上。遮罩MK係由具有較步驟ST2中之含矽膜SF之蝕刻速率低之蝕刻速率的材料形成。遮罩MK可由有機材料形成。遮罩MK例如可由非晶形碳膜、光阻膜、或SOC膜(旋塗碳膜)形成。或者，遮罩MK亦可為由氮化鈦、鎢、碳化鎢之類的含金屬材料形成之含金屬遮罩。遮罩MK可具有3μm以上之厚度。The substrate W may further have a mask MK. The mask MK is disposed on the silicon-containing film SF. The mask MK is formed of a material having an etching rate lower than that of the silicon-containing film SF in step ST2. The mask MK may be formed of an organic material. The mask MK may be formed, for example, of an amorphous carbon film, a photoresist film, or a SOC film (spin-on carbon film). Alternatively, the mask MK may also be a metal-containing mask formed of a metal-containing material such as titanium nitride, tungsten, or tungsten carbide. The mask MK may have a thickness of 3 μm or more.
遮罩MK被圖案化。即，遮罩MK具有步驟ST2中轉印至含矽膜SF之圖案。當遮罩MK之圖案轉印至含矽膜SF時，於含矽膜SF上形成孔或溝槽之類的開口。步驟ST2中形成於含矽膜SF之開口之縱橫比可為20以上，亦可為40或50以上。The mask MK is patterned. That is, the mask MK has the pattern transferred to the silicon-containing film SF in step ST2. When the pattern of the mask MK is transferred to the silicon-containing film SF, an opening such as a hole or a groove is formed on the silicon-containing film SF. The aspect ratio of the opening formed in the silicon-containing film SF in step ST2 can be greater than 20, and can also be greater than 40 or 50.
方法MT中使用電漿處理裝置來對含矽膜SF進行蝕刻。圖3係概略地表示一例示性實施方式之電漿處理裝置之圖。圖3所示之電漿處理裝置1具備腔室10。腔室10中提供內部空間10s。腔室10包含腔室本體12。腔室本體12具有大致圓筒形狀。腔室本體12例如由鋁形成。於腔室本體12之內壁面上設置有具有耐腐蝕性之膜。具有耐腐蝕性之膜可由氧化鋁、氧化釔等陶瓷形成。In method MT, a plasma processing device is used to etch the silicon-containing film SF. FIG. 3 is a diagram schematically showing a plasma processing device of an exemplary embodiment. The plasma processing device 1 shown in FIG. 3 has a chamber 10. An internal space 10s is provided in the chamber 10. The chamber 10 includes a chamber body 12. The chamber body 12 has a substantially cylindrical shape. The chamber body 12 is formed of aluminum, for example. A corrosion-resistant film is provided on the inner wall surface of the chamber body 12. The corrosion-resistant film can be formed of ceramics such as aluminum oxide and yttrium oxide.
於腔室本體12之側壁形成有通路12p。基板W通過通路12p於內部空間10s與腔室10外部之間被搬送。通路12p藉由閘閥12g開閉。閘閥12g沿著腔室本體12之側壁設置。A passage 12p is formed on the side wall of the chamber body 12. The substrate W is transported between the internal space 10s and the outside of the chamber 10 through the passage 12p. The passage 12p is opened and closed by a gate 12g. The gate 12g is provided along the side wall of the chamber body 12.
於腔室本體12之底部上設置有支持部13。支持部13由絕緣材料形成。支持部13具有大致圓筒形狀。支持部13於內部空間10s內，從腔室本體12之底部朝上方延伸。支持部13支持基板支持器14。基板支持器14構成為於內部空間10s內支持基板W。A support portion 13 is provided on the bottom of the chamber body 12. The support portion 13 is formed of an insulating material. The support portion 13 has a substantially cylindrical shape. The support portion 13 extends upward from the bottom of the chamber body 12 in the internal space 10s. The support portion 13 supports a substrate holder 14. The substrate holder 14 is configured to support a substrate W in the internal space 10s.
基板支持器14具有下部電極18及靜電吸盤20。基板支持器14可進而具有電極板16。電極板16由鋁等導體形成，具有大致圓盤形狀。下部電極18設置於電極板16上。下部電極18由鋁等導體形成，具有大致圓盤形狀。下部電極18電連接於電極板16。The substrate holder 14 has a lower electrode 18 and an electrostatic suction cup 20. The substrate holder 14 may further have an electrode plate 16. The electrode plate 16 is formed of a conductor such as aluminum and has a roughly disc shape. The lower electrode 18 is disposed on the electrode plate 16. The lower electrode 18 is formed of a conductor such as aluminum and has a roughly disc shape. The lower electrode 18 is electrically connected to the electrode plate 16.
靜電吸盤20設置於下部電極18上。基板W載置於靜電吸盤20之上表面之上。靜電吸盤20具有本體及電極。靜電吸盤20之本體具有大致圓盤形狀，由介電體形成。靜電吸盤20之電極為膜狀電極，設置於靜電吸盤20之本體內。靜電吸盤20之電極經由開關20s而連接於直流電源20p。當對靜電吸盤20之電極施加來自直流電源20p之電壓時，於靜電吸盤20與基板W之間產生靜電引力。基板W藉由該靜電引力被靜電吸盤20吸引而由靜電吸盤20保持。The electrostatic suction cup 20 is disposed on the lower electrode 18. The substrate W is placed on the upper surface of the electrostatic suction cup 20. The electrostatic suction cup 20 has a body and an electrode. The body of the electrostatic suction cup 20 has a roughly disc shape and is formed of a dielectric. The electrode of the electrostatic suction cup 20 is a film electrode and is disposed in the body of the electrostatic suction cup 20. The electrode of the electrostatic suction cup 20 is connected to a DC power source 20p via a switch 20s. When a voltage from the DC power source 20p is applied to the electrode of the electrostatic suction cup 20, an electrostatic attraction is generated between the electrostatic suction cup 20 and the substrate W. The substrate W is attracted by the electrostatic chuck 20 by the electrostatic attraction and is held by the electrostatic chuck 20.
於基板支持器14上配置邊緣環25。邊緣環25為環狀構件。邊緣環25可由矽、碳化矽或石英等形成。基板W配置於靜電吸盤20上且由邊緣環25包圍之區域內。An edge ring 25 is arranged on the substrate holder 14. The edge ring 25 is a ring-shaped component. The edge ring 25 can be formed of silicon, silicon carbide or quartz. The substrate W is arranged on the electrostatic chuck 20 and in the area surrounded by the edge ring 25.
於下部電極18之內部設置有流路18f。從設置於腔室10外部之冷卻器單元經由配管22a將熱交換介質(例如冷媒)供給至流路18f。供給至流路18f之熱交換介質經由配管22b返回至冷卻器單元。於電漿處理裝置1中，藉由熱交換介質與下部電極18之熱交換而調整載置於靜電吸盤20上之基板W之溫度。A flow path 18f is provided inside the lower electrode 18. A heat exchange medium (e.g., refrigerant) is supplied to the flow path 18f from a cooling unit provided outside the chamber 10 via a pipe 22a. The heat exchange medium supplied to the flow path 18f is returned to the cooling unit via a pipe 22b. In the plasma processing apparatus 1, the temperature of the substrate W mounted on the electrostatic chuck 20 is adjusted by heat exchange between the heat exchange medium and the lower electrode 18.
於電漿處理裝置1中設置有氣體供給管線24。氣體供給管線24將來自傳熱氣體供給機構之傳熱氣體(例如He氣體)供給至靜電吸盤20之上表面與基板W背面之間的間隙。A gas supply line 24 is provided in the plasma processing device 1. The gas supply line 24 supplies heat transfer gas (such as He gas) from a heat transfer gas supply mechanism to the gap between the upper surface of the electrostatic chuck 20 and the back surface of the substrate W.
電漿處理裝置1進而具備上部電極30。上部電極30設置於基板支持器14之上方。上部電極30隔著構件32支持於腔室本體12之上部。構件32由具有絕緣性之材料形成。上部電極30及構件32將腔室本體12之上部開口封閉。The plasma processing device 1 further includes an upper electrode 30. The upper electrode 30 is disposed above the substrate support 14. The upper electrode 30 is supported on the upper part of the chamber body 12 via a component 32. The component 32 is formed of an insulating material. The upper electrode 30 and the component 32 seal the upper opening of the chamber body 12.
上部電極30可包含頂板34及支持體36。頂板34之下表面係內部空間10s一側之下表面，劃分形成內部空間10s。頂板34可由產生較少焦耳熱之低電阻導電體或半導體形成。頂板34具有於頂板34之板厚方向上貫通該頂板34之複數個氣體噴出孔34a。The upper electrode 30 may include a top plate 34 and a support 36. The lower surface of the top plate 34 is the lower surface of one side of the internal space 10s, dividing and forming the internal space 10s. The top plate 34 may be formed of a low-resistance conductor or semiconductor that generates less Joule heat. The top plate 34 has a plurality of gas ejection holes 34a that penetrate the top plate 34 in the plate thickness direction of the top plate 34.
支持體36將頂板34裝卸自如地支持。支持體36由鋁等導電性材料形成。於支持體36之內部設置有氣體擴散室36a。支持體36具有從氣體擴散室36a朝下方延伸之複數個氣體孔36b。複數個氣體孔36b分別連通於複數個氣體噴出孔34a。於支持體36形成有氣體導入口36c。氣體導入口36c連接於氣體擴散室36a。於氣體導入口36c連接有氣體供給管38。The support body 36 supports the top plate 34 in a detachable manner. The support body 36 is formed of a conductive material such as aluminum. A gas diffusion chamber 36a is provided inside the support body 36. The support body 36 has a plurality of gas holes 36b extending downward from the gas diffusion chamber 36a. The plurality of gas holes 36b are respectively connected to the plurality of gas ejection holes 34a. A gas inlet 36c is formed in the support body 36. The gas inlet 36c is connected to the gas diffusion chamber 36a. A gas supply pipe 38 is connected to the gas inlet 36c.
於氣體供給管38，經由流量控制器群41及閥群42連接有氣體源群40。流量控制器群41及閥群42構成氣體供給部。氣體供給部可進而包含氣體源群40。氣體源群40包含複數個氣體源。複數個氣體源包含方法MT中所使用之處理氣體之供給源。流量控制器群41包含複數個流量控制器。流量控制器群41之複數個流量控制器分別為質量流量控制器或壓力控制式之流量控制器。閥群42包含複數個開閉閥。氣體源群40之複數個氣體源分別經由流量控制器群41之對應之流量控制器及閥群42之對應之開閉閥而連接於氣體供給管38。A gas source group 40 is connected to the gas supply pipe 38 via a flow controller group 41 and a valve group 42. The flow controller group 41 and the valve group 42 constitute a gas supply section. The gas supply section may further include a gas source group 40. The gas source group 40 includes a plurality of gas sources. The plurality of gas sources include a supply source of a processing gas used in method MT. The flow controller group 41 includes a plurality of flow controllers. The plurality of flow controllers of the flow controller group 41 are respectively mass flow controllers or pressure-controlled flow controllers. The valve group 42 includes a plurality of on-off valves. The plurality of gas sources of the gas source group 40 are connected to the gas supply pipe 38 via the corresponding flow controllers of the flow controller group 41 and the corresponding on-off valves of the valve group 42.
於電漿處理裝置1中，沿著腔室本體12之內壁面及支持部13之外周，裝卸自如地設置有防護罩46。防護罩46防止反應副產物附著於腔室本體12。防護罩46例如係藉由在由鋁形成之母材之表面形成具有耐腐蝕性之膜而構成。具有耐腐蝕性之膜可由氧化釔等陶瓷形成。In the plasma processing device 1, a protective cover 46 is detachably provided along the inner wall surface of the chamber body 12 and the outer periphery of the support portion 13. The protective cover 46 prevents the reaction byproducts from adhering to the chamber body 12. The protective cover 46 is formed, for example, by forming a corrosion-resistant film on the surface of a base material formed of aluminum. The corrosion-resistant film can be formed of ceramics such as yttrium oxide.
於支持部13與腔室本體12之側壁之間設置有隔板48。隔板48例如係藉由在由鋁形成之構件之表面形成具有耐腐蝕性之膜(氧化釔等膜)而構成。隔板48中形成有複數個貫通孔。於隔板48之下方且腔室本體12之底部設置有排氣口12e。排氣裝置50經由排氣管52而連接於排氣口12e。排氣裝置50包含壓力調整閥及渦輪分子泵等真空泵。A partition 48 is provided between the support portion 13 and the side wall of the chamber body 12. The partition 48 is formed, for example, by forming a corrosion-resistant film (such as a film of yttrium oxide) on the surface of a member formed of aluminum. A plurality of through holes are formed in the partition 48. An exhaust port 12e is provided below the partition 48 and at the bottom of the chamber body 12. The exhaust device 50 is connected to the exhaust port 12e via an exhaust pipe 52. The exhaust device 50 includes a vacuum pump such as a pressure regulating valve and a turbomolecular pump.
電漿處理裝置1具備第1高頻電源62及第2高頻電源64。第1高頻電源62係產生第1高頻電力之電源。第1高頻電力具有適於電漿生成之頻率。第1高頻電力之頻率例如為27MHz~100MHz之範圍內之頻率。第1高頻電源62經由匹配器66及電極板16而連接於下部電極18。匹配器66具有用以使第1高頻電源62之輸出阻抗與負載側(下部電極18側)之阻抗匹配之電路。再者，第1高頻電源62亦可經由匹配器66而連接於上部電極30。第1高頻電源62構成一例之電漿生成部。The plasma processing device 1 has a first high-frequency power source 62 and a second high-frequency power source 64. The first high-frequency power source 62 is a power source for generating a first high-frequency power. The first high-frequency power has a frequency suitable for plasma generation. The frequency of the first high-frequency power is, for example, a frequency in the range of 27 MHz to 100 MHz. The first high-frequency power source 62 is connected to the lower electrode 18 via a matcher 66 and an electrode plate 16. The matcher 66 has a circuit for matching the output impedance of the first high-frequency power source 62 with the impedance of the load side (lower electrode 18 side). Furthermore, the first high-frequency power source 62 can also be connected to the upper electrode 30 via the matcher 66. The first high-frequency power source 62 constitutes an example of a plasma generating unit.
第2高頻電源64係產生第2高頻電力之電源。第2高頻電力具有低於第1高頻電力之頻率的頻率。第2高頻電力與第1高頻電力一起使用時，第2高頻電力作為用以對基板W饋入離子之偏壓用高頻電力使用。第2高頻電力之頻率例如為400kHz~13.56MHz之範圍內之頻率。第2高頻電源64經由匹配器68及電極板16而連接於下部電極18。匹配器68具有用以使第2高頻電源64之輸出阻抗與負載側(下部電極18側)之阻抗匹配之電路。The second high-frequency power source 64 is a power source for generating the second high-frequency power. The second high-frequency power has a frequency lower than the frequency of the first high-frequency power. When the second high-frequency power is used together with the first high-frequency power, the second high-frequency power is used as a bias high-frequency power for feeding ions to the substrate W. The frequency of the second high-frequency power is, for example, a frequency in the range of 400kHz to 13.56MHz. The second high-frequency power source 64 is connected to the lower electrode 18 via the matching device 68 and the electrode plate 16. The matching device 68 has a circuit for matching the output impedance of the second high-frequency power source 64 with the impedance of the load side (lower electrode 18 side).
再者，亦可不使用第1高頻電力而使用第2高頻電力生成電漿，即，僅使用單一之高頻電力生成電漿。於此情形時，第2高頻電力之頻率可為大於13.56MHz之頻率，例如為40MHz。又，於此情形時，電漿處理裝置1亦可不具備第1高頻電源62及匹配器66。於此情形時，第2高頻電源64構成一例之電漿生成部。Furthermore, the plasma may be generated by using the second high-frequency power instead of the first high-frequency power, that is, only a single high-frequency power may be used to generate the plasma. In this case, the frequency of the second high-frequency power may be greater than 13.56 MHz, for example, 40 MHz. Furthermore, in this case, the plasma processing device 1 may not have the first high-frequency power supply 62 and the matching device 66. In this case, the second high-frequency power supply 64 constitutes an example of a plasma generating unit.
於電漿處理裝置1中進行電漿處理時，將氣體從氣體供給部供給至內部空間10s。又，藉由供給第1高頻電力及/或第2高頻電力，於上部電極30與下部電極18之間產生高頻電場。所產生之高頻電場使內部空間10s中之氣體生成電漿。When plasma treatment is performed in the plasma treatment device 1, gas is supplied from the gas supply unit to the internal space 10s. In addition, a high-frequency electric field is generated between the upper electrode 30 and the lower electrode 18 by supplying the first high-frequency power and/or the second high-frequency power. The generated high-frequency electric field causes the gas in the internal space 10s to generate plasma.
電漿處理裝置1可進而具備控制部80。控制部80可為具備處理器、記憶體等記憶部、輸入裝置、顯示裝置、信號之輸入輸出介面等之電腦。控制部80控制電漿處理裝置1之各部。控制部80中，操作員可使用輸入裝置進行指令之輸入操作等，以此來管理電漿處理裝置1。又，控制部80中，可藉由顯示裝置顯示電漿處理裝置1之運轉狀況使之可視化。進而，記憶部中儲存有控制程式及製程配方資料。藉由處理器執行控制程式，以此於電漿處理裝置1中執行各種處理。處理器執行控制程式，按照製程配方資料來控制電漿處理裝置1之各部。The plasma processing device 1 may further include a control unit 80. The control unit 80 may be a computer having a storage unit such as a processor, a memory, an input device, a display device, a signal input and output interface, and the like. The control unit 80 controls each unit of the plasma processing device 1. In the control unit 80, an operator may use an input device to input instructions, etc., to manage the plasma processing device 1. Moreover, in the control unit 80, the operating status of the plasma processing device 1 may be displayed by a display device to make it visible. Furthermore, a control program and process recipe data are stored in the memory unit. The control program is executed by the processor to perform various processes in the plasma processing device 1. The processor executes the control program to control each part of the plasma processing device 1 according to the process recipe data.
再次參照圖1。以下，針對方法MT，列舉使用電漿處理裝置1對圖2所示之基板W應用該方法MT之情形為例進行說明。於使用電漿處理裝置1之情形時，藉由控制部80之對電漿處理裝置1之各部之控制，可於電漿處理裝置1中執行方法MT。於以下說明中，亦對用以執行方法MT之控制部80之對電漿處理裝置1之各部之控制進行說明。Refer to FIG. 1 again. Hereinafter, the method MT will be described by taking the case where the plasma processing apparatus 1 is used to apply the method MT to the substrate W shown in FIG. 2 as an example. When the plasma processing apparatus 1 is used, the method MT can be executed in the plasma processing apparatus 1 by controlling the various parts of the plasma processing apparatus 1 by the control unit 80. In the following description, the control of the various parts of the plasma processing apparatus 1 by the control unit 80 for executing the method MT is also described.
方法MT係以步驟ST1開始。步驟ST1係於腔室10內準備基板W。基板W於腔室10內載置於靜電吸盤20上，且由靜電吸盤20保持。再者，基板W可具有300mm之直徑。The method MT starts with step ST1. Step ST1 is to prepare a substrate W in the chamber 10. The substrate W is placed on the electrostatic chuck 20 in the chamber 10 and is held by the electrostatic chuck 20. Furthermore, the substrate W may have a diameter of 300 mm.
方法MT中，繼而執行步驟ST2。步驟ST2係藉由源自在腔室10內由處理氣體所形成之電漿之化學物種，對含矽膜SF進行蝕刻。In method MT, step ST2 is then performed. Step ST2 is to etch the silicon-containing film SF by chemical species originating from the plasma formed by the processing gas in the chamber 10.
步驟ST2中使用之處理氣體含有鹵素元素及磷。處理氣體中所含之鹵素元素可為氟。處理氣體可包含氟碳或氫氟碳之至少一者。氟碳例如為CF4、C3F8、C4F6或C4F8中之至少一者。氫氟碳例如為CH2F2、CHF3或CH3F中之至少一者。氫氟碳亦可包含兩個以上之碳原子。處理氣體可包含含磷分子。含磷分子可為十氧化四磷(P4O10)、八氧化四磷(P4O8)、六氧化四磷(P4O6)之類的氧化物。十氧化四磷有時被稱作五氧化二磷(P2O5)。含磷分子亦可為三氟化磷(PF3)、五氟化磷(PF5)、三氯化磷(PCl3)、五氯化磷(PCl5)、三溴化磷(PBr3)、五溴化磷(PBr5)、碘化磷(PI3)之類的鹵化物。即，含磷分子可含有氟作為鹵素元素。或者，含磷分子亦可含有氟以外之鹵素元素作為鹵素元素。含磷分子亦可為磷醯氟(POF3)、磷醯氯(POCl3)、磷醯溴(POBr3)之類的磷醯鹵。含磷分子亦可為磷化氫(PH3)、磷化鈣(Ca3P2等)、磷酸(H3PO4)、磷酸鈉(Na3PO4)、六氟磷酸(HPF6)等。含磷分子亦可為氟化膦類(HxPFy)。此處，x與y之和為3或5。作為氟化膦類，可例示HPF2、H2PF3。處理氣體可包含該等分子中之一個以上之分子作為含磷分子。例如，處理氣體可包含PF3、PCl3、PF5、PCl5、POCl3、PH3、PBr3或PBr5中之至少一者作為含磷分子。再者，當含磷分子為液體或固體時，可藉由加熱等使之氣化後將其供給至腔室10內。The processing gas used in step ST2 contains a halogen element and phosphorus. The halogen element contained in the processing gas may be fluorine. The processing gas may contain at least one of a fluorocarbon or a hydrofluorocarbon. Fluorocarbon is, for example, at least one of CF4 , C3 F8 , C4 F6 or C4 F8. Hydrofluorocarbon is, for example, at least one of CH2 F2 , CHF3 or CH3 F. Hydrofluorocarbon may also contain two or more carbon atoms. The processing gas may contain a phosphorus-containing molecule. The phosphorus-containing molecule may be an oxide such as tetraphosphorus decoxide (P4 O10 ), tetraphosphorus octoxide (P4 O8 ), tetraphosphorus hexoxide (P4 O6 ). Tetraphosphorus decoxide is sometimes referred to as phosphorus pentoxide (P2 O5 ). The phosphorus-containing molecule may be a halogenide such as phosphorus trifluoride (PF3 ), phosphorus pentafluoride (PF5 ), phosphorus trichloride (PCl3 ), phosphorus pentachloride (PCl5 ), phosphorus tribromide (PBr3 ), phosphorus pentabromide (PBr5 ), phosphorus iodide (PI3 ). That is, the phosphorus-containing molecule may contain fluorine as a halogen element. Alternatively, the phosphorus-containing molecule may contain a halogen element other than fluorine as a halogen element. The phosphorus-containing molecule may be a phosphohalide such as phosphofluoride (POF3 ), phosphochloride (POCl3 ), phosphobromide (POBr3 ). The phosphorus-containing molecule may also be hydrogen phosphide (PH3 ), calcium phosphide (Ca3 P2 , etc.), phosphoric acid (H3 PO4 ), sodium phosphate (Na3 PO4 ), hexafluorophosphoric acid (HPF6 ), etc. The phosphorus-containing molecule may also be a phosphine fluoride (Hx PFy ). Here, the sum of x and y is 3 or 5. Examples of the phosphine fluoride include HPF2 and H2 PF3 . The process gas may contain one or more of these molecules as the phosphorus-containing molecule. For example, the process gas may contain at least one of PF3 , PCl3 , PF5 , PCl5 , POCl3 , PH3 , PBr3 or PBr5 as the phosphorus-containing molecule. Furthermore, when the phosphorus-containing molecules are liquid or solid, they can be vaporized by heating or the like and then supplied into the chamber 10 .
步驟ST2中使用之處理氣體可進而含有碳及氫。處理氣體可包含H2、氟化氫(HF)、烴(CxHy)、氫氟碳(CHxFy)或NH3中之至少一者作為含氫分子。烴例如為CH4或C3H6。此處，x及y分別為自然數。處理氣體可包含氟碳或烴(例如CH4)作為含碳分子。處理氣體亦可進而含有氧。處理氣體例如亦可包含O2。The processing gas used in step ST2 may further contain carbon and hydrogen. The processing gas may include at least one of H2 , hydrogen fluoride (HF), alkane (Cx Hy ), hydrofluorocarbon (CHx Fy ) or NH3 as a hydrogen-containing molecule. The alkane is, for example, CH4 or C3 H6 . Here, x and y are natural numbers. The processing gas may include fluorocarbon or alkane (for example, CH4 ) as a carbon-containing molecule. The processing gas may further contain oxygen. The processing gas may also include O2 , for example.
步驟ST2中使用之處理氣體包含含磷氣體作為磷之供給源。含磷氣體係上述含磷分子之氣體。一實施方式中，如上所述，步驟ST2適用於包含氧化矽膜及氮化矽膜之含矽膜SF。步驟ST2中，藉由設定含磷氣體之流量相對於處理氣體之總流量的比率，而設定(控制)氧化矽膜與氮化矽膜之交替積層膜之蝕刻速率相對於氧化矽膜之蝕刻速率的比。步驟ST2中，能以氧化矽膜之蝕刻速率與氧化矽膜和氮化矽膜之交替積層膜之蝕刻速率之間的差變小的方式，設定含磷氣體之流量相對於處理氣體之總流量的比率。一實施方式中，以氧化矽膜與氮化矽膜之交替積層膜之蝕刻速率相對於氧化矽膜之蝕刻速率的比為0.8以上1.2以下的方式，設定含磷氣體之流量相對於處理氣體之總流量的比率。含磷氣體之流量相對於處理氣體之總流量之比率例如可設定為10%以上50%以下。再者，亦可藉由於步驟ST2之蝕刻中變更含磷氣體之流量，而變更氧化矽膜與氮化矽膜之交替積層膜之蝕刻速率相對於氧化矽膜之蝕刻速率的比。The processing gas used in step ST2 includes a phosphorus-containing gas as a phosphorus supply source. The phosphorus-containing gas is a gas containing phosphorus molecules as described above. In one embodiment, as described above, step ST2 is applicable to a silicon-containing film SF including a silicon oxide film and a silicon nitride film. In step ST2, by setting the ratio of the flow rate of the phosphorus-containing gas to the total flow rate of the processing gas, the ratio of the etching rate of the alternating laminated film of the silicon oxide film and the silicon nitride film to the etching rate of the silicon oxide film is set (controlled). In step ST2, the ratio of the flow rate of the phosphorus-containing gas to the total flow rate of the processing gas can be set in such a way that the difference between the etching rate of the silicon oxide film and the etching rate of the alternating laminated film of the silicon oxide film and the silicon nitride film becomes smaller. In one embodiment, the ratio of the flow rate of the phosphorus-containing gas to the total flow rate of the processing gas is set in such a way that the ratio of the etching rate of the alternating laminated film of the silicon oxide film and the silicon nitride film to the etching rate of the silicon oxide film is greater than 0.8 and less than 1.2. The ratio of the flow rate of the phosphorus-containing gas to the total flow rate of the processing gas can be set to, for example, greater than 10% and less than 50%. Furthermore, the ratio of the etching rate of the alternating laminated film of the silicon oxide film and the silicon nitride film to the etching rate of the silicon oxide film can also be changed by changing the flow rate of the phosphorus-containing gas during the etching of step ST2.
步驟ST2中，將腔室10內之氣體壓力設定為所指定之壓力。步驟ST2中，腔室10內之氣體壓力可設定為10mTorr(1.3Pa)以上100mTorr(13.3Pa)以下之壓力。又，步驟ST2中，供給第1高頻電力及/或第2高頻電力，以於腔室10內由處理氣體生成電漿。第1高頻電力之位準可設定為2kW以上10kW以下之位準。第2高頻電力之位準可設定為2kW(基板W之每單位面積之電力位準為2.83W/cm2)以上之位準。第2高頻電力之位準亦可設定為10kW(基板W之每單位面積之電力位準為14.2W/cm2)以上之位準。In step ST2, the gas pressure in the chamber 10 is set to a specified pressure. In step ST2, the gas pressure in the chamber 10 can be set to a pressure of 10 mTorr (1.3 Pa) or more and 100 mTorr (13.3 Pa) or less. In step ST2, the first high-frequency power and/or the second high-frequency power are supplied to generate plasma from the processing gas in the chamber 10. The level of the first high-frequency power can be set to a level of 2 kW or more and 10 kW or less. The level of the second high-frequency power can be set to a level of 2 kW or more (the power level per unit area of the substrate W is 2.83 W/cm2 ) or more. The level of the second high frequency power can also be set to a level above 10 kW (the power level per unit area of the substrate W is 14.2 W/cm2 ).
控制部80以將處理氣體供給至腔室10內之方式控制氣體供給部，以此執行步驟ST2。又，控制部80以將腔室10內之氣體壓力設定為所指定之壓力之方式控制排氣裝置50。又，控制部80以供給第1高頻電力及/或第2高頻電力之方式控制第1高頻電源62及第2高頻電源64。The control unit 80 controls the gas supply unit to supply the processing gas into the chamber 10, thereby executing step ST2. Furthermore, the control unit 80 controls the exhaust device 50 to set the gas pressure in the chamber 10 to a specified pressure. Furthermore, the control unit 80 controls the first high-frequency power source 62 and the second high-frequency power source 64 to supply the first high-frequency power and/or the second high-frequency power.
一實施方式之方法MT中，步驟ST2開始時之基板W之溫度可設定為0℃以下之溫度。若將基板W之溫度設定為此種溫度，則步驟ST2中之含矽膜SF之蝕刻速率變高。控制部80可控制冷卻器單元，以此設定步驟ST2開始時之基板W之溫度。In the method MT of one embodiment, the temperature of the substrate W at the start of step ST2 can be set to a temperature below 0°C. If the temperature of the substrate W is set to such a temperature, the etching rate of the silicon-containing film SF in step ST2 becomes higher. The control unit 80 can control the cooling unit to set the temperature of the substrate W at the start of step ST2.
步驟ST2係藉由源自由處理氣體所形成之電漿之鹵素化學物種，對含矽膜SF進行蝕刻。一實施方式中，含矽膜SF之整個區域中從遮罩MK露出之部分被蝕刻(參照圖4(a))。Step ST2 is to etch the silicon-containing film SF by using halogen chemical species from plasma formed by the processing gas. In one embodiment, the entire area of the silicon-containing film SF exposed from the mask MK is etched (see FIG. 4(a)).
於一實施方式中，如圖1所示，方法MT亦可進而包含步驟ST3。步驟ST3係於劃分形成開口之側壁面上形成保護膜PF，該開口係藉由步驟ST2之蝕刻而形成於含矽膜SF(參照圖4(a))。保護膜PF含有矽及步驟ST2中使用之處理氣體中所含之磷。一實施方式中，步驟ST3與步驟ST2同時進行。一實施方式中，保護膜PF亦可進而含有處理氣體中所含之碳及/或氫。一實施方式中，保護膜PF亦可進而含有處理氣體中所含或含矽膜SF中所含之氧。根據步驟ST2中對氧化矽膜進行蝕刻之實驗例，保護膜PF之XPS(X-ray photoelectron spectroscopy，X射線光電子光譜)分析之結果為，觀察到Si-O之鍵結峰(bond peak)與P-O之鍵結峰。又，根據步驟ST2中對氮化矽膜進行蝕刻之實驗例，保護膜PF之XPS分析之結果為，觀察到Si-P之鍵結峰與P-N之鍵結峰。In one embodiment, as shown in FIG. 1 , method MT may further include step ST3. Step ST3 is to form a protective film PF on the sidewall surface where the opening is formed by etching in step ST2 in the silicon-containing film SF (see FIG. 4 (a)). The protective film PF contains silicon and phosphorus contained in the processing gas used in step ST2. In one embodiment, step ST3 is performed simultaneously with step ST2. In one embodiment, the protective film PF may further contain carbon and/or hydrogen contained in the processing gas. In one embodiment, the protective film PF may further contain oxygen contained in the processing gas or in the silicon-containing film SF. According to the experimental example of etching the silicon oxide film in step ST2, the result of XPS (X-ray photoelectron spectroscopy) analysis of the protective film PF is that the Si-O bond peak and the P-O bond peak are observed. In addition, according to the experimental example of etching the silicon nitride film in step ST2, the result of XPS analysis of the protective film PF is that the Si-P bond peak and the P-N bond peak are observed.
若處理氣體中不含磷，則如圖4(b)所示，含矽膜SF亦被朝橫向蝕刻。其結果為，形成於含矽膜SF之開口之寬度局部變寬。例如，形成於含矽膜SF之開口之寬度於遮罩MK附近局部變寬。If the processing gas does not contain phosphorus, as shown in FIG4(b), the silicon-containing film SF is also etched in the lateral direction. As a result, the width of the opening formed in the silicon-containing film SF is locally widened. For example, the width of the opening formed in the silicon-containing film SF is locally widened near the mask MK.
另一方面，於方法MT中，於劃分形成開口之側壁面上形成保護膜PF，該開口係藉由蝕刻而形成於含矽膜SF。一面藉由該保護膜PF保護側壁面，一面對含矽膜SF進行蝕刻。因此，根據方法MT，能夠於含矽膜SF之電漿蝕刻時抑制橫向蝕刻。On the other hand, in method MT, a protective film PF is formed on the sidewall surface of the opening formed by etching in the silicon-containing film SF. While the sidewall surface is protected by the protective film PF, the silicon-containing film SF is etched. Therefore, according to method MT, lateral etching can be suppressed during plasma etching of the silicon-containing film SF.
以下，參照圖5(a)及圖5(b)。圖5(a)係可應用圖1所示之蝕刻方法之另一例之基板的局部放大剖視圖，圖5(b)係應用圖1所示之蝕刻方法之另一例之基板的局部放大剖視圖。圖5(a)所示之基板W中，含矽膜SF具有單層膜SL及多層膜ML。單層膜SL例如為氧化矽膜、氮化矽膜或多晶矽膜。多層膜ML可包含所積層之一個以上之氧化矽膜及一個以上之氮化矽膜。多層膜ML亦可包含交替積層之複數個氧化矽膜及複數個氮化矽膜。或者，多層膜ML亦可包含所積層之一個以上之氧化矽膜及一個以上之多晶矽膜。多層膜ML亦可包含交替積層之複數個氧化矽膜及複數個多晶矽膜。或者，多層膜ML亦可包含所積層之一個以上之氧化矽膜、一個以上之多晶矽膜、及一個以上之氮化矽膜。In the following, refer to FIG. 5(a) and FIG. 5(b). FIG. 5(a) is a partially enlarged cross-sectional view of another example of a substrate to which the etching method shown in FIG. 1 can be applied, and FIG. 5(b) is a partially enlarged cross-sectional view of another example of a substrate to which the etching method shown in FIG. 1 can be applied. In the substrate W shown in FIG. 5(a), the silicon-containing film SF has a single-layer film SL and a multi-layer film ML. The single-layer film SL is, for example, a silicon oxide film, a silicon nitride film, or a polycrystalline silicon film. The multi-layer film ML may include one or more silicon oxide films and one or more silicon nitride films stacked. The multi-layer film ML may also include a plurality of silicon oxide films and a plurality of silicon nitride films stacked alternately. Alternatively, the multilayer film ML may include one or more silicon oxide films and one or more polycrystalline silicon films. The multilayer film ML may include a plurality of silicon oxide films and a plurality of polycrystalline silicon films alternately stacked. Alternatively, the multilayer film ML may include one or more silicon oxide films, one or more polycrystalline silicon films, and one or more silicon nitride films stacked.
上述方法MT可應用於圖5(a)所示之基板W。方法MT之步驟ST2中，同時對單層膜SL及多層膜ML進行蝕刻。如上所述，步驟ST2中使用含有鹵素元素及磷之處理氣體。作為一例，處理氣體可含有H2、CxHyFz(x、y、z為0以上之整數)、CxHyFz以外之氟分子或含氟分子、氟以外之鹵素元素或含有氟以外之鹵素之分子、及上述含磷分子。處理氣體中之含氟分子例如為NF3、SF6、HF。處理氣體中之鹵素元素或含鹵素之分子例如為Cl2、HBr、HI、ClF3、IF7。即，處理氣體中之鹵素元素或含鹵素之分子亦可不含氟。或者，處理氣體中之鹵素元素或含鹵素之分子亦可含有氟。包含含磷分子之氣體之流量相對於處理氣體之總流量的比率例如為3%以上20%以下。又，步驟ST2開始時，基板W之溫度設定為0℃以下之溫度，例如設定為-40℃或-70℃。The above method MT can be applied to the substrate W shown in FIG. 5( a ). In step ST2 of method MT, the single-layer film SL and the multi-layer film ML are etched simultaneously. As described above, a treatment gas containing a halogen element and phosphorus is used in step ST2. As an example, the treatment gas may contain H2 , Cx Hy Fz (x, y, z are integers greater than 0), fluorine molecules or fluorine-containing molecules other thanCx H y Fz , halogen elements other than fluorine or molecules containing halogens other than fluorine, and the above phosphorus-containing molecules. Examples of fluorine-containing molecules in the treatment gas are NF3 , SF6 , and HF. Examples of halogen elements or halogen-containing molecules in the treatment gas are Cl2 , HBr, HI, ClF3 , and IF7 . That is, the halogen elements or halogen-containing molecules in the processing gas may not contain fluorine. Alternatively, the halogen elements or halogen-containing molecules in the processing gas may also contain fluorine. The ratio of the flow rate of the gas containing phosphorus molecules to the total flow rate of the processing gas is, for example, 3% to 20%. In addition, at the beginning of step ST2, the temperature of the substrate W is set to a temperature below 0°C, for example, -40°C or -70°C.
方法MT中，如圖5(b)所示，一面藉由保護膜PF保護側壁面，一面對單層膜SL及多層膜ML進行蝕刻。因此，根據方法MT，能夠於同時對單層膜SL及多層膜ML進行電漿蝕刻時抑制橫向蝕刻。又，藉由於步驟ST2中使用上述處理氣體，而降低單層膜SL之蝕刻速率與多層膜ML之蝕刻速率之差。In method MT, as shown in FIG5(b), the side wall surface is protected by the protective film PF while the single-layer film SL and the multi-layer film ML are etched. Therefore, according to method MT, lateral etching can be suppressed when plasma etching is performed on the single-layer film SL and the multi-layer film ML at the same time. In addition, by using the above-mentioned processing gas in step ST2, the difference between the etching rate of the single-layer film SL and the etching rate of the multi-layer film ML is reduced.
以下，對用以評估方法MT之第1實驗進行說明。第1實驗中，準備複數個樣本基板。複數個樣本基板分別具有氧化矽膜及設置於該氧化矽膜上之遮罩。第1實驗中，執行方法MT，對複數個樣本基板之氧化矽膜進行蝕刻。用以對複數個樣本基板各自之氧化矽膜進行蝕刻(步驟ST2)之處理氣體包含流量互不相同之PF3氣體。步驟ST2中之其他條件如下。The following is a description of the first experiment for evaluating the method MT. In the first experiment, a plurality of sample substrates are prepared. The plurality of sample substrates respectively have a silicon oxide film and a mask disposed on the silicon oxide film. In the first experiment, the method MT is executed to etch the silicon oxide films of the plurality of sample substrates. The processing gas used to etch the silicon oxide films of the plurality of sample substrates (step ST2) includesPF3 gas with different flow rates. Other conditions in step ST2 are as follows.
步驟ST2中之腔室10內之氣體壓力：25mTorr(3.3Pa)Gas pressure in chamber 10 in step ST2: 25mTorr (3.3Pa)
步驟ST2中使用之處理氣體：50sccm之CH4氣體、100sccm之CF4氣體、50sccm之O2氣體Processing gases used in step ST2: 50 sccm CH4 gas, 100 sccm CF4 gas, 50 sccm O2 gas
步驟ST2中之第1高頻電力：40MHz、4500WThe first high frequency power in step ST2: 40MHz, 4500W
步驟ST2中之
步驟ST2中之基板溫度(蝕刻開始前之基板支持器之溫度)：-30℃Substrate temperature in step ST2 (temperature of substrate support before etching starts): -30℃
步驟ST2之執行期間之時長：600秒Duration of step ST2 execution: 600 seconds
第1實驗中，針對複數個樣本基板之各者，求出形成於氧化矽膜之開口之最大寬度及氧化矽膜之蝕刻速率。並且，求出步驟ST2中使用之處理氣體中之PF3氣體之流量與氧化矽膜之蝕刻速率的關係。又，求出步驟ST2中使用之處理氣體中之PF3氣體之流量與形成於氧化矽膜之開口之最大寬度的關係。圖6中示出處理氣體中之PF3氣體之流量與氧化矽膜之蝕刻速率的關係。又，圖7中示出處理氣體中之PF3氣體之流量與形成於氧化矽膜之開口之最大寬度的關係。如圖6所示，可確認出，藉由在處理氣體中含有磷，氧化矽膜之蝕刻速率變高。再者，可確認出，於處理氣體中之PF3氣體之流量為20sccm以上之情形時，與未添加PF3之情形相比，蝕刻速率成為1.5倍左右。又，如圖7所示，可確認出，藉由在處理氣體中含有磷，側壁面得以保護，氧化矽膜之開口之最大寬度變小，即，能夠抑制氧化矽膜之開口寬度局部變寬。可確認出，尤其在處理氣體中之PF3氣體之流量為15sccm之情形時，抑制氧化矽膜之開口寬度局部變寬之效果、即側壁面之保護效果變大。又，可確認出，於處理氣體中之PF3氣體之流量為50sccm以上之情形時，可更顯著地抑制氧化矽膜之開口寬度局部變寬。即，可確認出，於處理氣體中之PF3氣體之流量為50sccm以上之情形時，側壁面之保護效果更為顯著。In the first experiment, the maximum width of the opening formed in the silicon oxide film and the etching rate of the silicon oxide film were obtained for each of the plurality of sample substrates. In addition, the relationship between the flow rate of thePF3 gas in the processing gas used in step ST2 and the etching rate of the silicon oxide film was obtained. In addition, the relationship between the flow rate of thePF3 gas in the processing gas used in step ST2 and the maximum width of the opening formed in the silicon oxide film was obtained. FIG. 6 shows the relationship between the flow rate of thePF3 gas in the processing gas and the etching rate of the silicon oxide film. In addition, FIG. 7 shows the relationship between the flow rate of thePF3 gas in the processing gas and the maximum width of the opening formed in the silicon oxide film. As shown in FIG. 6 , it can be confirmed that the etching rate of the silicon oxide film increases by including phosphorus in the process gas. Furthermore, it can be confirmed that when the flow rate of PF3 gas in the process gas is 20 sccm or more, the etching rate is about 1.5 times higher than that when PF3 is not added. Also, as shown in FIG. 7 , it can be confirmed that by including phosphorus in the process gas, the sidewall surface is protected and the maximum width of the opening of the silicon oxide film is reduced, that is, the local widening of the opening width of the silicon oxide film can be suppressed. It can be confirmed that, especially when the flow rate of PF3 gas in the process gas is 15 sccm, the effect of suppressing the local widening of the opening width of the silicon oxide film, that is, the effect of protecting the sidewall surface becomes greater. In addition, it can be confirmed that when the flow rate ofPF3 gas in the process gas is 50 sccm or more, the local widening of the opening width of the silicon oxide film can be more significantly suppressed. In other words, it can be confirmed that when the flow rate ofPF3 gas in the process gas is 50 sccm or more, the protective effect of the side wall surface is more significant.
以下，對用以評估方法MT之第2實驗進行說明。第2實驗中，準備第1樣本基板及第2樣本基板。第1樣本基板具有作為氧化矽膜之單層膜。第2樣本基板具有包含交替積層之複數個氧化矽膜及複數個氮化矽膜之多層膜。第2實驗中，使用電漿處理裝置1執行方法MT，對第1樣本基板之單層膜及第2樣本基板之多層膜進行蝕刻。用於蝕刻(步驟ST2)之處理氣體含有H2、氫氟碳、含氟分子、含鹵素分子、及上述含磷分子。又，進行比較實驗。比較實驗中，使用與第2實驗之步驟ST2中使用之處理氣體不同之處理氣體，對第1樣本基板之單層膜及第2樣本基板之多層膜進行蝕刻。比較實驗中使用之處理氣體與第2實驗之步驟ST2中使用之處理氣體之不同點在於，不包含含磷分子。The following is a description of the second experiment for evaluating the method MT. In the second experiment, a first sample substrate and a second sample substrate are prepared. The first sample substrate has a single-layer film as a silicon oxide film. The second sample substrate has a multi-layer film including a plurality of silicon oxide films and a plurality of silicon nitride films alternately stacked. In the second experiment, the method MT is performed using a plasma processing device 1 to etch the single-layer film of the first sample substrate and the multi-layer film of the second sample substrate. The processing gas used for etching (step ST2) containsH2 , hydrofluorocarbon, fluorine-containing molecules, halogen-containing molecules, and the above-mentioned phosphorus-containing molecules. In addition, a comparative experiment is performed. In the comparative experiment, a processing gas different from the processing gas used in step ST2 of the second experiment was used to etch the single-layer film of the first sample substrate and the multi-layer film of the second sample substrate. The processing gas used in the comparative experiment is different from the processing gas used in step ST2 of the second experiment in that it does not contain phosphorus-containing molecules.
第2實驗及比較實驗中，求出多層膜之蝕刻速率相對於單層膜之蝕刻速率之比值。比較實驗中，於蝕刻開始時之第1樣本基板及第2樣本基板各自之溫度為-40℃之情形時，比值約為1.3。另一方面，第2實驗中，於蝕刻開始時之第1樣本基板及第2樣本基板各自之溫度為-40℃之情形時，比值約為1.17。又，第2實驗中，於蝕刻開始時之第1樣本基板及第2樣本基板各自之溫度為-70℃之情形時，比值約為1.05。根據該等實驗結果可確認，藉由在步驟ST2中使用含有含磷分子之處理氣體，而能夠降低單層膜之蝕刻速率與多層膜之蝕刻速率之間的差。又，可確認出，蝕刻開始時之基板溫度越低，單層膜之蝕刻速率與多層膜之蝕刻速率之間的差越小。In the second experiment and the comparative experiment, the ratio of the etching rate of the multi-layer film to the etching rate of the single-layer film was obtained. In the comparative experiment, when the temperature of the first sample substrate and the second sample substrate at the start of etching was -40°C, the ratio was about 1.3. On the other hand, in the second experiment, when the temperature of the first sample substrate and the second sample substrate at the start of etching was -40°C, the ratio was about 1.17. In addition, in the second experiment, when the temperature of the first sample substrate and the second sample substrate at the start of etching was -70°C, the ratio was about 1.05. According to these experimental results, it can be confirmed that the difference between the etching rate of a single-layer film and the etching rate of a multi-layer film can be reduced by using a processing gas containing phosphorus molecules in step ST2. In addition, it can be confirmed that the lower the substrate temperature at the beginning of etching, the smaller the difference between the etching rate of a single-layer film and the etching rate of a multi-layer film.
以下，對用以評估方法MT之第3實驗進行說明。第3實驗中，準備複數個第1樣本基板及複數個第2樣本基板。複數個第1樣本基板分別具有氧化矽膜(單層膜)。複數個第2樣本基板分別具有氧化矽膜與氮化矽膜之交替積層膜。第3實驗中，使用電漿處理裝置1執行方法MT，對複數個第1樣本基板之單層膜及複數個第2樣本基板之積層膜進行蝕刻。用於蝕刻(步驟ST2)之處理氣體包含H2氣體、氫氟碳氣體、含氟分子之氣體、不含氟之含鹵素分子之氣體、及含鹵素及磷之氣體(PF3氣體)。第3實驗中，於複數個第1樣本基板之單層膜之蝕刻中使用蝕刻時之溫度及PF3氣體之流量之比率互不相同之複數個組合。蝕刻時之溫度係蝕刻開始時之樣本基板之溫度(熱媒之溫度)。又，PF3氣體之流量之比率係PF3氣體之流量相對於處理氣體之總流量之比率。又，於複數個第2樣本基板之積層膜之蝕刻中使用在複數個第1樣本基板之單層膜之蝕刻中使用的蝕刻時之溫度及PF3氣體之流量之比率互不相同的複數個組合。再者，複數個第1樣本基板之單層膜及複數個第2樣本基板之交替積層膜之蝕刻時的第2高頻電力之有效功率為6kW。The following is a description of the third experiment for evaluating the method MT. In the third experiment, a plurality of first sample substrates and a plurality of second sample substrates are prepared. The plurality of first sample substrates respectively have a silicon oxide film (single-layer film). The plurality of second sample substrates respectively have alternating laminated films of silicon oxide films and silicon nitride films. In the third experiment, the method MT is performed using a plasma processing device 1 to etch the single-layer films of the plurality of first sample substrates and the laminated films of the plurality of second sample substrates. The processing gas used for etching (step ST2) includesH2 gas, hydrofluorocarbon gas, gas containing fluorine molecules, gas containing halogen molecules without fluorine, and gas containing halogen and phosphorus (PF3 gas). In the third experiment, a plurality of combinations of different ratios of the etching temperature and the flow rate ofPF3 gas were used in the etching of a single-layer film on a plurality of first sample substrates. The etching temperature is the temperature of the sample substrate at the start of etching (temperature of the heat medium). In addition, the flow rate ratio ofPF3 gas is the ratio of the flow rate ofPF3 gas to the total flow rate of the process gas. In addition, a plurality of combinations of different ratios of the etching temperature and the flow rate ofPF3 gas used in the etching of a single-layer film on a plurality of first sample substrates were used in the etching of a multilayer film on a plurality of second sample substrates. Furthermore, the effective power of the second high-frequency power during the etching of the single-layer films of the plurality of first sample substrates and the alternately laminated films of the plurality of second sample substrates was 6 kW.
第3實驗中，根據複數個第1樣本基板之單層膜之蝕刻結果，求出複數個第1樣本基板之單層膜各自之蝕刻速率。又，根據複數個第2樣本基板之積層膜之蝕刻結果，求出複數個第2樣本基板之積層膜各自之蝕刻速率。並且，求出上述複數個組合之各自情況下的氧化矽膜與氮化矽膜之交替積層膜之蝕刻速率相對於氧化矽膜(單層膜)之蝕刻速率的比。並且，求出PF3氣體之流量之比率與蝕刻速率之比的關係。圖8之曲線圖中示出了第3實驗中求出的PF3氣體之流量比率與蝕刻速率之比。如圖8所示，根據第3實驗之結果可確認，藉由調整PF3氣體之流量比率，能夠調整蝕刻速率之比。又，可確認出，藉由將PF3氣體之流量比率設為10%以上50%以下，能夠在不依賴於蝕刻開始時之樣本基板溫度的情況下將蝕刻速率之比設定為0.8以上1.2以下。In the third experiment, based on the etching results of the single-layer films of the plurality of first sample substrates, the etching rates of the single-layer films of the plurality of first sample substrates were obtained. Furthermore, based on the etching results of the multilayer films of the plurality of second sample substrates, the etching rates of the multilayer films of the plurality of second samplesubstrates were obtained. Furthermore, the ratio of the etching rate of the alternating multilayer films of silicon oxide film and silicon nitride film to the etching rate of the silicon oxide film (single-layer film) was obtained for each of the above-mentioned plurality of combinations. Furthermore, the relationship between the ratio of the flow rate of PF3 gas and the ratio of the etching rate was obtained. The curve diagram of FIG8 shows the ratio of the flow rate ratio ofPF3 gas and the etching rate obtained in the third experiment. As shown in FIG8 , the results of the third experiment confirmed that the etching rate ratio can be adjusted by adjusting the flow rate ratio of thePF3 gas. In addition, it was confirmed that the etching rate ratio can be set to 0.8 to 1.2 without depending on the sample substrate temperature at the start of etching by setting the flow rate ratio of thePF3 gas to 10% to 50%.
以上，對各種例示性實施方式進行了說明，但並不限定於上述所例示之實施方式，亦可進行多種追加、省略、替換及變更。又，能夠將不同實施方式中之要素組合而形成其他實施方式。Various exemplary implementations have been described above, but they are not limited to the above-described exemplary implementations, and various additions, omissions, replacements, and changes may be made. Furthermore, elements in different implementations may be combined to form other implementations.
例如，方法MT中使用之電漿處理裝置亦可為電漿處理裝置1以外之電容耦合型電漿處理裝置。或者，方法MT中使用之電漿處理裝置亦可為感應耦合型電漿處理裝置、電子回旋共振(ECR)電漿處理裝置、或使用微波等表面波生成電漿之電漿處理裝置等。For example, the plasma processing device used in method MT may be a capacitive coupling type plasma processing device other than plasma processing device 1. Alternatively, the plasma processing device used in method MT may be an inductive coupling type plasma processing device, an electron cyclotron resonance (ECR) plasma processing device, or a plasma processing device that generates plasma using surface waves such as microwaves, etc.
又，電漿處理裝置亦可代替第2高頻電源64或者除第2高頻電源64以外，還具備直流電源，該直流電源構成為將負極性直流電壓之脈衝斷續或週期性地施加至下部電極18。Furthermore, the plasma processing device may also include a DC power source instead of the second high-frequency power source 64 or in addition to the second high-frequency power source 64, and the DC power source is configured to apply a pulse of a negative polarity DC voltage to the lower electrode 18 intermittently or periodically.
根據以上說明，應當理解的是，本發明之各種實施方式係以說明為目的於本說明書中進行說明，可在不脫離本發明之範圍及主旨之情況下進行各種變更。因此，本說明書中所揭示之各種實施方式並不意圖進行限定，真正之範圍及主旨由隨附之申請專利範圍表示。According to the above description, it should be understood that the various embodiments of the present invention are described in this specification for the purpose of explanation, and various changes can be made without departing from the scope and gist of the present invention. Therefore, the various embodiments disclosed in this specification are not intended to be limiting, and the true scope and gist are indicated by the attached patent application scope.
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