本發明是有關於一種控制裝置以及記憶體系統。The present invention relates to a control device and a memory system.
現行記憶體的電源管理模式可以支援深度省電(Deep Power Down，DPD)模式。在暫時不需用到記憶體時可進入休眠狀態，無須更新記憶體，可減少待機時功率的消耗。但是，在DPD模式時的DPD電流ICC2更為嚴苛(小於1μA)。在製程微縮時，元件的關閉漏電流Ioff往往反而增大，尤其在高溫時更為嚴重。目前的產品是將內部電源int_VDD在DPD模式時關閉，藉以降低元件的關閉漏電流Ioff以符合ICC2 的設計規格。The current memory power management mode can support the Deep Power Down (DPD) mode. When the memory is not needed temporarily, it can enter the sleep state without updating the memory, which can reduce the power consumption in standby mode. However, the DPD current ICC2 in DPD mode is more stringent (less than 1μA). When the process is miniaturized, the off leakage current Ioff of the component often increases, especially at high temperatures. The current product turns off the internal power int_VDD in DPD mode to reduce the off leakage current Ioff of the component to meet the design specifications of ICC2.
㇐般在NAND 記憶體中會用熔絲記憶胞儲存在讀取、程式化及抹除時所需的電壓設定值。目前的做法是在DPD模式時將內部電源int_VDD關閉。然而在離開DPD模式時，待內部電源int_VDD 投入後，熔絲記憶胞的資訊需重新儲存到熔絲暫存器中。因此熔絲需進行重新儲存的操作，使得回復時間tRES可能會增加至超過3ms。因此，如何縮短回復時間tRES為一亟待解決的課題。Generally, in NAND memory, fuse cells are used to store the voltage settings required for reading, programming, and erasing. The current practice is to turn off the internal power supply int_VDD in DPD mode. However, when leaving DPD mode, after the internal power supply int_VDD is turned on, the information in the fuse memory cell needs to be stored again in the fuse register. Therefore, the fuse needs to be re-stored, which may increase the recovery time tRES to more than 3ms. Therefore, how to shorten the recovery time tRES is an issue that needs to be solved urgently.
本發明提供一種控制裝置，用於控制記憶體系統。所述控制裝置包括：第一周邊電路群，在所述記憶體系統為待機模式下，藉由第一電壓驅動；第二周邊電路群，耦接於所述第一周邊電路群，在所述記憶體系統為待機模式下，以第二電壓驅動；第三周邊電路群，耦接於所述第一周邊電路群與所述第一周邊電路群之間。所述第三周邊電路群架構為熔絲記憶電路，並且在所述記憶體系統基於深度省電模式訊號為第一邏輯值而進入深度省電模式時，所述熔絲記憶電路是使工作電壓處於上限值與下限值之間運作，所述上限值低於所述第二電壓。The present invention provides a control device for controlling a memory system. The control device includes: a first peripheral circuit group, which is driven by a first voltage when the memory system is in standby mode; a second peripheral circuit group, which is coupled to the first peripheral circuit group, which is driven by a second voltage when the memory system is in standby mode; and a third peripheral circuit group, which is coupled between the first peripheral circuit group and the first peripheral circuit group. The third peripheral circuit group is structured as a fuse memory circuit, and when the memory system enters a deep power saving mode based on a deep power saving mode signal being a first logic value, the fuse memory circuit operates so that the operating voltage is between an upper limit value and a lower limit value, and the upper limit value is lower than the second voltage.
本發明提供一種記憶體系統，其包括：記憶體陣列；以及控制裝置，用於控制所述記憶體陣列。所述控制裝置包括：第一周邊電路群，耦接於所述記憶體陣列，在所述記憶體陣列為待機模式下，與所述記憶體陣列共同以第一電壓驅動；第二周邊電路群，耦接於所述該記憶體陣列以及所述第一周邊電路群，在所述記憶體陣列為所述待機模式時，以第二電壓驅動；第三周邊電路群，耦接於所述第一周邊電路群與所述第一周邊電路群之間，其中所述第二周邊電路群架構為熔絲記憶電路，並且在所述記憶體系統基於深度省電模式訊號為第一邏輯值而進入深度省電模式時，所述熔絲記憶電路是使工作電壓處於上限值與下限值之間運作，所述上限值低於所述第二電壓。The present invention provides a memory system, comprising: a memory array; and a control device for controlling the memory array. The control device comprises: a first peripheral circuit group, coupled to the memory array, and driven together with the memory array with a first voltage when the memory array is in a standby mode; a second peripheral circuit group, coupled to the memory array and the first peripheral circuit group, and driven with a second voltage when the memory array is in the standby mode; and a third peripheral circuit group, The second peripheral circuit group is coupled between the first peripheral circuit group and the second peripheral circuit group, wherein the second peripheral circuit group is structured as a fuse memory circuit, and when the memory system enters a deep power saving mode based on a deep power saving mode signal being a first logic value, the fuse memory circuit operates so that the operating voltage is between an upper limit value and a lower limit value, and the upper limit value is lower than the second voltage.
本發明提供一種控制方法，用於控制記憶體系統。所述記憶體系統具有控制裝置，該控制裝置包括以第一電壓運作的第一周邊電路群、以第二電壓運作的第二周邊電路群以及與所述第一周邊電路群和所述第二電路群獨立設置的第三周邊電路群。所述控制方法包括：判斷所述記憶體系統是否要進入深度省電模式；當判斷所述記憶體系統進入所述深度省電模式時，對所述第三周邊電路群中的熔絲暫存器檢測工作電壓，其中所述熔絲暫存器用以儲存所述記憶體系統的操作的電壓資訊；以及直到離開所述深度省電模式為止，基於檢測的所述工作電壓，使所述熔絲暫存器的所述工作電壓在上限值與下限值之間，所述上限值低於所述第二電壓。The present invention provides a control method for controlling a memory system. The memory system has a control device, which includes a first peripheral circuit group operating at a first voltage, a second peripheral circuit group operating at a second voltage, and a third peripheral circuit group independently provided from the first peripheral circuit group and the second circuit group. The control method includes: determining whether the memory system is to enter a deep power saving mode; when determining that the memory system is to enter the deep power saving mode, detecting an operating voltage of a fuse register in the third peripheral circuit group, wherein the fuse register is used to store voltage information of the operation of the memory system; and until leaving the deep power saving mode, based on the detected operating voltage, making the operating voltage of the fuse register between an upper limit value and a lower limit value, wherein the upper limit value is lower than the second voltage.
記憶體系統中的熔絲暫存器會儲存記憶體之程式化、抹除與讀取等操作時所需要的一些電壓資訊，例如各種操作的電壓值等。在進行特定操作時，記憶體便會從熔絲暫存器讀取出相應的資訊，以進行該特定操作。The fuse register in the memory system stores some voltage information required for programming, erasing, and reading the memory, such as the voltage values of various operations. When performing a specific operation, the memory will read the corresponding information from the fuse register to perform the specific operation.
圖1是依據本發明一實施例所繪示的記憶體系統的配置示意圖。在本實施例中，記憶體系統10包括記憶體陣列20以及對記憶體陣列20進行控制的控制裝置30。在待機模式，記憶體陣列20藉由第一電壓V1被驅動。控制裝置30包括周邊電路群100以及周邊電路群200。周邊電路群100耦接於記憶體陣列20。在待機模式，周邊電路群100藉由第一電壓V1被驅動。也就是說，在待機模式，周邊電路群100與記憶體陣列20通過第一電壓V1而被共同驅動。此外，周邊電路群200耦接於記憶體陣列20以及周邊電路群100。周邊電路群200通過第二電壓V2而驅動。在此架構中，周邊電路群100可視為VDD電源域區塊。周邊電路群200可視為VCC電源域區塊。FIG1 is a configuration diagram of a memory system according to an embodiment of the present invention. In this embodiment, the memory system 10 includes a memory array 20 and a control device 30 for controlling the memory array 20. In standby mode, the memory array 20 is driven by a first voltage V1. The control device 30 includes a peripheral circuit group 100 and a peripheral circuit group 200. The peripheral circuit group 100 is coupled to the memory array 20. In standby mode, the peripheral circuit group 100 is driven by the first voltage V1. That is, in standby mode, the peripheral circuit group 100 and the memory array 20 are driven together by the first voltage V1. In addition, the peripheral circuit group 200 is coupled to the memory array 20 and the peripheral circuit group 100. The peripheral circuit group 200 is driven by the second voltage V2. In this architecture, the peripheral circuit group 100 can be regarded as a VDD power domain block. The peripheral circuit group 200 can be regarded as a VCC power domain block.
在本實施例中，周邊電路群100可以包括輸出入控制單元101與命令介面邏輯單元102。命令介面邏輯單元102可連接到周邊電路群300。此外，周邊電路群100至少還可以包括行/列控制器103、緊連邏輯(glue logic )單元104、周邊控制單元105以及如SRAM或ROM等的外部記憶體106。In this embodiment, the peripheral circuit group 100 may include an input/output control unit 101 and a command interface logic unit 102. The command interface logic unit 102 may be connected to the peripheral circuit group 300. In addition, the peripheral circuit group 100 may also include at least a row/column controller 103, a glue logic unit 104, a peripheral control unit 105, and an external memory 106 such as SRAM or ROM.
命令介面邏輯單元102耦接周邊電路群200的輸出入緩衝器201。命令介面邏輯單元102會經由輸出入緩衝器201接收命令串列CMDS。在待機模式，命令介面邏輯單元102會對命令串列CMDS進行識別。在識別出命令串列CMDS是深度省電執行命令串列時，命令介面邏輯單元102會對深度省電執行命令串列進行解碼以產生控制命令CCMD，並且將控制命令CCMD提供至周邊電路群200。The command interface logic unit 102 is coupled to the input/output buffer 201 of the peripheral circuit group 200. The command interface logic unit 102 receives the command serial CMDS via the input/output buffer 201. In the standby mode, the command interface logic unit 102 identifies the command serial CMDS. When the command serial CMDS is identified as a deep power saving execution command serial, the command interface logic unit 102 decodes the deep power saving execution command serial to generate a control command CCMD, and provides the control command CCMD to the peripheral circuit group 200.
周邊電路群200還包括準位移位器203、鎖存器204、電壓調節電路205、電源開關206以及周邊電路群210。準位移位器203耦接於周邊電路群100。準位移位器203對控制命令CCMD的電壓準位進行移位。鎖存器204耦接於準位移位器203以及解除命令串列解碼器202。鎖存器204對控制命令CCMD進行鎖存，並將控制命令CCMD提供至解除命令串列解碼器202。解除命令串列解碼器202會依據鎖存的控制命令CCMD提供具有第一邏輯值(例如高準位H)的DPD模式訊號DPDMD。The peripheral circuit group 200 further includes a level shifter 203, a latch 204, a voltage regulating circuit 205, a power switch 206, and a peripheral circuit group 210. The level shifter 203 is coupled to the peripheral circuit group 100. The level shifter 203 shifts the voltage level of the control command CCMD. The latch 204 is coupled to the level shifter 203 and the release command serial decoder 202. The latch 204 latches the control command CCMD and provides the control command CCMD to the release command serial decoder 202. The release command serial decoder 202 provides a DPD mode signal DPDMD having a first logic value (e.g., a high level H) according to the latched control command CCMD.
在本實施例中，電壓調節電路205耦接於記憶體陣列20、周邊電路群100以及解除命令串列解碼器202。電壓調節電路205依據具有第二邏輯值的深度省電訊號DPDMD將第二電壓V2 (VCC)調節為第一電壓V1 (VDD)，並將第一電壓V1 (VDD)提供至記憶體陣列20以及周邊電路群100。電壓調節電路205依據具有第一邏輯值的深度省電訊號DPDMD停止將第一電壓V1 (VDD)提供至記憶體陣列20以及周邊電路群100。In this embodiment, the voltage regulating circuit 205 is coupled to the memory array 20, the peripheral circuit group 100, and the deactivation command serial decoder 202. The voltage regulating circuit 205 regulates the second voltage V2 (VCC) to the first voltage V1 (VDD) according to the deep power saving signal DPDMD having the second logic value, and provides the first voltage V1 (VDD) to the memory array 20 and the peripheral circuit group 100. The voltage regulating circuit 205 stops providing the first voltage V1 (VDD) to the memory array 20 and the peripheral circuit group 100 according to the deep power saving signal DPDMD having the first logic value.
電源開關206耦接於周邊電路群210以及解除命令串列解碼器202。電源開關206依據具有第一邏輯值的DPD模式訊號DPDMD將第二電壓V2提供至周邊電路群210，並且依據具有第一邏輯值的DPD模式訊號DPDMD停止將第二電壓V2提供至周邊電路群210。因此，周邊電路群210在待機模式藉由第二電壓V2被驅動，並且在DPD模式停止被驅動。也就是說，在DPD模式，僅有輸入輸出緩衝器201、解除命令串列解碼器202、準位移位器203、鎖存器204維持運作。The power switch 206 is coupled to the peripheral circuit group 210 and the release command serial decoder 202. The power switch 206 provides the second voltage V2 to the peripheral circuit group 210 according to the DPD mode signal DPDMD having the first logic value, and stops providing the second voltage V2 to the peripheral circuit group 210 according to the DPD mode signal DPDMD having the first logic value. Therefore, the peripheral circuit group 210 is driven by the second voltage V2 in the standby mode, and stops being driven in the DPD mode. That is, in the DPD mode, only the input/output buffer 201, the release command serial decoder 202, the level shifter 203, and the latch 204 maintain operation.
此外，周邊電路群210例如是包括投電（power-on）電路211、能隙電路212以及類比電路213等適用於進入待機模式所需的電路。In addition, the peripheral circuit group 210 includes, for example, a power-on circuit 211 , a bandgap circuit 212 , and an analog circuit 213 , etc., which are suitable for entering the standby mode.
控制裝置30還進一步包括高電壓調節器400。高電壓調節器400耦接於周邊電路群200的電壓調節電路205。高電壓調節器400在待機模式將電壓調節電路205所提供的第一電壓V1調節為第三電壓V3，並將第三電壓V3提供至記憶體陣列20。第三電壓V3的電壓值高於第二電壓V2的電壓值。在DPD模式，高電壓調節器400則無法接收到電壓調節電路205所提供的第一電壓V1。因此，高電壓調節器400在DPD模式被禁能而不會提供第三電壓V3。The control device 30 further includes a high voltage regulator 400. The high voltage regulator 400 is coupled to the voltage regulator circuit 205 of the peripheral circuit group 200. In the standby mode, the high voltage regulator 400 regulates the first voltage V1 provided by the voltage regulator circuit 205 into a third voltage V3, and provides the third voltage V3 to the memory array 20. The voltage value of the third voltage V3 is higher than the voltage value of the second voltage V2. In the DPD mode, the high voltage regulator 400 cannot receive the first voltage V1 provided by the voltage regulator circuit 205. Therefore, the high voltage regulator 400 is disabled in the DPD mode and does not provide the third voltage V3.
根據本發明實施方式，記憶體系統10還包括周邊電路群300，其用來設置熔絲記憶電路310。通過此熔絲記憶電路310，在記憶體系統10進入DPD模式時，熔絲記憶電路310仍可維持運作，亦即持續保存記憶體操作時所需要的電壓設定值。換句話說，本發明實施例是將熔絲暫存器的工作電壓(即內部電源)VDDREG獨立分開，使得記憶體系統10在進入DPD模式時，用以維持熔絲暫存器可以正常工作的電壓。也就是說，在DPD模式下，熔絲記憶電路310不會被禁能，並且仍夠持續運作。According to the embodiment of the present invention, the memory system 10 further includes a peripheral circuit group 300, which is used to set a fuse memory circuit 310. Through this fuse memory circuit 310, when the memory system 10 enters the DPD mode, the fuse memory circuit 310 can still maintain operation, that is, continue to save the voltage setting value required for memory operation. In other words, the embodiment of the present invention is to independently separate the working voltage (i.e., internal power supply) VDDREG of the fuse register, so that when the memory system 10 enters the DPD mode, it is used to maintain the voltage at which the fuse register can work normally. That is, in the DPD mode, the fuse memory circuit 310 is not disabled and still continues to operate.
如圖2所示，根據本發明的實施方式，作為一個例子，熔絲記憶電路310包括低電壓檢測器312、熔絲暫存器314、邏輯電路316、電晶體318以及電容器C。As shown in FIG. 2 , according to an embodiment of the present invention, as an example, a fuse memory circuit 310 includes a low voltage detector 312, a fuse register 314, a logic circuit 316, a transistor 318, and a capacitor C.
熔絲記憶電路310耦接在控制裝置30的周邊電路群100與周邊電路群200之間。此外，熔絲記憶電路310接收來自周邊電路群200的DPD模式訊號DPDMD。有別於在第一電壓域工作的周邊電路群100以及在第二電壓域工作的周邊電路群200，熔絲記憶電路310是在第三電壓域進行運作。此第三電壓域是在DPD模式時，可以使熔絲記憶電路310內的熔絲暫存器304進行運作的工作電壓VDDREG，其可以略小於第二電壓V2 (即，VCC)。The fuse memory circuit 310 is coupled between the peripheral circuit group 100 and the peripheral circuit group 200 of the control device 30. In addition, the fuse memory circuit 310 receives the DPD mode signal DPDMD from the peripheral circuit group 200. Different from the peripheral circuit group 100 operating in the first voltage domain and the peripheral circuit group 200 operating in the second voltage domain, the fuse memory circuit 310 operates in the third voltage domain. The third voltage domain is an operating voltage VDDREG that enables the fuse register 304 in the fuse memory circuit 310 to operate in the DPD mode, which can be slightly less than the second voltage V2 (i.e., VCC).
如圖2與圖3所示，熔絲暫存器314是用以儲存記憶體陣列20進行各種操作時的電壓資訊(離開DPD模式後)。低電壓檢測器312是用以檢測熔絲暫存器314的工作電壓VDDREG，並且工作電壓VDDREG的大小，輸出低電壓檢測訊號DPD_CHR。如圖3所示，在時間點T1，記憶體系統10基於DPD模式訊號DPDMD變成第一邏輯值的高準位後，進入DPD模式。此時，原本熔絲暫存器314的工作電壓VDDREG等於第二電壓VCC。一旦進入DPD模式，工作電壓VDDREG便開始下降，而低於第二電壓VCC。As shown in FIG. 2 and FIG. 3 , the fuse register 314 is used to store voltage information when the memory array 20 performs various operations (after leaving the DPD mode). The low voltage detector 312 is used to detect the operating voltage VDDREG of the fuse register 314, and outputs the low voltage detection signal DPD_CHR according to the size of the operating voltage VDDREG. As shown in FIG. 3 , at time point T1, the memory system 10 enters the DPD mode after the DPD mode signal DPDMD becomes a high level of the first logical value. At this time, the original operating voltage VDDREG of the fuse register 314 is equal to the second voltage VCC. Once entering the DPD mode, the operating voltage VDDREG begins to decrease and is lower than the second voltage VCC.
當工作電壓VDDREG持續下降達到下限值VL時，此時低電壓檢測訊號DPD_CHR成為第一邏輯值(高準位)，即低電壓檢測器312輸出高準位的低電壓檢測訊號DPD_CHR。接著，通過對電容器C (後述)進行充電，工作電壓VDDREG便開始上升。當工作電壓VDDREG達到上限值VH時，低電壓檢測器312輸出第二邏輯值(低準位)的低電壓檢測訊號DPD_CHR。如此，在DPD模式下，工作電壓VDDREG反覆地在上限值VH與下限值VL之間變動，藉此使熔絲暫存器314在DPD模式下可以維持運作。在此例，上限值VH與下限值VL是在DPD模式中可以維持熔絲暫存器314運作的最低限電壓範圍。在一示例中，在周邊電路群200的第二電壓V2(即VCC)為1.8V時，上限值VH例如可設定為1.55V，下限值VL可設定為1.0V。When the operating voltage VDDREG continues to decrease and reaches the lower limit value VL, the low voltage detection signal DPD_CHR becomes a first logical value (high level), that is, the low voltage detector 312 outputs a high-level low voltage detection signal DPD_CHR. Then, by charging the capacitor C (described later), the operating voltage VDDREG begins to rise. When the operating voltage VDDREG reaches the upper limit value VH, the low voltage detector 312 outputs a low voltage detection signal DPD_CHR of a second logical value (low level). In this way, in the DPD mode, the operating voltage VDDREG repeatedly changes between the upper limit value VH and the lower limit value VL, thereby allowing the fuse register 314 to maintain operation in the DPD mode. In this example, the upper limit VH and the lower limit VL are the minimum voltage ranges that can maintain the operation of the fuse register 314 in the DPD mode. In one example, when the second voltage V2 (ie, VCC) of the peripheral circuit group 200 is 1.8V, the upper limit VH can be set to 1.55V, and the lower limit VL can be set to 1.0V.
邏輯電路316耦接至低電壓檢測器312，以接收深度省電模式訊號DPDMD以及低電壓檢測訊號DPD_CHR，以將兩者進行邏輯運算。此外，電晶體318具有作為控制端的閘極、第一端與第二端(源極/汲極)。控制端耦接至邏輯電路316的輸出，電晶體318的第一端耦接至第二電壓V2 (即VCC)。電晶體318是基於上述邏輯電路316的邏輯運算的結果進行開關。此外，電容器C具有耦接至電晶體318的所述第二端的第一端，以及耦接至接地的第二端。此外，電晶體318和電容器C的耦接節點N進一步與熔絲暫存器314耦接，以提供工作電壓VDDREG。The logic circuit 316 is coupled to the low voltage detector 312 to receive the deep power saving mode signal DPDMD and the low voltage detection signal DPD_CHR to perform a logic operation on the two. In addition, the transistor 318 has a gate as a control end, a first end and a second end (source/drain). The control end is coupled to the output of the logic circuit 316, and the first end of the transistor 318 is coupled to the second voltage V2 (i.e., VCC). The transistor 318 is switched based on the result of the logic operation of the above-mentioned logic circuit 316. In addition, the capacitor C has a first end coupled to the second end of the transistor 318, and a second end coupled to the ground. In addition, a coupling node N of the transistor 318 and the capacitor C is further coupled to the fuse register 314 to provide an operating voltage VDDREG.
此外，作為一個例子，邏輯電路316可以包括反相器INV與反或閘NOR。在此狀況下，電晶體318可以是PMOS電晶體。反相器INV的輸入端接收DPD模式訊號DPDMD。反相器INV可以將所接收的DPD模式訊號DPDMD進行反相。反相器INV的輸出端則耦接到反或閘NOR的一輸入端。反或閘NOR的另一輸入端接收來自低電壓檢測電器312的低電壓檢測訊號DPD_CHR。反或閘NOR的輸出則做為邏輯電路316的輸出端，並耦接到電晶體318的閘極。由此，可以通過邏輯電路316的邏輯運算結果來控制電晶體318的開關。此外，邏輯電路316和電晶體318也可以採用其他的架構，只要能達成上述的控制方式即可，本發明並未特別限制。In addition, as an example, the logic circuit 316 may include an inverter INV and an anti-OR gate NOR. In this case, the transistor 318 may be a PMOS transistor. The input end of the inverter INV receives the DPD mode signal DPDMD. The inverter INV can invert the received DPD mode signal DPDMD. The output end of the inverter INV is coupled to an input end of the anti-OR gate NOR. The other input end of the anti-OR gate NOR receives the low voltage detection signal DPD_CHR from the low voltage detection circuit 312. The output of the anti-OR gate NOR serves as the output end of the logic circuit 316 and is coupled to the gate of the transistor 318. Thus, the switching of transistor 318 can be controlled by the logic operation result of logic circuit 316. In addition, logic circuit 316 and transistor 318 can also adopt other structures as long as the above control method can be achieved, and the present invention is not particularly limited.
接著配合圖2與圖3進一步說明熔絲記憶電路310的操作。如圖3所示，在時間T1之間，即在待機模式，DPD模式訊號DPDMD為低準位(L狀態)，亦即，記憶體裝系統10沒有進入DPD模式。此時熔絲記憶電路310的低電壓檢測電器312所輸出的低電壓檢測訊號DPD_CHR為低準位L。在此期間，熔絲記憶電路310的熔絲暫存器314的工作電壓VDDREG大致上等於第二電壓V2，即VCC。在此期間，DPD模式訊號DPDMD為低準位而且低電壓檢測訊號DPD_CHR為低準位L，邏輯電路316基於兩者的邏輯運算結果，輸出低準位L的訊號。由此，電晶體318導通，並對熔絲暫存器314提供工作電壓VDDREG，其大致上等於第二電壓V2(即VCC)。在此同時，也對電容器C進行充電。Next, the operation of the fuse memory circuit 310 is further described with reference to FIG. 2 and FIG. 3. As shown in FIG. 3, during time T1, i.e., in the standby mode, the DPD mode signal DPDMD is at a low level (L state), i.e., the memory device 10 does not enter the DPD mode. At this time, the low voltage detection signal DPD_CHR output by the low voltage detection device 312 of the fuse memory circuit 310 is at a low level L. During this period, the operating voltage VDDREG of the fuse register 314 of the fuse memory circuit 310 is substantially equal to the second voltage V2, i.e., VCC. During this period, the DPD mode signal DPDMD is at a low level and the low voltage detection signal DPD_CHR is at a low level L. Based on the logical operation results of the two, the logic circuit 316 outputs a signal of a low level L. As a result, the transistor 318 is turned on and provides the operating voltage VDDREG to the fuse register 314, which is substantially equal to the second voltage V2 (ie, VCC). At the same time, the capacitor C is also charged.
在時間T1，記憶體系統10進入DPD模式時， DPD模式訊號DPDMD會成為高準位(H狀態)。此時，邏輯電路316接收DPD模式訊號DPDMD以及低電壓檢測訊號DPD_CHR後，對其進行邏輯運算，輸出高準位訊號，而使電晶體318成為關閉狀態。此時，電容器C開始對熔絲暫存器314進行充電，以提供熔絲暫存器314的工作電壓VDDREG。同時，低電壓檢測電器312開始運作。At time T1, when the memory system 10 enters the DPD mode, the DPD mode signal DPDMD becomes a high level (H state). At this time, after receiving the DPD mode signal DPDMD and the low voltage detection signal DPD_CHR, the logic circuit 316 performs a logic operation on them and outputs a high level signal, so that the transistor 318 becomes a closed state. At this time, the capacitor C starts to charge the fuse register 314 to provide the operating voltage VDDREG of the fuse register 314. At the same time, the low voltage detection circuit 312 starts to operate.
當低電壓檢測電器312檢測到熔絲暫存器314的工作電壓VDDREG下降到預設的下限值VL時，低電壓檢測電器312輸出高準位的低電壓檢測訊號DPD_CHR。此時，邏輯電路316的運算結果再次使電晶體318導通，以對熔絲暫存器314提供工作電壓，同時也對電容器C進行充電。When the low voltage detector 312 detects that the operating voltage VDDREG of the fuse register 314 drops to the preset lower limit VL, the low voltage detector 312 outputs a high-level low voltage detection signal DPD_CHR. At this time, the operation result of the logic circuit 316 turns on the transistor 318 again to provide the operating voltage to the fuse register 314 and charge the capacitor C at the same time.
之後，當工作電壓VDDREG到達預設的上限值VH時，低電壓檢測電器312輸出低準位的低電壓檢測訊號DPD_CHR。此時，邏輯電路316的運算結果再次使電晶體318關閉。此時，熔絲暫存器314所需的靜態電流及漏電流暫時由電容器所提供。Afterwards, when the working voltage VDDREG reaches the preset upper limit value VH, the low voltage detector 312 outputs a low-level low voltage detection signal DPD_CHR. At this time, the operation result of the logic circuit 316 turns off the transistor 318 again. At this time, the static current and leakage current required by the fuse register 314 are temporarily provided by the capacitor.
因此，當記憶體系統10進入DPD模式後，熔絲記憶電路310的低電壓檢測電路312會持續地檢測熔絲暫存器314的工作電壓VDDREG，使工作電壓VDDREG可以反覆地維持在下限值VL與上限值VH之間。亦即，上述的動作會一直持續而對熔絲暫存器314和對電容器C充放電，直到離開DPD模式為止。Therefore, when the memory system 10 enters the DPD mode, the low voltage detection circuit 312 of the fuse memory circuit 310 will continue to detect the operating voltage VDDREG of the fuse register 314, so that the operating voltage VDDREG can be repeatedly maintained between the lower limit value VL and the upper limit value VH. That is, the above-mentioned action will continue to charge and discharge the fuse register 314 and the capacitor C until leaving the DPD mode.
在時間點T2，記憶體系統10離開DPD模式。此時，記憶體系統10回到待機模式。此時，DPD模式訊號DPDMD為低準位(L狀態)。熔絲記憶電路310的低電壓檢測電器312所輸出的低電壓檢測訊號DPD_CHR為低準位L。在此期間，熔絲記憶電路310的熔絲暫存器314的工作電壓VDDREG回到第二電壓V2，即VCC (如1.8V)。在此同時，也對電容器C進行充電。At time point T2, the memory system 10 leaves the DPD mode. At this time, the memory system 10 returns to the standby mode. At this time, the DPD mode signal DPDMD is at a low level (L state). The low voltage detection signal DPD_CHR output by the low voltage detection device 312 of the fuse memory circuit 310 is at a low level L. During this period, the operating voltage VDDREG of the fuse register 314 of the fuse memory circuit 310 returns to the second voltage V2, that is, VCC (such as 1.8V). At the same time, the capacitor C is also charged.
如此，通過將熔絲記憶電路310獨立於周邊電路群100與周邊電路群200而設置，當記憶體系統10進入DPD模式後，熔絲記憶電路310仍可以最低限的工作電壓進行運作。因此，在記憶體系統10離開DPD模式後，熔絲記憶電路310的熔絲暫存器314所儲存的電壓資訊等可提供給周邊電路群100的命令介面邏輯單元102，而不需要將熔絲記憶胞所儲存的資訊重新儲存到熔絲暫存器314。因此，記憶體系統10離開DPD模式後的回復時間tRES可以進一步地縮短。Thus, by setting the fuse memory circuit 310 independently from the peripheral circuit group 100 and the peripheral circuit group 200, when the memory system 10 enters the DPD mode, the fuse memory circuit 310 can still operate at the minimum operating voltage. Therefore, after the memory system 10 leaves the DPD mode, the voltage information stored in the fuse register 314 of the fuse memory circuit 310 can be provided to the command interface logic unit 102 of the peripheral circuit group 100, without the need to re-store the information stored in the fuse memory cell to the fuse register 314. Therefore, the recovery time tRES of the memory system 10 after leaving the DPD mode can be further shortened.
圖4根據本發明一實施例所繪示的熔絲記憶電路中的低電壓檢測電路400的示意圖。如圖4所示，低電壓檢測電器312的上限值VH和下限值VL的控制是改變工作電壓VDDREG至接地間的PMOS電晶體個數對電阻R1之間的比例來決定。低電壓檢測電器312包括多個第一電晶體、電阻R1、第二電晶體N1、史密特觸發器S以及準位移位器LS。作為一個例子，多個第一電晶體例如是多個PMOS電晶體，其彼此串聯連接而成，例如圖4顯示M1~M7。第二電晶體例如是NMOS電晶體。FIG4 is a schematic diagram of a low voltage detection circuit 400 in a fuse memory circuit according to an embodiment of the present invention. As shown in FIG4 , the control of the upper limit value VH and the lower limit value VL of the low voltage detection circuit 312 is determined by changing the ratio between the number of PMOS transistors between the operating voltage VDDREG and the ground and the resistor R1. The low voltage detection circuit 312 includes a plurality of first transistors, a resistor R1, a second transistor N1, a Schmitt trigger S, and a level shifter LS. As an example, the plurality of first transistors are, for example, a plurality of PMOS transistors, which are connected in series with each other, such as M1 to M7 shown in FIG4 . The second transistor is, for example, an NMOS transistor.
多個PMOS電晶體M1~M17與電阻R1串聯，電阻R1的一端耦接到節點A (PMOS電晶體M1的一端)，電阻R1的另一端耦接到NMOS電晶體N1。多個PMOS電晶體M1~M17的閘極可以都接地。此外，NMOS電晶體N1的閘極受控於DPD模式訊號DPDMD。此外，史密特觸發器S的輸入端耦接到節點A，輸出端耦接到準位移位器LS。當記憶體系統10基於高準位的DPD模式訊號DPDMD而進入到DPD模式後，此時NMOS電晶體N1會導通，進而使低電壓檢測電器312開始運作。A plurality of PMOS transistors M1-M17 are connected in series with a resistor R1, one end of the resistor R1 is coupled to a node A (one end of the PMOS transistor M1), and the other end of the resistor R1 is coupled to an NMOS transistor N1. The gates of the plurality of PMOS transistors M1-M17 can all be grounded. In addition, the gate of the NMOS transistor N1 is controlled by a DPD mode signal DPDMD. In addition, the input end of the Schmitt trigger S is coupled to the node A, and the output end is coupled to the level shifter LS. When the memory system 10 enters the DPD mode based on the high-level DPD mode signal DPDMD, the NMOS transistor N1 is turned on, thereby starting the low voltage detection device 312 to operate.
如上述，低電壓檢測電器312檢測到工作電壓VDDREG到達上限值VH時會通過史密特觸發器S轉態，以輸出低準位的低電壓檢測訊號DPD_CHR。因此，可以利用導通PMOS電晶體M1~M17中的個數以決定轉態的電壓值。此外，史密特觸發器S輸出進一步傳送到準位移位器LS，以進行準位的移位。這是因為電晶體318、邏輯控制電路312等需要在VCC電壓域下運作，所以需要準位移位器LS進行準位的移位。As mentioned above, when the low voltage detector 312 detects that the working voltage VDDREG reaches the upper limit value VH, it will switch states through the Schmitt trigger S to output a low-level low voltage detection signal DPD_CHR. Therefore, the number of the turned-on PMOS transistors M1~M17 can be used to determine the voltage value of the switch. In addition, the output of the Schmitt trigger S is further transmitted to the level shifter LS to shift the level. This is because the transistor 318, the logic control circuit 312, etc. need to operate in the VCC voltage domain, so the level shifter LS is required to shift the level.
圖5是根據本發明實施方式所繪示的控制方法的流程示意圖。在步驟S100，記憶體系統10處於待機模式。接著，在步驟S102，記憶體系統10判斷是否有收到DPD模式訊號DPDMD。當記憶體系統10判斷接收到高準位的DPD模式訊號DPDMD(步驟S102，是)，亦即通知記憶體系統10要進入DPD模式，則執行步驟S104。反之，當記憶體系統10判斷DPD模式訊號DPDMD為低準位，亦即沒有要進入DPD模式，則回到步驟S100，記憶體系統10維持在待機模式。FIG5 is a flow chart of a control method according to an embodiment of the present invention. In step S100, the memory system 10 is in standby mode. Next, in step S102, the memory system 10 determines whether a DPD mode signal DPDMD is received. When the memory system 10 determines that a high-level DPD mode signal DPDMD is received (step S102, yes), that is, the memory system 10 is notified to enter the DPD mode, step S104 is executed. On the contrary, when the memory system 10 determines that the DPD mode signal DPDMD is a low level, that is, it does not want to enter the DPD mode, it returns to step S100, and the memory system 10 remains in standby mode.
在步驟S104，當記憶體系統10進入DPD模式，基於高準位的DPD模式訊號DPDMD，圖2的低電壓檢測器312開始動作，對熔絲暫存器316的工作電壓VDDREG進行持續性地檢測。In step S104, when the memory system 10 enters the DPD mode, based on the high-level DPD mode signal DPDMD, the low voltage detector 312 of FIG. 2 starts to operate and continuously detects the operating voltage VDDREG of the fuse register 316.
在步驟S106，使熔絲暫存器316的工作電壓VDDREG在上限值VH與下限值VL之間運作，藉此熔絲暫存器316在DPD模式下可以維持運作。如圖3所示，在進入DPD模式後，工作電壓VDDREG從1.8V開始下降，電晶體318關閉。此時，電容器C開始對熔絲暫存器316提供工作電壓VDDREG。電容器C持續放電後，工作電壓VDDREG開始下降。In step S106, the operating voltage VDDREG of the fuse register 316 is operated between the upper limit value VH and the lower limit value VL, so that the fuse register 316 can maintain operation in the DPD mode. As shown in FIG3, after entering the DPD mode, the operating voltage VDDREG starts to drop from 1.8V, and the transistor 318 is turned off. At this time, the capacitor C starts to provide the operating voltage VDDREG to the fuse register 316. After the capacitor C continues to discharge, the operating voltage VDDREG starts to drop.
之後，當低電壓檢測器312檢測到工作電壓VDDREG到達下限值VL，送出高準位的低電壓檢測訊號DPD_CHR。由此，電晶體318導通，開始對電容器C充電。當電容器C的電壓(要提供的工作電壓VDDREG)到達上限值VH，低電壓檢測器312送出低準位的低電壓檢測訊號DPD_CHR，由此電晶體318關閉，電容器C開始對熔絲暫存器316提供工作電壓VDDREG。Afterwards, when the low voltage detector 312 detects that the operating voltage VDDREG reaches the lower limit value VL, it sends a high-level low voltage detection signal DPD_CHR. As a result, the transistor 318 is turned on and starts to charge the capacitor C. When the voltage of the capacitor C (the operating voltage VDDREG to be provided) reaches the upper limit value VH, the low voltage detector 312 sends a low-level low voltage detection signal DPD_CHR, whereby the transistor 318 is turned off, and the capacitor C starts to provide the operating voltage VDDREG to the fuse register 316.
在步驟S108，判斷記憶體系統10是否要離開DPD模式。當DPD模式訊號DPDMD持續維持在高準位時，表示記憶體系統10仍沒有要離開DPD模式。亦即步驟S108判斷為“否”時，回到步驟S104，低電壓檢測器312繼續檢測工作電壓VDDREG，並且通過低電壓檢測器312的運作，使熔絲暫存器316的工作電壓VDDREG在上限值VH與下限值VL之間運作。反之，在步驟S108，如果判斷記憶體系統10要離開DPD模式，即DPD模式訊號DPDMD變成低準位，則回到步驟S100，記憶體系統10離開DPD模式並成為待機模式。In step S108, it is determined whether the memory system 10 is going to leave the DPD mode. When the DPD mode signal DPDMD continues to be maintained at a high level, it indicates that the memory system 10 is still not going to leave the DPD mode. That is, when the step S108 is determined to be "no", it returns to step S104, and the low voltage detector 312 continues to detect the operating voltage VDDREG, and through the operation of the low voltage detector 312, the operating voltage VDDREG of the fuse register 316 operates between the upper limit value VH and the lower limit value VL. On the contrary, in step S108, if it is determined that the memory system 10 is to leave the DPD mode, that is, the DPD mode signal DPDMD becomes a low level, then the process returns to step S100, and the memory system 10 leaves the DPD mode and becomes the standby mode.
綜上所述，在上述的電路架構下，熔絲暫存器316的工作電壓VDDREG在相對低的情況下，因元件的跨壓變小了，而元件的漏電流也變小了。如此，重新對電容器C充電的時間也變長，使得DPD模式電流ICC2可以小於1μA。In summary, under the above circuit structure, when the operating voltage VDDREG of the fuse register 316 is relatively low, the cross-voltage of the component is reduced, and the leakage current of the component is also reduced. In this way, the time to recharge the capacitor C is also extended, so that the DPD mode current ICC2 can be less than 1μA.
此外，根據本發明實施方式，因為熔絲暫存器是獨立於第一與第二周邊電路群，並且以另外的電壓域供電。因此，當記憶體系統進入DPD模式時，熔絲暫存器的狀態能夠維持。也就是說，即使在DPD模式，熔絲暫存器可以持續保存記憶體系統的操作的電壓資訊。故，在記憶體系統離開DPD模式後，不需要將電壓資訊重新儲存到熔絲暫存器。如此，回復時間tRES能夠縮短至3μs以內。In addition, according to the embodiment of the present invention, because the fuse register is independent of the first and second peripheral circuit groups and is powered by another voltage domain. Therefore, when the memory system enters the DPD mode, the state of the fuse register can be maintained. That is, even in the DPD mode, the fuse register can continue to save the voltage information of the operation of the memory system. Therefore, after the memory system leaves the DPD mode, it is not necessary to re-store the voltage information to the fuse register. In this way, the recovery time tRES can be shortened to less than 3μs.
10：記憶體系統 20：記憶體陣列 30：控制裝置 100、200、210、300：周邊電路群 101：輸出入控制單元 102：命令介面邏輯單元 103：行/列控制器 104：緊連邏輯 105：周邊控制單元 106：外部記憶體 201：輸出入緩衝器 202：解除命令串列解碼器 203、LS：準位移位器 204：鎖存器 205：電壓調節電路 206：電源開關 211：投電電路 212：能隙電路 213：類比電路 310：熔絲記憶電路 312：低電壓檢測器 314：熔絲暫存器 316：邏輯電路 318：電晶體 400：高電壓調節器 V1：第一電壓 V2、VCC：第二電壓 V3：第三電壓 N、A：節點 DPDMD：深度省電模式訊號 CMDS：命令串列 CCMD：控制命令 DPD_CHR：低電壓檢測訊號 VDD_REG：工作電壓 INV：反相器 M1~M17：PMOS電晶體 N1：NMOS電晶體 NOR：反或閘 R1：電阻 C：電容器 S：史密特觸發器 LS：準位移位器10: Memory system20: Memory array30: Control device100, 200, 210, 300: Peripheral circuit group101: Input/output control unit102: Command interface logic unit103: Row/column controller104: Closed logic105: Peripheral control unit106: External memory201: Input/output buffer202: Release command serial decoder203, LS: Level shifter204: Latch205: Voltage regulation circuit206: Power switch211: Throw circuit212: Bandgap circuit213: Analog circuit310: Fuse memory circuit312: Low voltage detector314: Fuse register316: Logic circuit318: Transistor400: High voltage regulatorV1: First voltageV2, VCC: Second voltageV3: Third voltageN, A: NodeDPDMD: Deep power saving mode signalCMDS: Command serialCCMD: Control commandDPD_CHR: Low voltage detection signalVDD_REG: Operating voltageINV: InverterM1~M17: PMOS transistorN1: NMOS transistorNOR: NOR gateR1: ResistorC: CapacitorS: Schmitt triggerLS: Level shifter
圖1是根據本發明實施例所繪示的記憶體系統的電路方塊。 圖2是圖1所示的熔絲記憶電路方塊圖。 圖3根據本發明實施例所繪示的熔絲記憶電路的動作時序圖。 圖4根據本發明實施例所繪示的熔絲記憶電路中的低電壓檢測電路的示意圖。 圖5根據本發明實施例所繪示的控制方法的流程示意圖。FIG. 1 is a circuit block diagram of a memory system according to an embodiment of the present invention.FIG. 2 is a block diagram of the fuse memory circuit shown in FIG. 1.FIG. 3 is an operation timing diagram of the fuse memory circuit according to an embodiment of the present invention.FIG. 4 is a schematic diagram of a low voltage detection circuit in a fuse memory circuit according to an embodiment of the present invention.FIG. 5 is a flow diagram of a control method according to an embodiment of the present invention.
10:記憶體系統10: Memory system
20:記憶體陣列20:Memory array
30:控制裝置30: Control device
100、200、210、300:周邊電路群100, 200, 210, 300: Peripheral circuit group
101:輸出入控制單元101: Input and output control unit
102:命令介面邏輯單元102: Command interface logic unit
103:行/列控制器103: Row/column controller
104:緊連邏輯104: Close Logic
105:周邊控制單元105: Peripheral control unit
106:外部記憶體106: External memory
201:輸出入緩衝器201: Input and output buffer
202:解除命令串列解碼器202: Release command serial decoder
203:準位移位器203: Level shifter
204:鎖存器204: Lock register
205:電壓調節電路205: Voltage regulation circuit
206:電源開關206: Power switch
211:投電電路211: Power circuit
212:能隙電路212: Bandgap circuit
213:類比電路213:Analog circuit
310:熔絲記憶電路310: Fuse memory circuit
400:高電壓調節器400: High voltage regulator
V1:第一電壓V1: first voltage
V2:第二電壓V2: Second voltage
V3:第三電壓V3: The third voltage
DPDMD:深度省電模式訊號DPDMD: Deep power saving mode signal
CMDS:命令串列CMDS: Command Serial Number
CCMD:控制命令CCMD: Control Command
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW113114564ATWI885864B (en) | 2024-04-18 | 2024-04-18 | Control device, control method and memory system |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW113114564ATWI885864B (en) | 2024-04-18 | 2024-04-18 | Control device, control method and memory system |
| Publication Number | Publication Date |
|---|---|
| TWI885864Btrue TWI885864B (en) | 2025-06-01 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW113114564ATWI885864B (en) | 2024-04-18 | 2024-04-18 | Control device, control method and memory system |
| Country | Link |
|---|---|
| TW (1) | TWI885864B (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200515144A (en)* | 2003-09-15 | 2005-05-01 | Infineon Technologies Ag | Method for refreshing a memory and integrated circuit including a refreshable memory |
| US20070147159A1 (en)* | 2005-12-28 | 2007-06-28 | Lee Young-Dae | Standby leakage current reduction circuit and semiconductor memory device comprising the standby leakage current reduction circuit |
| US20080112250A1 (en)* | 2006-11-13 | 2008-05-15 | Freebern Margaret A | Memory including deep power down mode |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200515144A (en)* | 2003-09-15 | 2005-05-01 | Infineon Technologies Ag | Method for refreshing a memory and integrated circuit including a refreshable memory |
| US20070147159A1 (en)* | 2005-12-28 | 2007-06-28 | Lee Young-Dae | Standby leakage current reduction circuit and semiconductor memory device comprising the standby leakage current reduction circuit |
| US20080112250A1 (en)* | 2006-11-13 | 2008-05-15 | Freebern Margaret A | Memory including deep power down mode |
| Publication | Publication Date | Title |
|---|---|---|
| US6882570B2 (en) | Power detecting circuit and method for stable power-on reading of flash memory device using the same | |
| US6219277B1 (en) | Device and method for the reading of EEPROM cells | |
| US6108246A (en) | Semiconductor memory device | |
| US8041975B2 (en) | Programmable I/O cell capable of holding its state in power-down mode | |
| US7352223B2 (en) | Delay circuit having a capacitor and having reduced power supply voltage dependency | |
| JP4820571B2 (en) | Semiconductor device | |
| KR100471185B1 (en) | Internal voltage converter scheme for controlling the power-up slope of internal supply voltage | |
| KR100287545B1 (en) | Nonvolatile Semiconductor Memory Devices | |
| TWI446355B (en) | Sensing circuit for memory cell with low supply power | |
| US5602777A (en) | Semiconductor memory device having floating gate transistors and data holding means | |
| KR19990053150A (en) | Latch Circuit of Flash Memory Cell with Automatic Sensing Time Tracking Circuit | |
| US7180811B2 (en) | Semiconductor memory device informing internal voltage level using ready/busy pin | |
| US5929681A (en) | Delay circuit applied to semiconductor memory device having auto power-down function | |
| JP5195915B2 (en) | Semiconductor integrated circuit device and electronic apparatus | |
| CN217444073U (en) | integrated circuit | |
| TWI885864B (en) | Control device, control method and memory system | |
| US6201380B1 (en) | Constant current/constant voltage generation circuit with reduced noise upon switching of operation mode | |
| US6906974B2 (en) | Sense amplifiers with output buffers and memory devices incorporating same | |
| KR102748491B1 (en) | Self-timing detection architecture for nonvolatile memory systems | |
| JPH10241385A (en) | Intermediate voltage generating circuit and semiconductor integrated circuit device having the same | |
| US6353560B1 (en) | Semiconductor memory device | |
| EP0806771B1 (en) | UPROM cell for low voltage supply | |
| US7548482B2 (en) | Memory device for early stabilizing power level after deep power down mode exit | |
| KR100316522B1 (en) | Current limiting sensing circuit for autoverify programing a nonvolatile memory | |
| US20030151961A1 (en) | Semiconductor memory device having internal circuit screening function |