TWI880785B - Memory structure with pillar-type bottom electrodes and method of manufacturing the same - Google Patents

Abstract

A memory structure with pillar-type bottom electrodes is provided in the present invention, including multiple pillar-type bottom electrodes composed of a first metal layer and a poly-Si core and contacting contacts in a substrate, an etch stop layer on first regions and second regions of the substrate, a middle supporting structure and a top supporting structure on the second regions and laterally connecting the pillar-type bottom electrodes, wherein the top supporting structure, the middle supporting structure, the etch stop layer and the pillar-type bottom electrodes define first capacitor spaces on the first regions and define second capacitor spaces and third capacitor spaces on the second regions, and a capacitive dielectric layer and a top electrode composed of the second metal layer and a poly-Si layer are formed in the capacitor spaces.

Description

Translated fromChinese

具有柱狀下電極的記憶體結構及其製造方法Memory structure with columnar lower electrode and manufacturing method thereof

本發明大體上與一種記憶體結構有關，更具體言之，其係關於一種具有柱狀下電極的記憶體結構及其製造方法。The present invention generally relates to a memory structure, and more particularly, to a memory structure having a pillar-shaped bottom electrode and a method for making the same.

得益於近年來在超微尺度下的半導體製程技術的突破與發展，記憶裝置的整合密度得以飛速地增加，其記憶單元(cell)所需的面積大幅地降低並可在較低的電壓下運作。然而，儘管單元面積得以減少，記憶裝置運作所需的電荷容量仍需維持在足夠的量值，以避免軟錯誤發生以及進一步減少其刷新時間。在這樣的情況下，為了達到足夠的電荷容量以因應下一世代的動態隨機存取記憶體(DRAM)需求，業界許多的開發與研究圍繞著採用高介電常數(high-k)材料的金屬-絕緣體-金屬(MIM)電容器而展開。Thanks to the breakthroughs and developments in semiconductor process technology at the ultra-micro scale in recent years, the integration density of memory devices has increased rapidly, and the area required for the memory cell has been greatly reduced and can operate at a lower voltage. However, despite the reduction in cell area, the charge capacity required for the operation of the memory device still needs to be maintained at a sufficient value to avoid soft errors and further reduce its refresh time. In this case, in order to achieve sufficient charge capacity to meet the needs of the next generation of dynamic random access memory (DRAM), many developments and researches in the industry revolve around metal-insulator-metal (MIM) capacitors using high-k materials.

在採用50至60奈米的金屬互連製程的DRAM裝置中，為了達到更大的電容，儲存節點(storage node)的型態從凹槽式(concave)演變為圓筒式(cylindrical)。然而，對於50奈米線寬以下更先進的記憶架構而言，圓筒式的儲存節點會有電容空間以及節點間隔絕的取捨問題。對此，近年業界提出了圓柱型態(pillar-type)的儲存節點，其架構在50奈米線寬以下的尺度規格下能確保電容空間又可兼顧節點間的隔絕性。In DRAM devices using 50 to 60 nanometer metal interconnect processes, in order to achieve greater capacitance, the shape of the storage node has evolved from concave to cylindrical. However, for more advanced memory architectures with line widths below 50 nanometers, cylindrical storage nodes will have trade-off issues in capacitor space and node isolation. In this regard, in recent years, the industry has proposed pillar-type storage nodes. Its architecture can ensure capacitor space and take into account the isolation between nodes under the specification of line width below 50 nanometers.

儘管如此，圓柱型態的儲存節點仍存在待改善的缺點，例如圓柱體在製程期間容易產生大量的剪應力，導致彎曲而橋接失效、高寬比過大的柱體容易傾倒等問題。故此，本領域的技術人士仍需對現有的圓柱型記憶體結構與相關製程進行改善，以期克服上述缺點。Despite this, cylindrical storage nodes still have shortcomings that need to be improved, such as the cylinder easily generates a large amount of shear stress during the manufacturing process, causing bending and bridge failure, and the cylinder with a large aspect ratio is prone to tipping, etc. Therefore, technical personnel in this field still need to improve the existing cylindrical memory structure and related processes in order to overcome the above shortcomings.

有鑑於前述現有技術的不足，本發明於此提出了一種新穎的記憶體結構，其特點在於採用由金屬與多晶矽構成的柱狀下電極，可有效降低應力，避免柱體彎曲而橋接失效。此外，透過所提出的相關製程，其可在相同的空間中界定出兩個以上的電容空間，進而提升每個儲存節點的有效電容面積以及其串聯電容值。In view of the above-mentioned shortcomings of the prior art, the present invention proposes a novel memory structure, which is characterized by using a columnar lower electrode composed of metal and polysilicon, which can effectively reduce stress and avoid column bending and bridge failure. In addition, through the proposed related process, it can define more than two capacitor spaces in the same space, thereby increasing the effective capacitance area of each storage node and its series capacitance value.

本發明的其一面向在於提出一種具有柱狀下電極的記憶體結構，包含：一基底，其上界定有多個第一區域以及多個第二區域；多個接觸件，位於該些第一區域與該些第二區域之間的該基底中；多個柱狀下電極，每個該柱狀下電極位於一該接觸件上並與之電性接觸，其中每個該柱狀下電極由一多晶矽內芯以及包覆該多晶矽內芯的側壁與底面的一第一金屬層所構成，且往與該基底垂直的一垂直方向延伸；一蝕刻停止層，位於該些第一區域以及該些第二區域上；一中間支撐結構，位於該些第二區域上方且側向連接該些柱狀下電極在該垂直方向上的中間部位；一頂部支撐結構，位於該些第二區域上方且側向連接該些柱狀下電極在該垂直方向上的頂端部位，其中該蝕刻停止層以及該些柱狀下電極在每一該第一區域上界定出一第一電容空間，該頂部支撐結構、該中間支撐結構、該蝕刻停止層以及該些柱狀下電極在每一該第二區域上界定出一第二電容空間以及一第三電容空間，該第二電容空間位於該第三電容空間上方；一電容介電層，共形地形成在該第一電容空間、該第二電容空間以及該第三電容空間的表面；以及一上電極，包含一第二金屬層與一多晶矽層，其中該第二金屬層共形地形成在該電容介電層的表面上，該多晶矽層形成在該金屬層上。One aspect of the present invention is to provide a memory structure with a columnar lower electrode, comprising: a substrate on which a plurality of first regions and a plurality of second regions are defined; a plurality of contacts located in the substrate between the first regions and the second regions; a plurality of columnar lower electrodes, each of which is located on and electrically contacts one of the contacts, wherein each of the columnar lower electrodes The invention comprises a polysilicon core and a first metal layer covering the sidewall and bottom of the polysilicon core and extending in a vertical direction perpendicular to the substrate; an etching stop layer located on the first regions and the second regions; an intermediate support structure located above the second regions and laterally connected to the middle portions of the columnar lower electrodes in the vertical direction; and a top support structure. The top support structure is located above the second regions and is laterally connected to the top ends of the columnar lower electrodes in the vertical direction, wherein the etching stop layer and the columnar lower electrodes define a first capacitor space on each of the first regions, and the top support structure, the middle support structure, the etching stop layer and the columnar lower electrodes define a second capacitor space and a first capacitor space on each of the second regions. Three capacitor spaces, the second capacitor space is located above the third capacitor space; a capacitor dielectric layer is conformally formed on the surfaces of the first capacitor space, the second capacitor space and the third capacitor space; and an upper electrode includes a second metal layer and a polysilicon layer, wherein the second metal layer is conformally formed on the surface of the capacitor dielectric layer, and the polysilicon layer is formed on the metal layer.

本發明的另一面向在於提出一種具有柱狀下電極的記憶體結構的製造方法，包含：提供一基底，該基底上界定有多個第一區域以及多個第二區域，且多個接觸件位於該些第一區域與該些第二區域之間的該基底中；在該基底上依序形成一蝕刻停止層、一第一塑形層、一中間支撐層、一第二塑形層以及一頂部支撐層；進行一第一光刻製程形成多個孔洞，該些孔洞往與該基底垂直的一垂直方向延伸並貫穿該頂部支撐層、該第二塑形層、該中間支撐層、該第一塑形層以及該蝕刻停止層，每一該孔洞露出下方的一該接觸件；在該些孔洞的表面形成一共形的第一金屬層，該第一金屬層與下方的該些接觸件直接接觸並覆蓋該頂部支撐層；在該些孔洞中填入一第一多晶矽層，該第一多晶矽層位於該第一金屬層上；進行一第二光刻製程移除位於該第一區域上方的該頂部支撐層的頂面上的該第一金屬層以及該頂部支撐層，如此露出該第一區域上方的該第二塑形層；移除位於該第二區域上方的該頂部支撐層的頂面上的該第一多晶矽層以及該第一金屬層，如此形成多個由該第一金屬層與該第一多晶矽層構成的柱狀下電極，並露出該第二區域上方的該頂部支撐層；移除該第一區域上方以及該第二區域上方的第二塑形層；移除該第一區域上方的該中間支撐層，如此露出該第一區域上方的該第一塑形層；移除該第一區域上方以及該第二區域上方的該第一塑形層，如此在每一該第一區域上形成一由該蝕刻停止層以及該些柱狀下電極所界定出的第一電容空間，在每一該第二區域上形成一由該中間支撐層、該頂部支撐層以及該些柱狀下電極所界定出的第二電容空間，且在每一該第二區域上形成由該中間支撐結構、該蝕刻停止層以及該些柱狀下電極所界定出的一第三電容空間；以及在該第一電容空間、該第二電容空間以及該第三電容空間中依序形成一共形的電容介電層、一共形的第二金屬層以及一第二多晶矽層，其中該第二金屬層與該第二多晶矽層構成一上電極。Another aspect of the present invention is to provide a method for manufacturing a memory structure with a columnar lower electrode, comprising: providing a substrate, on which a plurality of first regions and a plurality of second regions are defined, and a plurality of contacts are located in the substrate between the first regions and the second regions; sequentially forming an etching stop layer, a first shaping layer, a middle supporting layer, a second shaping layer and a top supporting layer on the substrate; performing a first photolithography process to form a plurality of holes, wherein the holes extend in a vertical direction perpendicular to the substrate and penetrate the top supporting layer, the second shaping layer, the middle supporting layer, and the second shaping layer. The invention relates to a method for forming a top support layer, a first shaping layer, and an etch stop layer, wherein each of the holes exposes a contact member below; forming a conformal first metal layer on the surface of the holes, wherein the first metal layer directly contacts the contact members below and covers the top support layer; filling the holes with a first polysilicon layer, wherein the first polysilicon layer is located on the first metal layer; performing a second photolithography process to remove the first metal layer and the top support layer on the top surface of the top support layer above the first region, thereby exposing the second shaping layer above the first region; removing the second shaping layer on the second region; and removing the second metal layer on the top surface of the top support layer. The first polysilicon layer and the first metal layer on the top surface of the top supporting layer above the second region are removed to form a plurality of columnar lower electrodes formed by the first metal layer and the first polysilicon layer, and the top supporting layer above the second region is exposed; the second shaping layer above the first region and the second region is removed; the first shaping layer above the first region is removed to expose the first shaping layer above the first region; the first shaping layer above the first region and the second region is removed to form a columnar lower electrode formed by the etching stop layer and the columnar lower electrodes on each of the first regions. A first capacitor space defined by the first capacitor space is formed on each of the second regions, a second capacitor space defined by the middle support layer, the top support layer and the columnar lower electrodes is formed, and a third capacitor space defined by the middle support structure, the etch stop layer and the columnar lower electrodes is formed on each of the second regions; and a conformal capacitor dielectric layer, a conformal second metal layer and a second polysilicon layer are sequentially formed in the first capacitor space, the second capacitor space and the third capacitor space, wherein the second metal layer and the second polysilicon layer constitute an upper electrode.

本發明的這類目的與其他目的在閱者讀過下文中以多種圖示與繪圖來描述的較佳實施例之細節說明後應可變得更為明瞭顯見。These and other objects of the present invention will become more apparent after the reader has read the following detailed description of the preferred embodiments described in various figures and drawings.

現在下文將詳細說明本發明的示例性實施例，其會參照附圖示出所描述之特徵，以便閱者理解並實現技術效果。閱者將可了解文中之描述說明僅係透過例示之方式來進行，其非意欲要限制本案。本案的各種實施例和實施例中彼此不衝突的各種特徵可以各種方式來加以組合或重新排列設置。在不脫離本發明的精神與範疇的情況下，對本案的修改、等同物或改進對於本領域技術人員來說是可以理解的，並且旨在包含在本案的範圍內。Now, the following will describe in detail exemplary embodiments of the present invention, which will refer to the attached drawings to illustrate the described features so that the reader can understand and achieve the technical effects. The reader will understand that the description in the text is only by way of example and is not intended to limit the present invention. Various embodiments of the present invention and various features that do not conflict with each other in the embodiments can be combined or rearranged in various ways. Without departing from the spirit and scope of the present invention, modifications, equivalents or improvements to the present invention are understandable to those skilled in the art and are intended to be included in the scope of the present invention.

閱者應能容易理解，本案中的「在…上」、「在…之上」和「在…上方」的含義應當以廣義的方式來解讀，以使得「在…上」不僅表示「直接在」某物「上」，而且還包括在某物「上」且其間有居間特徵或層結構的含義，並且「在…之上」或「在…上方」不僅表示「在」某物「之上」或「上方」的含義，而且還可以包括其「在」某物「之上」或「上方」且其間沒有居間特徵或層結構（即直接在某物上）的含義。此外，為了描述方便，諸如「在…之下」、「在…下方」、「下部」、「在…之上」、「上部」等空間相關的術語在本文中可用於描述一個元件或特徵與另一個或多個元件或特徵之間的關係，如附圖中所示出者。Readers should be able to easily understand that the meanings of “on,” “above,” and “over” in this case should be interpreted in a broad manner, so that “on” not only means “directly on” something, but also includes the meaning of being “on” something with intervening features or layers, and “on” or “over” not only means “on” or “above” something, but also includes the meaning of being “on” or “above” something with no intervening features or layers (i.e. directly on something). In addition, for convenience of description, spatially related terms such as "under", "beneath", "lower", "over", "upper", etc. may be used in this document to describe the relationship between one element or feature and another or more elements or features, as shown in the accompanying drawings.

如本文中使用的，術語「層」是指包括具有厚度的區域的材料部分。層可以在下方或上方結構的整體之上延伸，或者可以具有小於下方或上方結構的範圍。此外，層可以是厚度小於連續結構的厚度的均質或非均質連續結構的區域。例如，層可以位於在連續結構的頂面和底面之間或在頂面和底面處的任何相對的水平面之間。層可以水平、豎直和/或沿傾斜表面延伸。基底可以是層結構，其中可以包括一個或多個層，和/或可以在其上、其上方和/或其下方具有一個或多個層。層可以包括多個層。例如，互連層可以包括一個或多個導體和接觸層（其中形成接觸件、互連線和/或導孔件等）和一個或多個介電層。As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than that of a lower or upper structure. In addition, a layer may be an area of a homogeneous or inhomogeneous continuous structure having a thickness less than that of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any relative horizontal surfaces at the top and bottom surfaces. A layer may extend horizontally, vertically and/or along an inclined surface. A substrate may be a layered structure, which may include one or more layers, and/or may have one or more layers thereon, above and/or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which contacts, interconnects and/or vias are formed, etc.) and one or more dielectric layers.

閱者通常可以至少部分地從上下文中的用法理解本發明所用術語。例如，至少部分地取決於上下文，本文所使用的術語「一或多個」可以用於以單數意義描述任何特徵、結構或特性，或者可以用於以複數意義描述特徵、結構或特性的組合。類似地，至少部分地取決於上下文，諸如「一」、「一個」、「該」或「所述」之類的術語同樣可以被理解為傳達單數用法或者傳達複數用法。另外，術語「基於」可以被理解為不一定旨在傳達排他性的因素集合，而是可以允許存在不一定明確地描述的額外因素，這同樣至少部分地取決於上下文。The reader can generally understand the terms used in the present invention at least in part from the usage in the context. For example, depending at least in part on the context, the term "one or more" used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a", "an", "the" or "said" can also be understood to convey singular usage or to convey plural usage. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but can allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

閱者更能了解到，當「包含」與/或「含有」等詞用於本說明書時，其明定了所陳述特徵、區域、整體、步驟、操作、要素以及/或部件的存在，但並不排除一或多個其他的特徵、區域、整體、步驟、操作、要素、部件以及/或其組合的存在或添加的可能性。Readers can further understand that when the words "include" and/or "contain" are used in this specification, they specify the existence of the described features, regions, wholes, steps, operations, elements and/or components, but do not exclude the possibility of the existence or addition of one or more other features, regions, wholes, steps, operations, elements, components and/or combinations thereof.

首先請參照第1圖，其為根據本發明實施例一具有柱狀下電極的記憶體結構的截面示意圖。本發明的記憶體結構可為一DRAM，其設置在一基底100上。在本發明實施例中，基底100可包含一半導體基底以及形成在其上的一或多層介電層。該半導體基底的材質較佳為矽基底，如一P型摻雜的矽基底，但也可採用其他的含矽基底，包含三五族覆矽基底(如GaN-on-silicon)或是矽覆絕緣(silicon-on-insulator，SOI)基底等，或是其他摻雜類型的基底，不以此為限。半導體基底上可形成有各種摻雜區、主動區以及電晶體，且其中界定有記憶單元(cell)區域以及周邊(peripheral)區域。該介電層可為層間介電層(interlayer dielectric, ILD)，包含金屬沉積前介電層(pre-metal dielectric, PMD)及/或金屬間介電層(inter-metal dielectric, IMD)，其材質以氧化矽為主，包含未摻雜的矽玻璃(PSG)、硼磷矽玻璃(BPSG)、四乙氧基矽烷(TEOS)或是低介電常數(low-k)材料。由於本發明的結構與製程僅涉及記憶體部位，為了簡明之故，後續圖示將僅示出基底的記憶單元區域上的層間介電層部位，並以其來代表整個基底100，合先敘明。First, please refer to FIG. 1, which is a cross-sectional schematic diagram of a memory structure with a columnar lower electrode according to an embodiment of the present invention. The memory structure of the present invention may be a DRAM, which is disposed on asubstrate 100. In the embodiment of the present invention, thesubstrate 100 may include a semiconductor substrate and one or more dielectric layers formed thereon. The material of the semiconductor substrate is preferably a silicon substrate, such as a P-type doped silicon substrate, but other silicon-containing substrates may also be used, including III-V silicon-coated substrates (such as GaN-on-silicon) or silicon-coated insulator (SOI) substrates, etc., or other doped types of substrates, but are not limited thereto. Various doped regions, active regions and transistors may be formed on the semiconductor substrate, and a memory cell region and a peripheral region may be defined therein. The dielectric layer may be an interlayer dielectric (ILD), including a pre-metal dielectric (PMD) and/or an inter-metal dielectric (IMD), and the material thereof is mainly silicon oxide, including undoped silicon glass (PSG), borophosphosilicate glass (BPSG), tetraethoxysilane (TEOS) or a low-k material. Since the structure and process of the present invention only involve the memory area, for the sake of simplicity, the subsequent figures will only show the interlayer dielectric layer area on the memory cell area of the substrate, and use it to represent theentire substrate 100, which is described first.

復參照第1圖。基底100中形成有多個接觸件(contact)102，其材質可包含鎢(W)與氮化鈦(TiN)。該些接觸件102在基底100平面上可呈錯位陣列的排列型態(staggered arrangement)。接觸件102在基底100中界定出多個第一區域100a以及多個第二區域100b。以第1圖的截面圖為例，相鄰的三個接觸件102之間界定出了一第一區域100a與一第二區域100b，其上會具有不同的記憶體組態。關於基底100上的結構，每個接觸件102上都具有一柱狀下電極(pillar-type bottom electrode)117與之直接電性接觸。在本發明實施例中，柱狀下電極117係往與基底100垂直的方向延伸，且每個柱狀下電極117都由一第一金屬層116以及一多晶矽內芯118所構成，其中第一金屬層116包覆了多晶矽內芯118的側壁與底面等部位，該底面部位與一接觸件102電性接觸，復透過該接觸件102與下方作為存取開關的電晶體元件接觸，多晶矽內芯118的頂端從第一金屬層116中露出並可凸出而高於周圍的第一金屬層116。多晶矽內芯118中可進一步摻雜有雜質來增加其導電性，如磷(P)、砷(As)等N型摻質或是硼(B)等P型摻質。第一金屬層116的材料可為導電性佳的金屬，如鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)、氮化鋁鈦(TiAlN)、鎢(W)、氮化鎢(WN)或是上述材料之組合，其中以氮化鈦(TiN)為佳，其可身兼阻障層，避免多晶矽內芯118中的雜質粒子擴散汙染到周遭的層結構。在DRAM架構下，本發明實施例中的柱狀下電極117也可稱為儲存節點(storage node)，每個柱狀下電極117都與周圍結構構成了記憶體中儲存電荷數據的基本單元。Refer to FIG. 1 again. A plurality ofcontacts 102 are formed in thesubstrate 100, and the materials thereof may include tungsten (W) and titanium nitride (TiN). Thecontacts 102 may be arranged in a staggered array on the plane of thesubstrate 100. Thecontacts 102 define a plurality offirst regions 100a and a plurality ofsecond regions 100b in thesubstrate 100. Taking the cross-sectional view of FIG. 1 as an example, afirst region 100a and asecond region 100b are defined between threeadjacent contacts 102, and different memory configurations are provided thereon. With respect to the structure on thesubstrate 100, eachcontact 102 has a pillar-type bottom electrode 117 in direct electrical contact therewith. In the embodiment of the present invention, the columnarlower electrode 117 extends in a direction perpendicular to thesubstrate 100, and each columnarlower electrode 117 is composed of afirst metal layer 116 and apolycrystalline silicon core 118, wherein thefirst metal layer 116 covers the side walls and bottom surface of thepolycrystalline silicon core 118, and the bottom surface is electrically contacted with acontact 102, and is further contacted with the transistor element serving as an access switch below through thecontact 102. The top of thepolycrystalline silicon core 118 is exposed from thefirst metal layer 116 and can protrude and be higher than the surroundingfirst metal layer 116. Thepolysilicon core 118 may be further doped with impurities to increase its conductivity, such as N-type dopants such as phosphorus (P) and arsenic (As) or P-type dopants such as boron (B). The material of thefirst metal layer 116 may be a metal with good conductivity, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN) or a combination of the above materials, among which titanium nitride (TiN) is preferred, which can also serve as a barrier layer to prevent impurity particles in thepolysilicon core 118 from diffusing and contaminating the surrounding layer structures. In the DRAM architecture, the columnarlower electrode 117 in the embodiment of the present invention can also be called a storage node. Each columnarlower electrode 117 and the surrounding structure constitute a basic unit for storing charge data in the memory.

相較於傳統單一結構的柱狀下電極而言，例如完全由氮化鈦構成的柱狀下電極，氮化鈦在熱處理後所產生的高剪應力容易使柱體彎曲，造成下電極彼此橋接而失效。為了解決此問題，本發明提出了以金屬層外部與多晶矽內芯構成的混合式柱狀下電極117設計。金屬層與多晶矽的組合設計可大幅降低柱狀下電極117的剪應力，避免其彎曲橋接。再者，由於氮化鈦材料較貴，使用多晶矽內芯可降低柱狀下電極的材料成本，為其另一優點。此外，須注意本發明柱狀下電極117中的第一金屬層116與多晶矽內芯118為個別部位，其在不同的製程步驟中形成，有別於化合物型態的金屬矽（如氮化鈦矽，TiSiN）或是氮化鈦/氮化矽的多層疊構。氮化鈦矽或是氮化鈦/氮化矽疊層結構並無法達到如本發明般顯著地應力降低功效。Compared to a conventional single-structure columnar lower electrode, such as a columnar lower electrode made entirely of titanium nitride, the high shear stress generated by titanium nitride after heat treatment can easily cause the column to bend, resulting in the lower electrodes bridging each other and failing. To solve this problem, the present invention proposes a hybrid columnarlower electrode 117 design consisting of a metal layer exterior and a polycrystalline silicon core. The combination design of the metal layer and polycrystalline silicon can significantly reduce the shear stress of the columnarlower electrode 117 and prevent it from bending and bridging. Furthermore, since titanium nitride material is relatively expensive, the use of a polycrystalline silicon core can reduce the material cost of the columnar lower electrode, which is another advantage. In addition, it should be noted that thefirst metal layer 116 and thepolysilicon core 118 in the columnarlower electrode 117 of the present invention are separate parts, which are formed in different process steps, and are different from compound-type metal silicon (such as titanium silicon nitride, TiSiN) or titanium nitride/silicon nitride multi-layer structure. Titanium silicon nitride or titanium nitride/silicon nitride stacked structures cannot achieve the same significant stress reduction effect as the present invention.

復參照第1圖。在本發明實施例中，第一區域100a與第二區域100b上還具有一蝕刻停止層104與之直接接觸。蝕刻停止層104在製造過程中可避免蝕刻損傷非目標區域。蝕刻停止層104的材料可為氮化矽(Si₃N₄)或碳氮化矽(SiCN)。再者，第二區域100b上方還具有一中間支撐結構108與一頂部支撐結構112，其中中間支撐結構108側向連接周圍的柱狀下電極117在垂直方向上的中間部位，頂部支撐結構112則側向連接周圍的柱狀下電極117在垂直方向上的頂端部位。中間支撐結構108與頂部支撐結構112較佳在垂直方向上與下方的蝕刻停止層104完全重疊。在本發明實施例中，中間支撐結構108與頂部支撐結構112可在側面的方向提供柱狀下電極117物理支撐，避免製造期間柱狀下電極117因為高寬比過高而傾倒，造成下電極橋接失效等問題。中間支撐結構108與頂部支撐結構112的材質可與蝕刻停止層104相同，如氮化矽(Si₃N₄)或碳氮化矽(SiCN)。Referring to FIG. 1 again, in the present embodiment, anetch stop layer 104 is directly in contact with thefirst region 100a and thesecond region 100b. Theetch stop layer 104 can prevent etching damage to non-target regions during the manufacturing process. The material of theetch stop layer 104 can be silicon nitride (Si₃ N₄ ) or silicon carbonitride (SiCN). Furthermore, amiddle support structure 108 and atop support structure 112 are provided above thesecond region 100b, wherein themiddle support structure 108 is laterally connected to the middle portion of the surrounding columnarlower electrodes 117 in the vertical direction, and thetop support structure 112 is laterally connected to the top portion of the surrounding columnarlower electrodes 117 in the vertical direction. Themiddle support structure 108 and thetop support structure 112 preferably completely overlap theetch stop layer 104 below in the vertical direction. In the embodiment of the present invention, themiddle support structure 108 and thetop support structure 112 can provide physical support to the columnarlower electrode 117 in the lateral direction to prevent the columnarlower electrode 117 from tipping over due to excessively high aspect ratio during manufacturing, causing the lower electrode bridge failure, etc. The material of themiddle support structure 108 and thetop support structure 112 can be the same as that of theetch stop layer 104, such as silicon nitride (Si₃ N₄ ) or silicon carbonitride (SiCN).

復參照第1圖。除了支撐方面的功效，本發明的中間支撐結構108與頂部支撐結構112還可在記憶體結構中界定出不同的電容空間。以第1圖的截面圖為例，蝕刻停止層104以及柱狀下電極117在每一第一區域100a上界定出一第一電容空間S1，頂部支撐結構112、中間支撐結構108以及柱狀下電極117在每一第二區域100b上界定出一第二電容空間S2，而中間支撐結構108、蝕刻停止層104以及柱狀下電極117在每一第二區域100b上界定出一第三電容空間S3，該第二電容空間S2位於該第三電容空間S3正上方。其中，第一電容空間S1在垂直方向上的長度涵蓋了第二電容空間S2以及第三電容空間S3。須注意的是，儘管從截面圖來看是分隔的區域，圖中的第二電容空間S2以及第三電容空間S3實際上在側面方向上是與鄰近的第一電容空間S1連通的，三個電容空間共同圍繞著中間的柱狀下電極117。每個柱狀下電極117（即儲存節點）都會有對應的一第一電容空間S1、一第二電容空間S2以及一第三電容空間S3，其可與鄰近的柱狀下電極117共用。例如，以第1圖為例，第一電容空間S1為左邊與中間的柱狀下電極117所共用，第二電容空間S2與第三電容空間S3為右邊與中間的柱狀下電極117所共用。Refer to FIG. 1 again. In addition to the supporting effect, themiddle supporting structure 108 and thetop supporting structure 112 of the present invention can also define different capacitor spaces in the memory structure. Taking the cross-sectional view of FIG. 1 as an example, theetch stop layer 104 and the columnarlower electrode 117 define a first capacitance space S1 on eachfirst region 100a, thetop support structure 112, themiddle support structure 108 and the columnarlower electrode 117 define a second capacitance space S2 on eachsecond region 100b, and themiddle support structure 108, theetch stop layer 104 and the columnarlower electrode 117 define a third capacitance space S3 on eachsecond region 100b, and the second capacitance space S2 is located directly above the third capacitance space S3. The length of the first capacitance space S1 in the vertical direction covers the second capacitance space S2 and the third capacitance space S3. It should be noted that, although the cross-sectional view shows separated regions, the second capacitor space S2 and the third capacitor space S3 in the figure are actually connected to the adjacent first capacitor space S1 in the lateral direction, and the three capacitor spaces surround the middle columnarlower electrode 117. Each columnar lower electrode 117 (i.e., storage node) has a corresponding first capacitor space S1, a second capacitor space S2, and a third capacitor space S3, which can be shared with the adjacent columnarlower electrode 117. For example, taking FIG. 1 as an example, the first capacitor space S1 is shared by the left and middle columnarlower electrodes 117, and the second capacitor space S2 and the third capacitor space S3 are shared by the right and middle columnarlower electrodes 117.

在習知的柱狀下電極結構中，柱狀下電極之間的電容空間都如圖中的第一電容空間S1所示，其有效電容面積涵蓋了柱狀下電極的側壁與頂面。相較於此，對於本發明而言，記憶體結構中有一半以上的第一電容空間S1因為中間支撐結構108與頂部支撐結構112的關係而被拆分成第二電容空間S2以及第三電容空間S3，如此可增加有效電容面積，提高記憶體的串聯電容值(C_S)，適合應用於下一世代的DRAM架構。In the conventional columnar lower electrode structure, the capacitance space between the columnar lower electrodes is shown as the first capacitance space S1 in the figure, and its effective capacitance area covers the side wall and top surface of the columnar lower electrode. In contrast, in the present invention, more than half of the first capacitance space S1 in the memory structure is split into the second capacitance space S2 and the third capacitance space S3 due to the relationship between themiddle support structure 108 and thetop support structure 112, so that the effective capacitance area can be increased, and the series capacitance value (C_S ) of the memory is improved, which is suitable for application in the next generation of DRAM architecture.

復參照第1圖。對於每個電容空間S1~S3而言，其由外而內依序形成有電容介電層126、第二金屬層128以及多晶矽層130等結構。在本發明實施例中，第二金屬層128與多晶矽層130係作為記憶體結構的上電極129，電容介電層126則夾設在上電極129與多個柱狀下電極117之間。具體來說，電容介電層126係共形地形成在該些柱狀下電極117、頂部支撐結構112、中間支撐結構108以及蝕刻停止層104的表面，其涵蓋電容空間S1~S3的最外部區域。第二金屬層128係共形地形成在上述電容介電層126的表面，其涵蓋電容空間S1~S3的內部區域。多晶矽層130大體上會填滿電容空間S1~S3最內部剩餘的區域，也會覆蓋整個記憶體結構的頂面。但在一些實施例中，第二電容空間S2或第三電容空間S3內可能會因為上述層結構未完全填充的原因而產生空洞132。在實施例中，電容介電層126可為高介電常數(high-k)材料，如氧化鉿(HfO₂)、氧化鋯(ZrO₂)、氧化鋁(Al₂O₃)、氧化鈦(TiO₂)、氧化鉭 (Ta₂O₅)、氧化鈮(Nb₂O₅)、鈦酸鍶(SrTiO₃)等，其可避免電容介電層126過薄而穿隧漏電。第二金屬層128的材料可與下電極117的第一金屬層116相同，如氮化鈦(TiN)，其可身兼阻障層避免多晶矽層130中的雜質粒子擴散汙染到電容介電層126。Refer to FIG. 1 again. For each capacitor space S1-S3, acapacitor dielectric layer 126, asecond metal layer 128, and apolysilicon layer 130 are sequentially formed from the outside to the inside. In the embodiment of the present invention, thesecond metal layer 128 and thepolysilicon layer 130 are used as theupper electrode 129 of the memory structure, and thecapacitor dielectric layer 126 is sandwiched between theupper electrode 129 and a plurality of columnarlower electrodes 117. Specifically, thecapacitor dielectric layer 126 is conformally formed on the surfaces of the columnarlower electrodes 117, thetop support structure 112, themiddle support structure 108, and theetch stop layer 104, and covers the outermost regions of the capacitor spaces S1-S3. Thesecond metal layer 128 is conformally formed on the surface of thecapacitor dielectric layer 126, and covers the inner regions of the capacitor spaces S1-S3. Thepolysilicon layer 130 substantially fills the innermost remaining regions of the capacitor spaces S1-S3, and also covers the top surface of the entire memory structure. However, in some embodiments,voids 132 may be generated in the second capacitor space S2 or the third capacitor space S3 because the above layer structure is not completely filled. In an embodiment, thecapacitor dielectric layer 126 may be a high-k material, such as HfO₂ , ZrO₂ , Al₂ O₃ , TiO₂ , Ta₂ O₅ , Nb₂ O₅ , SrTiO₃ , etc., which can prevent thecapacitor dielectric layer 126 from being too thin and causing tunnel leakage. The material of thesecond metal layer 128 can be the same as that of thefirst metal layer 116 of thebottom electrode 117, such as titanium nitride (TiN), which can also serve as a barrier layer to prevent impurity particles in thepolysilicon layer 130 from diffusing and contaminating thecapacitor dielectric layer 126.

現在下文將依序參照第2圖至第11圖來說明根據本發明實施例上述具有柱狀下電極的記憶體結構的製造流程，圖中將以截面圖的形式來說明製程中各部件在垂直方向上的相對位置與連結關係，且圖中將以三根柱狀下電極117、一第一區域100a以及一第二區域100b的範圍為例來讓閱者了解其間的組成結構在製程中的演變關係。須注意在實際的結構中，視截面所切之位置，記憶體結構可能會有不同的截面組成與型態，不以此為限。Now, the following will sequentially refer to FIG. 2 to FIG. 11 to explain the manufacturing process of the memory structure with the columnar lower electrode according to the embodiment of the present invention. The relative positions and connection relationships of the components in the vertical direction during the manufacturing process will be explained in the form of cross-sectional views, and the scope of three columnarlower electrodes 117, afirst region 100a, and asecond region 100b will be used as examples to allow readers to understand the evolution relationship of the composition structure therebetween during the manufacturing process. It should be noted that in the actual structure, depending on the position of the cross section, the memory structure may have different cross-sectional compositions and shapes, and is not limited to this.

請參照第2圖。在製程一開始，提供一基底100作為本發明半導體元件的設置基礎。基底100可包含一半導體基底以及形成在其上的一或多層介電層。該半導體基底的材質較佳為矽基底，該介電層可為層間介電層(ILD)，圖中將僅示出基底上的層間介電層部位，以其來代表整個基底100。基底100中並形成有多個接觸件102，其材質可包含鎢(W)及氮化鈦(TiN)。接觸件102並在基底100中界定出多個第一區域100a以及多個第二區域100b。接著，在基底100上依序形成一蝕刻停止層104、一第一塑形層106、一中間支撐層108、一第二塑形層110以及一頂部支撐層112。蝕刻停止層104、中間支撐層108以及一頂部支撐層112可透過化學氣相沉積(CVD)製程形成，其材料可為氮化矽(Si₃N₄)或碳氮化矽(SiCN)。其中，頂部支撐層112的厚度（如50nm）較佳大於中間支撐層108的厚度（如20nm），其可在後續製程中達到選擇性功效。第一塑形層106與第二塑形層110也可透過CVD製程形成，其材料例如可包含氧化矽(SiO₂)，兩者厚度可相同。在本發明實施例中，蝕刻停止層104、中間支撐層108以及頂部支撐層112的材料相較於第一塑形層106與第二塑形層110的材料具有蝕刻選擇性，以在後續製程中提供選擇性蝕刻功效。Please refer to FIG. 2. At the beginning of the manufacturing process, asubstrate 100 is provided as a setting base for the semiconductor element of the present invention. Thesubstrate 100 may include a semiconductor substrate and one or more dielectric layers formed thereon. The material of the semiconductor substrate is preferably a silicon substrate, and the dielectric layer may be an interlayer dielectric layer (ILD). Only the interlayer dielectric layer portion on the substrate is shown in the figure to represent theentire substrate 100. A plurality ofcontacts 102 are formed in thesubstrate 100, and the material thereof may include tungsten (W) and titanium nitride (TiN). Thecontacts 102 define a plurality offirst regions 100a and a plurality ofsecond regions 100b in thesubstrate 100. Next, anetch stop layer 104, afirst shaping layer 106, anintermediate support layer 108, asecond shaping layer 110, and atop support layer 112 are sequentially formed on thesubstrate 100. Theetch stop layer 104, theintermediate support layer 108, and thetop support layer 112 can be formed by a chemical vapor deposition (CVD) process, and the material thereof can be silicon nitride (Si₃ N₄ ) or silicon carbonitride (SiCN). The thickness of the top support layer 112 (e.g., 50 nm) is preferably greater than the thickness of the intermediate support layer 108 (e.g., 20 nm), which can achieve a selective effect in subsequent processes. Thefirst shaping layer 106 and thesecond shaping layer 110 may also be formed by a CVD process, and their materials may include silicon oxide (SiO₂ ), for example, and the thickness of the two layers may be the same. In the embodiment of the present invention, the materials of theetch stop layer 104, themiddle support layer 108, and thetop support layer 112 have etching selectivity compared to the materials of thefirst shaping layer 106 and thesecond shaping layer 110, so as to provide selective etching effect in subsequent processes.

請參照第3圖。形成上述層結構後，接著進行一第一光刻製程圖案化蝕刻停止層104、第一塑形層106、中間支撐層108、第二塑形層110以及頂部支撐層112，在其中形成多個孔洞114，該些孔洞114往垂直基底100的方向延伸並貫穿頂部支撐層112、第二塑形層110、中間支撐層108、第一塑形層106以及蝕刻停止層104，使得每一孔洞114露出下方基底100中的一接觸件102。孔洞114在基底100平面上可呈錯位陣列的排列型態，不以此為限。上述第一光刻製程具體可包含在頂部支撐層112上形成具有孔洞圖案的光阻，之後以該光阻為遮罩進行一非等向性乾蝕刻製程，如深反應離子式蝕刻(deep reactive ion etching, DRIE)製程，蝕刻上述疊層結構直至蝕刻停止層104，如此在其中形成高深寬比的孔洞114。最後進行另一蝕刻製程移除孔洞114中的蝕刻停止層104，露出基底100中的接觸件102。這些孔洞114即界定出了本發明記憶體結構的下電極圖案（即儲存節點圖案）。Please refer to FIG. 3. After the above-mentioned layer structure is formed, a first photolithography process is then performed to pattern theetch stop layer 104, thefirst shaping layer 106, themiddle support layer 108, thesecond shaping layer 110 and thetop support layer 112, and a plurality ofholes 114 are formed therein. Theholes 114 extend in a direction perpendicular to thesubstrate 100 and penetrate thetop support layer 112, thesecond shaping layer 110, themiddle support layer 108, thefirst shaping layer 106 and theetch stop layer 104, so that eachhole 114 exposes acontact 102 in thesubstrate 100 below. Theholes 114 may be arranged in a staggered array on the plane of thesubstrate 100, but are not limited thereto. The first photolithography process may specifically include forming a photoresist with a hole pattern on thetop support layer 112, and then performing an anisotropic dry etching process, such as a deep reactive ion etching (DRIE) process, using the photoresist as a mask to etch the stacked structure until theetch stop layer 104, thereby forming ahole 114 with a high aspect ratio therein. Finally, another etching process is performed to remove theetch stop layer 104 in thehole 114, exposing thecontact 102 in thesubstrate 100. Theseholes 114 define the bottom electrode pattern (i.e., storage node pattern) of the memory structure of the present invention.

請參照第4圖。孔洞114形成後，接著在孔洞114的表面形成一共形的第一金屬層116，該第一金屬層116會與下方的接觸件102直接接觸並覆蓋頂部支撐層112。在實施例中，第一金屬層116的材料可為導電性佳的金屬，如鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)、氮化鋁鈦(TiAlN)、鎢(W)、氮化鎢(WN)或是上述材料之組合，其中以氮化鈦(TiN)為佳，其可透過低壓化學氣相沉積(LPCVD)、電漿輔助化學氣相沉積(PECVD)、或是階梯覆蓋率較佳的原子層沉積(ALD)等製程來形成。第一金屬層116形成後，接著在孔洞114中填入第一多晶矽層118，該第一多晶矽層118會位於第一金屬層116上，其填滿孔洞114並覆蓋整個基底頂面。第一多晶矽層118可透過階梯覆蓋率佳的LPCVD製程來形成，其中並可原位(in-situ)摻雜有雜質來增加其導電性，如磷(P)、砷(As)等N型摻質或是硼(B)等P型摻質。Please refer to FIG. 4 . After thehole 114 is formed, a conformalfirst metal layer 116 is then formed on the surface of thehole 114 . Thefirst metal layer 116 directly contacts thecontact 102 below and covers thetop support layer 112 . In an embodiment, the material of thefirst metal layer 116 may be a metal with good conductivity, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN) or a combination of the above materials, among which titanium nitride (TiN) is preferred, which can be formed by processes such as low pressure chemical vapor deposition (LPCVD), plasma assisted chemical vapor deposition (PECVD), or atomic layer deposition (ALD) with better step coverage. After thefirst metal layer 116 is formed, thefirst polysilicon layer 118 is then filled into thehole 114. Thefirst polysilicon layer 118 is located on thefirst metal layer 116, and fills thehole 114 and covers the entire substrate top surface. Thefirst polysilicon layer 118 can be formed by a LPCVD process with good step coverage, and can be in-situ doped with impurities to increase its conductivity, such as N-type dopants such as phosphorus (P) and arsenic (As) or P-type dopants such as boron (B).

請參照第5圖。第一金屬層116與第一多晶矽層118形成後，接著進行一第二光刻製程移除位於第一區域100a上方的頂部支撐層112的頂面上的第一金屬層116以及該頂部支撐層112，如此露出第一區域100a上方的第二塑形層110。此第二光刻製程具體可包含在第一多晶矽層118上形成具有孔洞圖案的光阻，之後以該光阻為遮罩進行一非等向性乾蝕刻製程移除第一區域100a上方的第一多晶矽層118、頂部支撐層112上的第一金屬層116以及該頂部支撐層112等部位，如此形成開孔119露出第一區域100a上方的第二塑形層110。第二區域100b上方的該些層結構則不受影響。Please refer to Figure 5. After thefirst metal layer 116 and thefirst polysilicon layer 118 are formed, a second photolithography process is then performed to remove thefirst metal layer 116 and thetop support layer 112 on the top surface of thetop support layer 112 above thefirst region 100a, thereby exposing thesecond shaping layer 110 above thefirst region 100a. The second photolithography process may specifically include forming a photoresist having a hole pattern on thefirst polysilicon layer 118, and then performing an anisotropic dry etching process using the photoresist as a mask to remove thefirst polysilicon layer 118 above thefirst region 100a, thefirst metal layer 116 on thetop support layer 112, and thetop support layer 112, thereby forming anopening 119 to expose thesecond shaping layer 110 above thefirst region 100a. The layer structures above thesecond region 100b are not affected.

請參照第6圖。開孔119形成後，接著移除位於第二區域100b上方的頂部支撐層112的頂面上的第一多晶矽層118以及第一金屬層116，如此形成多個由第一金屬層116與第一多晶矽層118構成的柱狀下電極117，並露出該第二區域100b上方的頂部支撐層112。此步驟可透過一選擇性的回蝕刻製程來達成，其蝕刻至第二區域100b上的頂部支撐層112露出為止，開孔119周圍的第一金屬層116可能也會被部分移除而導致其高度低於鄰接第二區域100b的第一金屬層116。第一區域100a上方已露出的第二塑形層110則不受影響。Please refer to FIG. 6. After theopening 119 is formed, thefirst polysilicon layer 118 and thefirst metal layer 116 on the top surface of thetop support layer 112 above thesecond region 100b are removed, so as to form a plurality of columnarlower electrodes 117 composed of thefirst metal layer 116 and thefirst polysilicon layer 118, and expose thetop support layer 112 above thesecond region 100b. This step can be achieved by a selective etching back process, which is etched until thetop support layer 112 on thesecond region 100b is exposed, and thefirst metal layer 116 around theopening 119 may also be partially removed, resulting in its height being lower than thefirst metal layer 116 adjacent to thesecond region 100b. Thesecond shaping layer 110 exposed above thefirst area 100a is not affected.

請參照第7圖。柱狀下電極117形成後，接著移除該第二塑形層110，如此在第一區域100a上方形成一由中間支撐層108以及該些柱狀下電極117所界定出的第一電容空間S1以及在第二區域100b上方形成一由中間支撐層108、頂部支撐層112以及該些柱狀下電極117所界定出的第二電容空間S2。可以看出第二塑形層110在本發明實施例中係作為犧牲性結構，其用以形塑電容空間。第二塑形層110可透過一浸蝕(wet dip)製程來移除，先前形成的開孔119則作為蝕刻通道，位於第二區域100b上方的第二塑形層110由於其與第一區域100a上方的第二塑形層110側向連通，所以也會在此製程中被移除。中間支撐層108與頂部支撐層112的材料由於相較於第二塑形層110的材料具有蝕刻選擇性，所以不會被移除。Please refer to FIG. 7. After the columnarlower electrode 117 is formed, thesecond shaping layer 110 is then removed, so that a first capacitor space S1 defined by themiddle supporting layer 108 and the columnarlower electrodes 117 is formed above thefirst region 100a, and a second capacitor space S2 defined by themiddle supporting layer 108, the top supportinglayer 112, and the columnarlower electrodes 117 is formed above thesecond region 100b. It can be seen that thesecond shaping layer 110 is used as a sacrificial structure in the embodiment of the present invention, which is used to shape the capacitor space. Thesecond shaping layer 110 can be removed by a wet dip process, and the previously formedopening 119 serves as an etching channel. Thesecond shaping layer 110 located above thesecond region 100b is also removed in this process because it is laterally connected to thesecond shaping layer 110 above thefirst region 100a. The materials of the middle supportinglayer 108 and the top supportinglayer 112 are not removed because they have etching selectivity compared to the materials of thesecond shaping layer 110.

請參照第8圖。第一電容空間S1與第二電容空間S2形成後，接著移除第一區域100a上方的中間支撐層108，如此露出該第一區域100a上方的第一塑形層106。此區域上的中間支撐層108可透過一選擇性的回蝕刻製程來移除。須注意當頂部支撐層112與中間支撐層108使用相同的材質時（如氮化矽），由於頂部支撐層112的厚度在設計上大於中間支撐層108的厚度，頂部支撐層112在中間支撐層108被蝕刻殆盡的情況下厚度會變薄，但仍舊覆蓋住第二區域100b上方的第二電容空間S2。Please refer to FIG. 8. After the first capacitor space S1 and the second capacitor space S2 are formed, themiddle support layer 108 above thefirst region 100a is removed, thereby exposing thefirst shaping layer 106 above thefirst region 100a. Themiddle support layer 108 on this region can be removed by a selective etching process. It should be noted that when thetop support layer 112 and themiddle support layer 108 use the same material (such as silicon nitride), since the thickness of thetop support layer 112 is designed to be greater than the thickness of themiddle support layer 108, the thickness of thetop support layer 112 will become thinner when themiddle support layer 108 is etched away, but it still covers the second capacitor space S2 above thesecond region 100b.

請參照第9圖。第一區域100a上方的中間支撐層108移除後，接著移除第一塑形層106，如此在第一區域100a上的第一電容空間S1會在垂直方向上延伸變大，而第二區域100b上則會形成由中間支撐層108、蝕刻停止層104以及該些柱狀下電極117界定出的一第三電容空間S3。可以看出第一塑形層106在本發明實施例中同樣作為犧牲性結構，其用以形塑電容空間。同樣地，第一塑形層106可透過一浸蝕製程來移除，先前形成的開孔119作為蝕刻通道，位於第二區域100b上方的第一塑形層106由於其與第一區域100a上方的第一塑形層106側向連通，所以也會在此製程中被移除。中間支撐層108與蝕刻停止層104的材料由於相較於第一塑形層106的材料具有蝕刻選擇性，所以不會被移除。Please refer to FIG. 9. After themiddle support layer 108 on thefirst region 100a is removed, thefirst shaping layer 106 is then removed, so that the first capacitor space S1 on thefirst region 100a is extended and enlarged in the vertical direction, and a third capacitor space S3 is formed on thesecond region 100b, which is defined by themiddle support layer 108, theetching stop layer 104 and the columnarlower electrodes 117. It can be seen that thefirst shaping layer 106 in the embodiment of the present invention is also used as a sacrificial structure for shaping the capacitor space. Similarly, thefirst shaping layer 106 can be removed by an immersion etching process. The previously formedopening 119 serves as an etching channel. Thefirst shaping layer 106 located above thesecond region 100b is laterally connected to thefirst shaping layer 106 above thefirst region 100a, so it will also be removed in this process. The materials of theintermediate support layer 108 and theetching stop layer 104 are not removed because they have etching selectivity compared to the material of thefirst shaping layer 106.

請參照第10圖。第一塑形層106移除後，接著在第一電容空間S1、第二電容空間S2以及第三電容空間S3中形成一共形的電容介電層126。電容介電層126係共形地形成在上述空間的裸露面上，包括第一金屬層116、頂部支撐層112、中間支撐層108以及蝕刻停止層104的表面以及柱狀下電極117的頂部，其都為有效電容面積。電容介電層126的材料可為高介電常數(high-k)材料，如氧化鉿(HfO₂)、氧化鋯(ZrO₂)、氧化鋁(Al₂O₃)、氧化鈦(TiO₂)、氧化鉭 (Ta₂O₅)、氧化鈮(Nb₂O₅)、鈦酸鍶(SrTiO₃)，其可透過CVD製程或是階梯覆蓋率較佳的ALD製程來形成。Please refer to FIG. 10. After thefirst shaping layer 106 is removed, a conformalcapacitor dielectric layer 126 is then formed in the first capacitor space S1, the second capacitor space S2, and the third capacitor space S3. Thecapacitor dielectric layer 126 is conformally formed on the exposed surface of the above space, including thefirst metal layer 116, thetop support layer 112, themiddle support layer 108, the surface of theetch stop layer 104, and the top of the columnarlower electrode 117, which are all effective capacitor areas. The material of thecapacitor dielectric layer 126 may be a high-k material, such as HfO₂ , ZrO₂ , Al₂ O₃ , TiO₂ , Ta₂ O₅ , Nb₂ O₅ , SrTiO₃ , which may be formed by a CVD process or an ALD process with better step coverage.

請參照第11圖。電容介電層126形成後，接著在第一電容空間S1、第二電容空間S2以及第三電容空間S3中形成一共形的第二金屬層128。第二金屬層128係共形地形成在上述空間的裸露面上，即先前所形成的電容介電層126的表面上。在本發明實施例中，電容空間S1~S3在第二金屬層128形成後較佳還有剩餘的空間，以便後續多晶矽層的填入。第二金屬層128的材料可為導電性佳的金屬，如鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)、氮化鋁鈦(TiAlN)、鎢(W)、氮化鎢(WN)或是上述材料之組合，其可透過LPCVD、PECVD、或是階梯覆蓋率較佳的原子層沉積ALD等製程來形成。第二金屬層128形成後，接著在剩餘的第一電容空間S1、第二電容空間S2以及第三電容空間S3中填入一多晶矽層130。多晶矽層130會形成在先前所形成的第二金屬層128上，其中並可原位(in-situ)摻雜有雜質來增加其導電性，如磷(P)、砷(As)等N型摻質或是硼(B)等P型摻質。在本發明實施例中，第二金屬層128與多晶矽層130共同構成了本發明記憶體結構的上電極129。如此，即完成了本發明記憶體結構之製作。須注意在一些實施例中，第二電容空間S2或第三電容空間S3內可能會因為上述層結構未能完全填充的緣故而產生空洞132。上電極129形成後，後續其上還可形成鈍化層以及ILD層等結構，然由於該些部位並非本發明之重點，故此處將省略其說明。Please refer to FIG. 11. After thecapacitor dielectric layer 126 is formed, a conformalsecond metal layer 128 is then formed in the first capacitor space S1, the second capacitor space S2, and the third capacitor space S3. Thesecond metal layer 128 is conformally formed on the exposed surface of the above-mentioned space, that is, the surface of the previously formedcapacitor dielectric layer 126. In the embodiment of the present invention, it is preferred that there is a remaining space in the capacitor spaces S1-S3 after thesecond metal layer 128 is formed, so as to facilitate the subsequent filling of the polysilicon layer. The material of thesecond metal layer 128 can be a metal with good conductivity, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN) or a combination of the above materials, which can be formed by LPCVD, PECVD, or atomic layer deposition ALD with good step coverage. After thesecond metal layer 128 is formed, apolysilicon layer 130 is then filled in the remaining first capacitor space S1, the second capacitor space S2 and the third capacitor space S3. Thepolysilicon layer 130 is formed on the previously formedsecond metal layer 128, and may be doped in-situ with impurities to increase its conductivity, such as N-type dopants such as phosphorus (P) and arsenic (As) or P-type dopants such as boron (B). In the embodiment of the present invention, thesecond metal layer 128 and thepolysilicon layer 130 together constitute theupper electrode 129 of the memory structure of the present invention. In this way, the fabrication of the memory structure of the present invention is completed. It should be noted that in some embodiments, a void 132 may be generated in the second capacitor space S2 or the third capacitor space S3 because the above-mentioned layer structure is not completely filled. After theupper electrode 129 is formed, a passivation layer and an ILD layer may be formed thereon. However, since these parts are not the focus of the present invention, their description will be omitted here.

從上述製程可知，本發明透過在基底上界定出兩種不同區域，並在其中一區域上形成開孔作為蝕刻通道，以在製程中逐步移除該區域上的頂部支撐結構與中間支撐結構以及兩區域上的塑形層，如此可在其中一區域上界定出兩個電容空間，進而增加有效電容面積，提高記憶體的串聯電容值，適合應用於下一世代的DRAM架構。另一方面，由金屬與多晶矽構成的柱狀下電極可以有效降低應力，避免柱體彎曲而橋接失效，為本發明的進步性與功效性所在。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。From the above process, it can be seen that the present invention defines two different areas on the substrate and forms an opening in one of the areas as an etching channel to gradually remove the top support structure and the middle support structure on the area and the shaping layer on the two areas during the process. In this way, two capacitor spaces can be defined on one of the areas, thereby increasing the effective capacitor area and improving the series capacitance value of the memory, which is suitable for application in the next generation of DRAM architecture. On the other hand, the columnar lower electrode composed of metal and polycrystalline silicon can effectively reduce stress and avoid column bending and bridge failure, which is the advancement and effectiveness of the present invention.The above is only a preferred embodiment of the present invention. All equal changes and modifications made according to the scope of the patent application of the present invention should be covered by the present invention.

100:基底 100a:第一區域 100b:第一區域 102:接觸件 104:蝕刻停止層 106:第一塑形層 108:中間支撐結構（層） 110:第二塑形層 112:頂部支撐結構（層） 114:孔洞 116:第一金屬層 117:柱狀下電極 118:第一多晶矽層（多晶矽內芯） 119:開孔 126:電容介電層 128:第二金屬層 129:上電極 130:多晶矽層 132:空洞 S1:（第一）電容空間 S2:（第二）電容空間 S3:（第三）電容空間100:substrate100a:first region100b: first region102: contact104: etch stop layer106: first shaping layer108: middle support structure (layer)110: second shaping layer112: top support structure (layer)114: hole116: first metal layer117: columnar lower electrode118: first polysilicon layer (polysilicon core)119: opening126: capacitor dielectric layer128: second metal layer129: upper electrode130: polysilicon layer132: cavityS1: (first) capacitor spaceS2: (second) capacitor spaceS3: (third) capacitor space

第1圖為根據本發明實施例一具有柱狀下電極的記憶體結構的截面示意圖；以及 第2圖至第11圖為根據本發明實施例一具有柱狀下電極的記憶體結構的製造流程的截面示意圖。 須注意本說明書中的所有圖示皆為圖例性質，為了清楚與方便圖示說明之故，圖示中的各部件在尺寸與比例上可能會被誇大或縮小地呈現，一般而言，圖中相同的參考符號會用來標示修改後或不同實施例中對應或類似的元件特徵。FIG. 1 is a schematic cross-sectional view of a memory structure with a columnar lower electrode according toEmbodiment 1 of the present invention; and FIG. 2 to FIG. 11 are schematic cross-sectional views of a manufacturing process of a memory structure with a columnar lower electrode according toEmbodiment 1 of the present invention. It should be noted that all the diagrams in this specification are of a legend nature. For the sake of clarity and convenience of illustration, the size and proportion of each component in the diagram may be exaggerated or reduced. Generally speaking, the same reference symbols in the diagram will be used to indicate corresponding or similar component features after modification or in different embodiments.

100:基底100: Base

100a:第一區域100a: First area

100b:第一區域100b: First area

102:接觸件102: Contacts

104:蝕刻停止層104: Etch stop layer

108:中間支撐結構(層)108: Middle support structure (layer)

112:頂部支撐結構(層)112: Top support structure (layer)

116:第一金屬層116: First metal layer

117:柱狀下電極117: Columnar lower electrode

118:第一多晶矽層(多晶矽內芯)118: First polysilicon layer (polysilicon core)

126:電容介電層126: Capacitor dielectric layer

128:第二金屬層128: Second metal layer

129:上電極129: Upper electrode

130:多晶矽層130: Polycrystalline silicon layer

132:空洞132: Hollow

S1:(第一)電容空間S1: (First) Capacitor Space

S2:(第二)電容空間S2: (Second) Capacitor Space

S3:(第三)電容空間S3: (Third) Capacitor Space

Claims (16)

Translated fromChinese

一種具有柱狀下電極的記憶體結構，包含： 一基底，該基底上界定有多個第一區域以及多個第二區域； 多個接觸件，位於該些第一區域與該些第二區域之間的該基底中； 多個柱狀下電極，每個該柱狀下電極位於一該接觸件上並與之電性接觸，其中每個該柱狀下電極由一多晶矽內芯以及包覆該多晶矽內芯的側壁與底面的一第一金屬層所構成且往與該基底垂直的一垂直方向延伸； 一蝕刻停止層，位於該些第一區域以及該些第二區域上； 一中間支撐結構，位於該些第二區域上方且側向連接該些柱狀下電極在該垂直方向上的中間部位； 一頂部支撐結構，位於該些第二區域上方且側向連接該些柱狀下電極在該垂直方向上的頂端部位，其中該蝕刻停止層以及該些柱狀下電極在每一該第一區域上界定出一第一電容空間，該頂部支撐結構、該中間支撐結構、該蝕刻停止層以及該些柱狀下電極在每一該第二區域上界定出一第二電容空間以及一第三電容空間，該第二電容空間位於該第三電容空間上方； 一電容介電層，共形地形成在該第一電容空間、該第二電容空間以及該第三電容空間的表面；以及 一上電極，包含一第二金屬層與一多晶矽層，其中該第二金屬層共形地形成在該電容介電層的表面上，該多晶矽層形成在該金屬層上。A memory structure with a columnar lower electrode, comprising:A substrate, on which a plurality of first regions and a plurality of second regions are defined;A plurality of contacts, located in the substrate between the first regions and the second regions;A plurality of columnar lower electrodes, each of which is located on and electrically connected to one of the contacts, wherein each of the columnar lower electrodes is composed of a polycrystalline silicon core and a first metal layer covering the sidewalls and bottom surface of the polycrystalline silicon core and extending in a vertical direction perpendicular to the substrate;An etch stop layer, located on the first regions and the second regions;A middle supporting structure, located above the second regions and laterally connected to the middle parts of the columnar lower electrodes in the vertical direction;A top supporting structure, located above the second regions and laterally connected to the top parts of the columnar lower electrodes in the vertical direction, wherein the etching stop layer and the columnar lower electrodes define a first capacitor space on each of the first regions, and the top supporting structure, the middle supporting structure, the etching stop layer and the columnar lower electrodes define a second capacitor space and a third capacitor space on each of the second regions, and the second capacitor space is located above the third capacitor space;A capacitor dielectric layer is conformally formed on the surface of the first capacitor space, the second capacitor space and the third capacitor space; andan upper electrode includes a second metal layer and a polysilicon layer, wherein the second metal layer is conformally formed on the surface of the capacitor dielectric layer, and the polysilicon layer is formed on the metal layer.如申請專利範圍第1項所述之具有柱狀下電極的記憶體結構，其中該第一電容空間在水平方向由內而外依序包含該多晶矽層、該第二金屬層以及該電容介電層。As described in the first item of the patent application scope, the memory structure with a columnar lower electrode, wherein the first capacitor space includes the polysilicon layer, the second metal layer and the capacitor dielectric layer in sequence from the inside to the outside in the horizontal direction.如申請專利範圍第1項所述之具有柱狀下電極的記憶體結構，其中該第二電容空間與該第三電容空間由內而外依序包含該多晶矽層、該第二金屬層以及該電容介電層。As described in the first item of the patent application scope, the memory structure with a columnar lower electrode, wherein the second capacitor space and the third capacitor space sequentially include the polysilicon layer, the second metal layer and the capacitor dielectric layer from the inside to the outside.如申請專利範圍第1項所述之具有柱狀下電極的記憶體結構，更包含空洞形成在該第二電容空間或該第三電容空間的該多晶矽層之中。The memory structure with a pillar-shaped lower electrode as described in claim 1 further includes a cavity formed in the polysilicon layer of the second capacitor space or the third capacitor space.如申請專利範圍第1項所述之具有柱狀下電極的記憶體結構，其中該蝕刻停止層的材料為氮化矽或碳氮化矽。The memory structure with a pillar-shaped bottom electrode as described in claim 1, wherein the material of the etch stop layer is silicon nitride or silicon carbonitride.如申請專利範圍第1項所述之具有柱狀下電極的記憶體結構，其中該中間支撐結構與該頂部支撐結構的材料為氮化矽或碳氮化矽。The memory structure with a columnar lower electrode as described in claim 1, wherein the material of the middle support structure and the top support structure is silicon nitride or silicon carbonitride.如申請專利範圍第1項所述之具有柱狀下電極的記憶體結構，其中該電容介電層的材料為高介電常數材料。As described in claim 1, the memory structure with a pillar-shaped lower electrode, wherein the material of the capacitor dielectric layer is a high dielectric constant material.如申請專利範圍第1項所述之具有柱狀下電極的記憶體結構，其中該基底包含一層間介電層，該些接觸件形成在該層間介電層中，該些柱狀下電極與該蝕刻停止層形成在該層間介電層上。The memory structure with a columnar lower electrode as described in claim 1, wherein the substrate comprises an inter-dielectric layer, the contacts are formed in the inter-dielectric layer, and the columnar lower electrodes and the etch stop layer are formed on the inter-dielectric layer.如申請專利範圍第1項所述之具有柱狀下電極的記憶體結構，其中該第一金屬層與該第二金屬層的材料為氮化鈦。As described in claim 1, the memory structure with a columnar bottom electrode, wherein the material of the first metal layer and the second metal layer is titanium nitride.一種具有柱狀下電極的記憶體結構的製造方法，包含： 提供一基底，該基底上界定有多個第一區域以及多個第二區域，且多個接觸件位於該些第一區域與該些第二區域之間的該基底中； 在該基底上依序形成一蝕刻停止層、一第一塑形層、一中間支撐層、一第二塑形層以及一頂部支撐層； 進行一第一光刻製程形成多個孔洞，該些孔洞往與該基底垂直的一垂直方向延伸並貫穿該頂部支撐層、該第二塑形層、該中間支撐層、該第一塑形層以及該蝕刻停止層，每一該孔洞露出下方的一該接觸件； 在該些孔洞的表面形成一共形的第一金屬層，該第一金屬層與下方的該些接觸件直接接觸並覆蓋該頂部支撐層； 在該些孔洞中填入一第一多晶矽層，該第一多晶矽層位於該第一金屬層上； 進行一第二光刻製程移除位於該第一區域上方的該頂部支撐層的頂面上的該第一金屬層以及該頂部支撐層，如此露出該第一區域上方的該第二塑形層； 移除位於該第二區域上方的該頂部支撐層的頂面上的該第一多晶矽層以及該第一金屬層，如此形成多個由該第一金屬層與該第一多晶矽層構成的柱狀下電極，並露出該第二區域上方的該頂部支撐層； 移除該第一區域上方以及該第二區域上方的第二塑形層； 移除該第一區域上方的該中間支撐層，如此露出該第一區域上方的該第一塑形層； 移除該第一區域上方以及該第二區域上方的該第一塑形層，如此在每一該第一區域上形成一由該蝕刻停止層以及該些柱狀下電極所界定出的第一電容空間，在每一該第二區域上形成一由該中間支撐層、該頂部支撐層以及該些柱狀下電極所界定出的第二電容空間，且在每一該第二區域上形成由該中間支撐結構、該蝕刻停止層以及該些柱狀下電極所界定出的一第三電容空間；以及 在該第一電容空間、該第二電容空間以及該第三電容空間中依序形成一共形的電容介電層、一共形的第二金屬層以及一第二多晶矽層，其中該第二金屬層與該第二多晶矽層構成一上電極。A method for manufacturing a memory structure with a columnar lower electrode, comprising: Providing a substrate, on which a plurality of first regions and a plurality of second regions are defined, and a plurality of contacts are located in the substrate between the first regions and the second regions; Sequentially forming an etch stop layer, a first shaping layer, an intermediate support layer, a second shaping layer and a top support layer on the substrate; Performing a first photolithography process to form a plurality of holes, the holes extending in a vertical direction perpendicular to the substrate and penetrating the top support layer, the second shaping layer, the intermediate support layer, the first shaping layer and the etch stop layer, each of the holes exposing a contact below; A conformal first metal layer is formed on the surface of the holes, the first metal layer directly contacts the contact parts below and covers the top support layer;A first polysilicon layer is filled in the holes, the first polysilicon layer is located on the first metal layer;A second photolithography process is performed to remove the first metal layer and the top support layer on the top surface of the top support layer above the first area, thereby exposing the second shaping layer above the first area;Removing the first polysilicon layer and the first metal layer on the top surface of the top support layer above the second region, thereby forming a plurality of columnar lower electrodes composed of the first metal layer and the first polysilicon layer, and exposing the top support layer above the second region;Removing the second shaping layer above the first region and above the second region;Removing the middle support layer above the first region, thereby exposing the first shaping layer above the first region;The first shaping layer above the first region and the second region is removed, so that a first capacitor space defined by the etch stop layer and the columnar lower electrodes is formed on each of the first regions, a second capacitor space defined by the middle support layer, the top support layer and the columnar lower electrodes is formed on each of the second regions, and a third capacitor space defined by the middle support structure, the etch stop layer and the columnar lower electrodes is formed on each of the second regions; and A conformal capacitor dielectric layer, a conformal second metal layer and a second polysilicon layer are sequentially formed in the first capacitor space, the second capacitor space and the third capacitor space, wherein the second metal layer and the second polysilicon layer constitute an upper electrode.如申請專利範圍第10項所述之具有柱狀下電極的記憶體結構的製造方法，其中第一光刻製程包含： 形成一具有孔洞圖案的光阻； 以該光阻為蝕刻遮罩進行乾蝕刻製程移除露出的該頂部支撐層、該第二塑形層、該中間支撐層、該第一塑形層以及該蝕刻停止層，如此形成該些孔洞。The manufacturing method of the memory structure with a columnar lower electrode as described in item 10 of the patent application scope, wherein the first photolithography process comprises: forming a photoresist with a hole pattern; performing a dry etching process using the photoresist as an etching mask to remove the exposed top support layer, the second shaping layer, the middle support layer, the first shaping layer and the etching stop layer, thereby forming the holes.如申請專利範圍第10項所述之具有柱狀下電極的記憶體結構的製造方法，其中第二光刻製程包含： 形成一具有該第一區域圖案的光阻； 以該光阻為蝕刻遮罩進行乾蝕刻製程移除露出的該第一多晶矽層、該第一金屬層以及該頂部支撐層，如此露出該第一區域上方的該第二塑形層。The manufacturing method of the memory structure with a columnar lower electrode as described in item 10 of the patent application scope, wherein the second photolithography process comprises: forming a photoresist having the first region pattern; performing a dry etching process using the photoresist as an etching mask to remove the exposed first polysilicon layer, the first metal layer and the top support layer, thereby exposing the second shaping layer above the first region.如申請專利範圍第10項所述之具有柱狀下電極的記憶體結構的製造方法，其中移除位於該第二區域上方的該頂部支撐層的頂面上的該第一多晶矽層以及該第一金屬層的步驟包含進行一回蝕刻製程。The method for manufacturing a memory structure with a columnar lower electrode as described in claim 10, wherein the step of removing the first polysilicon layer and the first metal layer on the top surface of the top support layer above the second region includes performing a back etching process.如申請專利範圍第10項所述之具有柱狀下電極的記憶體結構的製造方法，其中移除該第二塑形層的步驟包含進行一浸蝕製程。In the method for manufacturing a memory structure with a pillar-shaped bottom electrode as described in claim 10, the step of removing the second shaping layer includes performing an immersion etching process.如申請專利範圍第10項所述之具有柱狀下電極的記憶體結構的製造方法，其中移除該第一區域上方的該中間支撐層的步驟包含進行一回蝕刻製程。In the method for manufacturing a memory structure with a pillar-shaped lower electrode as described in claim 10, the step of removing the intermediate supporting layer above the first region includes performing an etching process.如申請專利範圍第10項所述之具有柱狀下電極的記憶體結構的製造方法，其中移除該第一塑形層的步驟包含進行一浸蝕製程。In the method for manufacturing a memory structure with a pillar-shaped lower electrode as described in claim 10, the step of removing the first shaping layer includes performing an immersion etching process.

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