TWI866252B - Electronic device - Google Patents

Abstract

An electronic device including a substrate and a plurality of control units is provided. The plurality of control units are disposed on the substrate, wherein each control units includes a transistor, an insulating layer, a first conductive layer, and a second conductive layer. The transistor includes a first electrode. The insulating layer is disposed on the transistor and has a through hole exposing the first electrode. The first conductive layer is disposed on the transistor, wherein a portion of the first conductive layer overlaps with the insulating layer, and other portion of the first conductive layer is electrically connected to the first electrode through the through hole. The second conductive layer partially overlaps with the first conductive layer at least and directly contacts the first conductive layer.

Description

Translated fromChinese

電子裝置Electronic devices

本發明是有關於一種電子裝置，且特別是有關於一種包括畫素電極的電子裝置。The present invention relates to an electronic device, and in particular to an electronic device including a pixel electrode.

現有的電子裝置中的畫素電極通過貫穿絕緣層的通孔與晶體管的電極電性連接。然而，若畫素電極的厚度太小，則設置於絕緣層的通孔中的畫素電極容易因地形因素而斷裂，使電子裝置的良率下降。相對地，若畫素電極的厚度太大，則會使電子裝置的穿透率下降。The pixel electrode in the existing electronic device is electrically connected to the electrode of the transistor through a through hole penetrating the insulating layer. However, if the thickness of the pixel electrode is too small, the pixel electrode disposed in the through hole of the insulating layer is easily broken due to topographic factors, which reduces the yield of the electronic device. Conversely, if the thickness of the pixel electrode is too large, the transmittance of the electronic device will be reduced.

本揭露的一些實施例是針對一種電子裝置，其具有的穿透率以及良率可提升。Some embodiments of the present disclosure are directed to an electronic device having improved transmittance and yield.

根據本揭露的一些實施例提供的電子裝置，其包括基板以及複數個控制單元。複數個控制單元設置於基板上，其中複數個控制單元的每一者包括晶體管、絕緣層、第一導電層以及第二導電層。晶體管包括第一電極。絕緣層設置於晶體管上，且具有通孔暴露第一電極。第一導電層設置於晶體管上，其中第一導電層的一部份與絕緣層重疊，且第一導電層的另一部分通過通孔電連接第一電極。第二導電層與第一導電層至少部分重疊，且直接接觸第一導電層。According to some embodiments of the present disclosure, an electronic device is provided, which includes a substrate and a plurality of control units. The plurality of control units are arranged on the substrate, wherein each of the plurality of control units includes a transistor, an insulating layer, a first conductive layer and a second conductive layer. The transistor includes a first electrode. The insulating layer is arranged on the transistor and has a through hole exposing the first electrode. The first conductive layer is arranged on the transistor, wherein a portion of the first conductive layer overlaps with the insulating layer, and another portion of the first conductive layer is electrically connected to the first electrode through the through hole. The second conductive layer overlaps with the first conductive layer at least partially and directly contacts the first conductive layer.

為讓本揭露的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合附圖作詳細說明如下。In order to make the above features and advantages of the present disclosure more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings.

現將詳細地參考本發明的示範性實施例，示範性實施例的實例說明於附圖中。只要有可能，相同元件符號在圖式和描述中用來表示相同或相似部分。Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and description to represent the same or like parts.

透過參考以下的詳細描述並同時結合附圖可以理解本揭露，須注意的是，為了使讀者能容易瞭解及圖式的簡潔，本揭露中的多張圖式只繪出電子裝置的一部分，且圖式中的特定元件並非依照實際比例繪圖。此外，圖中各元件的數量及尺寸僅作為示意，並非用來限制本揭露的範圍。The present disclosure can be understood by referring to the following detailed description and the accompanying drawings. It should be noted that in order to facilitate the reader's understanding and the simplicity of the drawings, the multiple drawings in the present disclosure only depict a portion of the electronic device, and the specific components in the drawings are not drawn according to the actual scale. In addition, the number and size of each component in the figure are only for illustration and are not used to limit the scope of the present disclosure.

本揭露通篇說明書與後附的申請專利範圍中會使用某些詞彙來指稱特定元件。本領域技術人員應理解，電子裝置製造商可能會以不同的名稱來指稱相同的元件。本文並不意在區分那些功能相同但名稱不同的元件。在下文說明書與申請專利範圍中，「包括」、「含有」、「具有」等詞為開放式詞語，因此其應被解釋為「含有但不限定為…」之意。因此，當本揭露的描述中使用術語「包括」、「含有」及/或「具有」時，其指定了相應的特徵、區域、步驟、操作及/或構件的存在，但不排除一個或多個相應的特徵、區域、步驟、操作及/或構件的存在。Certain terms are used throughout this disclosure and in the patent applications that follow to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may refer to the same component by different names. This document is not intended to distinguish between components that have the same function but different names. In the following description and patent applications, the words "include", "contain", "have" and the like are open-ended terms, and therefore should be interpreted as "including but not limited to..." Therefore, when the terms "include", "contain" and/or "have" are used in the description of this disclosure, they specify the existence of corresponding features, regions, steps, operations and/or components, but do not exclude the existence of one or more corresponding features, regions, steps, operations and/or components.

本文中所提到的方向用語，例如：「上」、「下」、「前」、「後」、「左」、「右」等，僅是參考附圖的方向。因此，使用的方向用語是用來說明，而並非用來限制本揭露。在附圖中，各圖式繪示的是特定實施例中所使用的方法、結構及/或材料的通常性特徵。然而，這些圖式不應被解釋為界定或限制由這些實施例所涵蓋的範圍或性質。舉例來說，為了清楚起見，各膜層、區域及/或結構的相對尺寸、厚度及位置可能縮小或放大。The directional terms mentioned herein, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are used to illustrate, but not to limit the present disclosure. In the accompanying drawings, each diagram depicts the general characteristics of the methods, structures and/or materials used in a particular embodiment. However, these diagrams should not be interpreted as defining or limiting the scope or nature covered by these embodiments. For example, for the sake of clarity, the relative size, thickness and position of each film layer, region and/or structure may be reduced or exaggerated.

當相應的構件（例如膜層或區域）被稱為「在另一個構件上」時，它可以直接在另一個構件上，或者兩者之間可存在有其他構件。另一方面，當構件被稱為「直接在另一個構件上」時，除非說明書中另有額外說明，則兩者之間不存在任何構件。另外，當一構件被稱為「在另一個構件上」時，兩者在俯視方向上有上下關係，而此構件可在另一個構件的上方或下方，而此上下關係取決於裝置的取向（orientation）。When a corresponding component (such as a film layer or region) is referred to as being "on another component", it may be directly on the other component, or other components may exist between the two. On the other hand, when a component is referred to as being "directly on another component", there is no component between the two unless otherwise specified in the specification. In addition, when a component is referred to as being "on another component", the two have a top-down relationship in a top-down direction, and the component may be above or below the other component, and the top-down relationship depends on the orientation of the device.

術語「等於」或「相同」、「實質上」或「大致上」一般解釋為在所給定的值的20%以內，或解釋為在所給定的值的10%、5%、3%、2%、1%或0.5%以內的範圍。The terms "equal to" or "same as", "substantially" or "substantially" are generally interpreted as being within 20% of a given value, or as being within a range of 10%, 5%, 3%, 2%, 1% or 0.5% of a given value.

說明書與申請專利範圍中所使用的序數例如「第一」、「第二」等之用詞用以修飾元件，其本身並不意含及代表該（或該些）元件有任何之前的序數，也不代表某一元件與另一元件的順序、或是製造方法上的順序，該些序數的使用僅用來使具有某命名的元件得以和另一具有相同命名的元件能作出清楚區分。申請專利範圍與說明書中可不使用相同用詞，據此，說明書中的第一構件在申請專利範圍中可能為第二構件。The ordinal numbers used in the specification and patent application, such as "first", "second", etc., are used to modify the components. They do not imply or represent any previous ordinal number of the component (or components), nor do they represent the order of one component to another component, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a component with a certain name clearly distinguishable from another component with the same name. The patent application and the specification may not use the same words. Accordingly, the first component in the specification may be the second component in the patent application.

須知悉的是，以下所舉實施例可以在不脫離本揭露的精神下，可將數個不同實施例中的特徵進行替換、重組、混合以完成其他實施例。各實施例間特徵只要不違背發明精神或相衝突，均可任意混合搭配使用。It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. The features of each embodiment can be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.

本揭露中所敘述之電性連接或電連接，皆可以指直接連接或間接連接，於直接連接的情況下，兩電路上元件的端點直接連接或以一導體線段互相連接，而於間接連接的情況下，兩電路上元件的端點之間具有開關、二極體、電容、電感、其他適合的元件，或上述元件的組合，但不限於此。The electrical connection or electrical connection described in this disclosure may refer to direct connection or indirect connection. In the case of direct connection, the end points of the components on the two circuits are directly connected or connected to each other by a conductor segment, and in the case of indirect connection, there are switches, diodes, capacitors, inductors, other suitable components, or combinations of the above components between the end points of the components on the two circuits, but not limited to these.

在本揭露中，厚度、長度、寬度與面積的量測方式可以是採用光學顯微鏡量測而得，厚度則可以由電子顯微鏡中的剖面影像量測而得，但不以此為限。另外，任兩個用來比較的數值或方向，可存在著一定的誤差。若第一值等於第二值，其隱含著第一值與第二值之間可存在著約10%的誤差；若第一方向垂直於第二方向，則第一方向與第二方向之間的角度可介於80度至100度之間；若第一方向平行於第二方向，則第一方向與第二方向之間的角度可介於0度至10度之間。In the present disclosure, the thickness, length, width and area can be measured by an optical microscope, and the thickness can be measured by a cross-sectional image in an electron microscope, but it is not limited to this. In addition, any two values or directions used for comparison may have a certain error. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

本揭露的電子裝置可為非自發光型顯示裝置或自發光型顯示裝置，且可為一種雙面顯示裝置。顯示裝置可例如包括二極體、液晶（liquid crystal）、發光二極體（light emitting diode，LED）、量子點（quantum dot，QD）、螢光（fluorescence）、磷光（phosphor）、其他適合之顯示介質或上述之組合。發光二極體可例如包括有機發光二極體（organic light emitting diode，OLED）、次毫米發光二極體（mini LED）、微型發光二極體（micro-LED）或量子點發光二極體（QDLED），但不以此為限。需注意的是，顯示裝置可為前述之任意排列組合，但不以此為限。此外，顯示裝置的外型可為矩形、圓形、多邊形、具有彎曲邊緣的形狀或其他適合的形狀。顯示裝置可以具有驅動系統、控制系統、光源系統等周邊系統。The electronic device disclosed herein may be a non-self-luminous display device or a self-luminous display device, and may be a double-sided display device. The display device may, for example, include a diode, a liquid crystal, a light emitting diode (LED), a quantum dot (QD), fluorescence, phosphor, other suitable display media, or a combination thereof. The light emitting diode may, for example, include an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro-light emitting diode (micro-LED), or a quantum dot light emitting diode (QDLED), but is not limited thereto. It should be noted that the display device may be any combination of the aforementioned arrangements, but is not limited thereto. In addition, the display device may be rectangular, circular, polygonal, have curved edges or other suitable shapes. The display device may have peripheral systems such as a drive system, a control system, and a light source system.

圖1為本揭露的一實施例的電子裝置的製作方法的流程圖，圖2為本揭露的一實施例的電子裝置的局部剖面示意圖，且圖3A為本揭露的一實施例的電子裝置的局部俯視示意圖。FIG. 1 is a flow chart of a method for manufacturing an electronic device according to an embodiment of the present disclosure, FIG. 2 is a partial cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure, and FIG. 3A is a partial top view schematic diagram of an electronic device according to an embodiment of the present disclosure.

以下將介紹本實施例的電子裝置10的製作方法，但須說明本揭露的電子裝置的製作方法並不以此為限。The following will introduce the manufacturing method of theelectronic device 10 of this embodiment, but it should be noted that the manufacturing method of the electronic device disclosed in this disclosure is not limited to this.

請同時參照圖1、圖2以及圖3A，在步驟S10中，形成晶體管DC於基板SB上。Please refer to FIG. 1 , FIG. 2 and FIG. 3A simultaneously. In step S10 , a transistor DC is formed on a substrate SB.

基板SB可例如包括可撓基板或不可撓基板，其中基板SB的材料可例如包括玻璃、塑膠或其組合。舉例而言，基板SB可包括石英、藍寶石（sapphire）、聚甲基丙烯酸甲酯（polymethyl methacrylate，PMMA）、聚碳酸酯（polycarbonate，PC）、聚醯亞胺（polyimide，PI）、聚對苯二甲酸乙二酯（polyethylene terephthalate，PET）或其他適合的材料或上述材料的組合。在本實施例中，基板SB的材料為玻璃，但本揭露不以此為限。The substrate SB may include, for example, a flexible substrate or a non-flexible substrate, wherein the material of the substrate SB may include, for example, glass, plastic, or a combination thereof. For example, the substrate SB may include quartz, sapphire, polymethyl methacrylate (PMMA), polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), or other suitable materials or a combination of the above materials. In the present embodiment, the material of the substrate SB is glass, but the present disclosure is not limited thereto.

在一些實施例中，可通過進行以下步驟以形成晶體管DC於基板SB上，但本揭露不以此為限。In some embodiments, the transistor DC may be formed on the substrate SB by performing the following steps, but the present disclosure is not limited thereto.

步驟(1)：形成遮光層BL於基板SB上。遮光層BL的形成方法可例如是通過先利用物理氣相沉積法或者其餘合適的製程形成遮光材料層（未示出）於基板SB上之後，再對此遮光材料層進行圖案化製程，本揭露不以此為限。遮光層BL可例如在基板SB的法線方向n上與後續將介紹的晶體管DC的半導體層SE的通道區CH至少部分重疊，藉此可減少半導體層SE的通道區CH因受外界的環境光照射而受影響劣化的情況。在一些實施例中，遮光層BL的材料可包括穿透率低於30%的材料，但本揭露不以此為限。Step (1): forming a light shielding layer BL on the substrate SB. The light shielding layer BL may be formed, for example, by first forming a light shielding material layer (not shown) on the substrate SB using a physical vapor deposition method or other suitable processes, and then performing a patterning process on the light shielding material layer, but the present disclosure is not limited thereto. The light shielding layer BL may, for example, at least partially overlap with the channel region CH of the semiconductor layer SE of the transistor DC to be introduced later in the normal direction n of the substrate SB, thereby reducing the degradation of the channel region CH of the semiconductor layer SE due to exposure to external ambient light. In some embodiments, the material of the light shielding layer BL may include a material with a transmittance lower than 30%, but the present disclosure is not limited thereto.

步驟(2)：形成緩衝層BF於基板SB上，其中緩衝層BF可覆蓋遮光層BL。緩衝層BF的形成方法可例如是利用化學氣相沉積法或者其餘合適的製程形成於基板SB上，本揭露不以此為限。緩衝層BF可例如具有與後續形成於其上的膜層相對好的結合性，但本揭露不以此為限。緩衝層BF的材料可例如為無機材料（例如：氧化矽、氮化矽、氮氧化矽或上述至少二種材料的堆疊層），緩衝層BF可例如為單層結構或多層結構。在本實施例中，緩衝層BF包括由緩衝子層BF1與緩衝子層BF2依序層疊的多層結構，其中緩衝子層BF1的材料包括氮化矽，且緩衝子層BF2的材料包括氧化矽，但本揭露不以此為限。在一些實施例中，緩衝子層BF1與緩衝子層BF2的材料可以互換。Step (2): forming a buffer layer BF on the substrate SB, wherein the buffer layer BF may cover the light shielding layer BL. The buffer layer BF may be formed on the substrate SB by chemical vapor deposition or other suitable processes, but the present disclosure is not limited thereto. The buffer layer BF may have, for example, relatively good adhesion to a film layer subsequently formed thereon, but the present disclosure is not limited thereto. The material of the buffer layer BF may be, for example, an inorganic material (for example: silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), and the buffer layer BF may be, for example, a single-layer structure or a multi-layer structure. In the present embodiment, the buffer layer BF comprises a multi-layer structure in which a buffer sub-layer BF1 and a buffer sub-layer BF2 are sequentially stacked, wherein the material of the buffer sub-layer BF1 comprises silicon nitride, and the material of the buffer sub-layer BF2 comprises silicon oxide, but the present disclosure is not limited thereto. In some embodiments, the materials of the buffer sub-layer BF1 and the buffer sub-layer BF2 can be interchangeable.

步驟(3)：形成半導體層SE於緩衝層BF上。半導體層SE的形成方法可例如通過先利用化學氣相沉積法或者其餘合適的製程形成半導體材料層（未示出）於緩衝層BF上之後，再對此半導體材料層進行圖案化製程，但本揭露不以此為限。在一些實施例中，半導體層SE具有通道區CH以及位於通道區CH相對側的源極區SR與汲極區DR，其中通道區CH與後續將提及的閘極G在基板SB的法線方向n上至少部分地重疊，且源極區SR與汲極區DR可各自與後續將提及的源極S與汲極D電性連接。在本實施例中，晶體管DC為一種雙閘極型薄膜晶體管，因此，通道區CH可包括有通道區CH1以及通道區CH2，其各自在基板SB的法線方向n上與後續將介紹的閘極G中的閘極G1以及閘極G2重疊，但本揭露不以此為限。Step (3): forming a semiconductor layer SE on the buffer layer BF. The semiconductor layer SE may be formed by, for example, first forming a semiconductor material layer (not shown) on the buffer layer BF by chemical vapor deposition or other suitable processes, and then performing a patterning process on the semiconductor material layer, but the present disclosure is not limited thereto. In some embodiments, the semiconductor layer SE has a channel region CH and a source region SR and a drain region DR located on opposite sides of the channel region CH, wherein the channel region CH and a gate G to be mentioned later at least partially overlap in the normal direction n of the substrate SB, and the source region SR and the drain region DR may be electrically connected to a source S and a drain D to be mentioned later, respectively. In this embodiment, the transistor DC is a dual-gate thin film transistor, and therefore, the channel region CH may include a channel region CH1 and a channel region CH2, each of which overlaps with the gate G1 and the gate G2 in the gate G to be introduced later in the normal direction n of the substrate SB, but the present disclosure is not limited to this.

半導體層SE的材料可例如包括低溫多晶矽（low temperature polysilicon，LTPS）、金屬氧化物（metal oxide）、非晶矽（amorphous silicon，a-Si）或其組合，但本揭露不以此為限。舉例而言，半導體層SE的材料可包含但不限於非晶矽、多晶矽、鍺、化合物半導體（例如氮化鎵、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦和/或銻化銦）、合金半導體（例如SiGe合金、GaAsP合金、AlInAs合金、AlGaAs合金、GaInAs合金、GaInP合金、GaInAsP合金）、金屬氧化物(例如銦鎵鋅氧化物（IGZO）、銦鋅氧化物（IZO）、銦鎵鋅氧化物（IGZTO）)、或包含多環芳香族化合物的有機半導體，或前述之組合。在本實施例中，半導體層SE的材料為低溫多晶矽，但本揭露不以此為限。The material of the semiconductor layer SE may include, for example, low temperature polysilicon (LTPS), metal oxide (metal oxide), amorphous silicon (a-Si) or a combination thereof, but the present disclosure is not limited thereto. For example, the material of the semiconductor layer SE may include but is not limited to amorphous silicon, polycrystalline silicon, germanium, compound semiconductors (such as gallium nitride, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium uranide), alloy semiconductors (such as SiGe alloys, GaAsP alloys, AlInAs alloys, AlGaAs alloys, GaInAs alloys, GaInP alloys, GaInAsP alloys), metal oxides (such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZTO)), or organic semiconductors containing polycyclic aromatic compounds, or a combination thereof. In the present embodiment, the material of the semiconductor layer SE is low-temperature polycrystalline silicon, but the present disclosure is not limited thereto.

步驟(4)：形成閘絕緣層GI、第一金屬層M1以及絕緣層ILD於緩衝層BF上，其中閘絕緣層GI例如設置於緩衝層BF上，第一金屬層M1例如包括閘極G並例如設置於閘絕緣層GI上，且絕緣層ILD例如設置於閘絕緣層GI上並例如覆蓋閘極G。Step (4): forming a gate insulation layer GI, a first metal layer M1 and an insulation layer ILD on the buffer layer BF, wherein the gate insulation layer GI is, for example, disposed on the buffer layer BF, the first metal layer M1 includes, for example, a gate G and is, for example, disposed on the gate insulation layer GI, and the insulation layer ILD is, for example, disposed on the gate insulation layer GI and, for example, covers the gate G.

在一些實施例中，閘絕緣層GI具有通孔GI_V1以及通孔GI_V2，絕緣層ILD具有通孔ILD_V1以及通孔ILD_V2，通孔GI_V1可與通孔ILD_V1連通為通孔VD並一起暴露出半導體層SE的汲極區DR，且通孔GI_V2與通孔ILD_V2連通為通孔VS並一起暴露出半導體層SE的源極區SR。In some embodiments, the gate insulation layer GI has a through hole GI_V1 and a through hole GI_V2, the insulation layer ILD has a through hole ILD_V1 and a through hole ILD_V2, the through hole GI_V1 can be connected with the through hole ILD_V1 to form a through hole VD and together expose the drain region DR of the semiconductor layer SE, and the through hole GI_V2 is connected with the through hole ILD_V2 to form a through hole VS and together expose the source region SR of the semiconductor layer SE.

閘絕緣層GI的形成方法可例如通過先利用化學氣相沉積法或者其餘合適的製程形成閘絕緣材料層（未示出）於緩衝層BF上之後，再對此閘絕緣材料層進行圖案化製程以形成通孔GI_V1以及通孔GI_V2，但本揭露不以此為限。閘絕緣層GI的材料可例如為無機材料（例如：氧化矽、氮化矽、氮氧化矽或上述至少二種材料的堆疊層）。在本實施例中，閘絕緣層GI為包括氧化矽的單層結構，但本揭露不以此為限。值得說明的是，上述的半導體層SE的通道區CH可在形成閘絕緣層GI之後對半導體材料層進行摻雜例如磷(P)、硼(B)等元素的離子而形成，且在半導體層SE的各位置的離子濃度可能不同。但本揭露不以此為限。The gate insulating layer GI may be formed by, for example, first forming a gate insulating material layer (not shown) on the buffer layer BF by chemical vapor deposition or other suitable processes, and then patterning the gate insulating material layer to form the through hole GI_V1 and the through hole GI_V2, but the present disclosure is not limited thereto. The material of the gate insulating layer GI may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials). In the present embodiment, the gate insulating layer GI is a single-layer structure including silicon oxide, but the present disclosure is not limited thereto. It is worth noting that the channel region CH of the semiconductor layer SE can be formed by doping the semiconductor material layer with ions of elements such as phosphorus (P) and boron (B) after forming the gate insulating layer GI, and the ion concentration at each position of the semiconductor layer SE may be different. However, the present disclosure is not limited thereto.

第一金屬層M1的形成方法可例如通過先利用物理氣相沉積法、金屬化學氣相沉積法或者其餘合適的製程形成第一金屬材料層（未示出）於閘絕緣層GI上之後，再對此第一金屬材料層進行圖案化製程，但本揭露不以此為限。在本實施例中，晶體管DC為一種雙閘極型薄膜晶體管，因此，第一金屬層M1包括彼此分離的閘極G1以及閘極G2，但本揭露不以此為限。在本實施例中，如圖3A所示出，第一金屬層M1還包括閘極線GL，其中閘極線GL朝第一方向d1延伸，且與閘極G1以及閘極G2電性連接，以將來自例如閘極驅動器（未示出）的訊號傳遞至晶體管DC，但本揭露不以此為限。上述的第一方向d1例如與基板SB的法線方向n正交，但本揭露不以此為限。第一金屬層M1的材料可例如包括合適的導電材料，本揭露不以此為限。值得說明的是，上述的半導體層SE的源極區SR與汲極區DR可在形成第一金屬層M1之後利用第一金屬層M1為罩幕以對半導體材料層進行摻雜而形成，但本揭露不以此為限。The first metal layer M1 may be formed by, for example, first forming a first metal material layer (not shown) on the gate insulating layer GI by physical vapor deposition, metal chemical vapor deposition or other suitable processes, and then performing a patterning process on the first metal material layer, but the present disclosure is not limited thereto. In the present embodiment, the transistor DC is a dual-gate thin film transistor, and therefore, the first metal layer M1 includes a gate G1 and a gate G2 separated from each other, but the present disclosure is not limited thereto. In the present embodiment, as shown in FIG. 3A , the first metal layer M1 further includes a gate line GL, wherein the gate line GL extends in a first direction d1 and is electrically connected to the gate G1 and the gate G2 to transmit a signal from, for example, a gate driver (not shown) to the transistor DC, but the present disclosure is not limited thereto. The first direction d1 mentioned above is, for example, orthogonal to the normal direction n of the substrate SB, but the present disclosure is not limited thereto. The material of the first metal layer M1 may, for example, include a suitable conductive material, but the present disclosure is not limited thereto. It is worth noting that the source region SR and the drain region DR of the semiconductor layer SE can be formed by doping the semiconductor material layer using the first metal layer M1 as a mask after forming the first metal layer M1, but the present disclosure is not limited thereto.

絕緣層ILD的形成方法可例如通過先利用化學氣相沉積法或者其餘合適的製程形成絕緣材料層（未示出）於閘絕緣層GI上之後，再對此絕緣材料層進行圖案化製程以形成通孔ILD_V1以及通孔ILD_V2，其中通孔ILD_V1以及通孔ILD_V2可各自與通孔GI_V1以及通孔GI_V2在同一個圖案化製程形成，但本揭露不以此為限。絕緣層ILD的材料可例如為無機材料（例如：氧化矽、氮化矽、氮氧化矽或上述至少二種材料的堆疊層），且絕緣層ILD可為單層結構或多層結構。在本實施例中，絕緣層ILD包括由絕緣子層ILD1與絕緣子層ILD2依序層疊的多層結構，其中絕緣子層ILD1的材料與絕緣子層ILD2的材料皆包括氮化矽，但本揭露不以此為限。在一些實施例中，絕緣層ILD的材料也可為有機材料。The insulating layer ILD may be formed by, for example, first forming an insulating material layer (not shown) on the gate insulating layer GI by chemical vapor deposition or other suitable processes, and then performing a patterning process on the insulating material layer to form the through hole ILD_V1 and the through hole ILD_V2, wherein the through hole ILD_V1 and the through hole ILD_V2 may be formed in the same patterning process as the through hole GI_V1 and the through hole GI_V2, but the present disclosure is not limited thereto. The material of the insulating layer ILD may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), and the insulating layer ILD may be a single-layer structure or a multi-layer structure. In this embodiment, the insulating layer ILD includes a multi-layer structure of insulating sub-layers ILD1 and ILD2 stacked in sequence, wherein the material of the insulating sub-layer ILD1 and the material of the insulating sub-layer ILD2 both include silicon nitride, but the present disclosure is not limited thereto. In some embodiments, the material of the insulating layer ILD may also be an organic material.

步驟(5)：形成第二金屬層M2於絕緣層ILD上。第二金屬層M2的形成方法可例如通過先利用物理氣相沉積法、金屬化學氣相沉積法或者其餘合適的製程形成第二金屬材料層（未示出）於絕緣層ILD上之後，再對此第二金屬材料層進行圖案化製程，但本揭露不以此為限。在本實施例中，第二金屬層M2包括源極S、汲極D、資料線DL及/或觸控訊號線TL，但本揭露不以此為限。源極S與汲極D例如彼此分離，其中源極S可例如通過通孔VS與半導體層SE的源極區SR電性連接，且汲極D可例如通過通孔VD與半導體層SE的汲極區DR電性連接。如圖3A所示出，資料線DL例如朝第二方向d2延伸，且例如與源極S電性連接，以將來自例如源極驅動器（未示出）的訊號傳遞至晶體管DC，但本揭露不以此為限。觸控訊號線TL亦例如朝第二方向d2延伸，且例如與後續將介紹的共用電極CE電性連接，以將來自共用電極CE的訊號傳遞至外部的訊號處理電路（未示出），但本揭露不以此為限。上述的第二方向d2例如與第一方向d1以及基板SB的法線方向n正交，但本揭露不以此為限。第二金屬層M2的材料可例如包括合適的導電材料，本揭露不以此為限。Step (5): forming a second metal layer M2 on the insulating layer ILD. The second metal layer M2 may be formed by, for example, first forming a second metal material layer (not shown) on the insulating layer ILD by physical vapor deposition, metal chemical vapor deposition or other suitable processes, and then performing a patterning process on the second metal material layer, but the present disclosure is not limited thereto. In the present embodiment, the second metal layer M2 includes a source S, a drain D, a data line DL and/or a touch signal line TL, but the present disclosure is not limited thereto. The source S and the drain D are, for example, separated from each other, wherein the source S may be, for example, electrically connected to the source region SR of the semiconductor layer SE through a through hole VS, and the drain D may be, for example, electrically connected to the drain region DR of the semiconductor layer SE through a through hole VD. As shown in FIG. 3A , the data line DL, for example, extends in the second direction d2, and is, for example, electrically connected to the source S to transmit a signal from, for example, a source driver (not shown) to the transistor DC, but the present disclosure is not limited thereto. The touch signal line TL also, for example, extends in the second direction d2, and is, for example, electrically connected to a common electrode CE to be described later, to transmit a signal from the common electrode CE to an external signal processing circuit (not shown), but the present disclosure is not limited thereto. The second direction d2 is, for example, orthogonal to the first direction d1 and the normal direction n of the substrate SB, but the disclosure is not limited thereto. The material of the second metal layer M2 may include, for example, a suitable conductive material, but the disclosure is not limited thereto.

至此，完成本實施例的晶體管DC的製作，但本揭露不以此為限。詳細地說，上述的半導體層SE、閘極G、源極S以及汲極D可組成晶體管DC。值得說明的是，本實施例雖示出晶體管DC為本領域技術人員所周知的任一種頂部閘極型薄膜電晶體，但本揭露不以此為限。At this point, the manufacturing of the transistor DC of this embodiment is completed, but the present disclosure is not limited thereto. Specifically, the semiconductor layer SE, the gate G, the source S and the drain D can form the transistor DC. It is worth noting that although the present embodiment shows that the transistor DC is any top gate type thin film transistor known to those skilled in the art, the present disclosure is not limited thereto.

請繼續參照圖1、圖2以及圖3A，在步驟S20中，形成平坦層PL於晶體管DC上，其中平坦層PL具有暴露出部分的晶體管DC的汲極D的通孔PL_V1。在一些實施例中，平坦層PL還具有通孔PL_V2，其中通孔PL_V2暴露出部分的觸控訊號線TL。從另一個角度來看，平坦層PL例如具有側壁PL_S1以及側壁PL_S2，其中側壁PL_S1以及側壁PL_S2可例如各自定義出通孔PL_V1與通孔PL_V2的輪廓。Please continue to refer to FIG. 1 , FIG. 2 and FIG. 3A . In step S20 , a planar layer PL is formed on the transistor DC, wherein the planar layer PL has a through hole PL_V1 exposing a portion of the drain D of the transistor DC. In some embodiments, the planar layer PL also has a through hole PL_V2, wherein the through hole PL_V2 exposes a portion of the touch signal line TL. From another perspective, the planar layer PL, for example, has a side wall PL_S1 and a side wall PL_S2, wherein the side wall PL_S1 and the side wall PL_S2 can, for example, respectively define the outlines of the through hole PL_V1 and the through hole PL_V2.

平坦層PL的形成方法可例如通過先利用化學氣相沉積法或者其餘合適的製程形成埋入平坦材料層（未示出）於絕緣層ILD上之後，再對此平坦氧化材料層進行圖案化製程以形成通孔PL_V1以及通孔PL_V2，但本揭露不以此為限。平坦層PL的材料可例如為有機材料（例如：聚醯亞胺系樹脂（Polyimide, PI）、環氧系樹脂（Epoxy resin）或壓克力系樹脂（acrylic resin）），但本揭露不以此為限。The planar layer PL may be formed by, for example, first forming a buried planar material layer (not shown) on the insulating layer ILD by chemical vapor deposition or other suitable processes, and then patterning the planar oxide material layer to form the through hole PL_V1 and the through hole PL_V2, but the present disclosure is not limited thereto. The material of the planar layer PL may be, for example, an organic material (e.g., polyimide (PI), epoxy resin, or acrylic resin), but the present disclosure is not limited thereto.

在一些實施例中，在形成平坦層PL於晶體管DC上之後，可形成共用電極CE於平坦層PL上。共用電極CE的形成方法可例如通過先利用物理氣相沉積法或者其餘合適的製程形成共用電極材料層（未示出）於平坦層PL上之後，再對此共用電極材料層進行圖案化製程，但本揭露不以此為限。在本實施例中，共用電極CE部分地填入平坦層PL的通孔PL_V2中以與觸控訊號線TL電性連接，但本揭露不以此為限。共用電極CE的材料可例如包括透明導電氧化物。舉例而言，共用電極CE的材料可包括氧化銦錫(indium tin oxide，ITO)、氧化銻鋅(antimony zinc oxide，AZO)、氧化錫(tin oxide，SnO)、氧化鋅(zinc oxide，ZnO)、氧化銦鋅(indium zinc oxide，IZO) 、氧化銻錫(antimony tin oxide，ATO)、氧化錫摻氟(fluorine doped tin oxide，FTO)、其它合適的透明導電材料或前述之任意組合，但本揭露不以此為限。In some embodiments, after forming a planar layer PL on the transistor DC, a common electrode CE may be formed on the planar layer PL. The common electrode CE may be formed by, for example, first forming a common electrode material layer (not shown) on the planar layer PL by physical vapor deposition or other suitable processes, and then patterning the common electrode material layer, but the present disclosure is not limited thereto. In the present embodiment, the common electrode CE is partially filled into the through hole PL_V2 of the planar layer PL to be electrically connected to the touch signal line TL, but the present disclosure is not limited thereto. The material of the common electrode CE may, for example, include a transparent conductive oxide. For example, the material of the common electrode CE may include indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), antimony tin oxide (ATO), fluorine doped tin oxide (FTO), other suitable transparent conductive materials or any combination thereof, but the present disclosure is not limited thereto.

請繼續參照圖1、圖2以及圖3A，在步驟S30中，形成絕緣層PV於平坦層PL上，其中絕緣層PV具有通孔PV_V，且絕緣層PV的通孔PV_V在基板SB的法線方向n上與平坦層PL的通孔PL_V1重疊。詳細地說，絕緣層PV可例如部分地填入平坦層PL的通孔PL_V1中並設置於平坦層PL的側壁PL_S1上，且可例如部分地覆蓋被平坦層PL的通孔PL_V1暴露的汲極D，使得絕緣層PV的通孔PV_V與平坦層PL的通孔PL_V1可一起暴露出部分的汲極D。Please continue to refer to FIG. 1 , FIG. 2 and FIG. 3A , in step S30 , an insulating layer PV is formed on the planar layer PL, wherein the insulating layer PV has a through hole PV_V, and the through hole PV_V of the insulating layer PV overlaps with the through hole PL_V1 of the planar layer PL in the normal direction n of the substrate SB. Specifically, the insulating layer PV may, for example, partially fill the through hole PL_V1 of the planar layer PL and be disposed on the side wall PL_S1 of the planar layer PL, and may, for example, partially cover the drain electrode D exposed by the through hole PL_V1 of the planar layer PL, so that the through hole PV_V of the insulating layer PV and the through hole PL_V1 of the planar layer PL may expose part of the drain electrode D together.

在一些實施例中，絕緣層PV還可填入平坦層PL的通孔PL_V2中並設置於平坦層PL的側壁PL_S2上，且可覆蓋填入於平坦層PL的通孔PL_V2中的共用電極CE。In some embodiments, the insulating layer PV may also be filled in the through hole PL_V2 of the planar layer PL and disposed on the side wall PL_S2 of the planar layer PL, and may cover the common electrode CE filled in the through hole PL_V2 of the planar layer PL.

絕緣層PV的形成方法可例如通過先利用化學氣相沉積法或者其餘合適的製程形成絕緣材料層（未示出）於平坦層PL上之後，再對此絕緣材料層進行圖案化製程以形成通孔PV_V，但本揭露不以此為限。絕緣層PV的材料可例如為無機材料（例如：氧化矽、氮化矽、氮氧化矽或上述至少二種材料的堆疊層），本揭露不以此為限。The insulating layer PV may be formed by, for example, first forming an insulating material layer (not shown) on the planar layer PL by chemical vapor deposition or other suitable processes, and then performing a patterning process on the insulating material layer to form the through hole PV_V, but the present disclosure is not limited thereto. The material of the insulating layer PV may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), and the present disclosure is not limited thereto.

請繼續參照圖1、圖2以及圖3A，在步驟S40中，形成第一導電層C1於絕緣層PV上，其中第一導電層C1的一部份與絕緣層PV重疊，且第一導電層C1的另一部分通過絕緣層PV的通孔PV_V電連接晶體管DC的汲極D。詳細地說，在本實施例中，第一導電層C1部分地填入平坦層PL的通孔PL_V1以及絕緣層PV的通孔PV_V中，第一導電層C1的一部份可例如與絕緣層PV依序設置於平坦層PL的側壁PL_S1上並例如與絕緣層PV重疊，且第一導電層C1的另一部份可例如通過絕緣層PV的通孔PV_V以與汲極D電性連接。在本實施例中，第一導電層C1的厚度T1可介於50nm~70nm（50nm≦T1≦70nm）。當第一導電層C1的厚度T1介於上述範圍時，可減少設置於平坦層PL的側壁PL_S1上的第一導電層C1產生斷裂的可能性，以提高電子裝置10的良率。第一導電層C1的材料可例如包括金屬、金屬氮化物、半導體材料、透明導電氧化物、其他任何合適的導電材料或其組合。舉例而言，第一導電層C1的材料可包括金(Au)、鎳(Ni)、鉑(Pt)、鈀(Pd)、銥(Ir)、鈦(Ti)、鉻(Cr)、鎢(W)、鋁(Al)、銅(Cu)、鉬(Mo)、鈦(Ti)、銀(Ag)、鎂(Mg)、其合金或其化合物、氧化銦錫(indium tin oxide，ITO)、氧化銻鋅(antimony zinc oxide，AZO)、氧化錫(tin oxide，SnO)、氧化鋅(zinc oxide，ZnO)、氧化銦鋅(indium zinc oxide，IZO) 、氧化銻錫(antimony tin oxide，ATO)、氧化錫摻氟(fluorine doped tin oxide，FTO)、其它合適的導電材料或前述之任意組合，但本揭露不以此為限。Please continue to refer to FIG. 1 , FIG. 2 and FIG. 3A , in step S40 , a first conductive layer C1 is formed on the insulating layer PV, wherein a portion of the first conductive layer C1 overlaps the insulating layer PV, and another portion of the first conductive layer C1 is electrically connected to the drain D of the transistor DC through the through hole PV_V of the insulating layer PV. Specifically, in the present embodiment, the first conductive layer C1 partially fills the through hole PL_V1 of the planar layer PL and the through hole PV_V of the insulating layer PV, a portion of the first conductive layer C1 may be sequentially disposed on the side wall PL_S1 of the planar layer PL and overlapped with the insulating layer PV, for example, and another portion of the first conductive layer C1 may be electrically connected to the drain D through the through hole PV_V of the insulating layer PV, for example. In the present embodiment, the thickness T1 of the first conductive layer C1 may be between 50 nm and 70 nm (50 nm≦T1≦70 nm). When the thickness T1 of the first conductive layer C1 is within the above range, the possibility of the first conductive layer C1 disposed on the sidewall PL_S1 of the planar layer PL being broken can be reduced, thereby improving the yield of theelectronic device 10. The material of the first conductive layer C1 may include, for example, metal, metal nitride, semiconductor material, transparent conductive oxide, any other suitable conductive material or a combination thereof. For example, the material of the first conductive layer C1 may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), titanium (Ti), silver (Ag), magnesium (Mg), alloys or compounds thereof, indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), antimony tin oxide (ATO), fluorine doped tin oxide (fluorine doped tin oxide) or the like. oxide, FTO), other suitable conductive materials or any combination thereof, but the present disclosure is not limited thereto.

第一導電層C1的形成方法可例如通過先利用物理氣相沉積法或者其餘合適的製程形成第一導電材料層（未示出）於絕緣層PV上之後，再對此第一導電材料層進行圖案化製程，但本揭露不以此為限。The first conductive layer C1 may be formed by, for example, first forming a first conductive material layer (not shown) on the insulating layer PV using physical vapor deposition or other suitable processes, and then performing a patterning process on the first conductive material layer, but the present disclosure is not limited thereto.

請繼續參照圖1、圖2以及圖3A，在步驟S50中，形成第二導電層C2於絕緣層PV上，其中第二導電層C2與第一導電層C1至少部分重疊，且第二導電層C2直接接觸第一導電層C1。本實施例的第二導電層C2例如作為電子裝置10的畫素電極使用，但本揭露不以此為限。在本實施例中，第二導電層C2與未設置於平坦層PL的通孔PL_V1中的第一導電層C1至少部分重疊，且與未設置於平坦層PL的通孔PL_V1中的第一導電層C1直接接觸。基於此，第二導電層C2可通過第一導電層C1以與汲極D電性連接，使得第二導電層C2的厚度T2可因此減少。在本實施例中，第二導電層C2的厚度T2介於5nm~50nm（5nm≦T2≦50nm）。當第二導電層C2的厚度T2介於上述範圍時，可增加電子裝置10的穿透率，以提高電子裝置10的亮度。第二導電層C2的材料可例如包括透明導電氧化物。舉例而言，第二導電層C2的材料可包括氧化銦錫(indium tin oxide，ITO)、氧化銻鋅(antimony zinc oxide，AZO)、氧化錫(tin oxide，SnO)、氧化鋅(zinc oxide，ZnO)、氧化銦鋅(indium zinc oxide，IZO) 、氧化銻錫(antimony tin oxide，ATO)、氧化錫摻氟(fluorine doped tin oxide，FTO)、其它合適的透明導電材料或前述之任意組合，但本揭露不以此為限。Please continue to refer to FIG. 1, FIG. 2 and FIG. 3A. In step S50, a second conductive layer C2 is formed on the insulating layer PV, wherein the second conductive layer C2 at least partially overlaps with the first conductive layer C1, and the second conductive layer C2 directly contacts the first conductive layer C1. The second conductive layer C2 of this embodiment is used as a pixel electrode of theelectronic device 10, for example, but the present disclosure is not limited thereto. In this embodiment, the second conductive layer C2 at least partially overlaps with the first conductive layer C1 not disposed in the through hole PL_V1 of the planar layer PL, and directly contacts the first conductive layer C1 not disposed in the through hole PL_V1 of the planar layer PL. Based on this, the second conductive layer C2 can be electrically connected to the drain D through the first conductive layer C1, so that the thickness T2 of the second conductive layer C2 can be reduced. In this embodiment, the thickness T2 of the second conductive layer C2 is between 5nm and 50nm (5nm≦T2≦50nm). When the thickness T2 of the second conductive layer C2 is within the above range, the transmittance of theelectronic device 10 can be increased to improve the brightness of theelectronic device 10. The material of the second conductive layer C2 can include, for example, a transparent conductive oxide. For example, the material of the second conductive layer C2 may include indium tin oxide (ITO), antimony zinc oxide (AZO), tin oxide (SnO), zinc oxide (ZnO), indium zinc oxide (IZO), antimony tin oxide (ATO), fluorine doped tin oxide (FTO), other suitable transparent conductive materials or any combination thereof, but the present disclosure is not limited thereto.

第二導電層C2的形成方法可例如通過先利用物理氣相沉積法或者其餘合適的製程形成第二導電材料層（未示出）於絕緣層PV上之後，再對此第二導電材料層進行圖案化製程，但本揭露不以此為限。需特別說明的是，如圖2所示，由於絕緣層PV、第一導電層C1與第二導電層C2的層疊關係，在鄰近通孔PL_V1洞口的地方，第二導電層C2的頂表面高於第一導電層C1的頂表面，且第一導電層C1的頂表面高於絕緣層PV的頂表面。而因為第一導電層C1與第二導電層C2的厚度差異，在距離通孔PL_V1洞口較遠的地方，第二導電層C2的頂表面低於前述鄰近通孔PL_V1洞口的第一導電層C1的頂表面。The second conductive layer C2 may be formed by, for example, first forming a second conductive material layer (not shown) on the insulating layer PV by physical vapor deposition or other suitable processes, and then performing a patterning process on the second conductive material layer, but the present disclosure is not limited thereto. It should be particularly noted that, as shown in FIG2 , due to the stacking relationship of the insulating layer PV, the first conductive layer C1 and the second conductive layer C2, the top surface of the second conductive layer C2 is higher than the top surface of the first conductive layer C1 near the opening of the through hole PL_V1, and the top surface of the first conductive layer C1 is higher than the top surface of the insulating layer PV. Due to the difference in thickness between the first conductive layer C1 and the second conductive layer C2, at a location farther from the opening of the through hole PL_V1, the top surface of the second conductive layer C2 is lower than the top surface of the first conductive layer C1 near the opening of the through hole PL_V1.

至此，完成本實施例的電子裝置10的製作，但本揭露製作電子裝置10的方法不以此為限。At this point, the manufacturing of theelectronic device 10 of this embodiment is completed, but the method for manufacturing theelectronic device 10 disclosed in this disclosure is not limited thereto.

以下將參照圖2以及圖3A與圖3B簡要介紹本實施例的電子裝置10的構造，其中圖3B為本揭露的一實施例的電子裝置中的開口區與遮蔽區的俯視示意圖，但本揭露不以此為限。The structure of theelectronic device 10 of this embodiment will be briefly described below with reference to FIG. 2 and FIG. 3A and FIG. 3B , wherein FIG. 3B is a top view schematic diagram of an opening area and a shielding area in an electronic device of an embodiment of the present disclosure, but the present disclosure is not limited thereto.

在本實施例中，電子裝置10包括基板SB以及複數個控制單元CU。複數個控制單元CU例如設置於基板SB上，其中複數個控制單元CU的每一者例如包括晶體管DC、絕緣層PV、第一導電層C1以及第二導電層C2。晶體管DC例如包括閘極G、第一電極（汲極D）以及第二電極（源極S）。絕緣層PV例如設置於晶體管DC上，且具有通孔PV_V暴露第一電極（汲極D）。第一導電層C1例如設置於晶體管DC上，其中第一導電層C1的一部份例如與絕緣層PV重疊，且第一導電層C1的另一部分通過通孔PV_V電連接第一電極（汲極D）。第二導電層C2例如與第一導電層C1至少部分重疊，且直接接觸第一導電層C1。In this embodiment, theelectronic device 10 includes a substrate SB and a plurality of control units CU. The plurality of control units CU are, for example, disposed on the substrate SB, wherein each of the plurality of control units CU includes, for example, a transistor DC, an insulating layer PV, a first conductive layer C1, and a second conductive layer C2. The transistor DC includes, for example, a gate G, a first electrode (drain D), and a second electrode (source S). The insulating layer PV is, for example, disposed on the transistor DC and has a through hole PV_V exposing the first electrode (drain D). The first conductive layer C1 is, for example, disposed on the transistor DC, wherein a portion of the first conductive layer C1 overlaps with the insulating layer PV, and another portion of the first conductive layer C1 is electrically connected to the first electrode (drain D) through the via PV_V. The second conductive layer C2 at least partially overlaps with the first conductive layer C1 and directly contacts the first conductive layer C1.

在本實施例中，電子裝置10包括由複數條第一走線（例如閘極線GL）與複數條第二走線（例如資料線DL）定義出的多個區域10R。詳細地說，電子裝置10還可例如包括設置於基板上的複數條第一走線（例如閘極線GL）以及複數條第二走線（例如資料線DL），其中第一走線可例如沿第一方向d1延伸，第二走線可例如沿第二方向d2延伸，且第一方向d1與第二方向d2不同。In this embodiment, theelectronic device 10 includes a plurality ofregions 10R defined by a plurality of first wirings (e.g., gate lines GL) and a plurality of second wirings (e.g., data lines DL). Specifically, theelectronic device 10 may also include, for example, a plurality of first wirings (e.g., gate lines GL) and a plurality of second wirings (e.g., data lines DL) disposed on a substrate, wherein the first wirings may extend, for example, along a first direction d1, and the second wirings may extend, for example, along a second direction d2, and the first direction d1 is different from the second direction d2.

如圖3A以及圖3B所示出，本實施例的電子裝置10的複數個控制單元CU中的一者可例如位於兩條相鄰第一走線（例如閘極線GL）與兩條相鄰第二走線（例如資料線DL）所圍成的區域10R內。電子裝置10的區域10R例如可包括開口區10RO以及遮蔽區10RB，即，開口區10RO及遮蔽區10RB位於兩條相鄰第一走線（例如閘極線GL）與兩條相鄰第二走線（例如資料線DL）所所圍成的區域10R內。詳細地說，電子裝置10還可例如包括遮蔽層BM，其中遮蔽層BM例如在基板SB的法線方向n上與第一導電層C1、第一走線（例如閘極線GL）、第二走線（例如資料線DL）以及晶體管DC中的各元件重疊。遮光圖案BM的材料可例如是黑色樹脂或反射性較低的金屬材料，藉此遮蔽不欲被使用者看到的電子裝置10內部的上述走線以及元件，以提升電子裝置10的顯示效果。也就是說，在本揭露中，與遮蔽層BM在基板SB的法線方向n上重疊處可定義為遮蔽區10RB，未重疊處可定義為開口區10RO。As shown in FIG. 3A and FIG. 3B , one of the plurality of control units CU of theelectronic device 10 of the present embodiment may be, for example, located in aregion 10R surrounded by two adjacent first wirings (e.g., gate lines GL) and two adjacent second wirings (e.g., data lines DL). Theregion 10R of theelectronic device 10 may, for example, include an opening region 10RO and a shielding region 10RB, that is, the opening region 10RO and the shielding region 10RB are located in theregion 10R surrounded by two adjacent first wirings (e.g., gate lines GL) and two adjacent second wirings (e.g., data lines DL). In detail, theelectronic device 10 may further include a shielding layer BM, wherein the shielding layer BM overlaps with the first conductive layer C1, the first wiring (e.g., the gate line GL), the second wiring (e.g., the data line DL), and each component in the transistor DC in the normal direction n of the substrate SB. The material of the light shielding pattern BM may be, for example, a black resin or a metal material with low reflectivity, thereby shielding the above wiring and components inside theelectronic device 10 that are not to be seen by the user, so as to enhance the display effect of theelectronic device 10. That is, in the present disclosure, the overlapped portion with the shielding layer BM in the normal direction n of the substrate SB may be defined as a shielding area 10RB, and the non-overlapped portion may be defined as an opening area 10RO.

在本實施例中，在俯視圖（圖3B）中，遮蔽層BM所定義出的複數個開口區10RO分別暴露第二導電層C2的一部份。詳細地說，如圖3A以及圖3B所示出，部分的第二導電層C2可在基板SB的法線方向n上不與遮蔽層BM重疊。由於第二導電層C2的材料包括上述的透明導電氧化物，因此可減少影響開口區10RO的穿透率的可能性。再者，本實施例的電子裝置10中的第二導電層C2的厚度T2介於5nm~50nm，其可增加開口區10RO的穿透率，以提高電子裝置10的亮度。In the present embodiment, in the top view (FIG. 3B), the plurality of opening regions 10RO defined by the shielding layer BM expose a portion of the second conductive layer C2 respectively. Specifically, as shown in FIG. 3A and FIG. 3B, a portion of the second conductive layer C2 may not overlap with the shielding layer BM in the normal direction n of the substrate SB. Since the material of the second conductive layer C2 includes the above-mentioned transparent conductive oxide, the possibility of affecting the transmittance of the opening region 10RO can be reduced. Furthermore, the thickness T2 of the second conductive layer C2 in theelectronic device 10 of the present embodiment is between 5 nm and 50 nm, which can increase the transmittance of the opening region 10RO to improve the brightness of theelectronic device 10.

在本實施例中，在俯視圖（圖3B）中，第一導電層C1位於複數個開口區10RO的每一者之外。詳細地說，如圖3A以及圖3B所示出，第一導電層C1在基板SB的法線方向n上與遮蔽層BM重疊，即，第一導電層C1位於遮蔽區10RB中。基於此，在本實施例中，在俯視圖（圖3A）中，第二導電層C2的面積可大於第一導電層C1的面積。In the present embodiment, in the top view (FIG. 3B), the first conductive layer C1 is located outside each of the plurality of opening regions 10RO. Specifically, as shown in FIG. 3A and FIG. 3B, the first conductive layer C1 overlaps with the shielding layer BM in the normal direction n of the substrate SB, that is, the first conductive layer C1 is located in the shielding region 10RB. Based on this, in the present embodiment, in the top view (FIG. 3A), the area of the second conductive layer C2 may be larger than the area of the first conductive layer C1.

另外，第一導電層C1可被遮蔽層BM遮蔽而減少影響開口區10RO的穿透率的可能性，使得第一導電層C1的材料選擇可具有較大的彈性。詳細地說，在一些實施例中，第一導電層C1的材料與第二導電層C2的材料相同，以簡化電子裝置10的製程。在另一些實施例中，根據電子裝置10的設計，可使第一導電層C1的材料與第二導電層C2的材料不同。再者，通過使第一導電層C1被遮蔽層BM遮蔽，第一導電層C1的厚度T1可設計為具有較厚的厚度，以增加填入於平坦層PL的通孔PL_V1中的第一導電層C1的穩定性同時減少較厚的第一導電層C1對穿透率的影響。在本實施例中，第一導電層C1的厚度T1大於第二導電層C2的厚度T2，其中第一導電層C1的厚度T1介於50nm~70nm。通過使第一導電層C1的厚度T1介於上述範圍，借此可減少設置於平坦層PL的側壁PL_S1上的第一導電層C1產生斷裂的可能性，以提高電子裝置10的良率。In addition, the first conductive layer C1 can be shielded by the shielding layer BM to reduce the possibility of affecting the transmittance of the opening area 10RO, so that the material selection of the first conductive layer C1 can have greater flexibility. In detail, in some embodiments, the material of the first conductive layer C1 is the same as the material of the second conductive layer C2 to simplify the manufacturing process of theelectronic device 10. In other embodiments, according to the design of theelectronic device 10, the material of the first conductive layer C1 can be different from the material of the second conductive layer C2. Furthermore, by making the first conductive layer C1 shielded by the shielding layer BM, the thickness T1 of the first conductive layer C1 can be designed to have a thicker thickness, so as to increase the stability of the first conductive layer C1 filled in the through hole PL_V1 of the planar layer PL and reduce the influence of the thicker first conductive layer C1 on the transmittance. In the present embodiment, the thickness T1 of the first conductive layer C1 is greater than the thickness T2 of the second conductive layer C2, wherein the thickness T1 of the first conductive layer C1 is between 50nm and 70nm. By making the thickness T1 of the first conductive layer C1 within the above range, the possibility of the first conductive layer C1 disposed on the side wall PL_S1 of the planar layer PL being broken can be reduced, so as to improve the yield of theelectronic device 10.

圖4為本揭露另一實施例的電子裝置的局部剖面示意圖。須說明的是，圖4的實施例可沿用圖2的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略相同技術內容的說明。Fig. 4 is a partial cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure. It should be noted that the embodiment of Fig. 4 may use the component numbers and part of the content of the embodiment of Fig. 2, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted.

圖4的電子裝置20與前述的電子裝置10的差異在於：第二導電層C2更設置於平坦層PL的通孔PL_V1中。即，在本實施例中，第二導電層C2可更與設置於平坦層PL的通孔PL_V1中的第一導電層C1至少部分重疊，且可更與設置於平坦層PL的通孔PL_V1中的第一導電層C1直接接觸。The difference between the electronic device 20 of FIG4 and the aforementionedelectronic device 10 is that the second conductive layer C2 is further disposed in the through hole PL_V1 of the planar layer PL. That is, in this embodiment, the second conductive layer C2 may at least partially overlap with the first conductive layer C1 disposed in the through hole PL_V1 of the planar layer PL, and may directly contact with the first conductive layer C1 disposed in the through hole PL_V1 of the planar layer PL.

綜上所述，在本揭露一些實施例提供的電子裝置中，通過設置具有相對大厚度的第一導電層於絕緣層的通孔中，借此可減少設置於絕緣層的通孔中的第一導電層及/或第二導電層產生斷裂的可能性，以提高本揭露一些實施例的電子裝置的良率。另外，本揭露一些實施例的電子裝置的第二導電層與第一導電層通過直接接觸而實現電連接，且通過設置具有相對小厚度的第二導電層以及將第一導電層設置於開口區之外，其可增加本揭露一些實施例的電子裝置中的開口區的穿透率，以提高本揭露一些實施例的電子裝置的亮度。In summary, in the electronic device provided by some embodiments of the present disclosure, by disposing a first conductive layer with a relatively large thickness in the through hole of the insulating layer, the possibility of the first conductive layer and/or the second conductive layer disposed in the through hole of the insulating layer being broken can be reduced, so as to improve the yield of the electronic device of some embodiments of the present disclosure. In addition, the second conductive layer of the electronic device of some embodiments of the present disclosure is electrically connected to the first conductive layer through direct contact, and by disposing a second conductive layer with a relatively small thickness and disposing the first conductive layer outside the opening area, it can increase the transmittance of the opening area in the electronic device of some embodiments of the present disclosure, so as to improve the brightness of the electronic device of some embodiments of the present disclosure.

10、20:電子裝置10, 20: Electronic devices

10R:區域10R: Region

10RB:遮蔽區10RB: Shelter area

10RO:開口區10RO: Opening area

BF:緩衝層BF: Buffer layer

BF1、BF2:緩衝子層BF1, BF2: Buffer sublayer

BL:遮光層BL:Light-shielding layer

BM:遮蔽層BM: shielding layer

C1:第一導電層C1: First conductive layer

C2:第二導電層C2: Second conductive layer

CE:共用電極CE: Common Electrode

CH、CH1、CH2:通道區CH, CH1, CH2: Channel area

CU:控制單元CU: Control Unit

D:汲極D: Drain

d1:第一方向d1: first direction

d2:第二方向d2: second direction

DC:晶體管DC: Transistor

DL:資料線DL: Data Line

DR:汲極區DR: Drain region

G、G1、G2:閘極G, G1, G2: Gate

GI:閘絕緣層GI: Gate Insulation Layer

GI_V1、GI_V2、ILD_V1、ILD_V2、PL_V1、PL_V2、PV_V、VD、VS:通孔GI_V1, GI_V2, ILD_V1, ILD_V2, PL_V1, PL_V2, PV_V, VD, VS: through hole

GL:閘極線GL: Gate Line

ILD:絕緣層ILD: Insulating layer

ILD1、ILD2:絕緣子層ILD1, ILD2: Insulating sublayer

M1:第一金屬層M1: First metal layer

M2:第二金屬層M2: Second metal layer

n:法線方向n: normal direction

PL:平坦層PL: Flat layer

PL_S1、PL_S2:側壁PL_S1, PL_S2: side wall

PV:絕緣層PV: Insulation layer

S:源極S: Source

S10、S20、S30、S40、S50:步驟S10, S20, S30, S40, S50: Steps

SB:基板SB: Substrate

SE:半導體層SE: Semiconductor layer

SR:源極區SR: Source region

T1、T2:厚度T1, T2: thickness

TL:觸控訊號線TL: Touch signal line

圖1為本揭露的一實施例的電子裝置的製作方法的流程圖。 圖2為本揭露的一實施例的電子裝置的局部剖面示意圖。 圖3A為本揭露的一實施例的電子裝置的局部俯視示意圖。 圖3B為本揭露的一實施例的電子裝置中的開口區與遮蔽區的局部俯視示意圖。 圖4為本揭露的另一實施例的電子裝置的局部剖面示意圖。FIG. 1 is a flow chart of a method for manufacturing an electronic device according to an embodiment of the present disclosure.FIG. 2 is a partial cross-sectional schematic diagram of an electronic device according to an embodiment of the present disclosure.FIG. 3A is a partial top view schematic diagram of an electronic device according to an embodiment of the present disclosure.FIG. 3B is a partial top view schematic diagram of an opening area and a shielding area in an electronic device according to an embodiment of the present disclosure.FIG. 4 is a partial cross-sectional schematic diagram of an electronic device according to another embodiment of the present disclosure.

10:電子裝置10: Electronic devices

BF:緩衝層BF: Buffer layer

BF1、BF2:緩衝子層BF1, BF2: Buffer sublayer

BL:遮光層BL: Shading layer

C1:第一導電層C1: first conductive layer

C2:第二導電層C2: Second conductive layer

CE:共用電極CE: Common Electrode

CH、CH1、CH2:通道區CH, CH1, CH2: channel area

CU:控制單元CU: Control Unit

D:汲極D: Drain

DC:晶體管DC: Transistor

DR:汲極區DR: Drain region

G、G1、G2:閘極G, G1, G2: Gate

GI:閘絕緣層GI: Gate insulation layer

GI_V1、GI_V2、ILD_V1、ILD_V2、PL_V1、PL_V2、PV_V、VD、VS:通孔GI_V1, GI_V2, ILD_V1, ILD_V2, PL_V1, PL_V2, PV_V, VD, VS: through hole

ILD:絕緣層ILD: Insulating layer

ILD1、ILD2:絕緣子層ILD1, ILD2: insulating sublayer

n:法線方向n: normal direction

PL:平坦層PL: Flat layer

PL_S1、PL_S2:側壁PL_S1, PL_S2: side wall

PV:絕緣層PV: Insulation layer

S:源極S: Source

SB:基板SB: Substrate

SE:半導體層SE: semiconductor layer

SR:源極區SR: Source region

T1、T2:厚度T1, T2: thickness

TL:觸控訊號線TL: Touch signal line

Claims (9)

Translated fromChinese

一種電子裝置，包括：基板；以及複數個控制單元，設置於所述基板上，其中複數個控制單元的一者包括：晶體管，包括第一電極；絕緣層，設置於所述晶體管上，且具有通孔暴露所述第一電極；第一導電層，設置於所述晶體管上，其中所述第一導電層的一部份與所述絕緣層重疊，且所述第一導電層的另一部分通過所述通孔電連接所述第一電極；以及第二導電層，與所述第一導電層至少部分重疊，且直接接觸所述第一導電層，其中在俯視圖中，所述第二導電層的面積大於所述第一導電層的面積，其中所述第一導電層的厚度大於所述第二導電層的厚度。An electronic device includes: a substrate; and a plurality of control units disposed on the substrate, wherein one of the plurality of control units includes: a transistor including a first electrode; an insulating layer disposed on the transistor and having a through hole exposing the first electrode; a first conductive layer disposed on the transistor, wherein a portion of the first conductive layer overlaps with the insulating layer, and another portion of the first conductive layer is electrically connected to the first electrode through the through hole; and a second conductive layer at least partially overlaps with the first conductive layer and directly contacts the first conductive layer, wherein in a top view, the area of the second conductive layer is larger than the area of the first conductive layer, and the thickness of the first conductive layer is larger than the thickness of the second conductive layer.如請求項1所述的電子裝置，其中所述第二導電層包括透明導電材料。An electronic device as described in claim 1, wherein the second conductive layer comprises a transparent conductive material.如請求項1所述的電子裝置，其中所述第一導電層的材料與所述第二導電層的材料不同。An electronic device as described in claim 1, wherein the material of the first conductive layer is different from the material of the second conductive layer.如請求項1所述的電子裝置，其中所述第二導電層的一部分設置於所述絕緣層的所述通孔中。An electronic device as described in claim 1, wherein a portion of the second conductive layer is disposed in the through hole of the insulating layer.如請求項1所述的電子裝置，其中在鄰近所述通孔處，所述第二導電層的頂表面高於所述第一導電層的頂表面，且所述第一導電層的所述頂表面高於所述絕緣層的頂表面。An electronic device as described in claim 1, wherein the top surface of the second conductive layer is higher than the top surface of the first conductive layer adjacent to the through hole, and the top surface of the first conductive layer is higher than the top surface of the insulating layer.如請求項1所述的電子裝置，其更包括：複數條第一走線與複數條第二走線，設置於所述基板上，所述複數條第一走線分別沿第一方向延伸，所述複數條第二走線分別沿第二方向延伸，其中所述第一方向與所述第二方向不同，且所述複數個控制單元的所述一者位於兩條相鄰第一走線與兩條相鄰第二走線所圍成的區域內。The electronic device as described in claim 1 further comprises: a plurality of first routing lines and a plurality of second routing lines, which are arranged on the substrate, wherein the plurality of first routing lines extend along a first direction respectively, and the plurality of second routing lines extend along a second direction respectively, wherein the first direction is different from the second direction, and the one of the plurality of control units is located in an area surrounded by two adjacent first routing lines and two adjacent second routing lines.如請求項6所述的電子裝置，其更包括複數個開口區，且在所述俯視圖中，所述複數個開口區的一者位於所述兩條相鄰第一走線與所述兩條相鄰第二走線所圍成的所述區域內。The electronic device as described in claim 6 further includes a plurality of opening areas, and in the top view, one of the plurality of opening areas is located within the area enclosed by the two adjacent first traces and the two adjacent second traces.如請求項7所述的電子裝置，其中在所述俯視圖中，所述複數個開口區的所述每一者暴露所述第二導電層的一部份。An electronic device as described in claim 7, wherein in the top view, each of the plurality of opening areas exposes a portion of the second conductive layer.如請求項7所述的電子裝置，其中所述第一導電層位於所述複數個開口區的所述每一者之外。An electronic device as described in claim 7, wherein the first conductive layer is located outside each of the plurality of opening areas.

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